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integrated circuit systems, inc. general description features ics9150-04 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation. pentium pro? and sdram frequency generator 9150-04 revd 07/27/98 pin configuration ? generates five processor, six bus, one 14.31818mhz (3.3v) three ioapic, 16 sdram clocks, 48mhz usb clock and 24mhz super i/o clock. ? synchronous clocks skew matched to 250 ps window on cpuclks and 500ps window on pciclks ? skew from cpu (earlier) to pci clock - 1 to 4ns, 2.6ns nom. ? power management control input pins when mode low ? vdd(1:4) - 3.3v 10% (inputs 5v tolerant w/series r ) ? vddl(1:2) - 2.5v or 3.3v 5% ?i 2 c interface for programming stopclocks plus spread spectrum options (0.5% or 1.5%, center spread or down spread) ? 56-pin ssop package 56-pin ssop the ics9150-04 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro or cyrix. eight different reference frequency multiplying factors are selectable from 50 to 83.3mhz. features include five cpu, seven pci and sixteen sdram clocks. one reference output is available equal to the crystal frequency, plus three ioapic outputs powered by vddl1. one 48 mhz for usb is provided plus a 24 mhz. spread spectrum built in up to 1.5% modulation to reduce emi. serial programming i 2 c interface allows changing functions, stop clock programing and frequency selection. rise time adjustment for vdd at 3.3v or 2.5v cpu. additionally, the device meets the pentium power-up stabilization, which requires that cpu and pci clocks be stable within 2ms after power-up. high drive pciclk and sdram outputs typically provide greater than 1 v/ns slew rate into 30pf loads. cpuclk outputs typically provide better than 1v/ns slew rate into 20pf loads while maintaining 505% duty cycle. the ref 24 and 48 mhz and sdram 12, 13 clock outputs typically provide better than 0.5v/ns slew rates. power groups vdd1 = ref, x1, x2 vdd2 = pciclk_f, pciclk(0:5) vdd3 = sdram (0:15), supply for pll core, vdd4 = 48mhz, 24mhz vddl1 = ioapic (0:2) vddl2 = cpuclk (0:4) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9150-04 pin descriptions pin number pin name type description 2 ioapic2 out ioapic clock output (14.318mhz) powered by vddl1 cpu3.3#_2.5 in indicates whether vddl1 & vddl2 are 3.3 or 2.5v. output buffer strength compensates for vddl selection to maintain cpu to sdram skew. high = 2.5v, low = 3.3v. has pull-up to vddl1, must use series resistor for 3.3 or 5v logic levels. 3 ref0 out 14.318 mhz reference clock outputs. 4, 10, 17, 23, 31, 34, 40, 47, 53 gnd pwr ground. 5 x1 in 14.318mhz input. has internal load cap, (nominal 33pf). 6x2 out crystal output. has internal load cap (33pf) and feedback resistor to x1 8 pciclk_f out free running bus clock during pci_stop#=0. fs1 1 in latched frequency select input. has pull-up to vdd2. 9 pciclk0 out bus clock output fs2 1 in latched frequency select input. has pull-up to vdd2. 11, 12, 13, 14 pciclk (1:4) out bus clock outputs. 27 sdata in serial data in for serial config port. (i 2 c) 28 sclk in clock input for serial config port. (i 2 c) 30 24mhz out 24mhz clock output for super i/o or fd. fs0 1 in latched frequency select input. has pull-up to vdd4. 29 48mhz out 48mhz clock output for usb. mode 1 in latched input for mode select. converts 2 outputs to power management cpu_stop# and pci_stop# when low. has pull- up to vdd4. 1, 7, 15, 20, 26, 37, 43 vdd2, vdd1, vdd3, vdd4 pwr nominal 3.3v power supply, see power groups for function. 50, 56 vddl2, vddl1 pwr cpu and ioapic clock buffer power supply, either 2.5 or 3.3v nominal. 18, 19, 21, 22, 24, 25, 32, 33, 35, 36, 38, 39, 41, 42, 44, 45 sdram (0:15) out sdram clocks 55 ioapic0 out ioapic clock output. (14.318 mhz) poweredby vddl1 46, 48, 49, 51, 52 cpuclk (0:4) out cpu output clocks. powered by vddl2 (60 or 66.6mhz) 54 ioapic1 out ioapic clock output. (14.31818 mhz) powered by vddl1 cpu_stop# in halts cpuclk clocks at logic "0" level when low. (in mobile, mode=0) 16 pciclk5 out pci bus clock 5 pci_stop# in halts pciclk (0:4) at logic "0" level when low. (in mobile, mode=0) notes: 1: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low.
3 ics9150-04 definitions 5 latched inputs at internal power-on reset: mode ................................ 48mhz/mode cpu 3.3_2.5#v .................. ioapic2/cpu3.3#_2.5 fs0 ..................................... 24mhz/fs0 fs1 ..................................... pciclk_f/fs1 fs2 ..................................... pciclk0/fs2 pin shared as 2 realtime inputs pins 27, 28 - i 2 c serial input sdata & sclk pull-ups 2 pins with input latch or i/o have ioapic output function with vddl1 which can be at 2.5v or 3.3v. these inputs will have to use series resistor (above 100 w) to external vin to be 3.3 & 5v logic input tolerant. pmos output stage provides input clamp diode to vddl. ? nwell resistor pull-ups 100 to 150k w to local vdd (ie on ioapic pins use vddl1, on fs1, 2 use vdd2, fs0=vdd4 and pci_stop#) functionality v dd 1,2,3 = 3.3v5%, v ddl 1,2 = 2.5v5% or 3.35%, ta=0 to 70c crystal (x1, x2) = 14.31818mhz fs2 fs1 fs0 cpu, sdram(mhz) pciclk (mhz) ref, ioapic (mhz) 1 1 1 66.8 33.4 (1/2 cpu) 14.318 1 1 0 60.0 30.0 (1/2 cpu) 14.318 1 0 1 75.0 37.5 (1/2 cpu) 14.318 1 0 0 83.3 33.3 14.318 0 1 1 68.5 34.25 (1/2 cpu) 14.318 0 1 0 83.3 41.65 (1/2 cpu) 14.318 0 0 1 75.0 32 14.318 0 0 0 50.0 25.0 (1/2 cpu) 14.318
4 ics9150-04 mode pin - power management input control power management functionality spread spectrum functionality cpu 3.3#_2.5v buffer selector for cpuclk driver. cpu3.3#_2.5 latched input le ve l buffer selected for operation at: 1 2.5v vdd 0 3.3v vdd byte0, bit1 ss_en byte0, bit2 ss_type byte0, bit7 cpu, sdram and pci clocks ref, ioapic 24,48mhz 1 0 0 frequency modulated in center spread spectrum mode +1.5%, -1.5% 14.318mhz 24,48mhz 1 frequency modulated in center spread spectrum mode +0.5%, -0.5% 14.318mhz 24,48mhz 1 0 frequency modulated in down spread spectrum mode +0%, -3.0% 14.318mhz 24,48mhz 1 frequency modulated in down spread spectrum mode +0%, -1.0% 14.318mhz 24,48mhz 0 x x normal, steady frequency mode 14.318mhz 24,48mhz mode, pin 55 pin 54 pin 16 0 cpu_stop# input pci_stop# input 1 ioapic1 output pciclk5 output cpu_stop# pci_stop# cpuclk outputs pciclk(0:5) outputs pciclk_f, ref, ioapic 48mhz and sdram crystal osc vco 0 0 stopped low stopped low running running running 0 1 stopped low running running running running 1 0 running stopped low running running running 1 1 running running running running running
5 ics9150-04 vdd(1,2,3,4) this is the power supply to the internal core logic of the device as well as the clock output buffers for ref, pciclk, and sdram. this pin operates at 3.3v volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. vddl1,2 this is the power supply for the cpuclk and ioapic output buffers. the voltage level for these outputs may be 2.5 or 3.3volts. clocks from the buffers that each supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the dc parameter table in this data sheet. gnd this is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. x1 this input pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. with nominal value of 33pf no external load cap is needed for a cl=17 to 18pf crystal. x2 this output pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. the x2 pin will also implement an internal crystal loading capacitor that is nominally 33pf. cpuclk (0:4) these output pins are the clock outputs that drive processor and other cpu related circuitry that requires clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by the voltage level applied to the vddl2 pin of the device. see the functionality table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. sdram(0:15) these output clocks are used to drive dynamic ram?s and are low skew copies of the cpu clocks. the voltage swing of the sdram?s output is controlled by the supply voltage that is applied to vdd3 of the device. operates at 3.3 volts. ioapic (0:2) these outputs are fixed frequency output clocks that run at the reference input frequency (typically 14.31818mhz) . its voltage level swing is controlled by vddl1 and may operate at 2.5 or 3.3volts. ref0 the ref output is a fixed frequency clock that runs at the same frequency as the input reference clock x1 or the crystal (typically 14.31818mhz) attached across x1 and x2. technical pin function descriptions pciclk_f this output is equal to pciclk(0:5). it is free running, and will not be stopped by pci_stop#. pciclk (0:5) these output clocks generate all the pci timing requirements for a pentium/pro based system. they conform to the current pci specification. they run at 1/2 cpu frequency, for most choices of fs (0:2). fs(0:2) these input pins control the frequency of the clocks at the cpu, pciclk and sdram output pins. these inputs are bidirectional input/output pins, latched at internal power-on- reset. mode this input pin is used to select the input function of the i/o pins. an active low will place the i/o pins in the input mode and enable the stop clock functions. (this is the power management mode) cpu_stop# this is a synchronous active low input pin used to stop the cpuclk clocks in an active low state. all other clocks including sdram clocks will continue to run while this function is enabled. the cpuclk?s will have a turn on latency of at least 3 cpu clocks. this input pin valid only when mode=0 (power management mode) pci_stop# this is a synchronous active low input pin used to stop the pciclk clocks in an active low state. it will not effect pciclk_f nor any other outputs. this input pin valid only when mode=0 (power management mode) i 2 c (sdata, sclk) the sdata and sclock inputs are use to program the device. the clock generator is a slave-receiver device in the i 2 c protocol. it will allow read-back of the registers. see configuration map for register functions. the i 2 c specification in philips i 2 c peripherals data handbook (1996) should be followed. 48mhz this is a fixed frequency clock output at 48mhz that is typically used to drive usb devices. 24mhz this pin is a fixed frequency clock output typically used to drive super i/o devices. cpu 3.3#_2.5 this input pin controls the cpu output buffer strength for skew matching cpu and sdram outputs to compensate for the external vddl supply condition. it is important to use this function when selecting power supply requirements for vddl1,2. a logic ?1? (ground) will indicate 2.5v operation and a logic ?0? will indicate 3.3v operation. this pin has an internal pullup resistor to vdd.
6 ics9150-04 byte0: functionality and frequency select register serial configuration command bitmap general i 2 c serial interface information (default bits 0-3 to logic 0) a. for the clock generator to be addressed by an i 2 c controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte. b. the clock generator is a slave/receiver i 2 c component. it can "read back "(in philips i 2 c protocol) the data stored in the latches for verification. (set r/w# to 1 above). there is no byte count supported, so it does not meet the intel smb piix4 protocol. c. the data transfer rate supported by this clock generator is 100k bits/sec (standard mode) d. the input is operating at 3.3v logic levels. e. the data byte format is 8 bit bytes. f. to simplify the clock generator i 2 c interface, the protocol is set to use only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. g . the fixed clocks 24, 48mhz are not addressable in the registers for stopping. these outputs are always running, except in tristate mode. h. at power-on, all registers are set to a default condition. see byte 0 detail for default condition, bytes 1 through 5 default to a 1 (enabled output state) then byte 0, 1, 2, etc in sequence until stop. byte 0, 1, 2, etc in sequence until stop. clock generator address (7 bits) ack + 8 bits dummy command code ack + 8 bits dummy byte count ack a(6:0) & r/w# d2 (h) clock generator address (7 bits) ack byte 0 ack byte 1 ack a(6:0) & r/w# d3 (h) i 2 c is a trademark of philips corporation note: pwd = power-up default note 1. default at power-up will be for latched logic inputs to define the frequency. bits 4, 5, 6 are default to 000. if bit 3 is written to a 1 to use bits 6:4, then these should be defined to the desired frequency at same write cycle. bit description pwd bit 7 0 - 1.5% spread spectrum modulation 1 - 0.5% spread spectrum modulation 0 bit 6:4 bit6 bit5 bit4 111 110 101 100 011 010 001 000 cpu clock 66.8 60.0 75.0 83.3 68.5 83.3 75.0 50.0 pci 33.4(1/2 cpu) 30.0 (1/2 cpu) 37.5 (1/2 cpu) 33.3 34.5 (1/2 cpu) 41.65 (1/2 cpu) 32.0 25.0 (1/2 cpu) note 1 bit 3 0 - frequency is selected by hardware select, latched inputs 1 - frequency is selected by bit 6:4 (above) 0 bit 2 0 - spread spectrum center spread type. (default) 1 - spread spectrum down spread type. 0 bit 1 bit 0 bit1 1 1 0 0 bit0 1 - tri-state 0 - spread spectrum enable 1 - testmode 0 - normal operation 0 0
7 ics9150-04 select functions notes: 1. ref is a test clock on the x1 inputs during test mode. function description outputs cpu pci, pci_f sdram ref ioapic tri - state hi-zhi-zhi-zhi-zhi-z test mode tclk/2 1 tclk/4 1 tclk/2 1 tclk 1 tclk 1 byte 1: cpu clock register notes: 1 = enabled; 0 = disabled, outputs held low byte 2: pciclk clock register byte 4: sdram clock register notes: 1 = enabled; 0 = disabled, outputs held low notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pwd description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 46 1 cpuclk4 (act/inact) bit 3 48 1 cpuclk3 (act/inact) bit 2 49 1 cpuclk2 (act/inact) bit 1 51 1 cpuclk1 (act/inact) bit 0 52 1 cpuclk0 (act/inact) byte 3: sdram clock register notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pwd description bit 7 35 1 sdram7 (act/inact) bit 6 36 1 sdram6 (act/inact) bit 5 38 1 sdram5 (act/inact) bit 4 39 1 sdram4 (act/inact) bit 3 41 1 sdram3 (act/inact) bit 2 42 1 sdram2 (act/inact) bit 1 44 1 sdram1 (act/inact) bit 0 45 1 sdram0 (act/inact) bit pin# pwd description bit 7 - 1 reserved bit 6 8 1 pciclk_f (act/inact) bit 5 16 1 pciclk5 (act/inact) desktop mode only bit 4 14 1 pciclk4 (act/inact) bit 3 13 1 pciclk3 (act/inact) bit 2 12 1 pciclk2 (act/inact) bit 1 11 1 pciclk1 (act/inact) bit 0 9 1 pciclk0 (act/inact) bit pin# pwd description bit 7 24 1 sdram15 (act/inact) bit 6 25 1 sdram14 (act/inact) bit 5 32 1 sdram13 (act/inact) bit 4 33 1 sdram12 (act/inact) bit 3 18 1 sdram11 (act/inact) bit 2 19 1 sdram10 (act/inact) bit 1 21 1 sdram9 (act/inact) bit 0 22 1 sdram8 (act/inact)
8 ics9150-04 ics9150-04 power management requirements notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . signal signal state latency no. of rising edges of free running pciclk cpu_ stop# 0 (disabled) 2 1 1 (enabled) 1 1 pci_stop# 0 (disabled) 2 1 1 (enabled) 1 1 byte 5: peripheral clock register notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pwd description bit 7 - 1 reserved bit 6 2 1 ioapic2 (act/inact) bit 5 54 1 ioapic1 (act/inact) desktop mode only bit 4 55 1 ioapic0 (act/inact) bit 3 - 1 reserved bit 2 - 1 reserved bit 1 - 1 reserved bit 0 3 1 ref0 (act/inact) byte 6: peripheral clock register notes: 1. byte 6 is reserved by integrated circuit systems for future applications. bit pin# pwd description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 - 1 reserved bit 3 - 1 reserved bit 2 - 1 reserved bit 1 - 1 reserved bit 0 - 1 reserve
9 ics9150-04 cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9150-04 . the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9150-04. 3. all other clocks continue to run undisturbed. 4. pci_stop# is shown in a high (true) state. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9150 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9150. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state. pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9150-04 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ics9150-04 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock.
10 ics9150-04 pins 2, 8, 9, 29 and 30 on the ics9150-04 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. shared pin operation - input/output pins fig. 1 these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
11 ics9150-04 fig. 2a fig. 2b
12 ics9150-04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a operating i dd3.3op c l = 0 pf; select @ 66mhz 135 160 ma supply current input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 2 ms settling time 1 t s from 1st crossing to 1% target freq. ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 2 ms skew 1 t cpu-sdram1 v t = 1.5 v; v dd = 3.3; 200 350 ps 66.8 mhz; sdram leads t cpu-pci1 v t = 1.5 v; 12.24 ns 1 guarenteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units i dd2.5op c l = 0 pf; select @ 66m 5 30 ma t cpu-sdram2 v t = 1.5v; v tl = 1.25v; v ddl = 2.5; 66.8mhz; sdram leads 500 800 ps t cpu-pci 2 v t = 1.5v; v tl = 1.25v; cpu leads 1 2.5 4 ns 1 guarenteed by desi g n, not 100% tested in production. operating supply current skew 1
13 ics9150-04 electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance rdsp2b 1 v o = v dd *(0.5) 10 25 w output impedance rdsn2b 1 v o = v dd *(0.5) 10 25 w output high voltage voh2b i oh = -8 ma 2 2.2 v output low voltage vol2b i ol = 12 ma 0.3 0.4 v output high current ioh2b v oh = 2.0 v -20 -16 ma output low current iol2b v ol = 0.7 v 19 26 ma rise time tr2b 1 v ol = 0.4 v, v oh = 2.0 v 2.5 3 ns fall time tf2b 1 v oh = 2.0 v, v ol = 0.4 v 1.6 2 ns duty cycle dt2b 1 v t = 1.25 v 43 46 55 % skew tsk2b 1 v t = 1.25 v 60 250 ps jitter, single edge displacement 2 tjsed2b 1 v t = 1.25 v 200 300 ps jitter, one sigma tj1s2b 1 v t = 1.25 v 80 150 ps jitter, absolute tjabs2b 1 v t = 1.25 v -300 80 300 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period. electrical characteristics - cpu t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2 a 1 v o = v dd *(0.5) 10 20 w output impedance r dsn2 a 1 v o = v dd *(0.5) 10 20 w output high voltage v oh2 a i oh = -28 ma 2.5 2.6 v output low voltage v ol2 a i ol = 27 ma 0.35 0.4 v output high current i oh2a v oh = 2.0 v -29 -23 ma output low current i ol2a v ol = 0.8 v 33 37 ma rise time t r2a 1 v ol = 0.4 v, v oh = 2.4 v 1.9 2.5 ns fall time t f2a 1 v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle d t2a 1 v t = 1.5 v 45 48 55 % skew t sk2a 1 v t = 1.5 v 80 250 ps jitter, single edge displacement 2 tjsed2a 1 v t = 1.25 v 200 250 ps jitter, one sigma t j1s2a 1 v t = 1.5 v 60 150 ps jitter, absolute t jabs2a 1 v t = 1.5 v -300 200 300 ps
14 ics9150-04 electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.3 2 ns duty cycle d t1 1 v t = 1.5 v 45 49 55 % skew t sk1 1 v t = 1.5 v 80 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v, synchronous, excluding select 4 30 150 ps t j1s1a v t = 1.5 v, synchronous, select 4 385 550 ps t j1s1b v t = 1.5 v, as ynchronous , s elect 1 175 250 ps jitter, absolute 1 t jabs1 v t = 1.5 v, synchronous, excluding select 4 -250 100 250 ps t j1s1a v t = 1.5 v, s ynchronous , s elect 4 -700 510 700 ps t jabs1b v t = 1.5 v, asynchronous, select 1 -500 390 500 ps 1 guarenteed by design, not 100% tested in production.
15 ics9150-04 electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 w output impedance r dsn3 1 v o = v dd *(0.5) 10 24 w output high voltage v oh3 i oh = -28 ma (except sdram12,13) 2.4 3 v v oh3 a i oh = -16 ma (sdram12,13) 2.4 2.6 v output low voltage v ol3 i ol = 23 ma (except sdram12,13) 0.2 0.4 v v ol3 a i ol = 9 ma (sdram12,13) 0.3 0.4 v output high current i oh3 v oh = 2.0 v (except sdram12,13) -60 -40 ma i oh3 a v oh = 2.0 v (sdram12,13) -32 -22 ma output low current i ol3 v ol = 0.8 v (except sdram12,13) 41 50 ma i ol3a v ol = 0.8 v (sdram12,13) 16 25 ma t r3 1 v ol = 0.4 v, v oh = 2.4 (except sdram12,13) 1.2 2 ns t r3a 1 v ol = 0.4 v, v oh = 2.4 v (sdram12,13) 2.5 4 ns t f3 1 v oh = 2.4 v, v ol = 0.4 (except sdram12,13) 1.1 2 ns t f3a 1 v oh = 2.4 v, v ol = 0.4 v (sdram12,13) 2.7 4 ns duty cycle d t3 1 v t = 1.5 v 45 51 57 % skew t sk3 1 v t = 1.5 v (except sdram12,13) 285 500 ps jitter, one sigma t j 1s3 1 v t = 1.5 v 50 150 ps jitter, absolute t j abs3 1 v t = 1.5 v -250 - 250 ps 1 guaranteed by design, not 100% tested in production. rise time fall time
16 ics9150-04 electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4 b 1 v o = v dd *(0.5) 10 30 w output impedance r dsn4 b 1 v o = v dd *(0.5) 10 30 w output high voltage v oh4 \ b i oh = -8 ma 2 2.1 v output low voltage v ol4b i ol = 12 ma 0.3 0.4 v output high current i oh4 b v oh = 1.7 v -20 -16 ma output low current i ol4 b v ol = 0.7 v 19 26 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 1.9 4 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 1.5 3.2 ns duty cycle d t4b 1 v t = 1.25 v 455355% skew t sk4b 1 v t = 1.25 v 60 250 ps jitter, one sigma t j1s4b 1 v t = 1.25 v 1 3 % jitter, absolute t jabs4b 1 v t = 1.25 v -5 5 % 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o4 14.318 mhz output impedance r dsp4a 1 v o = v dd *(0.5) 10 30 w output impedance r dsn4 a 1 v o = v dd *(0.5) 10 30 w output high voltage v oh4 a i oh = -16 ma 2.4 2.6 v output low voltage v ol4a i ol = 9 ma 0.3 0.4 v output high current i oh4 a v oh = 2.0 v -32 -22 ma output low current i ol4 a v ol = 0.8 v 16 25 ma rise time t r4a 1 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time t f4a 1 v oh = 2.4 v, v ol = 0.4 v 2.2 4 ns duty cycle d t4a 1 v t = 1.5 v 45 53 57 % skew t sk4a 1 v t = 1.25 v 60 250 ps jitter, one sigma t j1s4a 1 v t = 1.5 v 1 3 % jitter, absolute t jabs4a 1 v t = 1.5 v -5 - 5 % 1 guaranteed by design, not 100% tested in production.
17 ics9150-04 electrical characteristics - 24mhz, 48mhz, ref0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o2 4 m 24 mhz output frequency f o4 8 m 48 mhz output frequency f oref 14.318 mhz output impedance r dsp5 1 v o = v dd *(0.5) 20 60 w output impedance r dsn5 1 v o = v dd *(0.5) 20 60 w output high voltage v oh5 i oh = -16 ma 2.4 2.6 v output low voltage v ol5 i ol = 9 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 25 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.7 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 2.1 4 ns duty cycle d t5 1 v t = 1.5 v 45 54 57 % jitter, one sigma t j1s5 1 v t = 1.5 v 1 3 % jitter, absolute t jabs5 1 v t = 1.5 v -5 - 5 % 1 guaranteed by design, not 100% tested in production.
18 ics9150-04 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. 3 optional crystal load capacitors are recommended. capacitor values: c1, c2 : crystal load values determined by user c3 : 100pf ceramic all unmarked capacitors are 0.01f ceramic
19 ics9150-04 ssop package ordering information ICS9150F-04 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 ad .720 .725 .730 56 a2 .088 .090 .092 b .008 .010 .0135 c.005- .010 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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