View ISPLSI2192VE-180LT128I_2647426.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

isplsi 2192ve 3.3v in-system programmable superfast high density pld 2192ve_08 1 features superfast high density in-system programmable logic 8000 pld gates 96 i/o pins, nine or twelve dedicated inputs 192 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic pinout compatible with isplsi 2096v and 2096ve 3.3v low voltage architecture interfaces with standard 5v ttl devices high performance e 2 cmos technology f max = 225mhz maximum operating frequency t pd = 4.0ns propagation delay electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power in-system programmable 3.3v in-system programmability (isp) using boundary scan test access port (tap) open-drain output option for flexible bus interface capability, allowing easy implementation of wired- or bus arbitration logic increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping 100% ieee 1149.1 boundary scan testable the ease of use and fast system speed of plds with the density and flexibility of fpgas enhanced pin locking capability three dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control flexible pin placement optimized global routing pool provides global interconnectivity ispdesignexpert ?logic compiler and com- plete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms functional block diagram description the isplsi 2192ve is a high density programmable logic device containing 192 registers, nine or twelve dedicated input pins, three dedicated clock input pins, two dedicated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2192ve features in-system programmability through the bound- ary scan test access port (tap) and is 100% ieee 1149.1 boundary scan testable. the isplsi 2192ve offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable sys- tems. the basic unit of logic on the isplsi 2192ve device is the generic logic block (glb). the glbs are labeled a0, a1 .. f7 (see figure 1). there are a total of 48 glbs in the isplsi 2192ve device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. copyright ?2001 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. april 2001 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com output routing pool output routing pool f7 f6 f5 f4 f3 f2 f1 f0 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 output routing pool output routing pool output routing pool e7 e6 e5 e4 e3 e2 e1 e0 c0 c1 c2 c3 c4 c5 c6 c7 clk0 clk1 clk2 d7 d6 d5 d4 d3 d2 d1 d0 output routing pool logic array dq dq dq dq global routing pool (grp) glb 0139/2192ve
specifications isplsi 2192ve 2 functional block diagram figure 1. isplsi 2192ve functional block diagram the 2192ve contains 96 i/o cells. each i/o cell is directly connected to an i/o pin and can be individually pro- grammed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4ma or sink 8ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. device pins can be safely driven to 5v signal levels to support mixed-voltage systems. eight glbs, 16 i/o cells, two dedicated inputs and an orp are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 16 universal i/o cells by the orp. each isplsi 2192ve device contains six megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2192ve device are selected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2192ve are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. the default configuration when the device is in bulk erased state is totem-pole configuration. the open-drain/totem-pole option is selectable through the ispdesignexpert software tools. output routing pool (orp) b0 b1 b2 b3 b4 b5 b6 b7 output routing pool (orp) c0 c1 c2 c3 c4 c5 c6 c7 output routing pool (orp) f7 f6 f5 f4 f3 f2 f1 f0 input bus output routing pool (orp) e7 e6 e5 e4 e3 e2 e1 e0 input bus a0 a1 a2 a3 a4 a5 a6 a7 output routing pool (orp) generic logic blocks (glbs) megablock input bus global routing pool (grp) d7 d6 d5 d4 d3 d2 d1 d0 output routing pool (orp) i/o 94 i/o 95 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 in 11* i/o 78 i/o 79 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 in 9 in 10 i/o 17 i/o 16 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 in 3 i/o 33 i/o 32 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 y0 y1 y2 i/o 47 in 5* in4 in 7/tck in 6/tdo i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 tdi/in 0 tms/in 1 i/o 4 i/o 5 bscan reset input bus input bus lnput bus 2192ve block.eps in 8 goe 0 goe 1 in 2* *note: dedicated inputs 2, 5 and 11 are not available with 128-pin packages. clk 0 clk 1 clk 2
specifications isplsi 2192ve 3 absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition erase reprogram specifications capacitance (t a =25 c, f=1.0 mhz) c symbol table 2-0006/2192ve c parameter i/o capacitance 8 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 3.3v, v = 0.0v v = 3.3v, v = 0.0v cc cc i/o in c clock and global output enable capacitance 12 3 pf v = 3.3v, v = 0.0v cc y table 2-0008/2192ve parameter minimum maximum units erase/reprogram cycles 10,000 cycles t a = 0 c to + 70 c symbol table 2-0005/2192ve v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 3.0 2.0 v 0.5 3.6 5.25 0.8 v v v ss commercial
specifications isplsi 2192ve 4 switching test conditions figure 2. test load input pulse levels table 2-0003/2192ve input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 1.5ns 10% to 90% 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. dc electrical characteristics over recommended operating conditions output load conditions (see figure 2) test condition r1 r2 cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 348 ? 35pf active high active low c 316 ? 348 ? 5pf 348 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/2192ve v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using twelve 16-bit counters. 3. typical values are at v = 3.3v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2192ve 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current bscan input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 0v v v (max.) 0v v v 0v v v v = 3.3v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in il in il cc out clock il ih condition min. typ. max. units 3 2.4 275 0.4 10 10 -10 -150 -150 -100 v v a a a a a ma ma cc a out cc cc (v - 0.2)v v v v v 5.25v cc cc in in cc + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a/2192ve
specifications isplsi 2192ve 5 external timing parameters over recommended operating conditions u s e 2 1 9 2 v e -2 2 5 f o r n e w d e s ig n s t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030a/2192ve 1 3 2 1 tsu2 + tco1 ( ) description # parameter a 1 data propagation delay, 4pt bypass, orp bypass ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass ns t su2 9 glb reg. setup time before clock ns t co2 a 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock ns t r1 a 12 ext. reset pin to output delay, orp bypass ns t rw1 13 ext. reset pulse duration ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t goeen b 16 global oe output enable ns t goedis c 17 global oe output disable ns t wh 18 external synchronous clock pulse duration, high ns t wl 19 external synchronous clock pulse duration, low ns -180 min. max. 5.0 180 0.0 4.5 0.0 4.0 2.5 2.5 125 200 3.5 3.5 4.5 7.0 10.0 10.0 5.0 5.0 7.5 -225 min. max. 4.0 225 0.0 3.5 0.0 3.5 2.0 2.0 150 250 2.5 3.2 3.7 6.0 6.0 6.0 4.5 4.5 6.2
specifications isplsi 2192ve 6 external timing parameters over recommended operating conditions t pd1 units -135 min. test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030b/2192ve 1 3 2 1 tsu2 + tco1 ( ) -100 min. max. max. description # parameter a 1 data propagation delay, 4pt bypass, orp bypass 7.5 10.0 ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback 135 100 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass 0.0 ns t su2 9 glb reg. setup time before clock 6.0 ns t co2 a 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock 0.0 ns t r1 a 12 ext. reset pin to output delay, orp bypass ns t rw1 13 ext. reset pulse duration 5.0 ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t goeen b 16 global oe output enable ns t goedis c 17 global oe output disable ns t wh 18 external synchronous clock pulse duration, high 3.5 ns t wl 19 external synchronous clock pulse duration, low 3.5 ns 100 143 5.0 4.0 5.0 9.0 12.0 12.0 7.0 7.0 10.0 77 100 6.5 0.0 8.0 0.0 6.5 5.0 5.0 13.0 5.0 6.0 12.5 15.0 15.0 9.0 9.0
specifications isplsi 2192ve 7 u s e 2 1 9 2 v e -2 2 5 f o r n e w d e s ig n s internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036e/2192ve v0.1 inputs units -225 min. max. description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb 0.3 0.5 0.2 3.2 3.2 3.2 0.0 0.3 0.3 4.0 2.9 3.2 1.6 2.0 1.5 2.2 0.9 0.4 2.6 2.6 1.9 0.9 1.1 3.7 0.7 1.8 0.8 0.9 1.1 ns global reset -180 min. max. 0.5 1.1 0.6 3.4 3.4 3.4 0.0 0.3 0.6 4.3 5.9 4.0 1.6 2.0 1.9 2.4 1.4 0.4 3.0 3.0 2.0 1.2 1.4 4.4 1.2 2.3 1.0 1.2 1.4
specifications isplsi 2192ve 8 internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036d/2192ve v0.1 inputs units -135 min. -100 min. max. max. description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock 1.7 ns t gh 30 glb register hold time after clock 4.8 ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay 2.6 ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 2.4 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 2.6 ns clocks t gr 45 global reset to glb 0.7 2.5 1.8 6.2 6.2 6.2 1.0 0.3 3.1 7.1 9.1 5.6 1.6 2.0 5.2 4.7 1.7 0.7 3.4 3.4 5.6 2.4 2.6 7.1 0.5 1.7 1.2 4.7 4.7 4.7 0.5 0.3 1.1 6.1 6.9 4.6 1.6 2.0 3.7 3.7 1.5 0.5 3.4 3.4 3.6 1.6 1.8 5.8 1.2 3.8 1.6 1.6 1.8 ns global reset
specifications isplsi 2192ve 9 isplsi 2192ve timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0 #42 #40, 41 0491/2192ve #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock = = = = t su logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.3 + 0.2 + 3.2) + (0.7) - (0.3 + 0.2 + 0.8) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.3 + 0.2 + 3.2) + (1.8) - (0.3 + 0.2 + 3.2) = = = = t co note: calculations are based upon timing specifications for the isplsi 2192ve-225l. clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.3 + 0.2 + 3.2) + (0.3) + (0.9 + 1.6) table 2-0042a/2192ve v0.1 3.1ns 1.8ns 6.5ns
specifications isplsi 2192ve 10 power consumption power consumption in the isplsi 2192ve device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127/2192ve i cc can be estimated for the isplsi 2192ve using the following equation: i cc = 25 + (# of pts * 0.670) + (# of nets * max freq * 0.0051) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 300 250 400 0 40 80 120 160 200 f max (mhz) i cc (ma) notes: configuration of twelve 16-bit counters typical current at 3.3v, 25 c 450 isplsi 2192ve 500 350 240
specifications isplsi 2192ve 11 reset 15 g4 goe 0, goe 1 80, 17 f12, g2 y0, y1, y2 14, 83, 78 f3, f10, g11 bscan 19 f1 tdi/in 0 20 g3 tms/in 1 48 j6 tdo/in 6 112 c7 tck/in 7 77 g12 in 2-5, in 8-11 , 49, 82, , 84, 113, 13, m7, j7, f9, g10, e12, b6, f2, e1 gnd 18, 34, 50, 63, 79, 98, 111, a1, a12, d4, d9, e5, e8, f6, 127 f7, g6, g7, h5, h8, j4, j9, m1, m12 vcc 2, 16, 31, 47, 66, 81, 95, 114 b1, b12, e6, e7, f5, f8, g5, g8, h6, h7, l1, l12 nc 1 k2 signal descriptions reset active low (0) reset pin resets all the registers in the device. goe 0, goe1 global output enable input pins. y0, y1, y2 dedicated clock input these clock inputs are connected to one of the clock inputs of all the glbs in the device. bscan input dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. tdi/in 0 input this pin performs two functions. when bscan is logic low, it functions as a serial data input pin to load programming data into the device. when bscan is high, it functions as a dedicated input pin. tck/in 7 input this pin performs two functions. when bscan is logic low, it functions as a clock pin for the boundary scan state machine. when bscan is high, it functions as a dedicated input pin. tms/in 1 input this pin performs two functions. when bscan is logic low, it functions as a mode control pin for the boundary scan state machine. when bscan is high, it functions as a dedicated input pin. tdo/in 6 output/input this pin performs two functions. when bscan is logic low, it functions as an output pin to read serial shift register data. when bscan is high, it functions as a dedicated input pin. in 2-5, in 8-11 dedicated input pins to the device. gnd ground (gnd) vcc vcc nc 1 no connect i/o input/output pins these are the general purpose i/o pins used by the logic array. signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd. signal locations signal name 128-pin tqfp 144-ball fpbga 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2192ve 12 i/o locations i/o 0 21 h4 i/o 1 22 g1 i/o 2 23 h2 i/o 3 24 h1 i/o 4 25 h3 i/o 5 26 j1 i/o 6 27 j3 i/o 7 28 k1 i/o 8 29 j2 i/o 9 30 m2 i/o 10 32 l2 i/o 11 33 l3 i/o 12 35 k3 i/o 13 36 m3 i/o 14 37 l4 i/o 15 38 k4 i/o 16 39 m4 i/o 17 40 j5 i/o 18 41 m5 i/o 19 42 k5 i/o 20 43 l5 i/o 21 44 m6 i/o 22 45 l6 i/o 23 46 k6 i/o 24 51 l7 i/o 25 52 k7 i/o 26 53 j8 i/o 27 54 m8 i/o 28 55 l8 i/o 29 56 k8 i/o 30 57 m9 i/o 31 58 l9 i/o 32 59 k9 i/o 33 60 m10 i/o 34 61 l10 i/o 35 62 m11 i/o 36 64 k10 i/o 37 65 k11 i/o 38 67 l11 i/o 39 68 k12 i/o 40 69 j11 i/o 41 70 j12 i/o 42 71 j10 i/o 43 72 h9 i/o 44 73 h11 i/o 45 74 h12 i/o 46 75 h10 i/o 47 76 g9 128 144 signal tqfp fpbga i/o 48 85 f11 i/o 49 86 d12 i/o 50 87 e9 i/o 51 88 e10 i/o 52 89 e11 i/o 53 90 c12 i/o 54 91 d10 i/o 55 92 d11 i/o 56 93 b11 i/o 57 94 c11 i/o 58 96 c10 i/o 59 97 a11 i/o 60 99 b10 i/o 61 100 a10 i/o 62 101 c9 i/o 63 102 b9 i/o 64 103 a9 i/o 65 104 d8 i/o 66 105 b8 i/o 67 106 c8 i/o 68 107 a8 i/o 69 108 b7 i/o 70 109 a7 i/o 71 110 d7 i/o 72 115 c6 i/o 73 116 a6 i/o 74 117 d6 i/o 75 118 b5 i/o 76 119 c5 i/o 77 120 a5 i/o 78 121 d5 i/o 79 122 c4 i/o 80 123 b4 i/o 81 124 a4 i/o 82 125 c3 i/o 83 126 b3 i/o 84 128 a3 i/o 85 1 c2 i/o 86 3 b2 i/o 87 4 d2 i/o 88 5 a2 i/o 89 6 d3 i/o 90 7 e2 i/o 91 8 c1 i/o 92 9 e3 i/o 93 10 e4 i/o 94 11 d1 i/o 95 12 f4 128 144 signal tqfp fpbga
specifications isplsi 2192ve 13 pin configuration isplsi 2192ve 128-pin tqfp pinout diagram vcc i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 in10 y0 reset vcc goe 1 gnd bscan i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 vcc i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 8 y1 in4 vcc goe 0 y2 tck/in 7 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 vcc i/o 84 gnd i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 in 9 gnd i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 59 i/o 10 gnd i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 tms/in 1 in3 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 gnd isplsi 2192ve top view vcc tdi/in 0 i/o 58 tdo/in 6 gnd i/o 37 i/o 11 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 64 96 122 i/o 36 vcc 0124-2192ve
specifications isplsi 2192ve 14 signal configuration isplsi 2192ve 144-ball fpbga signal diagram 10 11 12 987654321 10 11 12 987654321 a b c d e f g h j k l m a b c d e f g h j k l m i/o 59 i/o 61 i/o 64 i/o 68 i/o 70 i/o 73 i/o 77 i/o 81 i/o 84 i/o 88 gnd gnd gnd gnd i/o 35 i/o 33 i/o 30 i/o 27 i/o 21 i/o 18 i/o 16 i/o 13 i/o 9 gnd in 2 gnd i/o 56 i/o 60 i/o 63 i/o 66 i/o 69 i/o 75 i/o 80 i/o 83 i/o 86 i/o 57 i/o 53 i/o 58 i/o 62 i/o 67 tdo/ in 6 i/o 72 i/o 76 i/o 79 i/o 82 i/o 85 i/o 91 i/o 55 i/o 49 i/o 54 i/o 65 i/o 71 i/o 74 i/o 78 i/o 89 i/o 87 i/o 94 gnd in 8 gnd y0 vcc vcc i/o 52 i/o 51 i/o 50 i/o 92 i/o 93 i/o 90 vcc y1 in 4 in 11 bscan in 10 vcc gnd gnd i/o 48 goe 0 i/o 95 vcc in 5 y2 reset goe 1 vcc gnd gnd i/o 47 i/o 1 tdi/ in 0 tck/ in 7 gnd gnd vcc vcc i/o 43 i/o 3 i/o 2 i/o 4 i/o 0 i/o 45 i/o 44 i/o 46 gnd gnd in 3 i/o 5 i/o 8 i/o 6 tms/ in 1 i/o 17 i/o 41 i/o 40 i/o 42 i/o 26 i/o 7 i/o 12 i/o 23 i/o 19 i/o 15 i/o 39 i/o 37 i/o 36 i/o 32 i/o 29 i/o 25 vcc in 9 vcc i/o 38 i/o 34 i/o 31 i/o 28 i/o 24 i/o 22 i/o 20 i/o 14 i/o 11 i/o 10 vcc vcc nc 1 1 ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. 144-bga/2192ve isplsi 2192ve bottom view
specifications isplsi 2192ve 15 part number description isplsi 2192ve ordering information device number isplsi 2192ve xxx x xxxx grade blank = commercial x speed 225 = 225 mhz f max 180 = 180 mhz f max* 135 = 135 mhz f max 100 = 100 mhz f max power l = low package - device family 0212b/2192ve t128 = 128-pin tqfp b144 = 144-ball fpbga *isplsi 2192ve-225 recommended for new designs. i = industrial table 2-0041d/2192ve 135 7.5 128-pin tqfp isplsi 2192ve-135lt128 135 7.5 144-ball fpbga isplsi 2192ve-135lb144 family f max (mhz) ordering number package t pd (ns) isplsi commercial 100 128-pin tqfp 10 isplsi 2192ve-100lt128 100 144-ball fpbga 10 isplsi 2192ve-100lb144 180 128-pin tqfp 5.0 isplsi 2192ve-180lt128* 225 144-ball fpbga 4.0 isplsi 2192ve-225lb144 225 128-pin tqfp 4.0 isplsi 2192ve-225lt128 180 144-ball fpbga 5.0 isplsi 2192ve-180lb144* *isplsi 2192ve-225 recommended for new designs. table 2-0041a/2192ve 180 5.0 128-pin tqfp isplsi 2192ve-180lt128i family f max (mhz) ordering number package t pd (ns) isplsi industrial

▲Up To Search▲

Price & Availability of ISPLSI2192VE-180LT128I

	To Download ISPLSI2192VE-180LT128I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .