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mc1451512 through mc1451582 motorola 1 ! !" ! cmos the devices described in this document are typically used as lowpower , phaselocked loop frequency synthesizers. when combined with an external lowpass filter and voltagecontrolled oscillator , these devices can provide all the remaining functions for a pll frequency synthesizer operating up to the device's frequency limit. for higher vco frequency operation, a down mixer or a prescaler can be used between the vco and the synthesizer ic. these frequency synthesizer chips can be found in the following and other applications: catv tv tuning am/fm radios scanning receivers twoway radios amateur radio r osc control logic n a f p/p + 1 vco output frequency contents page device detail sheets mc1451512 parallelinput, singlemodulus 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mc1451522 parallelinput, dualmodulus 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mc1451552 serialinput, singlemodulus 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mc1451562 serialinput, dualmodulus 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mc1451572 serialinput, singlemodulus 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mc1451582 serialinput, dualmodulus 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . family characteristics maximum ratings 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc electrical characteristics 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac electrical characteristics 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing requirements 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frequency characteristics 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phase detector/lock detector output waveforms 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . design considerations phaselocked loop e lowpass filter design 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . crystal oscillator considerations 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dualmodulus prescaling 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . order this document by mc1451512/d
semiconductor technical data ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 2
interfaces with singlemodulus prescalers the m c145151 2 i s p rogramme d b y 1 4 p arallelinpu t d at a l ine s f o r t he n counter and three input lines for the r counter . the device features consist of a reference oscillator, selectablereference divider, digitalphase detector, and 14bit programmable dividebyn counter. the mc1451512 is an improvedperformance dropin replacement for the mc1451511. the power consumption has decreased and esd and latchup performance have improved. ? operating temperature range: 40 to 85 c ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on or offchip reference oscillator operation ? lock detect signal ? n counter output available ? single modulus/parallel programming ? 8 userselectable r v alues: 8, 128, 256, 512, 1024, 2048, 2410, 8192 ? n range = 3 to 16383 ? alinearizedo digital phase detector enhances transfer function linearity ? two error signal options: singleended (threestate) or doubleended ? chip complexity: 8000 fets or 2000 equivalent gates semiconductor technical data p suffix plastic dip case 710 dw suffix sog package case 751f ordering information mc145151p2 plastic dip mc145151dw2 sog package 5 4 3 2 1 10 9 8 7 6 11 12 13 14 20 21 22 23 24 25 26 19 27 28 18 17 16 15 ra2 pd out v dd v ss f in n0 f r ra0 n3 n2 n1 ra1 f v f v n10 n11 osc out osc in ld n5 n6 n7 n4 n9 n12 n13 n8 t/r pin assignment 1 28 1 28 ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 3 14 x 8 rom reference decoder 14bit n counter f v mc1451512 block diagram f r 14bit r counter transmit offset adder phase detector b phase detector a lock detect ld pd out ra2 f in v dd osc in osc out t/r 14 14 f v n13 n11 n9 n7 n6 n4 n2 n0 note: n0 n13 inputs and inputs ra0, ra1, and ra2 have pullup resistors that are not shown. ra0 ra1 pin descriptions input pins f in frequency input (pin 1) input to the n portion of the synthesizer . f in is typically derived from loop vco and is ac coupled into the device. for larger a mplitud e s ignals ( standar d c mo s l ogi c l evels ) d c coupling may be used. ra0 ra2 reference address inputs (pins 5, 6, 7) these three inputs establish a code defining one of eight possible d ivid e v alue s f or t h e t ota l r eferenc e d ivider , a s defined by the table below. pullup resistors ensure that inputs left open remain at a logic 1 and require only a spst switch to alter data to the zero state. reference address code total divide value ra2 ra1 ra0 divide value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 128 256 512 1024 2048 2410 8192 n0 n11 n counter programming inputs (pins 11 20, 22 25) these inputs provide the data that is preset into the n counter when it reaches the count of zero. n0 is the least sig - nificant and n13 is the most significant. pullup resistors en- sure that inputs left open remain at a logic 1 and require only an spst switch to alter data to the zero state. t/r transmit/receive offset adder input (pin 21) this input controls the of fset added to the data provided at the n inputs. this is normally used for of fsetting the vco frequency b y a n a moun t e qua l t o t h e i f f requenc y o f t he transceiver. this of fset is fixed at 856 when t/r is low and gives no of fset when t/r is high. a pullup resistor ensures that no connection will appear as a logic 1 causing no of fset addition. osc in , osc out reference oscillator input/output (pins 27, 26) these pins form an onchip reference oscillator when con - nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be connected from o sc in to ground and o sc out to ground. osc in may also serve as the input for an externallygener - ated reference signal. this signal is typically ac coupled to osc in , b u t f or l arge r a mplitud e s ignal s ( standar d c mos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . output pins pd out phase detector a output (pin 4) threestate output of phase detector for use as looperror signal. doubleended outputs are also available for this pur- pose (see f v and f r ). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: highimped - ance state
mc1451512 through mc1451582 motorola 4 f r , f v phase detector b outputs (pins 8, 9) these phase detector outputs can be combined externally for a looperror signal. a singleended output is also avail - able for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v a nd f r r emai n h ig h e xcep t f o r a s mal l m inimu m t ime period when both pulse low in phase. f v n counter output (pin 10) this is the buf fered output of the n counter that is inter - nally connected to the phase detector input. with this output available, the n counter can be used independently. ld lock detector output (pin 28) essentially a high level when loop is locked (f r , f v of same phase and frequency). pulses low when loop is out of lock. power supply v dd positive power supply (pin 3) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 2) the m os t n egativ e s upply p otential . t hi s p i n i s u sually ground. typical applications figure 1. 5 mhz to 5.5 mhz local oscillator channel spacing = 1 khz 0 1 1 1 0 0 0 1 0 0 0 = 5 mhz 1 0 1 0 1 1 1 1 1 0 0 = 5.5 mhz 5 5.5 mhz voltage controlled oscillator nc nc pd out ra0 ra1 ra2 n13 n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 mc1451512 f in osc out osc in 2.048 mhz figure 2. synthesizer for land mobile radio uhf bands notes: 1. f r = 4.1667 khz; r = 2410; 21.4 mhz low side injection during receive. 2. frequency values shown are for the 440 470 mhz band. similar implementation applies to the 406 440 mhz band. for 470 512 mhz, consider reference oscillator frequency x9 for mixer injection signal (90.3750 mhz). 60.2500 mhz a0o a1o a1o choice of detector error signals lock detect signal t: 13.0833 18.0833 mhz r: 9.5167 14.5167 mhz t: 73.3333 78.3333 mhz r: 69.7667 74.7667 mhz x6 vco loop filter down mixer x6 t/r v ss v dd channel programming n = 2284 to 3484 transmit (adds 856 to n value) receive ref. osc. 10.0417 mhz (onchip osc. optional) a1o a0o a0o f v ld ra0 ra1 ra2 osc in osc out mc1451512 + v transmit: 440.0 470.0 mhz receive: 418.6 448.6 mhz (25 khz steps) pd out f r f v f in mc1451512 data sheet continued on page 23
mc1451512 through mc1451582 motorola 5
interfaces with dualmodulus prescalers the mc1451522 is programmed by sixteen parallel inputs for the n and a counters and three input lines for the r counter. the device features consist of a reference oscillator , selectablereference divider , twooutput phase detector , 10bit p rogrammabl e d ivideby n c ounter , a n d 6 bi t p rogrammable a counter. the mc1451522 is an improvedperformance dropin replacement for the mc1451521. p owe r c onsumptio n h a s d ecrease d a nd e s d a n d l atchup performance have improved. ? operating temperature range: 40 to 85 c ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on or offchip reference oscillator operation ? lock detect signal ? dual modulus/parallel programming ? 8 userselectable r values: 8, 64, 128, 256, 512, 1024, 1160, 2048 ? n range = 3 to 1023, a range = 0 to 63 ? chip complexity: 8000 fets or 2000 equivalent gates ? see application note an980 semiconductor technical data p suffix plastic dip case 710 dw suffix sog package case 751f ordering information mc145152p2 plastic dip mc145152dw2 sog package 5 4 3 2 1 10 9 8 7 6 11 12 13 14 20 21 22 23 24 25 26 19 27 28 18 17 16 15 f r ra0 v dd v ss f in n0 f v ra1 n3 n2 n1 ra2 mc a5 a3 a4 osc out osc in ld n5 n6 n7 n4 n9 a2 a0 n8 a1 pin assignment 1 28 1 28 ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 6 12 x 8 rom reference decoder f v mc1451522 block diagram f r 12bit r counter phase detector lock detect ld f in osc in osc out 12 n0 n2 n4 n5 n7 n9 note: n0 n9, a0 a5, and ra0 ra2 have pullup resistors that are not shown. 10bit n counter control logic mc 6bit a counter a5 a3 a2 a0 ra2 ra0 ra1 pin descriptions input pins f in frequency input (pin 1) input to the positive edge triggered n and a counters. f in is typically derived from a dualmodulus prescaler and is ac coupled i nt o t h e d evice . f or l arge r a mplitud e s ignals (standard cmos logic levels) dc coupling may be used. ra0, ra1, ra2 reference address inputs (pins 4, 5, 6) these three inputs establish a code defining one of eight possible d ivid e v alue s f o r t h e t otal r eferenc e d ivider . t he total reference divide values are as follows: reference address code total divide value ra2 ra1 ra0 divide value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 512 1024 1160 2048 n0 n9 n counter programming inputs (pins 11 20) the n inputs provide the data that is preset into the n counter when it reaches the count of 0. n0 is the least signifi - cant digit and n9 is the most significant. pullup resistors en - sure that inputs left open remain at a logic 1 and require only a spst switch to alter data to the zero state. a0 a5 a counter programming inputs (pins 23, 21, 22, 24, 25, 10) the a inputs define the number of clock cycles of f in that require a l ogic 0 o n t h e m c o utpu t ( see dualmodulus prescaling section). the a inputs all have internal pullup resistors that ensure that inputs left open will remain at a logic 1. osc in , osc out reference oscillator input/output (pins 27, 26) these pins form an onchip reference oscillator when con - nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be connected from o sc in to ground and o sc out to ground. osc in may also serve as the input for an externallygener- ated reference signal. this signal is typically ac coupled to osc in , b u t f or l arge r a mplitud e s ignal s ( standar d c mos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . output pins f r , f v phase detector b outputs (pins 7, 8) these phase detector outputs can be combined externally for a looperror signal. if the frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v a nd f r r emai n h ig h e xcep t f o r a s mal l m inimu m t ime period when both pulse low in phase. mc dualmodulus prescale control output (pin 9) signal generated by the onchip control logic circuitry for controlling a n e xterna l d ualmodulu s p rescaler . t h e m c level will be low at the beginning of a count cycle and will remain low until the a counter has counted down from its programmed value. at this time, mc goes high and remains high until the n counter has counted the rest of the way down from its programmed value (n a additional counts since both n and a are counting down during the first
mc1451512 through mc1451582 motorola 7 portion of the cycle). mc is then set back low , the counters preset to their respective programmed values, and the above sequence repeated. this provides for a total programmable divide value (n t ) = n ? p + a where p and p + 1 represent the dualmodulus prescaler divide values respectively for high and low mc levels, n the number programmed into the n counter, and a the number programmed into the a counter. ld lock detector output (pin 28) essentially a high level when loop is locked (f r , f v of same phase and frequency). pulses low when loop is out of lock. power supply v dd positive power supply (pin 3) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 2) the m os t n egativ e s upply p otential . t hi s p i n i s u sually ground. typical applications figure 1. synthesizer for land mobile radio vhf bands notes: 1. offchip oscillator optional. 2. the f r and f v outputs are fed to an external combiner/loop filter. see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . lock detect signal 10.24 mhz note 1 r1 mc33171 note 2 + 150 175 mhz 5 khz steps mc12017 64/65 prescaler mc1451522 mc ld a0 a5 n9 osc in v dd v ss osc out ra2 ra1 f r f v f in vco ra0 n0 + v r1 r2 c r2 c a1o a1o a1o no connects channel programming
mc1451512 through mc1451582 motorola 8 figure 2. 666channel, computercontrolled, mobile radiotelephone synthesizer for 800 mhz cellular radio systems lock detect signal r1 + receiver first l.o. 825.030 844.980 mhz (30 khz steps) mc12017 64/65 prescaler note 6 mc1451522 note 5 mc ld a0 a5 n9 osc in v dd v ss osc out ra2 ra1 f r f v f in vco ra0 n0 + v r1 r2 c r2 c a1o a1o a1o no connects channel programming notes: 1. receiver 1st i.f . = 45 mhz, low side injection; receiver 2nd i.f . = 11.7 mhz, low side injection. 2. duplex operation with 45 mhz receiver/transmit separation. 3. f r = 7.5 khz; r = 2048. 4. n total = n 64 + a = 27501 to 28166; n = 429 to 440; a = 0 to 63. 5. mc1451582 may be used where serial data entry is desired. 6. high frequency prescalers (e.g., mc12018 [520 mhz] and mc12022 [1 ghz]) may be used for higher frequency vco and f ref implementations. 7. the f r and f v outputs are fed to an external combiner/loop filter. see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . ref. osc. 15.360 mhz (onchip osc. optional) x2 x4 note 6 x4 note 6 transmitter modulation transmitter signal 825.030 844.980 mhz (30 khz steps) receiver 2nd l.o. 30.720 mhz note 7 mc1451522 data sheet continued on page 23
mc1451512 through mc1451582 motorola 9
interfaces with singlemodulus prescalers th e m c145155 2 i s p rogramme d b y a c locked , s eria l i nput , 1 6bi t d ata stream. the device features consist of a reference oscillator , selectablerefer- ence d ivider , d igitalphas e d etector , 1 4bi t p rogrammabl e d ividebyn counter, and the necessary shift register and latch circuitry for accepting serial input data. the mc1451552 is an improvedperformance dropin replacement for the mc1451551. p owe r c onsumptio n h a s d ecrease d a nd e s d a n d l atchup performance have improved. ? operating temperature range: 40 to 85 c ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on or offchip reference oscillator operation with buffered output ? compatible with the serial peripheral interface (spi) on cmos mcus ? lock detect signal ? two opendrain switch outputs ? 8 userselectable r v alues: 16, 512, 1024, 2048, 3668, 4096, 6144, 8192 ? single modulus/serial programming ? n range = 3 to 16383 ? alinearizedo digital phase detector enhances transfer function linearity ? two error signal options: singleended (threestate) or doubleended ? chip complexity: 6504 fets or 1626 equivalent gates semiconductor technical data p suffix plastic dip case 707 dw suffix sog package case 751d ordering information mc145155p2 plastic dip mc145155dw2 sog package pin assignments v dd f v ra2 ra1 f in ld v ss pd out f r ref out osc out osc in ra0 clk data enb sw1 sw2 14 15 16 17 18 10 11 12 13 5 4 3 2 1 9 8 7 6 plastic dip pd out f r f v ra2 ra1 f in ld nc v ss v dd 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 nc ref out osc out osc in ra0 clk data enb sw1 sw2 sog package nc = no connection 1 18 20 1 ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 10 14 x 8 rom reference decoder 14bit n counter f v f r 14bit r counter latch phase detector b phase detector a lock detect ld pd out f in v dd osc in osc out enb 14 14 sw2 sw1 f r f v latch 14bit shift register data 2bit shift register clk 14 ref out mc1451552 block diagram ra2 ra0 ra1 pin descriptions input pins f in frequency input (pdip pin 9, sog pin 10) input to the n portion of the synthesizer . f in is typically derived from loop vco and is ac coupled into the device. for larger a mplitud e s ignals ( standar d c mo s l ogi c l evels ) d c coupling may be used. ra0, ra1, ra2 reference address inputs (pdip pins 18, 1, 2; sog pins 20, 1, 2) these three inputs establish a code defining one of eight possible d ivid e v alue s f or t h e t ota l r eferenc e d ivider , a s defined by the table below: reference address code total divide value ra2 ra1 ra0 divide value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 512 1024 2048 3668 4096 6144 8192 clk, data shift register clock, serial data inputs (pdip pins 10, 11; sog pins 11, 12) each lowtohigh transition clocks one bit into the onchip 16bit shift register . the data input provides programming information for the 14bit n counter and the two switch sig - nals sw1 and sw2. the entry format is as follows: sw2 sw1 n msb n lsb n counter bits last data bit in (bit no. 16) first data bit in (bit no. 1) enb latch enable input (pdip pin 12, sog pin 13) when high (1), enb transfers the contents of the shift reg - ister into the latches, and to the programmable counter in - puts, and the switch outputs sw1 and sw2. when low (0), enb inhibits the above action and thus allows changes to be made in the shift register data without af fecting the counter programming and switch outputs. an onchip pullup esta - blishes a continuously high level for enb when no external signal is applied. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pdip pins 17, 16; sog pins 19, 18) these pins form an onchip reference oscillator when con - nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be connected f ro m o sc in t o g roun d a n d o sc out t o g round. osc in may also serve as the input for an externallygener - ated reference signal. this signal is typically ac coupled to osc in , b u t f o r l arge r a mplitud e s ignal s ( standar d c mos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out .
mc1451512 through mc1451582 motorola 11 output pins pd out phase detector a output (pdip, sog pin 6) threestate output of phase detector for use as loop error signal. doubleended outputs are also available for this pur- pose (see f v and f r ). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: highimped - ance state f r , f v phase detector b outputs (pdip, sog pins 4, 3) these phase detector outputs can be combined externally for a looperror signal. a singleended output is also avail - able for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v a nd f r r emai n h ig h e xcep t f o r a s mal l m inimu m t ime period when both pulse low in phase. ld lock detector output (pdip pin 8, sog pin 9) essentially a high level when loop is locked (f r , f v of same phase and frequency). ld pulses low when loop is out of lock. sw1, sw2 band switch outputs (pdip pins 13, 14; sog pins 14, 15) sw1 and sw2 provide latched opendrain outputs corre - sponding to data bits numbers one and two. these outputs can be tied through external resistors to voltages as high as 15 v , i ndependen t o f t h e v dd s uppl y v oltage . t hes e a re typically used for band switch functions. a logic 1 causes the output to assume a highimpedance state, while a logic 0 causes the output to be low. ref out buffered reference oscillator output (pdip, sog pin 15) buffered output of onchip reference oscillator or exter - nally provided referenceinput signal. power supply v dd positive power supply (pdip, sog pin 5) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pdip, sog pin 7) the m os t n egativ e s upply p otential . t hi s p i n i s u sually ground. typical applications figure 1. microprocessorcontrolled tv/catv tuning system with serial interface f in 3 led display mc14489 keyboard cmos mpu/mcu enb clk data 1/2 mc1458* mc1451552 mc12073/74 prescaler uhf/vhf tuner or catv front end 4.0 mhz f v f r + * the f r and f v outputs are fed to an external combiner/loop filter . see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter .
mc1451512 through mc1451582 motorola 12 figure 2. am/fm radio synthesizer to am/fm oscillators to display mc12019 20 prescaler am osc fm osc f in keyboard cmos mpu/mcu enb clk data 1/2 mc1458* mc1451552 2.56 mhz f v f r + * the f r and f v outputs are fed to an external combiner/loop filter . see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . mc1451552 data sheet continued on page 23
mc1451512 through mc1451582 motorola 13
! interfaces with dualmodulus prescalers th e m c145156 2 i s p rogramme d b y a c locked , s eria l i nput , 1 9bi t d ata stream. the device features consist of a reference oscillator , selectablerefer- ence d ivider , d igitalphas e d etector , 1 0bi t p rogrammabl e d ividebyn counter, 7 bi t p rogrammabl e d ivideby a c ounter , a n d t h e n ecessary s hift register and latch circuitry for accepting serial input data. the mc1451562 is an improvedperformance dropin replacement for the mc1451561. p owe r c onsumptio n h a s d ecrease d a nd e s d a n d l atchup performance have improved. ? operating temperature range: 40 to 85 c ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? on or offchip reference oscillator operation with buffered output ? compatible with the serial peripheral interface (spi) on cmos mcus ? lock detect signal ? two opendrain switch outputs ? dual modulus/serial programming ? 8 userselectable r v alues: 8, 64, 128, 256, 640, 1000, 1024, 2048 ? n range = 3 to 1023, a range = 0 to 127 ? alinearizedo digital phase detector enhances transfer function linearity ? two error signal options: singleended (threestate) or doubleended ? chip complexity: 6504 fets or 1626 equivalent gates semiconductor technical data p suffix plastic dip case 738 dw suffix sog package case 751d ordering information mc145156p2 plastic dip mc145156dw2 sog package pin assignment pd out f r f v ra2 ra1 f in ld mc v ss v dd 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 test ref out osc out osc in ra0 clk data enb sw1 sw2 1 20 1 20 ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 14 12 x 8 rom reference decoder f v f r 12bit r counter phase detector b phase detector a lock detect ld pd out f in v dd osc in osc out enb 12 10 sw2 sw1 f r f v latch data 2bit shift register clk 10 ref out 10bit shift register 7bit shift register a counter latch n counter latch 7bit a counter 10bit n counter control logic mc 7 7 mc1451562 block diagram ra2 ra0 ra1 pin descriptions input pins f in frequency input (pin 10) input to the positive edge triggered n and a counters. f in is typically derived from a dualmodulus prescaler and is ac c ouple d i nt o t h e d evice . f o r l arge r a mplitud e s ignals (standard cmos logic levels), dc coupling may be used. ra0, ra1, ra2 reference address inputs (pins 20, 1, 2) these three inputs establish a code defining one of eight possible d ivid e v alue s f or t h e t ota l r eferenc e d ivider , a s defined by the table below: reference address code total divide value ra2 ra1 ra0 divide value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 640 1000 1024 2048 clk, data shift register clock, serial data inputs (pins 11, 12) each lowtohigh transition clocks one bit into the onchip 19bit shift register . the data input provides programming in - formation for the 10bit n counter , the 7bit a counter , and the two switch signals sw1 and sw2. the entry format is as follows: sw2 sw1 n msb a lsb n counter bits last data bit in (bit no. 19) first data bit in (bit no. 1) a counter bits n lsb a msb enb latch enable input (pin 13) when high (1), enb transfers the contents of the shift reg - ister into the latches, and to the programmable counter in - puts, and the switch outputs sw1 and sw2. when low (0), enb inhibits the above action and thus allows changes to be made in the shift register data without af fecting the counter programming and switch outputs. an onchip pullup esta - blishes a continuously high level for enb when no external signal is applied. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pins 19, 18) these pins form an onchip reference oscillator when con - nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be connected f ro m o sc in t o g roun d a n d o sc out t o g round. osc in may also serve as the input for an externallygener - ated reference signal. this signal is typically ac coupled to osc in , b u t f or l arge r a mplitud e s ignal s ( standar d c mos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . test factory test input (pin 16) used in manufacturing. must be left open or tied to v ss .
mc1451512 through mc1451582 motorola 15 output pins pd out phase detector a output (pin 6) threestate output of phase detector for use as looperror signal. doubleended outputs are also available for this pur- pose (see f v and f r ). frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: highimped - ance state f r , f v phase detector b outputs (pins 4, 3) these phase detector outputs can be combined externally for a looperror signal. a singleended output is also avail - able for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v a nd f r r emai n h ig h e xcep t f o r a s mal l m inimu m t ime period when both pulse low in phase. mc dualmodulus prescale control output (pin 8) signal generated by the onchip control logic circuitry for controlling a n e xterna l d ualmodulu s p rescaler . t h e m c level will be low at the beginning of a count cycle and will remain low until the a counter has counted down from its programmed value. at this time, mc goes high and remains high until the n counter has counted the rest of the way down from its programmed value (n a additional counts since both n and a are counting down during the first por - tion o f t he c ycle) . m c i s t he n s e t b ac k l ow , t h e c ounters preset to their respective programmed values, and the above sequence repeated. this provides for a total programmable divide value (n t ) = n p + a where p and p + 1 represent the dualmodulus prescaler divide values respectively for high and low mc levels, n the number programmed into the n counter, and a the number programmed into the a counter. ld lock detector output (pin 9) essentially a high level when loop is locked (f r , f v of same phase and frequency). ld pulses low when loop is out of lock. sw1, sw2 band switch outputs (pins 14, 15) sw1 and sw2 provide latched opendrain outputs corre - sponding to data bits numbers one and two. these outputs can be tied through external resistors to voltages as high as 15 v , i ndependen t o f t h e v dd s uppl y v oltage . t hes e a re typically used for band switch functions. a logic 1 causes the output to assume a highimpedance state, while a logic 0 causes the output to be low. ref out buffered reference oscillator output (pin 17) buffered output of onchip reference oscillator or exter - nally provided referenceinput signal. power supply v dd positive power supply (pin 5) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 7) the m os t n egativ e s upply p otential . t hi s p i n i s u sually ground.
mc1451512 through mc1451582 motorola 16 typical applications figure 1. am/fm radio broadcast synthesizer sw2 sw1 f v f r pd out mc f in enb data clk ref out v ss v dd ld ra0 ra1 ra2 osc in osc out notes 1 and 2 optional loop error signal mc12019 20/21 dual modulus prescaler vco am b + + 12 v fm b + + 12 v lock detect signal to display driver (e.g., mc14489) cmos mpu/mcu key board + v 3.2 mhz mc1451562 1/2 mc1458 note 3 + notes: 1. for am: channel spacing = 5 khz, r = 640 (code 100). 2. for fm: channel spacing = 25 khz, r = 128 (code 010). 3. the f r and f v outputs are fed to an external combiner/loop filter . see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . figure 2. avionics navigation or communication synthesizer nav = 01 com = 10 channel selection vco lock detect signal to display driver (e.g., mc14489) cmos mpu/mcu + v 3.2 mhz (note 3) mc1451562 mc33171 note 5 sw2 sw1 f v f r pd out mc f in enb data clk ref out v ss v dd ld ra0 ra1 ra2 osc in osc out mc12016 (notes 2 and 4) 40/41 dual modulus prescaler + vco range nav: 97.300 107.250 mhz comt: 118.000 135.975 mhz comr: 139.400 157.375 mhz r/t notes: 1. for nav: f r = 50 khz, r = 64 using 10.7 mhz lowside injection, n total = 1946 2145. for comt: f r = 25 khz, r = 128, n total = 4720 5439. for comr: f r = 25 khz, r = 128, using 21.4 mhz highside injection, n total = 5576 6295. 2. a 32/33 dual modulus approach is provided by substituting an mc12015 for the mc12016. the devices are pin equivalent. 3. a 6.4 mhz oscillator crystal can be used by selecting r = 128 (code 010) for nav and r = 256 (code 011) for com. 4. mc12013 + mc10131 combination may also be used to form the 40/41 prescaler. 5. the f r and f v outputs are fed to an external combiner/loop filter . see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . mc1451562 data sheet continued on page 23
mc1451512 through mc1451582 motorola 17
! interfaces with singlemodulus prescalers the mc1451572 has a fully programmable 14bit reference counter , as well as a fully programmable n counter . the counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. the mc1451572 is an improvedperformance dropin replacement for the mc1451571. p owe r c onsumptio n h a s d ecrease d a nd e s d a n d l atchup performance have improved. ? operating temperature range: 40 to 85 c ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? fully programmable reference and n counters ? r range = 3 to 16383 ? n range = 3 to 16383 ? f v and f r outputs ? lock detect signal ? compatible with the serial peripheral interface (spi) on cmos mcus ? alinearizedo digital phase detector ? singleended (threestate) or doubleended phase detector outputs ? chip complexity: 6504 fets or 1626 equivalent gates semiconductor technical data p suffix plastic dip case 648 dw suffix sog package case 751g ordering information mc145157p2 plastic dip mc145157dw2 sog package pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 s/r out f r ref out f v f r clk data enb v dd f v osc out osc in f in ld v ss pd out 1 16 1 16 ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 18 14bit shift register 14bit n counter f v mc1451572 block diagram f r reference counter latch phase detector b phase detector a lock detect ld pd out f in osc in osc out enb 14 14 14bit shift register data clk 14 ref out n counter latch 14bit r counter 14 s/r out f r f v 1bit control s/r pin descriptions input pins f in frequency input (pin 8) input frequency from vco output. a rising edge signal on this i nput d ecrement s t he n c ounter . t hi s i npu t h a s a n inverte r b iase d i n t h e l inea r r egio n t o a llo w u se w ith a c coupled signals as low as 500 mv pp. for larger amplitude signals (standard cmos logic levels), dc coupling may be used. clk, data shift clock, serial data inputs (pins 9, 10) each lowtohigh transition of the clock shifts one bit of data into the onchip shift registers. the last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the n counter latch. the entry format is as follows: lsb msb control first data bit into shift register enb latch enable input (pin 11) a logic high on this pin latches the data from the shift regis - ter into the reference divider or n latches depending on the control bit. the reference divider latches are activated if the control bit is at a logic high and the n latches are activated if the control bit is at a logic low . a logic low on this pin allows the u se r t o c hang e t h e d at a i n t h e s hif t r egister s w ithout af fecting the counters. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pins 1, 2) these pins form an onchip reference oscillator when con - nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be connected from o sc in to ground and o sc out to ground. osc in may also serve as the input for an externallygener- ated reference signal. this signal is typically ac coupled to osc in , b u t f or l arge r a mplitud e s ignal s ( standar d c mos logic levels) dc coupling may also be used. in the external reference mode, no connection is required to osc out . output pins pd out singleended phase detector a output (pin 5) this s ingleende d ( threestate ) p has e d etecto r o utput produces a looperror signal that is used with a loop filter to control a vco. frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: highimped - ance state f r , f v doubleended phase detector b outputs (pins 16, 15) these outputs can be combined externally for a looperror signal. a singleended output is also available for this pur - pose (see pd out ).
mc1451512 through mc1451582 motorola 19 if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v a nd f r r emai n h ig h e xcep t f o r a s mal l m inimu m t ime period when both pulse low in phase. f r , f v r counter output, n counter output (pins 13, 3) buffered, divided reference and f in frequency outputs. the f r and f v outputs are connected internally to the r and n counter o utput s r espectively , a llowin g t h e c ounter s t o b e used independently , as well as monitoring the phase detector inputs. ld lock detector output (pin 7) this output is essentially at a high level when the loop is locked (f r , f v of same phase and frequency), and pulses low when loop is out of lock. ref out buffered reference oscillator output (pin 14) this output can be used as a second local oscillator , refer- ence oscillator to another frequency synthesizer , or as the system clock to a microprocessor controller. s/r out shift register output (pin 12) this output can be connected to an external shift register to provide band switching, control information, and counter programming code checking. power supply v dd positive power supply (pin 4) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 6) the m os t n egativ e s upply p otential . t hi s p i n i s u sually ground. mc1451572 data sheet continued on page 23
mc1451512 through mc1451582 motorola 20
! interfaces with dualmodulus prescalers the mc1451582 has a fully programmable 14bit reference counter , as well as fully programmable n and a counters. the counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. the mc1451582 is an improvedperformance dropin replacement for the mc1451581. p owe r c onsumptio n h a s d ecrease d a nd e s d a n d l atchup performance have improved. ? operating temperature range: 40 to 85 c ? low power consumption through use of cmos technology ? 3.0 to 9.0 v supply range ? fully programmable reference and n counters ? r range = 3 to 16383 ? n range = 3 to 1023 ? dual modulus capability; a range = 0 to 127 ? f v and f r outputs ? lock detect signal ? compatible with the serial peripheral interface (spi) on cmos mcus ? alinearizedo digital phase detector ? singleended (threestate) or doubleended phase detector outputs ? chip complexity: 6504 fets or 1626 equivalent gates semiconductor technical data p suffix plastic dip case 648 dw suffix sog package case 751g ordering information mc145158p2 plastic dip mc145158dw2 sog package pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 mc f r ref out f v f r clk data enb v dd f v osc out osc in f in ld v ss pd out 1 16 1 16 ? motorola, inc. 1995 rev 1 8/95
mc1451512 through mc1451582 motorola 21 14bit shift register 7bit a counter f v mc1451582 block diagram f r reference counter latch phase detector b phase detector a lock detect ld pd out f in osc in osc out enb 14 10 7bit s/r data clk 10 ref out a counter latch 14bit r counter 14 mc f r f v 1bit control s/r 10bit s/r n counter latch 10bit n counter control logic 7 7 pin descriptions input pins f in frequency input (pin 8) input frequency from vco output. a rising edge signal on this input decrements the a and n counters. this input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mv pp. for larger ampli - tude signals (standard cmos logic levels), dc coupling may be used. clk, data shift clock, serial data inputs (pins 9, 10) each lowtohigh transition of the clk shifts one bit of data into the onchip shift registers. the last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the a, n counter latch. the data entry format is as follows: lsb msb control first data bit into shift register r msb control n first data bit into shift register a lsb msb lsb enb latch enable input (pin 11) a logic high on this pin latches the data from the shift regis - ter into the reference divider or n, a latches depending on the control bit. the reference divider latches are activated if the control bit is at a logic high and the n, a latches are activated if the control bit is at a logic low. a logic low on this pin allows the user to change the data in the shift registers without af fecting the counters. enb is normally low and is pulsed high to transfer data to the latches. osc in , osc out reference oscillator input/output (pins 1, 2) these pins form an onchip reference oscillator when con - nected to terminals of an external parallel resonant crystal. frequency setting capacitors of appropriate value must be connected from o sc in to ground and o sc out to ground. osc in may also serve as the input for an externallygener- ated reference signal. this signal is typically ac coupled to osc in , but for larger amplitude signals (standard cmos log - ic levels) dc coupling may also be used. in the external refer - ence mode, no connection is required to osc out .
mc1451512 through mc1451582 motorola 22 output pins pd out phase detector a output (pin 5) this s ingleende d ( threestate ) p has e d etecto r o utput produces a looperror signal that is used with a loop filter to control a vco. frequency f v > f r or f v leading: negative pulses frequency f v < f r or f v lagging: positive pulses frequency f v = f r and phase coincidence: highimped - ance state f r , f v phase detector b outputs (pins 16, 15) doubleended phase detector outputs. these outputs can be c ombine d e xternall y f o r a l ooperro r s ignal . a s ingle ended output is also available for this purpose (see pd out ). if frequency f v is greater than f r or if the phase of f v is leading, then error information is provided by f v pulsing low. f r remains essentially high. if the frequency f v is less than f r or if the phase of f v is lagging, then error information is provided by f r pulsing low. f v remains essentially high. if the frequency of f v = f r and both are in phase, then both f v a nd f r r emai n h ig h e xcep t f o r a s mal l m inimu m t ime period when both pulse low in phase. mc dualmodulus prescale control output (pin 12) this output generates a signal by the onchip control logic circuitry for controlling an external dualmodulus prescaler . the mc level is low at the beginning of a count cycle and remains low until the a counter has counted down from its programmed value. at this time, mc goes high and remains high until the n counter has counted the rest of the way down from its programmed value (n a additional counts since both n and a are counting down during the first por - tion of the cycle). mc is then set back low , the counters pre- set to their respective programmed values, and the above sequence repeated. this provides for a total programmable divide value (n t ) = n p + a where p and p + 1 represent the dualmodulus prescaler divide values respectively for high and low modulus control levels, n the number programmed into the n counter , and a the number programmed into the a counter . note that when a prescaler is needed, the dual modulus v ersio n o ffers a d istinc t a dvantage . t h e d ual modulus prescaler allows a higher reference frequency at the phase detector input, increasing system performance ca - pability, and simplifying the loop filter design. f r , f v r counter output, n counter output (pins 13, 3) buffered, divided reference and f in frequency outputs. the f r and f v outputs are connected internally to the r and n counter outputs respectively, allowing the counters to be used independently , as well as monitoring the phase detector inputs. ld lock detector output (pin 7) this output is essentially at a high level when the loop is locked (f r , f v of same phase and frequency), and pulses low when loop is out of lock. ref out buffered reference oscillator output (pin 14) this output can be used as a second local oscillator , refer- ence oscillator to another frequency synthesizer , or as the system clock to a microprocessor controller. power supply v dd positive power supply (pin 4) the positive power supply potential. this pin may range from + 3 to + 9 v with respect to v ss . v ss negative power supply (pin 6) the m os t n egativ e s upply p otential . t hi s p i n i s u sually ground.
mc1451512 through mc1451582 motorola 23 mc14515x2 famil y characteristics and descriptions maximum ratings* (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage 0.5 to + 10.0 v v in , v out input or output voltage (dc or transient) except sw1, sw2 0.5 to v dd + 0.5 v v out output voltage (dc or transient), sw1, sw2 (r pullup = 4.7 k w ) 0.5 to + 15 v i in , i out input or output current (dc or transient), per pin 10 ma i dd , i ss supply current, v dd or v ss pins 30 ma p d power dissipation, per package2 500 mw t stg storage temperature 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur . functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. 2power dissipation temperature derating: plastic dip: 12 mw/ c from 65 to 85 c sog package: 7 mw/ c from 65 to 85 c electrical characteristics (voltages referenced to v ss ) symbol parameter test condition v dd v 40 c 25 c 85 c unit symbol parameter test condition v dd v min max min max min max unit v dd power supply voltage range e 3 9 3 9 3 9 v i ss dynamic supply current f in = osc in = 10 mhz, 1 v pp ac coupled sine wave r = 128, a = 32, n = 128 3 5 9 e e e 3.5 10 30 e e e 3 7.5 24 e e e 3 7.5 24 ma i ss quiescent supply current (not including pullup current component) v in = v dd or v ss i out = 0 m a 3 5 9 e e e 800 1200 1600 e e e 800 1200 1600 e e e 1600 2400 3200 m a v in input voltage e f in , osc in input ac coupled sine wave e 500 e 500 e 500 e mv pp v il lowlevel input voltage e f in , osc in v out 2.1 v input dc v out 3.5 v coupled v out 6.3 v square wave 3 5 9 e e e 0 0 0 e e e 0 0 0 e e e 0 0 0 v v ih highlevel input voltage e f in , osc in v out 0.9 v input dc v out 1.5 v coupled v out 2.7 v square wave 3 5 9 3.0 5.0 9.0 e e e 3.0 5.0 9.0 e e e 3.0 5.0 9.0 e e e v v il lowlevel input voltage e except f in , osc in 3 5 9 e e e 0.9 1.5 2.7 e e e 0.9 1.5 2.7 e e e 0.9 1.5 2.7 v v ih highlevel input voltage e except f in , osc in 3 5 9 2.1 3.5 6.3 e e e 2.1 3.5 6.3 e e e 2.1 3.5 6.3 e e e v i in input current (f in , osc in ) v in = v dd or v ss 9 2 50 2 25 2 22 m a i il input leakage current (data, clk, enb e without pullups) v in = v ss 9 e 0.3 e 0.1 e 1.0 m a i ih input leakage current (all inputs except f in , osc in ) v in = v dd 9 e 0.3 e 0.1 e 1.0 m a (continued) these devices contain protection circuitry to protect against damage due to high static voltages or electric fields. however , precau - tions must be taken to avoid applications of any voltage higher than maximum rated voltages to these highimpedance circuits. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd except for sw1 and sw2. sw1 and sw2 can be tied through external resistors to voltages as high as 15 v , indepen - dent of the supply voltage. unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ), except for inputs with pullup devices. unused outputs must be left open.
mc1451512 through mc1451582 motorola 24 dc electrical characteristics (continued) symbol parameter test condition v dd v 40 c 25 c 85 c unit symbol parameter test condition v dd v min max min max min max unit i il pullup current (all inputs with pullups) v in = v ss 9 20 400 20 200 20 170 m a c in input capacitance e e 10 e 10 e 10 pf v ol lowlevel output voltage e osc out i out 0 m a v in = v dd 3 5 9 e e e 0.9 1.5 2.7 e e e 0.9 1.5 2.7 e e e 0.9 1.5 2.7 v v oh highlevel output voltage e osc out i out 0 m a v in = v ss 3 5 9 2.1 3.5 6.3 e e e 2.1 3.5 6.3 e e e 2.1 3.5 6.3 e e e v v ol lowlevel output voltage e other outputs i out 0 m a 3 5 9 e e e 0.05 0.05 0.05 e e e 0.05 0.05 0.05 e e e 0.05 0.05 0.05 v v oh highlevel output voltage e other outputs i out 0 m a 3 5 9 2.95 4.95 8.95 e e e 2.95 4.95 8.95 e e e 2.95 4.95 8.95 e e e v v (br)dss draintosource breakdown voltage e sw1, sw2 r pullup = 4.7 k w e 15 e 15 e 15 e v i ol lowlevel sinking current e mc v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 1.30 1.90 3.80 e e e 1.10 1.70 3.30 e e e 0.66 1.08 2.10 e e e ma i oh highlevel sourcing current e mc v out = 2.7 v v out = 4.6 v v out = 8.5 v 3 5 9 0.60 0.90 1.50 e e e 0.50 0.75 1.25 e e e 0.30 0.50 0.80 e e e ma i ol lowlevel sinking current e ld v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 0.25 0.64 1.30 e e e 0.20 0.51 1.00 e e e 0.15 0.36 0.70 e e e ma i oh highlevel sourcing current e ld v out = 2.7 v v out = 4.6 v v out = 8.5 v 3 5 9 0.25 0.64 1.30 e e e 0.20 0.51 1.00 e e e 0.15 0.36 0.70 e e e ma i ol lowlevel sinking current e sw1, sw2 v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 0.80 1.50 3.50 e e e 0.48 0.90 2.10 e e e 0.24 0.45 1.05 e e e ma i ol lowlevel sinking current e other outputs v out = 0.3 v v out = 0.4 v v out = 0.5 v 3 5 9 0.44 0.64 1.30 e e e 0.35 0.51 1.00 e e e 0.22 0.36 0.70 e e e ma i oh highlevel sourcing current e other outputs v out = 2.7 v v out = 4.6 v v out = 8.5 v 3 5 9 0.44 0.64 1.30 e e e 0.35 0.51 1.00 e e e 0.22 0.36 0.70 e e e ma i oz output leakage current e pd out v out = v dd or v ss output in off state 9 e 0.3 e 0.1 e 1.0 m a i oz output leakage current e sw1, sw2 v out = v dd or v ss output in off state 9 e 0.3 e 0.1 e 3.0 m a c out output capacitance e pd out pd out e threestate e e 10 e 10 e 10 pf
mc1451512 through mc1451582 motorola 25 ac electrical characteristics (c l = 50 pf, input t r = t f = 10 ns) symbol parameter v dd v guaranteed limit 25 c guaranteed limit 40 to 85 c unit t plh , t phl maximum propagation delay, f in to mc (figures 1 and 4) 3 5 9 110 60 35 120 70 40 ns t phl maximum propagation delay, enb to sw1, sw2 (figures 1 and 5) 3 5 9 160 80 50 180 95 60 ns t w output pulse width, f r , f v , and ld with f r in phase with f v (figures 2 and 4) 3 5 9 25 to 200 20 to 100 10 to 70 25 to 260 20 to 125 10 to 80 ns t tlh maximum output transition time, mc (figures 3 and 4) 3 5 9 115 60 40 115 75 60 ns t thl maximum output transition time, mc (figures 3 and 4) 3 5 9 60 34 30 70 45 38 ns t tlh , t thl maximum output transition time, ld (figures 3 and 4) 3 5 9 180 90 70 200 120 90 ns t tlh , t thl maximum output transition time, other outputs (figures 3 and 4) 3 5 9 160 80 60 175 100 65 ns switching waveforms test point device under test c l * * includes all probe and fixture capacitance. test point device under test c l * * includes all probe and fixture capacitance. v dd 15 k w t tlh 90% 10% t thl any output figure 1. figure 2. 50% output 50% input t plh e v ss v dd t phl 50% f r , f v , ld* * f r in phase with f v . t w output output figure 3. figure 4. test circuit figure 5. test circuit
mc1451512 through mc1451582 motorola 26 timing requirements (input t r = t f = 10 ns unless otherwise indicated) symbol parameter v dd v guaranteed limit 25 c guaranteed limit 40 to 85 c unit f clk serial data clock frequency, assuming 25% duty cycle note: refer to clk t w(h) below (figure 6) 3 5 9 dc to 5.0 dc to 7.1 dc to 10 dc to 3.5 dc to 7.1 dc to 10 mhz t su minimum setup time, data to clk (figure 7) 3 5 9 30 20 18 30 20 18 ns t h minimum hold time, clk to data (figure 7) 3 5 9 40 20 15 40 20 15 ns t su minimum setup time, clk to enb (figure 7) 3 5 9 70 32 25 70 32 25 ns t rec minimum recovery time, enb to clk (figure 7) 3 5 9 5 10 20 5 10 20 ns t w(h) minimum pulse width, clk and enb (figure 6) 3 5 9 50 35 25 70 35 25 ns t r , t f maximum input rise and fall times e any input (figure 8) 3 5 9 5 4 2 5 4 2 m s switching waveforms figure 6. figure 7. v ss e v dd 50% 50% last clk previous data latched first clk enb clk data 50% e v dd v ss e v dd v ss e v dd v ss t su t su t rec t h 50% clk, enb t w(h) e v dd v ss 4 f clk 1 * *assumes 25% duty cycle. t t 90% 10% t f any output figure 8.
mc1451512 through mc1451582 motorola 27 frequency characteristics (voltages references to v ss , c l = 50 pf, input t r = t f =10 ns unless otherwise indicated) symbol parameter test condition v dd v 40 c 25 c 85 c unit symbol parameter test condition v dd v min max min max min max unit f i input frequency (f in , osc in ) r 8, a 0, n 8 v in = 500 mv pp ac coupled sine wave 3 5 9 e e e 6 15 15 e e e 6 15 15 e e e 6 15 15 mhz r 8, a 0, n 8 v in = 1 v pp ac coupled sine wave 3 5 9 e e e 12 22 25 e e e 12 20 22 e e e 7 20 22 mhz r 8, a 0, n 8 v in = v dd to v ss dc coupled square wave 3 5 9 e e e 13 25 25 e e e 12 22 25 e e e 8 22 25 mhz note: usually, the pll ' s propagation delay from f in to mc plus the setup time of the prescaler determines the upper frequency limit of the system. the upper frequency limit is found with the following formula: f = p / (t p + t set ) where f is the upper frequency in hz, p is the lower of the dual modulus prescaler ratios, t p is the f in to mc propagation delay in seconds, and t set is the prescaler setup time in seconds. for example, with a 5 v supply , the f in to mc delay is 70 ns. if the mc12028a prescaler is used, the setup time is 16 ns. thus, if the 64/65 ratio is utilized, the upper frequency limit is f = p / (t p + t set ) = 64/(70 + 16) = 744 mhz. v h = high voltage level. v l = low voltage level. * at this point, when both f r and f v are in phase, the output is forced to near midsupply . note: the pd out generates error pulses during outoflock conditions. when locked in phase and frequency the output is high and the voltage at this pin is determined by the lowpass filter capacitor . f r reference osc r f v feedback (f in n) pd out f r f v ld * v h v l v h v l v h high impedance v h v l v h v l v h v l v l figure 9. phase detector/lock detector output waveforms
mc1451512 through mc1451582 motorola 28 design considerations phaselocked loop e lowpass filter design c) _ + a c r 2 c vco c vco r 2 b) a) c vco pd out pd out f r e f v e pd out e f r f v r 1 r 1 r 1 r 1 r 2 note: sometimes r 1 is split into two series resistors, each r 1 2. a capacitor c c is then placed from the midpoint to ground to further filter f v and f r . the value of c c should be such that the corner frequency of this network does not significantly af fect w n . the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter . definitions: n = t otal division ratio in feedback loop k f (phase detector gain) = v dd / 4 p for pd out k f (phase detector gain) = v dd /2 p for f v and f r k vco (vco gain) = 2 pd f vco d v vco for a typical design w n (natural frequency) 2 p fr 10 (at phase detector input). damping factor: z @ 1 recommended reading: gardner, floyd m., phaselock techniques (second edition). new york, wileyinterscience, 1979. manassewitsch, vadim, frequency synthesizers: theory and design (second edition). new york, wileyinterscience, 1980. blanchard, alain, phaselocked loops: application to coherent receiver design. new york, wileyinterscience, 1976. egan, william f., frequency synthesis by phase lock. new york, wileyinterscience, 1981. rohde, ulrich l., digital pll frequency synthesizers theory and design. englewood cliffs, nj, prenticehall, 1983. berlin, howard m., design of phaselocked loop circuits, with experiments. indianapolis, howard w. sams and co., 1978. kinley, harold, the pll synthesizer cookbook. blue ridge summit, pa, tab books, 1980. an535, phaselocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phaselocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 1987. f r e f v e f(s) = assuming gain a is very large, then: f(s) = z = w n = nr 1 c r 1 sc + 1 w n = z = w n r 2 c 2 r 2 sc + 1 r 1 sc 1 n w n 2k f k vco f(s) = z = w n = (r 1 + r 2 )sc + 1 r 2 sc + 1 nc(r 1 + r 2 ) r 2 c + n k f k vco k f k vco ncr 1 0.5 w n k f k vco k f k vco
mc1451512 through mc1451582 motorola 29 crystal oscillator considerations the following options may be considered to provide a ref - erence f requenc y t o m otorola' s c mo s f requenc y s ynthe- sizers. use of a hybrid crystal oscillator commercially available temperaturecompensated crystal oscillators (tcxos) or crystalcontrolled data clock oscilla - tors provide very stable reference frequencies. an oscillator capable of sinking and sourcing 50 m a at cmos logic levels may be direct or dc coupled to osc in . in general, the highest frequency c apability i s o btaine d u tilizin g a d irectcoupled square w av e h avin g a r ailtorai l ( v dd t o v ss ) v oltage swing. if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to osc in may be used. osc out , an unbuffered output, should be left floating. for additional information about tcxos and data clock oscillators, please consult the latest version of the eem elec- tronic engineers master catalog, the gold book, or similar publications. design an offchip reference the user may design an of fchip crystal oscillator using ics specifically developed for crystal oscillator applications, such as the mc12061 mecl device. the reference signal from the mecl device is ac coupled to osc in . for large am - plitude signals (standard cmos logic levels), dc coupling is used. osc out , an unbuf fered output, should be left floating. in general, the highest frequency capability is obtained with a directcoupled s quar e w av e h avin g r ailtorai l v oltage swing. use of the onchip oscillator circuitry the onchip amplifier (a digital inverter) along with an ap - propriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the d esire d o perating f requency , s houl d b e c onnecte d a s shown in figure 10. figure 10. pierce crystal oscillator circuit r1* c2 c1 frequency synthesizer osc out osc in * may be deleted in certain cases. see text. r f for v dd = 5.0 v , the crystal should be specified for a load - ing capacitance, c l , which does not exceed 32 pf for fre - quencies to approximately 8.0 mhz, 20 pf for frequencies in the area of 8.0 to 15 mhz, and 10 pf for higher frequencies. these are guidelines that provide a reasonable compromise between ic capacitance, drive capability , swamping varia - tions in stray and ic input/output capacitance, and realistic c l v alues . t h e s hun t l oa d c apacitance , c l , p resented across the crystal can be estimated to be: c l = c in c out c in + c out + c a + c o + c1 ? c2 c1 + c2 where c in = 5 pf (see figure 11) c out = 6 pf (see figure 11) c a = 1 pf (see figure 11) c o = the crystal's holder capacitance (see figure 12) c1 and c2 = external capacitors (see figure 10) figure 11. parasitic capacitances of the amplifier c in c out c a figure 12. equivalent crystal networks note: values are supplied by crystal manufacturer (parallel resonant crystal). 2 1 2 1 2 1 r s l s c s r e x e c o the oscillator can be atrimmedo onfrequency by making a portion or all of c1 variable. the crystal and associated com - ponents must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray i nductance , a n d s tartu p s tabilizatio n t ime . i n s ome cases, stray capacitance should be added to the value for c in and c out . power is dissipated in the ef fective series resistance of the crystal, r e , in figure 12. the drive level specified by the crys - tal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency . r1 in figure 10 limits the drive level. the use of r1 may not be necessary in some cases (i.e., r1 = 0 w ). to verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a func - tion of voltage at osc out . (care should be taken to minimize loading.) the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal will de- crease in frequency or become unstable with an increase in supply v oltage . t h e o peratin g s uppl y v oltag e m us t b e r e- duced or r1 must be increased in value if the overdriven condition e xists . t h e u se r s houl d n ot e t ha t t h e o scillator startup time is proportional to the value of r1. through t he p roces s o f s upplyin g c rystal s f o r u s e w ith cmo s i nverters , m an y c rystal m anufacturer s h av e d evel- oped expertise in cmos oscillator design with crystals. dis - cussions w it h s uc h m anufacturer s c an p rov e v er y h elpful (see table 1).
mc1451512 through mc1451582 motorola 30 table 1. partial list of crystal manufacturers name address phone united states crystal corp. crystek crystal statek corp. 3605 mccart ave., ft. worth, tx 76110 2351 crystal dr., ft. myers, fl 33907 512 n. main st., orange, ca 92668 (817) 9213013 (813) 9362109 (714) 6397810 note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. recommended reading technical note tn24, statek corp. technical note tn7, statek corp. e. hafner , athe piezoelectric crystal unit definitions and method of measuremento, proc. ieee, v ol. 57, no. 2 feb., 1969. d. k emper , l . r osine , a quart z c rystal s f o r f requency controlo, electrotechnology , june, 1969. p. j. ottowitz, aa guide to crystal selectiono, electronic design , may, 1966. dualmodulus prescaling overview the technique of dualmodulus prescaling is well estab - lished as a method of achieving high performance frequency synthesizer o peratio n a t h ig h f requencies . b asically , t he approach a llow s r elativel y l owfrequenc y p rogrammable counters t o b e u se d a s h ighfrequenc y p rogrammable counters with speed capability of several hundred mhz. this is possible without the sacrifice in system resolution and per - formance that results if a fixed (singlemodulus) divider is used for the prescaler. in d ualmodulu s p rescaling , t h e l owe r s pee d c ounters must be uniquely configured. special control logic is neces - sary to select the divide value p or p + 1 in the prescaler for the required amount of time (see modulus control definition). motorola's d ualmodulu s f requenc y s ynthesizers c ontain this feature and can be used with a variety of dualmodulus prescalers to allow speed, complexity and cost to be tailored to the system requirements. prescalers having p , p + 1 di - vide values in the range of 3/ 4 to 128/ 129 can be con - trolled by most motorola frequency synthesizers. several dualmodulus prescaler approaches suitable for use with the mc1451522, mc1451562, or mc1451582 are: mc12009 mc12011 mc12013 mc12015 mc12016 mc12017 mc12018 mc12022a mc12032a 5/ 6 8/ 9 10/ 11 32/ 33 40/ 41 64/ 65 128/ 129 64/65 or 128/129 64/65 or 128/129 440 mhz 500 mhz 500 mhz 225 mhz 225 mhz 225 mhz 520 mhz 1.1 ghz 2.0 ghz design guidelines the system total divide value, n total (n t ) will be dictated by the application: n t = frequency into the prescaler frequency into the phase detector = n p + a n is the number programmed into the n counter, a is the number programmed into the a counter , p and p + 1 are the two selectable divide ratios available in the dualmodu - lus prescalers. t o have a range of n t values in sequence, the a counter is programmed from zero through p 1 for a particular value n in the n counter. n is then incremented to n + 1 and the a is sequenced from 0 through p 1 again. there a r e m inimu m a n d m aximu m v alue s t ha t c a n b e achieved for n t . these values are a function of p and the size of the n and a counters. the constraint n a always applies. if a max = p 1, then n min p 1. then n tmin = (p 1) p + a or (p 1) p since a is free to assume the value of 0. n tmax = n max p + a max to maximize system frequency capability, the dualmodu- lus p rescale r o utpu t m us t g o f rom l o w t o h ig h a fte r e ach group of p or p + 1 input cycles. the prescaler should divide by p when its modulus control line is high and by p + 1 when its mc is low. for the maximum frequency into the prescaler (f vcomax ), the value used for p must be large enough such that: 1. f vcomax divided by p may not exceed the frequency capability of f in (input to the n and a counters). 2. the period of f vco divided by p must be greater than the sum of the times: a. propagation delay through the dualmodulus pre - scaler. b. prescaler setup or release time relative to its mc signal. c. propagation time from f in to the mc output for the frequency synthesizer device. a s ometime s u sefu l s implificatio n i n t h e p rogramming code can be achieved by choosing the values for p of 8, 16, 32, or 64. for these cases, the desired value of n t results when n t in binary is used as the program code to the n and a counters treated in the following manner: 1. assume the a counter contains aao bits where 2 a p. 2. always program all higher order a counter bits above aao to 0. 3. assume the n counter and the a counter (with all the higher order bits above aao ignored) combined into a single binary counter of n + a bits in length (n = number of divider stages in the n counter). the msb of this ahy - potheticalo counter is to correspond to the msb of n and the lsb is to correspond to the lsb of a. the system divide value, n t , now results when the value of n t in binary is used to program the anewo n + a bit counter. by using the two devices, several dualmodulus values are achievable (shown in figure 13).
mc1451512 through mc1451582 motorola 31 mc device b device a device b mc12009 mc12011 mc12013 device a mc10131 mc10138 mc10154 20/ 21 50/ 51 40/ 41 or 80/ 81 64/ 65 or 128/ 129 32/ 33 80/ 81 40/ 41 100/ 101 80/ 81 note: mc12009, mc1201 1, and mc12013 are pin equivalent. mc12015, mc12016, and mc12017 are pin equivalent. figure 13. dualmodulus values
mc1451512 through mc1451582 motorola 32 package dimensions p suffix plastic dip case 64808 (mc1451572, mc145158d) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 1 8 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 p suffix plastic dip case 70702 (mc1451552) min min max max millimeters inches dim 22.22 6.10 3.56 0.36 1.27 1.02 0.20 2.92 23.24 6.60 4.57 0.56 1.78 1.52 0.30 3.43 0 0.51 0.875 0.240 0.140 0.014 0.050 0.040 0.008 0.115 0.915 0.260 0.180 0.022 0.070 0.060 0.012 0.135 15 1.02 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc 0 0.020 15 0.040 a b c d f g h j k l m n notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 9 10 18 b a h f g d seating plane n k m j l c
mc1451512 through mc1451582 motorola 33 p suffix plastic dip case 71002 (mc1451512, mc1451522) 0.100 bsc 0.600 bsc 2.54 bsc 15.24 bsc min min max max millimeters inches dim 36.45 13.72 3.94 0.36 1.02 1.65 0.20 2.92 0 0.51 37.21 14.22 5.08 0.56 1.52 2.16 0.38 3.43 15 1.02 1.435 0.540 0.155 0.014 0.040 0.065 0.008 0.115 0 0.020 1.465 0.560 0.200 0.022 0.060 0.085 0.015 0.135 15 0.040 a b c d f g h j k l m n notes: 1. positional tolerance of leads (d), shall be within 0.25mm (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 14 15 28 b a c n k m j d seating plane f h g l p suffix plastic dip case 73803 (mc1451562) 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e g f d 20 pl j 20 pl l m -t- seating plane 1 10 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b
mc1451512 through mc1451582 motorola 34 dw suffix sog package case 751d04 (mc1451552, mc1451562) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 dw suffix sog package case 751f04 (mc1451512, mc1451522) min min max max millimeters inches dim a b c d f g j k m p r 17.80 7.40 2.35 0.35 0.41 0.23 0.13 0 10.05 0.25 18.05 7.60 2.65 0.49 0.90 0.32 0.29 8 10.55 0.75 0.701 0.292 0.093 0.014 0.016 0.009 0.005 0 0.395 0.010 0.711 0.299 0.104 0.019 0.035 0.013 0.011 8 0.415 0.029 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. -a- -b- 1 14 15 28 -t- c seating plane 0.010 (0.25) b m m m j -t- k 26x g 28x d 14x p r x 45 f 0.010 (0.25) t a b m s s
mc1451512 through mc1451582 motorola 35 dw suffix sog package case 751g02 (mc1451572, mc1451582) dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k
mc1451512 through mc1451582 motorola 36 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 mc1451512/d
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