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mos integrated circuit pd703078y, 703079y, 70f3079y v850/sf1 tm 32-bit single-chip microcontrollers document no. u15183ej2v0ds00 (2nd edition) date published january 2002 n cp(k) printed in japan data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points. ? 2000, 2002 description the pd703078y, 703079y, and 70f3079y (v850/sf1) are 32-bit single-chip microcontrollers of the v850 series tm for av equipment. a 32-bit cpu, rom, ram, timer/counters, serial interfaces, an a/d converter, dma controller, and fcan controller are integrated on a single chip. the pd70f3079y has flash memory in place of the internal mask rom of the pd703078y and 703079y. because flash memory allows the program to be written and erased electrically with the device mounted on the board, these products are ideal for the evaluation stages of system development, small-scale production of a variety of products, and rapid development of new products. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. v850/sf1 hardware user?s manual: u14665e v850 series architecture user?s manual: u10243e features { number of instructions: 74 { minimum instruction execution time: 62.5 ns (16 mhz internal operation) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { memory space: 16 mb linear address space { internal memory rom: 256 kb ( pd703078y, 703079y: mask rom) 256 kb ( pd70f3079y: flash memory) ram: 16 kb ( pd703078y, 703079y, 70f3079y) { interrupt/exception: pd703078y (external: 8, internal: 35 sources, exception: 1 source) pd703079y, 70f3079y (external: 8, internal: 38 sources, exception: 1 source) { i/o lines total: 83 { timer/counters: 16-bit timer (3 channels: tm0, tm1, tm7) 8-bit timer (5 channels: tm2 to tm6) { watch timer: 1 channel { watchdog timer: 1 channel { serial interface ? asynchronous serial interface (uart0, uart1) ? clocked serial interface (csi0, csi1, csi3) ? 3-wire variable length serial interface (csi4) ? i 2 c bus interface (i 2 c0)
data sheet u15183ej2v0ds 2 pd703078y, 703079y, 70f3079y { 10-bit resolution a/d converter: 12 channels { dma controller: 6 channels { regulator: 3.5 to 5.5 v input internal 3.0 v ( pd703078y, 703079y) 4.0 to 5.5 v input internal 3.0 v ( pd70f3079y) { rom correction: 4 places can be corrected { power-saving function: halt/idle/stop modes { motor vehicle lan (fcan controller): 2 ch ( pd703079y, 70f3079y) 1 ch ( pd703078y) { packages: 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) { pd70f3079y ? can be replaced with pd703078y and 703079y (internal mask rom) in mass production applications { av equipment (car audio, etc.) ordering information part number package internal rom pd703078ygc- -8eu pd703078ygf- -3ba note pd703079ygc- -8eu pd703079ygf- -3ba note pd70f3079ygc-8eu pd70f3079ygf-3ba note 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) mask rom mask rom mask rom mask rom flash memory flash memory note under development remarks 1. indicates rom code suffix. 2. romless versions are not provided.
data sheet u15183ej2v0ds 3 pd703078y, 703079y, 70f3079y pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) ? pd703078ygc- -8eu ? pd703079ygc- -8eu ? pd70f3079ygc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p01/intp0 p13/si1/rxd0 p14/so1/txd0 p15/sck1/asck0 p100/kr0/to7 p101/kr1/ti70 p102/kr2/ti00 p103/kr3/ti01 p104/kr4/to0 p105/kr5/ti10 p106/kr6/ti11 p107/kr7/to1 gnd2 p110/wait p111 p112 p113 p114/cantx1 p115/canrx1 p02/intp1 p116/cantx2 note 2 p117/canrx2 note 2 p03/intp2 xt1 xt2 p77/ani7 p76/ani6 p75/ani5 p74/ani4 adcgnd adcv dd p73/ani3 p72/ani2 p71/ani1 p70/ani0 p07/intp6 p34/vm45/ti71 p33/ti5/to5 p32/ti4/to4 p31/ti3/to3 p30/ti2/to2 p27 p26 p06/intp5 p25/sck4 p24/so4 p23/si4 p05/intp4/adtrg p22/sck3/asck1 p21/so3/txd1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p80/ani8 p81/ani9 p82/ani10 p83/ani11 p00/nmi gnd0 cpureg v dd0 x2 x1 reset clkout ic/v pp note 1 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 gnd1 p10/si0/sda0 p11/so0 p12/sck0/scl0 p20/si3/rxd1 p96/hldrq p95/hldak p94/astb portgnd p93/dstb p92/r/w p91/uben p90/lben portv dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p04/intp3 notes 1. ic: connect directly to v ss ( pd703078y, 703079y). v pp : connect to gnd0 to gnd2 in normal operation mode ( pd70f3079y). 2. cantx2 and canrx2 are available only in the pd703079y and 70f3079y.
data sheet u15183ej2v0ds 4 pd703078y, 703079y, 70f3079y 100-pin plastic qfp (14 20) ? pd703078ygf- -3ba ? pd703079ygf- -3ba ? pd70f3079ygf-3ba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p15/sck1/asck0 p100/kr0/to7 p101/kr1/ti70 p102/kr2/ti00 p103/kr3/ti01 p104/kr4/to0 p105/kr5/ti10 p106/kr6/ti11 p107/kr7/to1 gnd2 p110/wait p111 p112 p113 p114/cantx1 p115/canrx1 p02/intp1 p116/cantx2 note 2 p117/canrx2 note 2 p03/intp2 p74/ani4 adcgnd adcv dd p73/ani3 p72/ani2 p71/ani1 p70/ani0 p07/intp6 p34/vm45/ti71 p33/ti5/to5 p32/ti4/to4 p31/ti3/to3 p30/ti2/to2 p27 p26 p06/intp5 p25/sck4 p24/so4 p23/si4 p05/intp4/adtrg 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p75/ani5 p76/ani6 p77/ani7 p80/ani8 p81/ani9 p82/ani10 p83/ani11 p00/nmi gnd0 cpureg v dd0 x2 x1 reset clkout ic/v pp note 1 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p10/si0/sda0 p11/so0 p12/sck0/scl0 p01/intp0 p13/si1/rxd0 p14/so1/txd0 p22/sck3/asck1 p21/so3/txd1 portgnd p20/si3/rxd1 p96/hldrq p95/hldak p94/astb p93/dstb p92/r/w p91/uben p90/lben portv dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p04/intp3 gnd1 xt2 xt1 notes 1. ic: connect directly to v ss ( pd703078y, 703079y). v pp : connect to gnd0 to gnd2 in normal operation mode ( pd70f3079y). 2. cantx2 and canrx2 are available only in the pd703079y and 70f3079y.
data sheet u15183ej2v0ds 5 pd703078y, 703079y, 70f3079y pin identification a16 to a21: address bus p50 to p57: port 5 ad0 to ad15: address/data bus p60 to p65: port 6 adcgnd: ground for analog p70 to p77: port 7 adcv dd power supply for analog p80 to p83: port 8 adtrg: a/d trigger input p90 to p96: port 9 ani0 to ani11: analog input p100 to p107: port 10 asck0, asck1: asynchronous serial clock p110 to p117: port 11 astb: address strobe reset: reset canrx1, canrx2: fcan receive data r/w: read/write status cantx1, cantx2: fcan transmit data rxd0, rxd1: receive data clkout: clock output sck0, sck1, cpureg: regulator control sck3, sck4: serial clock dstb: data strobe scl0: serial clock gnd0, gnd1, sda0: serial data gnd2: ground si0, si1, si3, si4: serial input hldak: hold acknowledge so0, so1, so3, hldrq: hold request so4: serial output ic: internally connected ti00, ti01, ti10, intp0 to intp6: interrupt request from peripherals ti11, ti2 to ti5, kr0 to kr7 : key return ti70, ti71: timer input lben: lower byte enable to0 to to5, to7: timer output nmi: non-maskable interrupt request txd0, txd1: transmit data portgnd: ground for port uben: upper byte enable portv dd1 power supply for port v dd0 : power supply p00 to p07: port 0 vm45: v dd = 4.5 v monitor output p10 to p15: port 1 v pp : programming power supply p20 to p27: port 2 wait: wait p30 to p34: port 3 x1, x2: crystal for main clock p40 to p47: port 4 xt1, xt2: crystal for subclock
data sheet u15183ej2v0ds 6 pd703078y, 703079y, 70f3079y internal block diagram notes 1. pd703078y, 703079y: 256 kb (mask rom) pd70f3079y: 256 kb (flash memory) 2. pd7030379y, 70f3079y only 3. pd70f3079y only 4. pd703078y, 703079y only intc sio csi0/i 2 c0 csi1/uart0 csi3/uart1 variable length csi4 fcan key return function watch timer watchdog timer dmac: 6ch timer/counters 16-bit timer: tm0, tm1, tm7 16-bit timer: tm2 to tm6 nmi so0 si0/sda0 sck0/scl0 so1/txd0 si1/rxd0 sck1/asck0 so3/txd1 si3/rxd1 sck3/asck1 so4 si4 sck4 kr0 to kr7 cantx1 canrx1 cantx2 note 2 canrx2 note 2 intp0 to intp6 ti00, ti01, ti10, ti11, ti70, ti71 ti2/to2 ti3/to3 ti4/to4 ti5/to5 to0, to1, to7 rom ram alu multiplier 16 16 32 rom correction cpu pc bcu cg ports a/d converter instruction queue 32-bit barrel shifter system registers general-purpose registers 32 bits 32 16 kb note1 3.0 v regulator hldrq (p96) hldak (p95) astb (p94) dstb (p93) r/w (p92) uben (p91) lben (p90) wait (p110) a16 to a21 (p60 to p65) ad0 to ad15 (p40 to p47, p50 to p57) clkout x1 x2 xt1 xt2 reset p110 to p117 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p34 p20 to p27 p10 to p15 p00 to p07 adcv dd adcgnd ani0 to ani11 adtrg cpureg v dd0 gnd0 vm45 portv dd portgnd gnd1 gnd2 v pp note 3 ic note 4
data sheet u15183ej2v0ds 7 pd703078y, 703079y, 70f3079y contents 1. differences between products ...........................................................................................8 2. pin functions ............................................................................................................... ...................9 2.1 port pins ................................................................................................................... .................................. 9 2.2 non-port pins............................................................................................................... ............................ 12 2.3 pin i/o circuits and recommended connection of unused pins ....................................................... 15 3. electrical specifications ................................................................................................... ...19 3.1 normal operation mode ...................................................................................................... .................... 20 3.2 flash memory programming mode ( pd70f3079y only)..................................................................... 44 4. package drawings ............................................................................................................ .........45 5. recommended soldering conditions ................................................................................47
data sheet u15183ej2v0ds 8 pd703078y, 703079y, 70f3079y 1. differences between products product name rom common name part number type size ram size i 2 cfcan pd703078y 1 channel pd703079y mask rom v850/sf1 pd70f3079y flash memory 256 kb 16 kb i 2 c incorporated 2 channels cautions 1. there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. 2. when replacing the flash memory versions with mask rom versions, write the same code in the empty area of the internal rom.
data sheet u15183ej2v0ds 9 pd703078y, 703079y, 70f3079y 2. pin functions 2.1 port pins (1/3) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5 p07 i/o no port 0 8-bit i/o port input/output can be specified in 1-bit units. intp6 p10 si0/sda0 p11 so0 p12 sck0/scl0 p13 si1/rxd0 p14 so1/txd0 p15 i/o no port 1 6-bit i/o port input/output can be specified in 1-bit units. sck1/asck0 p20 si3/rxd1 p21 so3/txd1 p22 sck3/asck1 p23 si4 p24 so4 p25 sck4 p26 ? p27 i/o no port 2 8-bit i/o port input/output can be specified in 1-bit units. ? p30 ti2/to2 p31 ti3/to3 p32 ti4/to4 p33 ti5/to5 p34 i/o no port 3 5-bit i/o port input/output can be specified in 1-bit units. vm45/ti71 p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output can be specified in 1-bit units. ad7 remark pull: on-chip pull-up resistor
data sheet u15183ej2v0ds 10 pd703078y, 703079y, 70f3079y (2/3) pin name i/o pull function alternate function p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output can be specified in 1-bit units. a21 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 input no port 8 4-bit input port ani11 p90 lben p91 uben p92 r/w p93 dstb p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output can be specified in 1-bit units. hldrq remark pull: on-chip pull-up resistor
data sheet u15183ej2v0ds 11 pd703078y, 703079y, 70f3079y (3/3) pin name i/o pull function alternate function p100 kr0/to7 p101 kr1/ti7 p102 kr2/ti00 p103 kr3/ti01 p104 kr4/to0 p105 kr5/ti10 p106 kr6/ti11 p107 i/o yes port 10 8-bit i/o port input/output can be specified in 1-bit units. kr7/to1 p110 wait p111 ? p112 ? p113 ? p114 cantx1 p115 canrx1 p116 cantx2 note p117 i/o no port 11 8-bit i/o port input/output can be specified in 1-bit units. canrx2 note note only for the pd703079y, 70f3079y remark pull: on-chip pull-up resistor
data sheet u15183ej2v0ds 12 pd703078y, 703079y, 70f3079y 2.2 non-port pins (1/3) pin name i/o pull function alternate function a16 to a21 output no higher address bus used for external memory expansion p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no 16-bit multiplexed address/data bus used for external memory expansion p50 to p57 adcgnd ? ? ground potential for a/d converter ? adcv dd ? ? power supply pin and reference voltage pin for a/d converter ? adtrg input no a/d converter external trigger input p05/intp4 ani0 to ani7 p70 to p77 ani8 to ani11 input no analog input to a/d converter p80 to p83 asck0 p15/sck1 asck1 input no baud rate clock input for uart0 and uart1 p22/sck3 astb output no external address strobe signal output p94 canrx1 input can1 receive data i nput p115 canrx2 input can2 receive data input ( pd703079y and 70f3079y only) p117 cantx1 output can1 transmit data output p114 cantx2 output no can2 transmit data output ( pd703079y and 70f3079y only) p116 clkout output ? internal system clock output ? cpureg ? ? connection of regulator output stabilize capacitance ? dstb output no external data strobe signal output p93 gnd0 to gnd2 ?? ground potential ? hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 ic ?? internally connected ( pd703078y and 703079y only) ? intp0 to intp3 external interrupt request input (analog noise elimination) p01 to p04 intp4 p05/adtrg intp5 external interrupt request input (digital noise elimination) p06 intp6 input no external interrupt request input (digital noise elimination for remote control) p07 kr0 p100/to7 kr1 p101/ti70 kr2 p102/ti00 kr3 p103/ti01 kr4 p104/to0 kr5 p105/ti10 kr6 p106/ti11 kr7 input yes key return input p107/ti01 lben output no external data bus?s lower byte enable signal output p90 nmi input no non-maskable interrupt request input p00 portgnd ? ? ground potential for port output ? portv dd ? ? positive power supply for port output ? remark pull: on-chip pull-up resistor
data sheet u15183ej2v0ds 13 pd703078y, 703079y, 70f3079y (2/3) pin name i/o pull function alternate function reset input ? system reset input ? r/w output no external read/write status p92/wrh rxd0 p13/si1 rxd1 input no serial receive data input for uart0 and uart1 p20/si3 sck0 p12/scl0 sck1 p15/asck0 sck3 serial clock i/o for csi0, csi1, csi3 (3-wire type) p22/asck1 sck4 i/o no serial clock i/o for variable-length csi4 (3-wire type) p25 scl0 i/o no serial clock i/o for i 2 c0 p12/sck0 sda0 i/o no serial transmit/receive data i/o for i 2 c0 p10/si0 si0 p10/sda0 si1 p13/rxd0 si3 serial receive data input for csi0, csi1, csi3 (3-wire type) p20/rxd1 si4 input no serial receive data input for variable-length csi4 (3-wire type) p23 so0 p11 so1 p14/txd0 so3 serial transmit data output for csi0, csi1, csi3 (3-wire type) p21/txd1 so4 output no serial transmit data output for variable-length csi4 (3-wire type) p24 ti00 external count clock input/external capture trigger input for tm0 p102/kr2 ti01 external capture trigger input for tm0 p103/kr3 ti10 external count clock input/external capture trigger input for tm1 p105/kr5 ti11 yes external capture trigger input for tm1 p106/kr6 ti2 external count clock input for tm2 p30/to2 ti3 external count clock input for tm3 p31/to3 ti4 external count clock input for tm4 p32/to4 ti5 no external count clock input for tm5 p33/to5 ti70 yes external count clock input/external capture trigger input for tm7 p101/kr1 ti71 input no external capture trigger input for tm7 p34/vm45 to0 pulse signal output for tm0 p104/kr4 to1 yes pulse signal output for tm1 p107/kr7 to2 pulse signal output for tm2 p30/ti2 to3 pulse signal output for tm3 p31/ti3 to4 pulse signal output for tm4 p32/ti4 to5 no pulse signal output for tm5 p33/ti5 to7 output yes pulse signal output for tm7 p100/kr0 txd0 p14/so1 txd1 output no serial transmit data output for uart0 and uart1 p24/so3 remark pull: on-chip pull-up resistor
data sheet u15183ej2v0ds 14 pd703078y, 703079y, 70f3079y (3/3) pin name i/o pull function alternate function uben output no higher byte enable signal output for external data bus p91 v dd0 ?? positive power supply pin ? vm45 output no v dd = 4.5 v monitor output p34/ti71 v pp ?? high-voltage apply pin for program write/verify ( pd70f3079y only) ? wait input yes control signal input for inserting wait in bus cycle p110 x1 input ? x2 ? no resonator connection for main clock ? xt1 input ? xt2 ? no resonator connection for sub system clock ? remark pull: on-chip pull-up resistor
data sheet u15183ej2v0ds 15 pd703078y, 703079y, 70f3079y 2.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 2-1. for the i/o schematic circuit diagram of each type, refer to figure 2-1. table 2-1. types of pin i/o circuits and connection of unused pins (1/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection of unused pins p00 nmi portv dd p01 to p04 intp0 to intp3 p05 intp4/adtrg p06, p07 intp5, intp6 8 p10 si0/sda0 10 p11 so0 5 p12 sck0/scl0 10 p13 si1/rxd0 8 p14 so1/txd0 5 p15 sck1/asck0 8 portv dd p20 si3/rxd1 8 p21 so3/txd1 5 p22 sck3/asck1 p23 si4 8 p24 so4 5 p25 sck4 p26 ? 8 p27 ? 5 portv dd p30 to p33 ti2/to2 to ti5/to5 portv dd p34 vm45/ti71 8 p40 to p47 ad0 to ad7 5 portv dd p50 to p57 ad8 to ad15 5 portv dd p60 to p65 a16 to a21 5 portv dd input: individually connect to portv dd or portgnd via a resistor. output: leave open. p70 to p77 ani0 to ani7 9 adcv dd p80 to p83 ani8 to ani11 9 adcv dd individually connect to adcv dd or adcgnd via a resistor. p90 lben p91 uben p92 r/w p93 dstb p94 astb p95 hldak p96 hldrq 5portv dd input: individually connect to portv dd or portgnd via a resistor. output: leave open.
data sheet u15183ej2v0ds 16 pd703078y, 703079y, 70f3079y table 2-1. types of pin i/o circuits and connection of unused pins (2/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection of unused pins p100 kr0/to7 p101 kr1/ti70 p102 kr2/ti00 p103 kr3/ti01 p104 kr4/to0 p105 kr5/ti10 p106 kr6/ti11 p107 kr7/to1 8-a portv dd input: individually connect to portv dd or portgnd via a resistor. output: leave open. p110 wait p111 to p113 ? 5 p114 cantx1 5 p115 canrx1 8 p116 cantx2 note 1 5 p117 canrx2 note 1 8 portv dd input: individually connect to portv dd or portgnd via a resistor. output: leave open. clkout ? 4portv dd leave open. reset ? 2portv dd ? x1 ??? ? x2 ??? ? xt1 ??? connect to gnd0 to gnd2 via a resistor. xt2 ??? leave open. v pp note 2 ??? connect to gnd0 to gnd2. ic note 3 ??? connect directly to gnd0 to gnd2. cpureg ??? ? v dd0 ??? ? gnd0 to gnd2 ??? ? adcv dd ??? ? adcgnd ??? ? portv dd ??? ? portgnd ??? ? notes 1. pd703079y, 70f3079y only 2. pd70f3079y only 3. pd703078y, 703079y only
data sheet u15183ej2v0ds 17 pd703078y, 703079y, 70f3079y figure 2-1. pin i/o circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics push-pull output that can be set for high-impedance output (both p-ch and n-ch off) in data output disable p-ch out v dd n-ch data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch p-ch v dd pull-up enable in comparator + ? v ref (threshold voltage) p-ch n-ch input enable type 4 type 5 type 9 type 8-a type 8 data output disable p-ch in/out v dd n-ch
data sheet u15183ej2v0ds 18 pd703078y, 703079y, 70f3079y figure 2-1. pin i/o circuits (2/2) type 10 data output disable p-ch in/out v dd n-ch open drain
data sheet u15183ej2v0ds 19 pd703078y, 703079y, 70f3079y 3. electrical specifications absolute maximum ratings (t a = 25c) parameter symbol conditions ratings unit supply voltage v dd v dd0 , portv dd , adcv dd pins ?0.3 to +6.0 v v i1 v dd0 , portv dd , adcv dd pins ?0.3 to v dd +0.3 note 1 v input voltage v i2 v pp pin ( pd70f3079y only) ?0.3 to +8.5 v analog input voltage v an note 2 (adcv dd pin) ?0.3 to v dd +0.3 note 1 v per pin 8.0 ma output current, low i ol total for all pins 25 ma per pin ?8.0 ma total for p00, p05 to p07, p20 to p27, p30 to p34, p90 to 96 and their alternate-function pins ?25 ma output current, high i oh total for p01 to p04, p10 to p15, p40 to p47, p50 to p57, p60 to p65, p100 to p107, p110 to p117 and their alternate-function pins ?25 ma output voltage v o ?0.3 to v dd + 0.3 note 1 v normal operation mode ?40 to +85 c operating ambient temperature t a flash memory programming mode ( pd70f3079y only) ?20 to +85 c pd703078y, 703079y ?65 to +150 c storage temperature t stg pd70f3079y ?40 to + 125 c notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. ports 7, 8, and their alternate-function pins cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-collector pins are possible, as are direct connections to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u15183ej2v0ds 20 pd703078y, 703079y, 70f3079y 3.1 normal operation mode operating conditions (1) operating voltage parameter symbol conditions min. typ. max. unit pd70f3079y 4.5 5.5 v 0.5 f cpu 16 mhz, when all functions are operating (except the a/d converter) pd703078y, 703079y 4.0 5.5 v pd70f3079y 4.0 5.5 v v dd0 0.5 f cpu 12 mhz, f xt = 32.768 khz, when all functions are operating (except the a/d converter) pd703078y, 703079y 3.5 5.5 v pd70f3079y 4.5 5.5 v 0.5 f cpu 16 mhz pd703078y, 703079y 4.0 5.5 v pd70f3079y 4.0 5.5 v portv dd 0.5 f cpu 12 mhz, f xt = 32.768 khz pd703078y, 703079y 3.5 5.5 v when the a/d converter is operating, v dd0 = adcv dd 4.5 5.5 v supply voltage adcv dd when the a/d converter is stopped 4.0 5.5 v (2) cpu operating frequency parameter symbol conditions min. typ. max. unit main system clock operation 0.5 16 mhz cpu operating frequency f cpu subsystem clock operation 32.768 khz
data sheet u15183ej2v0ds 21 pd703078y, 703079y, 70f3079y recommended oscillator (1) main system clock oscillator (t a = ?40 to +85c) (a) connection of ceramic resonator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit oscillation frequency f xx 416mhz ? upon reset release 2 21 /f xx s oscillation stabilization time ? upon stop mode release note s note the typ. value differs depending on the setting of the oscillation stabilization time select register (osts). cautions 1. main system clock oscillator operates on the output voltage of the on-chip regulator. external clock input is prohibited. 2. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 3. ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
data sheet u15183ej2v0ds 22 pd703078y, 703079y, 70f3079y (2) subsystem clock oscillator (t a = ?40 to +85c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32.768 khz oscillation stabilization time ? when reset is released 10 s cautions 1. subsystem clock oscillator operates on the output voltage of the on-chip regulator. external clock input is prohibited. 2. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 3. sufficiently evaluate the matching between the resonator and the pd703078y, 703079y, and 70f3079y.
data sheet u15183ej2v0ds 23 pd703078y, 703079y, 70f3079y dc characteristics (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = adcgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, adcv dd = 4.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v, adcv dd = 4.5 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7v dd v dd v input voltage, high v ih2 note 2 0.8v dd v dd v v il1 note 1 00.3v dd v input voltage, low v il2 note 2 00.2v dd v v oh = v dd ? 1 v ? 1.0 ma output current, high i oh1 note 3 v oh = v dd ? 0.5 v ? 100 a v ol = 1 v 1.0 ma output current, low i ol1 note 3 v ol = 0.5 v 100 a input leakage current, high i ih1 note 4 v in = v dd 5.0 a input leakage current, low i il1 note 4 v in = 0 v ? 5.0 a output off-leakage current i l1 note 5 v oh = v dd 5.0 a pull-up resistor r l1 note 6 v in = 0 v 10 30 100 k ? notes 1. p11, p14, p21, p24, p27, p34, p40 to p47, p50 to p57, p60 to p65, p70 to p77, p80 to p83, p90 to p96, p100, p104, p107, p110 to p114, p116, and other alternate-function pins 2. p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25, p26, p30 to p33, p101 to p103, p105, p106, p115, p117, reset, and other alternate-function pins 3. all output pins and other alternate-function pins 4. all input pins and other alternate-function pins 5. p10, p12 (in n-ch open-drain mode) 6. p100 to p107 (in key return mode)
data sheet u15183ej2v0ds 24 pd703078y, 703079y, 70f3079y dc characteristics (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = adcgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, adcv dd = 4.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v, adcv dd = 4.5 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode note 1 15 30 ma i dd2 in halt mode note 2 920ma i dd3 in idle mode note 3 0.5 3 ma i dd4 in stop mode note 4 15 100 a i dd5 in normal mode (subsystem operation) note 5 50 200 a i dd6 in halt mode (subsystem operation) note 6 30 180 a pd703078y, pd703079y i dd7 in idle mode (subsystem operation) note 7 20 160 a i dd1 in normal operation mode note 1 25 50 ma i dd2 in halt mode note 2 920ma i dd3 in idle mode note 3 0.5 4 ma i dd4 in stop mode note 4 15 100 a i dd5 in normal mode (subsystem operation) note 5 200 600 a i dd6 in halt mode (subsystem operation) note 6 150 300 a supply current pd70f3079y i dd7 in idle mode (subsystem operation) note 7 90 200 a notes 1. f cpu = f xx = 16 mhz, v in = v cpureg , peripheral functions operating (except fcan) 2. f cpu = f xx = 16 mhz, v in = v cpureg , cpu stopped, peripheral functions operating (except fcan) 3. f xx = 16 mhz, v in = v cpureg , all peripheral functions stopped (watch timer operating) 4. f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, all peripheral functions stopped (watch timer operating with subsystem clock) 5. f cpu = f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, all peripheral functions operating (except fcan) 6. f cpu = f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, cpu stopped, peripheral functions operating (except fcan) 7. f xt = 32.768 khz, v in = v cpureg , main clock oscillator stopped, all peripheral functions stopped (watch timer operating)
data sheet u15183ej2v0ds 25 pd703078y, 703079y, 70f3079y data retention characteristics (t a = ?40 to +85c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode note (no functions operating) 2.2 5.5 v data retention current i dddr stop mode note (no functions operating) 10 100 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage hold time (from stop mode setting) t hvd 0ms stop release signal input time t drel 0ns data retention high-level input voltage v ihdr all input ports 0.9v dddr v dddr v data retention low-level input voltage v ildr all input ports 0 0.1v dddr v note subsystem stopped t hvd v dddr t drel v ihdr v ihdr t fvd t rvd v dd nmi, intpn (input) (released by falling edge) setting stop mode reset (input) nmi, intpn (input) (released by rising edge) v ildr
data sheet u15183ej2v0ds 26 pd703078y, 703079y, 70f3079y ac characteristics (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = adcgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, adcv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = adcv dd = 4.0 to 5.5 v) ac test input test points (v dd : v dd0 , portv dd , adcv dd ) v dd 0 v v ih v il v ih v il test points input signal ac test output test points (v dd : v dd0 , portv dd ) load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v oh v ol v oh v ol test points output signal v dd 0 v
data sheet u15183ej2v0ds 27 pd703078y, 703079y, 70f3079y (1) clock timing (a) t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v parameter symbol conditions min. max. unit clkout output cycle <1> t cyk 62.5 ns 31 s clkout high-level width <2> t wkh 0.4t cyk ? 12 ns clkout low-level width <3> t wkl 0.4t cyk ? 12 ns clkout rise time <4> t kr 12 ns clkout fall time <5> t kf 12 ns (b) t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v parameter symbol conditions min. max. unit clkout output cycle <1> t cyk 83 ns 31 s clkout high-level width <2> t wkh 0.4t cyk ? 15 ns clkout low-level width <3> t wkl 0.4t cyk ? 15 ns clkout rise time <4> t kr 15 ns clkout fall time <5> t kf 15 ns clkout (output) <2> <4> <5> <3> <1>
data sheet u15183ej2v0ds 28 pd703078y, 703079y, 70f3079y (2) output waveform (other than port 4, port 5, port 6, port 9, and clkout) (t a = ?40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit output rise time <6> t or 35 ns output fall time <7> t of 35 ns (3) reset timing (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit reset pin high-level width <8> t wrsh 500 ns reset pin low-level width <9> t wrsl 500 ns <7> <6> output signal <8> <9> reset (input)
data sheet u15183ej2v0ds 29 pd703078y, 703079y, 70f3079y (4) bus timing (a) clock asynchronous (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v) parameter symbol conditions min. max. unit address setup time (to astb ) <10> t sast 0.5t ? 25 ns address hold time (from astb ) <11> t hsta 0.5t ? 15 ns delay time from dstb to address float <12> t fda 0ns data input setup time from address <13> t said (2 + n)t ? 55 ns data input setup time from dstb <14> t sdid (1 + n)t ? 45 ns data input setup time from astb <15> t sasid (1.5 + n)t ? 62 ns delay time from astb to dstb <16> t dstd 0.5t ? 15 ns data input hold time (from dstb ) <17> t hdid 0ns address output time from dstb <18> t dda (1 + i)t ? 15 ns delay time from dstb to astb <19> t ddst1 0.5t ? 15 ns delay time from dstb to astb <20> t ddst2 (1.5 + i)t ? 15 ns dstb low-level width <21> t wdl (1 + n)t ? 20 ns astb high-level width <22> t wsth t ? 15 ns data output time from dstb <23> t ddod 20 ns data output setup time (to dstb ) <24> t sodd (1 + n)t ? 30 ns data output hold time (from dstb ) <25> t hdod t ? 15 ns <26> t sawt1 n 1 1.5t ? 55 ns wait setup time (to address) <27> t sawt2 (1.5 + n)t ? 55 ns <28> t hawt1 n 1 (0.5 + n)t ns wait hold time (from address) <29> t hawt2 (1.5 + n)t ns <30> t sstwt1 n 1t ? 40 ns wait setup time (to astb ) <31> t sstwt2 (1 + n)t ? 40 ns <32> t hstwt1 n 1ntns wait hold time (from astb ) <33> t hstwt2 (1 + n)t ns hldrq high-level width <34> t whqh t + 10 ns hldak low-level width <35> t whal t ? 15 ns delay time from hldak to bus output <36> t dhac 0ns delay time from hldrq to hldak <37> t dhqha1 1.5t (2n + 7.5)t + 25 ns delay time from hldrq to hldak <38> t dhqha2 0.5t 1.5t + 25 ns remarks 1. t: 1/f cpu (f cpu : cpu clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle cycles inserted in the bus cycle. 4. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
data sheet u15183ej2v0ds 30 pd703078y, 703079y, 70f3079y (b) clock asynchronous (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit address setup time (to astb ) <10> t sast 0.5t ? 32 ns address hold time (from astb ) <11> t hsta 0.5t ? 22 ns delay time from dstb to address float <12> t fda 0ns data input setup time from address <13> t said (2 + n)t ? 70 ns data input setup time from dstb <14> t sdid (1 + n)t ? 60 ns data input setup time from astb <15> t sasid (1.5 + n)t ? 70 ns delay time from astb to dstb <16> t dstd 0.5t ? 15 ns data input hold time (from dstb ) <17> t hdid 0ns address output time from dstb <18> t dda (1 + i)t ? 15 ns delay time from dstb to astb <19> t ddst1 0.5t ? 15 ns delay time from dstb to astb <20> t ddst2 (1.5 + i)t ? 15 ns dstb low-level width <21> t wdl (1 + n)t ? 35 ns astb high-level width <22> t wsth t ? 15 ns data output time from dstb <23> t ddod 25 ns data output setup time (to dstb ) <24> t sodd (1 + n)t ? 35 ns data output hold time (from dstb ) <25> t hdod t ? 25 ns <26> t sawt1 n 1 1.5t ? 70 ns wait setup time (to address) <27> t sawt2 (1.5 + n)t ? 70 ns <28> t hawt1 n 1 (0.5 + n)t ns wait hold time (from address) <29> t hawt2 (1.5 + n)t ns <30> t sstwt1 n 1t ? 55 ns wait setup time (to astb ) <31> t sstwt2 (1 + n)t ? 55 ns <32> t hstwt1 n 1ntns wait hold time (from astb ) <33> t hstwt2 (1 + n)t ns hldrq high-level width <34> t whqh t + 10 ns hldak low-level width <35> t whal t ? 25 ns delay time from hldak to bus output <36> t dhac 0ns delay time from hldrq to hldak <37> t dhqha1 1.5t (2n + 7.5)t + 25 ns delay time from hldrq to hldak <38> t dhqha2 0.5t 1.5t + 25 ns remarks 1. t: 1/f cpu (f cpu : cpu clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle cycles inserted in the bus cycle. 4. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
data sheet u15183ej2v0ds 31 pd703078y, 703079y, 70f3079y (c) clock synchronous (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v) parameter symbol conditions min. max. unit delay time from clkout to address <39> t dka 035ns delay time from clkout to address float <40> t fka ? 12 15 ns delay time from clkout to astb <41> t dkst 030ns delay time from clkout to dstb <42> t dkd 030ns data input setup time (to clkout ) <43> t sidk 20 ns data input hold time (from clkout ) <44> t hkid 5ns delay time from clkout to data output <45> t dkod 35 ns wait setup time (to clkout ) <46> t swtk 25 ns wait hold time (from clkout ) <47> t hkwt 5ns hldrq setup time (to clkout ) <48> t shqk 20 ns hldrq hold time (from clkout ) <49> t hkhq 5ns delay time from clkout to address float (during bus hold) <50> t dkf 19 ns delay time from clkout to hldak <51> t dkha 35 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (d) clock synchronous (t a = ?40 to +85c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit delay time from clkout to address <39> t dka 045ns delay time from clkout to address float <40> t fka ? 17 15 ns delay time from clkout to astb <41> t dkst 035ns delay time from clkout to dstb <42> t dkd 035ns data input setup time (to clkout ) <43> t sidk 20 ns data input hold time (from clkout ) <44> t hkid 5ns delay time from clkout to data output <45> t dkod 45 ns wait setup time (to clkout ) <46> t swtk 29 ns wait hold time (from clkout ) <47> t hkwt 5ns hldrq setup time (to clkout ) <48> t shqk 24 ns hldrq hold time (from clkout ) <49> t hkhq 5ns delay time from clkout to address float (during bus hold) <50> t dkf 19 ns delay time from clkout to hldak <51> t dkha 40 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
data sheet u15183ej2v0ds 32 pd703078y, 703079y, 70f3079y (e) read cycle (clkout synchronous/asynchronous, 1 wait) note r/w, uben, lben remark broken lines indicate high impedance. clkout (output) astb (output) t1 t2 tw <39> < 16 > < 21 > < 46 > dstb, rd (output) wait (input) ad0 to ad15 (i/o) < 40 > < 10 > < 44 > < 41 > t3 < 43 > < 13 > < 22 > < 17 > < 14 > < 20 > < 18 > < 19 > < 42 > < 12 > < 30 > < 32 > < 26 > < 28 > < 27 > < 29 > < 31 > < 47 > < 46 > < 47 > data address < 41 > < 11 > < 42 > < 33 > a16 to a21 (output) note (output) < 15 >
data sheet u15183ej2v0ds 33 pd703078y, 703079y, 70f3079y (f) write cycle (clkout synchronous/asynchronous, 1 wait) note r/w, uben, lben remark broken lines indicate high impedance. clkout (output) astb (output) t1 t2 tw <39> < 16 > < 21 > < 46 > a16 to a21 (output) note (output) dstb, wrl, wrh (output) wait (input) ad0 to ad15 (i/o) < 45 > < 10 > < 41 > t3 < 22 > < 24 > < 25 > < 19 > < 42 > < 23 > < 30 > < 32 > < 26 > < 28 > < 27 > < 29 > < 31 > < 47 > < 46 > < 47 > data address < 41 > < 11 > < 42 > < 33 >
data sheet u15183ej2v0ds 34 pd703078y, 703079y, 70f3079y (g) bus hold timing note r/w, uben, lben remark broken lines indicate high impedance. clkout (output) th < 48 >< 49 > th th th ti < 48 > < 37 > < 51 >< 51 > <35> < 38 > <34> <50> <36> a16 to a19 (output) note (output) hldrq (input) hldak (output) astb (output) dstb, rd (output) wrl, wrh (output) ad0 to ad15 (i/o) data
data sheet u15183ej2v0ds 35 pd703078y, 703079y, 70f3079y (5) interrupt timing (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit nmi high-level width <52> t wnih 500 ns nmi low-level width <53> t wnil 500 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn high-level width <54> t with n = 6, digital noise elimination 3tsmp + 20 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn low-level width <55> t witl n = 6, digital noise elimination 3tsmp + 20 ns remarks 1. t: 1/f xx 2. tsmp: noise elimination sampling clock cycle <52> <53> nmi (input) <54> <55> intpn (input) remark n = 0 to 6
data sheet u15183ej2v0ds 36 pd703078y, 703079y, 70f3079y (6) rpu timing (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit tin0, tin1 high-level width <56> t tihn n = 0, 1, 7 2t sam + 20 note ns tin0, tin1 low-level width <57> t tiln n = 0, 1, 7 2t sam + 20 note ns tim high-level width <58> t tihm m = 2 to 5 3t + 20 ns tim low-level width <59> t tilm m = 2 to 5 3t + 20 ns note t sam (count clock cycle) can select the following cycles by setting the prmn2 to prmn0 bits of prescaler mode registers n0, n1 (prmn0, prmn1). when n = 0 (tm0), t sam = 2t, 4t, 16t, 64t, 256t, or 1/intwtni cycle when n = 1 (tm1), t sam = 2t, 4t, 16t, 32t, 128t, or 256t cycle however, when the tin0 valid edge is selected as the count clock, t sam = 4t. remark t: 1/f xx remark n = 0, 1, 7 m = 2 to 5 <56> <57> tin0, tin1 (input) <58> <59> tim (input)
data sheet u15183ej2v0ds 37 pd703078y, 703079y, 70f3079y (7) asynchronous serial interface (uart0, uart1) timing (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) parameter symbol conditions min. max. unit asckn cycle time <60> t kcy13 200 ns asckn high-level width <61> t kh13 80 ns asckn low-level width <62> t kl13 80 ns remark n = 0, 1 <63> <62> <60> asckn (input) remark n = 0, 1
data sheet u15183ej2v0ds 38 pd703078y, 703079y, 70f3079y (8) 3-wire serial interface (csi0, csi1 csi3) timing (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v) (a) master mode parameter symbol conditions min. max. unit sckn cycle <63> t kcy1 note 1 400 ns sckn high-level width <64> t kh1 note 1 140 ns sckn low-level width <65> t kl1 note 1 140 ns sin setup time (to sckn ) <66> t sik1 note 1 50 ns sin hold time (from sckn ) <67> t ksi1 note 1 50 ns note 2 80 ns delay time from sckn to son output <68> t kso1 note 1 100 ns notes 1. pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v 2. pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v remark n = 0, 1, 3 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <63> t kcy2 note 1 400 ns sckn high-level width <64> t kh2 note 1 140 ns sckn low-level width <65> t kl2 note 1 140 ns sin setup time (to sckn ) <66> t sik2 note 1 50 ns sin hold time (from sckn ) <67> t ksi2 note 1 50 ns note 2 80 ns delay time from sckn to son output <68> t kso2 note 1 100 ns notes 1. pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v 2. pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v remark n = 0, 1, 3
data sheet u15183ej2v0ds 39 pd703078y, 703079y, 70f3079y <67> <68> <66> <63> <64> <65> remarks 1. broken lines indicate high impedance. 2. n = 0, 1, 3 sckn (i/o) sin (input) son (output) input data output data
data sheet u15183ej2v0ds 40 pd703078y, 703079y, 70f3079y (9) 3-wire variable length serial interface (csi4) timing (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v) (a) master mode parameter symbol conditions min. max. unit sck4 cycle <69> t kcy1 note 1 200 ns sck4 high-level width <70> t kh1 note 1 60 ns sck4 low-level width <71> t kl1 note 1 60 ns si4 setup time (to sck4 ) <72> t sik1 note 1 25 ns si4 hold time (from sck4 ) <73> t ksi1 note 1 20 ns note 2 55 ns delay time from sck4 to so4 output <74> t kso1 note 1 70 ns notes 1. pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v 2. pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v (b) slave mode parameter symbol conditions min. max. unit sck4 cycle <69> t kcy2 note 1 200 ns sck4 high-level width <70> t kh2 note 1 60 ns sck4 low-level width <71> t kl2 note 1 60 ns si4 setup time (to sck4 ) <72> t sik2 note 1 25 ns si4 hold time (from sck4 ) <73> t ksi2 note 1 20 ns note 2 55 ns delay time from sck4 to so4 output <74> t kso2 note 1 70 ns notes 1. pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v 2. pd703078y, 703079y: v dd0 = portv dd = 4.0 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.5 to 5.5 v
data sheet u15183ej2v0ds 41 pd703078y, 703079y, 70f3079y remark broken lines indicate high impedance. <69> <71> <70> <72> <73> <74> si4 (input) so4 (output) sck4 (i/o) output data input data
data sheet u15183ej2v0ds 42 pd703078y, 703079y, 70f3079y (10) i 2 c bus mode (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) (1/2) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0 clock frequency ? f clk 0 100 0 400 khz bus-free time (between stop/start conditions) <75> t buf 4.7 ? 1.3 ? s hold time note 1 <76> t hd:sta 4.0 ? 0.6 ? s scl0 clock low-level width <77> t low 4.7 ? 1.3 ? s scl0 clock high-level width <78> t high 4.0 ? 0.6 ? s setup time for start/restart conditions <79> t su:sta 4.7 ? 0.6 ? s cbus compatible master 5.0 ??? s data hold time i 2 c mode <80> t hd:dat 0 note 2 ? 0 note 2 0.9 note 3 s data setup time <81> t su:dat 250 ? 100 note 4 ? ns sda0 and scl0 signal rise time <82> t r ? 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time <83> t f ? 300 20 + 0.1cb note 5 300 ns stop condition setup time <84> t su:sto 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter <85> t sp ?? 050ns capacitance load of each bus line ? cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0 signal (at v ihmin. . of scl0 signal) in order to occupy the undefined area at the falling edge of scl0. 3. if the system does not extend the scl0 signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0 signal ? s low state hold time: t hd : dat 250 ns ? if the system extends the scl0 signal ? s low state hold time: transmit the following data bit to the sda0 line prior to the scl0 line release (t rmax. + t su : dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf)
data sheet u15183ej2v0ds 43 pd703078y, 703079y, 70f3079y (10) i 2 c bus mode (t a = ? 40 to +85 c, gnd0 = gnd1 = gnd2 = portgnd = 0 v, pd703078y, 703079y: v dd0 = portv dd = 3.5 to 5.5 v, pd70f3079y: v dd0 = portv dd = 4.0 to 5.5 v) (2/2) a/d converter characteristics (t a = ? 40 to +85 c, v dd0 = adcv dd = 4.5 to 5.5 v, gnd0 = gnd1 = gnd2 = adcgnd = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution ? 10 10 10 bit overall error note 1 ? adm2 = 01h 1.0 %fsr conversion time t conv 510 s zero-scale error note 1 ainl 0.4 %fsr full-scale error note 1 ainl adm2 = 01h 0.6 %fsr integral linearity error note 2 inl adm2 = 01h 6.0 lsb differential linearity error note 2 dnl adm2 = 01h 6.0 lsb analog power supply voltage av dd adcv dd pin 4.5 5.5 v analog input voltage v ian 0 adcv dd v adcv dd current ai dd adm2 = 01h 4 8 ma notes 1. excluding quantization error ( 0.05 %fsr) 2. excluding quantization error ( 0.5 lsb) remarks 1. lsb: least significant bit fsr: full scale range 2. adm2: a/d converter mode register 2 power-on-clear circuit, 4.5 v detection flag characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v poch cpu operation 2.7 3.0 3.3 v poc circuit detection voltage v pocl stop mode 1.5 1.8 2.1 v vm45 flag setting voltage vm45 3.7 4.2 4.5 v stop condition start condition restart condition stop condition scl0 (i/o) sda0 (i/o) <76> <75> <77> <78> <82> <83> <80> <81> <79> <76> <85> <84> <83> <82>
data sheet u15183ej2v0ds 44 pd703078y, 703079y, 70f3079y 3.2 flash memory programming mode ( pd70f3079y only) basic characteristics (t a = ? 20 to +85 c, v dd = adcv dd = portv dd = 4.5 to 5.5 v, gnd0 = gnd1 = gnd2 = adcgnd = portgnd = 0 v) parameter symbol conditions min. typ. max. unit v pp supply voltage v pp2 during flash memory programming 7.5 7.8 8.1 v v dd supply current i dd v pp = v pp2 f xx = 16 mhz 53 ma v pp supply current i pp v pp = v pp2 100 ma step erase time t er note 1 0.2 s overall erase time per area t era when the step erase time = 0.2 s note 2 20 s/area write-back time t wb note 3 1ms number of write-backs per write-back command c wb when the write-back time = 1 ms note 4 300 count/write- back command number of erase/write-backs c erwb 16 count step writing time t wr note 5 20 s overall writing time per word t wrw when the step writing time = 20 s (1 word = 4 bytes) note 6 20 200 s/word number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite note 7 100 count/ area notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. the recommended setting value of the write-back time is 1 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 20 s. 6. 20 s is added to the actual writing time per word. the internal verify time during and after the writing is not included. 7. when writing initially to shipped products, it is counted as one rewrite for both ? erase to write ? and ? write only ? . example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh
data sheet u15183ej2v0ds 45 pd703078y, 703079y, 70f3079y 4. package drawings 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.000.20 14.000.20 0.50 (t.p.) 1.00 j 16.000.20 k c 14.000.20 i 0.08 1.000.20 l 0.500.20 f 1.00 n p q 0.08 1.400.05 0.100.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 +0.05 -0.04 m 0.17 +0.03 -0.07 r3 +7 -3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet u15183ej2v0ds 46 pd703078y, 703079y, 70f3079y 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m0.15 + 0.10 ? 0.05 c d a b s
data sheet u15183ej2v0ds 47 pd703078y, 703079y, 70f3079y 5. recommended soldering conditions the pd703078y, 703079y, and 70f3079y should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. caution the recommended soldering conditions for the following products have not been determined. ? ? ? ? pd703078ygf-xxx-3ba ? ? ? ? pd703079ygf-xxx-3ba ? ? ? ? pd70f3079ygf-3ba table 5-1. surface mounting type soldering conditions pd703078ygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703079ygc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3079ygc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time: 20 to 40 seconds max. (at 200 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
data sheet u15183ej2v0ds 48 pd703078y, 703079y, 70f3079y [memo]
data sheet u15183ej2v0ds 49 pd703078y, 703079y, 70f3079y [memo]
data sheet u15183ej2v0ds 50 pd703078y, 703079y, 70f3079y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. reference document electrical characteristics for microcomputer (u15170j) note note this document number is that of the japanese version. v850/sf1 and v850 series are trademarks of nec corporation.
data sheet u15183ej2v0ds 51 pd703078y, 703079y, 70f3079y regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v?lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
pd703078y, 703079y, 70f3079y license not needed: pd70f3079y the customer must judge the need for license: pd703078y, 703079y the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of november, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a pa rticular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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