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? 1998 microchip technology inc. ds21178c-page 1 m 24aa00/24lc00/24c00 device selection table features low power cmos technology - 500 m a typical active current - 250 na typical standby current organized as 16 bytes x 8 bits 2-wire serial interface bus, i 2 c compatible 100 khz (1.8v) and 400 khz (5v) compatibility self-timed write cycle (including auto-erase) 4 ms maximum byte write cycle time 1,000,000 erase/write cycles guaranteed esd protection > 4 kv data retention > 200 years 8l dip, soic, tssop and 5l sot-23 packages temperature ranges available: description the microchip technology inc. 24aa00/24lc00/ 24c00 (24xx00*) is a 128-bit electrically erasable prom memory organized as 16 x 8 with a 2-wire serial interface. low voltage design permits operation down to 1.8 volts for the 24xx00 version, and every version maintains a maximum standby current of only 1 m a and typical active current of only 500 m a. this device was designed for where a small amount of eeprom is needed for the storage of calibration values, id num- bers or manufacturing information, etc. the 24xx00 is available in 8-pin pdip, 8-pin soic (150 mil), 8-pin tssop and the 5-pin sot-23 packages. package types block diagram device v cc range temp range 24aa00 1.8 - 6.0 c,i 24lc00 2.5 - 6.0 c,i 24c00 4.5 - 5.5 c,i,e - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c - automotive (e): -40 c to +125 c 24xx00 1 2 3 4 8 7 6 5 15 4 3 24xx00 24xx00 8-pin pdip/soic 8-pin tssop 5-pin sot-23 nc nc nc vss v cc nc scl sda nc nc nc v ss v cc nc scl sda scl v ss sda v cc nc 1 2 3 4 8 7 6 5 2 hv generator eeprom array ydec xdec sense amp r/w control memory control logic i/o control logic sda scl v cc v ss 128 bit i 2 c bus serial eeprom i 2 c is a trademark of philips corporation. *24xx00 is used in this document as a generic part number for the 24aa00/24lc00/24c00 devices.
24aa00/24lc00/24c00 ds21178c-page 2 ? 1998 microchip technology inc. 1.0 electrical characteristics 1.1 maxim um ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ................-0.6v to v cc +1.0v storage temperature ..................................... -65?c to +150?c ambient temp. with power applied................. -65?c to +125?c soldering temperature of leads (10 seconds) ............. +300?c esd protection on all pins................................................4 kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended peri- ods may affect device reliability. table 1-1 pin function table figure 1-1: bus timing data name function v ss sda scl v cc nc ground serial data serial clock +1.8v to 6.0v (24aa00) +2.5v to 6.0v (24lc00) +4.5v to 5.5v (24c00) no internal connection table 1-2 dc characteristics all parameters apply across the recom- mended operating ranges unless other- wise noted commercial (c): tamb = 0?c to +70?c, v cc = 1.8v to 6.0v industrial (i): tamb = -40?c to +85?c, v cc = 1.8v to 6.0v automotive (e) tamb = -40?c to +125?c, v cc = 4.5v to 5.5v parameter symbol min. max. units conditions scl and sda pins: high level input voltage v ih 0.7 v cc v (note) low level input voltage v il 0.3 v cc v (note) hysteresis of schmitt trigger inputs v hys .05 v cc v vcc 3 2.5v (note) low level output voltage v ol .40 v i ol = 3.0 ma, v cc = 4.5v i ol = 2.1 ma, v cc = 2.5v input leakage current i li -10 10 m av in = v cc or v ss output leakage current i lo -10 10 m av out = v cc or v ss pin capacitance (all inputs/outputs) c in , c out ?0pfv cc = 5.0v (note) tamb = 25?c, f = 1 mhz operating current i cc write 2 ma v cc = 5.5v, scl = 400 khz i cc read 1 ma v cc = 5.5v, scl = 400 khz standby current i ccs ? m av cc = 5.5v, sda = scl = v cc note: this parameter is periodically sampled and not 100% tested. t f t high t r t su : sta t low t hd : dat t su : dat t su : sto t buf t aa t sp scl sda in sda out t hd : sta
24aa00/24lc00/24c00 ? 1998 microchip technology inc. ds21178c-page 3 table 1-3 ac characteristics all parameters apply across all recommended operating ranges unless otherwise noted commercial (c): tamb = 0?c to +70?c, v cc = 1.8v to 6.0v industrial (i): tamb = -40?c to +85?c, v cc = 1.8v to 6.0v automotive (e): tamb = -40?c to +125?c, v cc = 4.5v to 5.5v parameter symbol min max units conditions clock frequency f clk 100 100 400 khz 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v clock high time t high 4000 4000 600 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v clock low time t low 4700 4700 1300 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v sda and scl rise time (note 1) t r 1000 1000 300 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v sda and scl fall time t f 300 ns (note 1) start condition hold time t hd : sta 4000 4000 600 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v start condition setup time t su : sta 4700 4700 600 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v data input hold time t hd : dat 0 ns (note 2) data input setup time t su : dat 250 250 100 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v stop condition setup time t su : sto 4000 4000 600 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v output valid from clock (note 2) t aa 3500 3500 900 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v bus free time: time the bus must be free before a new transmis- sion can start t buf 4700 4700 1300 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 6.0v output fall time from v ih minimum to v il maximum t of 20+0.1 cb 250 ns (note 1), cb 100 pf input ?ter spike suppression (sda and scl pins) t sp 50 ns (notes 1, 3) write cycle time t wc ?ms endurance 1m cycles 25 c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. cb = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the unde?ed region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys speci?ations are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti speci?ation for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a speci? application, please consult the total endurance model which can be obtained on microchips bbs or web- site.
24aa00/24lc00/24c00 ds21178c-page 4 ? 1998 microchip technology inc. 2.0 pin descriptions 2.1 sd a serial data this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10 k w for 100 khz, 2 k w for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 2.2 scl serial cloc k this input is used to synchronize the data transfer from and to the device. 2.3 noise pr otection the scl and sda inputs have schmitt trigger and ?ter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 3.0 functional description the 24xx00 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is de?ed as a transmitter, and a device receiving data as a receiver. the bus has to be con- trolled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions, while the 24xx00 works as slave. both master and slave can operate as transmitter or receiver, but the master device deter- mines which mode is activated. 4.0 bus characteristics the following bus protocol has been de?ed: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been de?ed (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 star t data t ransf er (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 0.1 stop data t ransf er (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.3 data v alid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited.
24aa00/24lc00/24c00 ? 1998 microchip technology inc. ds21178c-page 5 4.4 ac kno wledg e each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition (figure 4-2). figure 4-1: data transfer sequence on the serial bus figure 4-2: acknowledge timing note: the 24xx00 does not generate any acknowledge bits if an internal program- ming cycle is in progress. (a) (b) (c) (d) (a) (c) scl sda start condition address or acknowledge valid data allowed to change stop condition scl 9 8 7 6 5 4 3 2 1 123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit
24aa00/24lc00/24c00 ds21178c-page 6 ? 1998 microchip technology inc. 5.0 device addressing after generating a start condition, the bus master transmits a control byte consisting of a slave address and a read/wr ite bit that indicates what type of opera- tion is to be performed. the slave address for the 24xx00 consists of a 4-bit device code (1010) followed by three don't care bits. the last bit of the control byte determines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. (figure 5-1). the 24xx00 monitors the bus for its corresponding slave address all the time. it gener- ates an acknowledge bit if the slave address was true and it is not in a programming mode. figure 5-1: control byte format 6.0 write operations 6.1 byte write following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the r/w bit (which is a logic low) are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24xx00. only the lower four address bits are used by the device, and the upper four bits are don? cares. the 24xx00 will acknowledge the address byte and the master device will then trans- mit the data word to be written into the addressed memory location. the 24xx00 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24xx00 will not generate acknowledge signals (figure 7-2). after a byte write command, the internal address counter will not be incremented and will point to the same address location that was just written. if a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort and no data will be written. if more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. if more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write command will abort and no data will be written. the 24xx00 employs a v cc thresh- old detector circuit which disables the internal erase/ write logic if the v cc is below 1.5v (24aa00 and 24lc00) or 3.8v (24c00) at nominal conditions. 1010xxx sack r/w device select bits don? care bits slave address acknowledge bit start bit read/wr ite bit
24aa00/24lc00/24c00 ? 1998 microchip technology inc. ds21178c-page 7 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be re-sent. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for ?w diagram. figure 7-1: acknowledge polling flow figure 7-2: byte write send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k 10 x 10 x xx x = don? care bit xxx 0
24aa00/24lc00/24c00 ds21178c-page 8 ? 1998 microchip technology inc. 8.0 read operations read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 8.1 current ad dress read the 24xx00 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the device issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (figure 8-1). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, ?st the word address must be set. this is done by sending the word address to the device as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24xx00 will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (figure 8-2). after this command, the internal address counter will point to the address loca- tion following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the device transmits the ?st data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the device to transmit the next sequentially addressed 8-bit word (figure 8-3). to provide sequential reads the 24xx00 contains an internal address pointer which is incremented by one at the completion of each read operation. this address pointer allows the entire memory contents to be serially read during one operation. figure 8-1: current address read figure 8-2: random read figure 8-3: sequential read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00xxx1 x = don? care bit p bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k x xxx s1 1 00xxx0 s1 1 00xxx1 x = don? care bit p bus activity master sda line bus activity s t o p control byte a c k n o a c k data n data n + 1 data n + 2 data n + x a c k a c k a c k
24aa00/24lc00/24c00 ? 1998 microchip technology inc. ds21178c-page 9 notes:
24aa00/24lc00/24c00 ds21178c-page 10 ? 1998 microchip technology inc. notes:
24aa00/24lc00/24c00 ? 1998 microchip technology inc. ds21178c-page 11 24xx00 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales of?e. sales and suppor t package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body) st = tssop, 8-lead ot = sot-23, 5-lead temperature range: blank = 0?c to +70?c i = ?0?c to +85?c e = ?0?c to +125?c device: 24aa00 128 bit 1.8v i 2 c serial eeprom 24aa00t 128 bit 1.8v i 2 c serial eeprom (tape and reel) 24lc00 128 bit 2.5v i 2 c serial eeprom 24lc00t 128 bit 2.5v i 2 c serial eeprom (tape and reel) 24c00 128 bit 5.0v i 2 c serial eeprom 24c00t 128 bit 5.0v i 2 c serial eeprom (tape and reel) 24xx00 /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales of?e 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide web site (www.microchip.com)
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip t echnology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectua l property rights arising from such use or otherwise. use of microchip s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or other wise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip t echnology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21178c-page 12 ? 1998 microchip technology inc. all rights reserved. ?1998, microchip technology incorporated, usa. 7/98 printed on recycled paper. m americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602 786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. 42705 grand river, suite 201 novi, mi 48375-1727 tel: 248-374-1888 fax: 248-374-2878 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia paci? rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison of?e no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?n road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-1189-21-5858 fax: 44-1189-21-5835 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 m?chen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 6/11/98 w orldwide s ales and s ervice microchip received iso 9001 quality system certi?ation for its worldwide headquarters, design, and wafer fabrication facilities in january, 1997. our ?ld-programmable picmicro 8-bit mcus, serial eeproms, related specialty memory products and development systems conform to the stringent quality standards of the international standard organization (iso).

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