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isplsi 2064ve 3.3v in-system programmable high density superfast pld 2064v e_07 1 features superfast high density programmable logic ?2000 pld gates ?64 and 32 i/o pin versions, four dedicated inputs ?64 registers ?high speed global interconnect ?wide input gating for fast counters, state machines, address decoders, etc. ?small logic block size for random logic ?100% functional, jedec and pinout compatible with isplsi 2064v devices 3.3v low voltage 2064 architecture ?interfaces with standard 5v ttl devices high-performance e 2 cmos technology ? f max = 280mhz maximum operating frequency ? t pd = 3.5ns propagation delay ?electrically erasable and reprogrammable ?non-volatile ?100% tested at time of manufacture ?unused product term shutdown saves power in-system programmable 3.3v in-system programmability (isp) using boundary scan test access port (tap) open-drain output option for flexible bus interface capability, allowing easy implementation of wired-or or bus arbitration logic increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping 100% ieee 1149.1 boundary scan testable the ease of use and fast system speed of plds with the density and flexibility of fpgas ?enhanced pin locking capability ?three dedicated clock input pins ?synchronous and asynchronous clocks ?programmable output slew rate control ?flexible pin placement ?optimized global routing pool provides global interconnectivity ispdesignexpert ?logic compiler and com- plete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms functional block diagram global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) b3 b2 b1 b0 input bus output routing pool (orp) a2 glb logic array dq dq dq dq a4 a5 a6 a7 b7 b6 b5 b4 input bus output routing pool (orp) input bus output routing pool (orp) 0139a/2064v description the isplsi 2064ve is a high density programmable logic device available in 64 and 32 i/o-pin versions. the device contains 64 registers, four dedicated input pins, three dedicated clock input pins, two dedicated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2064ve features in-system programmability through the boundary scan test ac- cess port (tap) and is 100% ieee 1149.1 boundary scan testable. the isplsi 2064ve offers non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. the basic unit of logic on the isplsi 2064ve device is the generic logic block (glb). the glbs are labeled a0, a1?7 (see figure 1). there are a total of 16 glbs in the isplsi 2064ve device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. copyright ?2001 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. january 2001 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com
2 specifications isplsi 2064ve functional block diagram figure 1. isplsi 2064ve functional block diagram (64-i/o and 32-i/o versions) the 64-i/o 2064ve contains 64 i/o cells, while the 32- i/o version contains 32 i/o cells. each i/o cell is directly connected to an i/o pin and can be individually pro- grammed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. device pins can be safely driven to 5-volt signal levels to support mixed-voltage systems. eight glbs, 32 or 16 i/o cells, two dedicated inputs and two or one orps are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 32 or 16 universal i/o cells by two or one orps. each isplsi 2064ve device contains two megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2064ve device are selected using the dedicated clock pins. three dedicated clock pins (y0, tdo/in 2 global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) b3 b2 b1 b0 input bus output routing pool (orp) a2 clk 0 clk 1 clk 2 goe 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 tdi/in 0 tms/in 1 i/o 4 i/o 5 bscan reset 0139b/2064ve i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 input bus output routing pool (orp) i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 y0 y1 y2 i/o 31 output routing pool (orp) megablock input bus a4 a5 a6 a7 b7 b6 b5 b4 goe 1 tck/in 3 generic logic blocks (glbs) y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2064ve are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. the default configuration when the device is in bulk erased state is totem-pole configuration. the open-drain/totem-pole option is selectable through the ispdesignexpert software tools. tms/in 2 global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) b3 b2 b1 b0 output routing pool (orp) a2 clk 0 clk 1 clk 2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 tdi/in 0 tdo/in 1 i/o 4 i/o 5 bscan 0139b/2064ve.32io i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 input bus output routing pool (orp) goe1/y0 reset /y1 tck/y2 output routing pool (orp) megablock input bus a4 a5 a6 a7 b7 b6 b5 b4 goe0/in 3 generic logic blocks (glbs) input bus
3 specifications isplsi 2064ve c symbol table 2-0006/2064ve c parameter i/o capacitance 6 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 3.3v, v = 0.0v v = 3.3v, v = 0.0v cc cc i/o in c clock and global output enable capacitance 10 3 pf v = 3.3v, v = 0.0v cc y absolute maximum ratings 1 supply voltage v cc ................................................... -0.5 to +5.4v input voltage applied ..................................... -0.5 to +5.6v off-state output voltage applied .................. -0.5 to +5.6v storage temperature ..................................... -65 to 150 c case temp. with power applied .................... -55 to 125 c max. junction temp. (t j ) with power applied ............ 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition capacitance (ta=25 c, f=1.0 mhz) table 2-0008/2064ve parameter minimum maximum units erase/reprogram cycles 10000 cycles erase reprogram specifications t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/2064v v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 3.0 3.0 2.0 v 0.5 3.6 3.6 5.25 0.8 v v v v ss commercial industrial
4 specifications isplsi 2064ve switching test conditions + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a/2064v figure 2. test load dc electrical characteristics over recommended operating conditions v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using four 16-bit counters. 3. typical values are at v = 3.3v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2064ve 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current bscan input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 0v v v (max.) 0v v v 0v v v v = 3.3v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in il in il cc out clock il ih condition min. typ. max. units 3 2.4 90 0.4 10 10 -10 -150 -150 -100 v v a a a a a ma ma cc a out cc cc (v 0.2)v v v v v 5.25v in cc cc in cc input pulse levels table 2-0003/2064ve input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. 1.5 ns 10% to 90% test condition r1 r2 cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 348 ? 35pf active high active low c 316 ? 348 ? 5pf 348 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/2064v output load conditions (see figure 2)
5 specifications isplsi 2064ve external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030a/2064ve v.0.0 1 3 2 1 tsu2 + tco1 ( ) description # parameter a 1 data propagation delay, 4pt bypass, orp bypass ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass ns t su2 9 glb reg. setup time before clock ns t co2 a 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock ns t r1 a 12 ext. reset pin to output delay, orp bypass ns t rw1 13 ext. reset pulse duration ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t goeen b 16 global oe output enable ns t goedis c 17 global oe output disable ns t wh 18 external synchronous clock pulse duration, high ns t wl 19 external synchronous clock pulse duration, low ns -200 min. max. 4.5 200 0.0 4.0 0.0 4.0 2.5 2.5 133 200 3.0 3.5 4.5 6.0 8.0 8.0 5.0 5.0 7.0 -280 min. max. 3.5 280 0.0 3.0 0.0 3.5 1.6 1.6 182 300 2.3 2.5 3.3 5.5 6.0 6.0 3.5 3.5 5.5
6 specifications isplsi 2064ve external timing parameters over recommended operating conditions t pd1 units -100 min. test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030b/2064ve v.0.0 1 3 2 1 tsu2 + tco1 ( ) max. description # parameter a 1 data propagation delay, 4pt bypass, orp bypass 10.0 ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback 100 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass 0.0 ns t su2 9 glb reg. setup time before clock 8.0 ns t co2 a 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock 0.0 ns t r1 a 12 ext. reset pin to output delay, orp bypass ns t rw1 13 ext. reset pulse duration 6.5 ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t goeen b 16 global oe output enable ns t goedis c 17 global oe output disable ns t wh 18 external synchronous clock pulse duration, high 5.0 ns t wl 19 external synchronous clock pulse duration, low 5.0 ns 77 100 6.5 5.0 6.0 12.5 15.0 15.0 9.0 9.0 13.0 -135 min. max. 7.5 135 0.0 6.0 0.0 5.0 3.5 3.5 100 143 5.0 4.0 5.0 9.0 12.0 12.0 7.0 7.0 10.0
7 specifications isplsi 2064ve internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/2064ve v.0.0 inputs units -280 -200 min. min. max. max. description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb 0.4 0.8 0.4 2.3 2.3 2.3 0.0 0.2 0.4 4.1 2.9 2.9 1.2 1.8 1.1 1.6 1.2 0.4 2.3 2.3 1.2 0.7 0.9 3.5 0.6 1.7 0.8 0.7 0.9 0.5 1.1 0.6 2.9 2.9 2.9 0.0 0.3 0.4 4.3 3.9 4.0 1.5 2.0 1.4 1.9 1.5 0.5 3.0 3.0 2.0 1.2 1.4 3.6 1.2 1.8 1.0 1.2 1.4 ns global reset
8 specifications isplsi 2064ve internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036b/2064ve v.0.0 inputs units -135 min. -100 min. max. max. description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb 0.5 1.7 1.2 4.7 4.7 4.7 0.5 0.3 1.1 6.1 6.9 5.0 1.6 2.0 3.7 3.7 1.5 0.5 3.4 3.4 3.6 1.6 1.8 5.8 1.2 3.8 1.6 1.6 1.8 0.7 2.5 1.8 6.2 6.2 6.2 1.0 0.3 3.1 7.1 9.1 5.6 1.6 2.0 5.2 4.7 1.7 0.7 3.4 3.4 5.6 2.4 2.6 7.1 1.7 4.8 2.6 2.4 2.6 ns global reset
9 specifications isplsi 2064ve isplsi 2064ve timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0,1 #42 #40, 41 0491/2064 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock = = = = t su logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.4 + 0.4 + 2.3) + (0.6) - (0.4 + 0.4 + 0.8) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.4 + 0.4 + 2.9) + (1.7) - (0.4 + 0.4 + 2.3) = = = = t co clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.4 + 0.4 + 2.9) + (0.2) + (1.2 + 1.2) table 2-0042/2064ve note: calculations are based on timing specifications for the isplsi 2064ve-280l. 2.1ns 2.3ns 6.3ns
10 specifications isplsi 2064ve power consumption power consumption in the isplsi 2064ve device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127/2064ve i cc can be estimated for the isplsi 2064ve using the following equation: i cc (ma) = 8 + (# of pts * 0.67) + (# of nets * fmax * 0.0045) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. notes: configuration of four 16-bit counters typical current at 3.3v, 25 c 100 140 0 50 100 150 200 250 300 f max (mhz) isplsi 2064ve 160 180 120 80 i cc (ma)
11 specifications isplsi 2064ve 32-i/o signal descriptions goe 0/in 3 this pin performs one of two functions. it can be programmed to function as a global output enable pin or a dedicated input pin. goe 1/y0 this pin performs one of two functions. (1) it can be programmed to function as a global output enable or a dedicated clock input. (2) this clock input is connected to one of the clock inputs of all glbs on the device. reset /y1 this pin performs two functions: (1) active low (0) reset pin which resets all of the registers in the device. (2) when active low (0), it functions as a dedicated clock input. bscan input dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. tdi/in 0 input this pin performs two functions. (1) when bscan is logic low, it functions as a serial data input pin to load programming data into the device. (2) when bscan is high, it functions as a dedicated input pin. tms/in 2 input this pin performs two functions. (1) when bscan is logic low, it functions as a m ode control pin for the boundary scan state machine. (2) when bscan is high, it functions as a dedicated input pin. tdo/in 1 output/input this pin performs two functions. (1) when bscan is logic low, it functions as an output pin to read serial shift register data. (2) when bscan is high, it functions as a dedicated input pin. tck/y2 input this pin performs two functions. (1) when bscan is logic low, it functions as a clock pin for the boundary scan state machine. (2) when bscan is high, it functions as a dedicated clock input. gnd ground (gnd) vcc vcc nc 1 no connect i/o input/output pins these are the general purpose i/o pins used by the logic array. 64-i/o signal descriptions reset active low (0) reset pin resets all the registers in the device. goe 0, goe1 global output enable input pins. y0, y1, y2 dedicated clock input these clock inputs are connected to one of the clock inputs of all the glbs in the device. bscan input dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. tdi/in 0 input this pin performs two functions. (1) when bscan is logic low, it functions as a serial data input pin to load programming data into the device. w hen bscan is high, it functions as a dedicated input pin. tck/in 3 input this pin performs two functions. (1) when bscan is logic low, it functions as a clock pin for the boundary scan state machine. (2) when bscan is high, it functions as a dedicated input pin. tms/in 1 input this pin performs two functions. (1) when bscan is logic low, it functions as a m ode control pin for the boundary scan state machine. (2) when bscan is high, it functions as a dedicated input pin. tdo/in 2 output/input this pin performs two functions. (1) when bscan is logic low, it functions as an output pin to read serial shift register data. (2) when bscan is high, it functions as a dedicated input pin. gnd ground (gnd) vcc vcc nc 1 no connect i/o input/output pins these are the general purpose i/o pins used by the logic array. signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd. signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd.
12 specifications isplsi 2064ve 64-i/o signal locations 32-i/o signal locations l a n g i sa g b a c l l a b - 0 0 1p f q t n i p - 0 0 1 t e s e r 2 d1 1 1 e o g , 0 e o g1 e , 9 f3 1 , 2 6 2 y , 1 y , 0 y8 f , 6 f , 3 e0 6 , 5 6 , 0 1 n a c s b 5 e5 1 0 n i / i d t2 f6 1 3 n i / k c t0 1 g9 5 1 n i / s m t5 j7 3 2 n i / o d t6 b7 8 d n g6 k , 9 g , 1 f , 7 b6 8 , 1 6 , 9 3 , 4 1 c c v4 j , 0 1 f , 2 e , 5 a9 8 , 3 6 , 6 3 , 2 1 c n 1 , 4 c , 3 c , 8 a , 6 a , 7 e , 8 d , 6 d , 1 d , 4 f , 0 1 e , 9 e , 8 h , 7 h , 5 g , 3 g 5 k , 3 k , 5 2 , 1 2 , 9 , 4 , 0 5 , 4 4 , 8 3 , 1 3 , 1 7 , 6 6 , 4 6 , 4 5 , 4 9 , 8 8 , 1 8 , 5 7 0 0 1 , s l a n g i s e v i t c a y n a o t d e t c e n n o c e b o t t o n e r a s n i p c n . 1 . d n g r o c c v l a n g i sp f q t n i p - 4 4c c l p n i p - 4 4 3 n i / 0 e o g0 42 0 y / 1 e o g5 1 1 t e s e r 1 y / 9 25 3 n a c s b 73 1 0 n i / i d t8 4 1 2 n i / s m t0 36 3 1 n i / o d t8 14 2 2 y / k c t7 23 3 d n g9 3 , 7 13 2 , 1 c c v8 2 , 64 3 , 2 1 c n 1 , s l a n g i s e v i t c a y n a o t d e t c e n n o c e b o t t o n e r a s n i p c n . 1 . d n g r o c c v i/o locations i/o 0 g1 17 9 15 i/o 1f3181016 i/o 2e4191117 i/o 3h1201218 i/o 4g2221319 i/o 5j1231420 i/o 6h2241521 i/o 7k1261622 i/o 8j2271925 i/o 9k2282026 i/o 10 h3 29 21 27 i/o 11 j3 30 22 28 i/o 12 g4 32 23 29 i/o 13 h4 33 24 30 i/o 14 k4 34 25 31 i/o 15 h5 35 26 32 i/o 16 f5 40 31 37 i/o 17 j6 41 32 38 i/o 18 k7 42 33 39 i/o 19 h6 43 34 40 i/o 20 k8 45 35 41 i/o 21 g6 46 36 42 i/o 22 j7 47 37 43 i/o 23 k9 48 38 44 i/o 24 j8 49 41 3 i/o 25 k10 51 42 4 i/o 26 j9 52 43 5 i/o 27 j10 53 44 6 i/o 28 h9 55 1 7 i/o 29 h10 56 2 8 i/o 30 g7 57 3 9 i/o 31 g8 58 4 10 i/o 32 d10 67 i/o 33 e8 68 i/o 34 f7 69 i/o 35 c10 70 i/o 36 d9 72 i/o 37 b10 73 i/o 38 c9 74 i/o 39 a10 76 i/o 40 b9 77 i/o 41 a9 78 i/o 42 c8 79 i/o 43 b8 80 i/o 44 d7 82 i/o 45 c7 83 i/o 46 a7 84 i/o 47 c6 85 i/o 48 e6 90 i/o 49 b5 91 i/o 50 a4 92 i/o 51 c5 93 i/o 52 a3 95 i/o 53 d5 96 i/o 54 b4 97 i/o 55 a2 98 i/o 56 b3 99 i/o 57 a1 1 i/o 58 b2 2 i/o 59 b1 3 i/o 60 c2 5 i/o 61 c1 6 i/o 62 d4 7 i/o 63 d3 8 100 100 44 44 signal cabga tqfp tqfp plcc
13 specifications isplsi 2064ve signal configuration isplsi 2064ve 100-ball cabga signal diagram (0.8mm ball pitch/10.0 x 10.0mm body size) 10987654321 a b c d e f g h j k a b c d e f g h j k 10987654321 i/o 39 i/o 41 i/o 46 i/o 50 i/o 52 i/o 55 i/o 57 nc 1 nc 1 vcc i/o 35 i/o 38 i/o 42 i/o 45 i/o 47 i/o 51 i/o 60 i/o 61 nc 1 nc 1 tck/ in 3 i/o 31 i/o 30 i/o 21 i/o 12 i/o 4 i/o 0 nc 1 gnd nc 1 i/o 29 i/o 28 i/o 19 i/o 13 i/o 10 i/o 15 i/o 6 i/o 3 nc 1 nc 1 i/o 27 i/o 26 i/o 24 i/o 22 i/o 17 i/o 11 tms/ in 1 i/o 8 i/o 5 vcc i/o 25 1 ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. i/o 23 i/o 20 i/o 18 i/o 14 i/o 9 i/o 7 gnd nc 1 nc 1 goe 0 i/o 34 i/o 16 i/o 1 tdi/ in 0 nc 1 gnd 100-bga/2064ve vcc y2 y1 i/o 32 i/o 36 i/o 44 i/o 53 i/o 62 i/o 63 nc 1 nc 1 nc 1 reset i/o 33 i/o 48 i/o 2 goe 1 nc 1 vcc y0 nc 1 nc 1 bscan i/o 37 i/o 40 i/o 43 i/o 54 i/o 49 tdo/ in 2 i/o 56 i/o 58 i/o 59 gnd isplsi 2064ve bottom view
14 specifications isplsi 2064ve pin configuration isplsi 2064ve 100-pin tqfp pinout diagram (0.5mm lead pitch/14.0 x 14.0mm body size) i/o 57 i/o 58 i/o 59 1 nc i/o 60 i/o 61 i/o 62 i/o 63 1 nc y0 reset vcc goe 1 gnd bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 1 nc i/o 4 i/o 5 i/o 6 1 nc nc 1 i/o 38 i/o 37 i/o 36 nc 1 i/o 35 i/o 34 i/o 33 i/o 32 nc 1 y1 nc 1 vcc goe 0 gnd y2 tck/in 3 i/o 31 i/o 30 i/o 29 i/o 28 nc 1 i/o 27 i/o 26 i/o 25 nc 1 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 nc 1 i/o 51 i/o 50 i/o 49 i/o 48 vcc nc 1 tdo/in 2 gnd i/o 47 i/o 46 i/o 45 i/o 44 nc 1 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 1 nc i/o 12 i/o 13 i/o 14 i/o 15 vcc tms/in 1 1 nc gnd i/o 16 i/o 17 i/o 18 i/o 19 1 nc i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 1 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 isplsi 2064ve top view 1. nc pins are not to be connected to any active signals, vcc or gnd. 100 tqfp/2064ve
15 specifications isplsi 2064ve pin configuration isplsi 2064ve 44-pin plcc pinout diagram (0.05in lead pitch/0.65 x 0.65in body size) i/o 18 i/o 17 i/o 16 tms/in 2 reset /y1 vcc tck/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 goe1/y0 vcc bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0/in 3 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2064ve top view 1 2 3 4 6 5 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 44 tqfp/2064ve i/o 18 i/o 17 i/o 16 tms/in 2 reset /y1 vcc tck/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 goe1/y0 vcc bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0/in 3 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2064ve top view 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 18 5 19 4 20 3 21 2 22 1 23 44 24 43 25 42 26 41 27 40 28 44 plcc/2064ve pin configuration isplsi 2064ve 44-pin tqfp pinout diagram (0.8mm lead pitch/10.0 x 10.0mm body size)
16 specifications isplsi 2064ve part number description isplsi 2064ve ordering information 135 7.5 100-pin tqfp isplsi 2064ve-135lt100 table 2-0041a/2064ve 135 100-ball cabga 7.5 isplsi 2064ve-135lb100 family f max (mhz) 200 ordering number package 100-pin tqfp t pd (ns) 4.5 isplsi isplsi 2064ve-200lt100 64 64 135 7.5 44-pin plcc isplsi 2064ve-135lj44 135 44-pin tqfp 7.5 isplsi 2064ve-135lt44 32 32 i/os 64 200 100-ball cabga 4.5 isplsi 2064ve-200lb100 64 280 100-pin tqfp 3.5 isplsi 2064ve-280lt100 64 280 100-ball cabga 3.5 isplsi 2064ve-280lb100 64 200 44-pin plcc 4.5 isplsi 2064ve-200lj44 32 200 44-pin tqfp 4.5 isplsi 2064ve-200lt44 32 280 44-pin tqfp 3.5 isplsi 2064ve-280lt44 32 100 100 100-pin tqfp 10 10 isplsi 2064ve-100lt100 100-ball cabga isplsi 2064ve-100lb100 64 64 100 100 44-pin plcc 10 10 isplsi 2064ve-100lj44 44-pin tqfp isplsi 2064ve-100lt44 32 32 commercial table 2-0041b/2064ve isplsi 135 7.5 100-pin tqfp isplsi 2064ve-135lt100i 64 135 7.5 44-pin tqfp isplsi 2064ve-135lt44i 32 industrial family f max (mhz) ordering number package t pd (ns) i/os device number isplsi 2064ve xxx x xxxx grade blank = commercial i = industrial x speed 280 = 280 mhz f max 200 = 200 mhz f max 135 = 135 mhz f max 100 = 100 mhz f max power l = low package t100 = 100-pin tqfp b100 = 100-ball cabga t44 = 44-pin tqfp j44 = 44-pin plcc device family 0212/2064ve

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