april 1999 f dc6561an dual n-channel logic level powertrench tm mosfet general description features absolute maximum ratings t a = 25c unless otherwise note symbol parameter ratings units v dss drain-source voltage 30 v v gss gate-source voltage - continuous 20 v i d drain current - continuous 2.5 a - pulsed 10 p d maximum power dissipation ( note 1a) 0.96 w (note 1b) 0.9 (note 1c) 0.7 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 130 c/w r q jc thermal resistance, junction-to-case (note 1) 60 c/w FDC6561AN rev.c these n- channel logic level mosfets are produced using fairchild semiconductor 's advanced powertrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance . these devices are well suited for all applications where small size is desireable but especially low cost dc/dc conversion in battery powered systems. 2.5 a, 3 0 v. ?r ds(on ) = 0.095 w @ v gs = 10 v r ds(on ) = 0.145 w @ v gs = 4 .5 v very fast switching. low gate charge (2.1nc typical). supersot tm -6 package: small footprint (72 % smaller than s tandard so-8); l ow profile (1mm thick). soic-16 sot-23 supersot t m -8 so-8 sot-223 supersot t m -6 d1 s2 g1 d2 s1 g2 supersot -6 tm pin 1 .561 1 5 3 2 6 4 ? 1999 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 23.6 mv/ o c i dss zero gate voltage drain current v ds = 24 v , v gs = 0 v 1 a t j = 55 o c 10 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.8 3 v d v gs(th) / d t j gate threshold voltage temp.coefficient i d = 250 a , referenced to 25 o c -4 mv/ o c r ds(on) static drain-source on-resistance v gs = 10 v, i d = 2.5 a 0.082 0.095 w t j = 125 o c 0.122 0.152 v gs = 4.5 v, i d = 2.0 a 0.113 0.145 i d (on) on-state drain current v gs = 10 v, v ds = 5 v 10 a g fs forward transconductance v ds = 5 v, i d = 2.5 a 5 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, 220 pf c oss output capacitance f = 1.0 mhz 50 pf c rss reverse transfer capacitance 25 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = 5 v, i d = 1 a, 6 12 ns t r turn - on rise time v gs = 10 v, r gen = 6 w 10 18 ns t d(off) turn - off delay time 12 22 ns t f turn - off fall time 2 6 ns q g total gate charge v ds = 15 v, i d = 2 .5 a 2.3 3.2 nc q gs gate-source charge v gs = 5 v 0.7 1 nc q gd gate-drain charge 0.9 1.3 nc drain-source diode characteristics i s continuous source diode current 0.75 a v sd drain-source diode forward voltage v gs = 0 v, i s = 0.75 a (note 2 ) 0.78 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. FDC6561AN rev.c c. 180 o c/w on a minimum pad. b . 140 o c/w on a 0.005 in 2 pad of 2oz copper. a . 130 o c/w on a 0.125 in 2 pad of 2oz copper.
FDC6561AN rev.c 0 1 2 3 4 0 2 4 6 8 10 v , drain-source voltage (v) i , drain-source current (a) v =10v gs 3.5v 4.5v 4.0v ds d 6.0v 3.0v 0 2 4 6 8 10 0.8 1 1.2 1.4 1.6 1.8 2 i , drain current (a) drain-source on-resistance v = 4.0v gs 10v 6.0v 4.5v d 7.0v r , normalized 5.0v ds(on) typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 3. on-resistance variation with temperature . figure 5. transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.0001 0.001 0.01 0.1 1 10 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c a 25c -55c v = 0v gs sd s figure 4 . on-resistance variation with gate-t o -source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = 10 v gs i = 2.5 a d r , normalized ds(on) 2 4 6 8 10 0.05 0.1 0.15 0.2 0.25 0.3 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) t = 25c a i = 1.3a d t = 125c a 1 2 3 4 5 6 0 2 4 6 8 10 v , gate to source voltage (v) i , drain current (a) gs 25c 125c v = 5v ds d t = -55c a figure 6 . body diode forward voltage varia tion with source current and temperature.
FDC6561AN rev.c figure 10 . single pulse maximum power dissipation. 0.1 0.5 1 2 5 10 30 10 20 50 100 200 500 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical characteristics (continued) 0 1 2 3 4 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs i = 2.5a d 10v 15v v = 5v ds 0.1 0.3 1 3 10 30 50 0.01 0.03 0.1 0.3 1 3 10 30 v , drain-source voltage (v) i , drain current (a) ds d rds(on) limit v = 10v single pulse r =180c/w t = 25c gs a q ja dc 1s 10ms 100ms 1ms 100us 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =180c/w t = 25c a q ja figure 11 . transient thermal response curve . thermal characterization performed using the conditions described in n ote 1c . transient thermal response will change depending on the circuit board design. 0.0001 0.001 0.01 0.1 1 10 100 300 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 r(t), normalized effective duty cycle, d = t / t 1 2 t - t = p * r (t) q ja a j p(pk) t 1 t 2 r (t) = r(t) * r r = 180 c/w q ja q ja q ja
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