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ramtron international corporation ? http://www.ramtron.com 1850 ramtron drive colorado springs ? mcu customer service: 1 - 800 - 943 - 4625, 1 - 514 - 871 - 2447, ext. 20 8 colorado , usa, 8092 1 ? 1 - 800 - 545 - fram, 1 - 719 - 481 - 7000 page 1 of 50 VRS51C1100 datasheet rev 1. 1 versa 8051 mcu with 128kb of iap/isp flash overview the VRS51C1100 is based on the standard 8051 microcontroller architecture and is a pin compatible drop - in replacement for the 8051. the VRS51C1100 is a imed at a diversity of applications that require a large amount of program/data memory with non - volatile data storage and/or code/field based firmware upgrade capability coupled with comprehensive peripheral support . it features 64k b of in - system/in - application programmable flash memory , 64k b data flash me mory , 1k b of ram , 4 pwm outputs, a uart, three 16 - bit timers/counters, a watchdog timer and power down features. the vrs51c1000 is available with firmware that enables in - system programming (firmware based boot - loader) of the flash memory via the uart int erface (ispvx version). general flash memory programming is supported by device programmers available from ramtron or other 3rd party commercial programmer suppliers. the VRS51C1100 is available in plcc - 44 , qfp - 44 and dip - 40 packages and functions over the industrial temperature range. f igure 1: VRS51C1100 f unctional d iagram port 0 8051 processor port 3 port 2 port 1 pwm port 4 64 kb program flash 2 interrupt inputs uart 1024 bytes of ram reset timer 0 timer 2 timer 1 power control watchdog timer address / data bus 8 8 8 8 4 4 64 kb data flash feature set 80 c 51 /80c5 2 pin compatible 64k b program + 64k b data flash memory in - system / in - application flash programming (is p/iap) program voltage: 5v 1024 bytes on chip data ram four 8 - bit i/os + one 4 - bit i/o 4 pwm outputs on p1.3 to p1.7 one full duplex uart serial port three 16 - bit timers/counters watch d og timer bit operation instruction 8 - bit unsigned multiply and divis ion instructions bcd arithmetic direct and indirect addressing two levels of interrupt priority and nested interrupts power saving modes code protection function low emi (inhibit ale) operating temperature range - 40oc to +85oc f igure 2: VRS51C1100 qfp - 44 and plcc - 44 p in out d iagrams 1 44 11 12 22 23 33 34 vrs 51 c 1100 qfp - 44 p 2 . 6 / a 1 4 p 2 . 5 / a 1 3 # p s e n p 2 . 7 / a 1 5 p 4 . 1 a l e p 0 . 7 / a d 7 # e a p 0 . 5 / a d 5 p 0 . 6 / a d 6 p 0 . 4 / a d 4 # rd / p 3 . 7 # wr / p 3 . 6 xtal 1 xtal 2 p 4 . 0 vss p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 11 p 2 . 2 / a 10 p 2 . 4 / a 12 p 1 . 6 p w m 3 / p 1 . 5 r e s p 1 . 7 p 4 . 3 r x d / p 3 . 0 # i n t 0 / p 3 . 2 t x d / p 3 . 1 t 0 / p 3 . 4 # i n t 1 / p 3 . 3 t 1 / p 3 . 5 pwm 1 / p 1 . 3 pwm 2 / p 1 . 4 t 2 ex / p 1 . 1 pwm 0 / p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / ad 0 vdd p 0 . 2 / ad 2 p 0 . 1 / ad 1 p 0 . 3 / ad 3 p 1 . 6 pwm 3 / p 1 . 5 res p 1 . 7 p 4 . 3 rxd / p 3 . 0 # int 0 / p 3 . 2 txd / p 3 . 1 t 0 / p 3 . 4 # int 1 / p 3 . 3 t 1 / p 3 . 5 # r d / p 3 . 7 # w r / p 3 . 6 x t a l 1 x t a l 2 p 4 . 0 v s s p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 1 1 p 2 . 2 / a 1 0 p 2 . 4 / a 1 2 p 2 . 6 / a 14 p 2 . 5 / a 13 # psen p 2 . 7 / a 15 p 4 . 1 ale p 0 . 7 / ad 7 # ea p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 4 / ad 4 p w m 1 / p 1 . 3 p w m 2 / p 1 . 4 t 2 e x / p 1 . 1 p w m 0 / p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / a d 0 v d d p 0 . 2 / a d 2 p 0 . 1 / a d 1 p 0 . 3 / a d 3 1 vrs 51 c 1000 plcc - 44 6 7 17 18 28 29 39 40
VRS51C1100 _______________________________________________________________________________________________ www.ramtro n.com page 2 of 50 pin descriptions for qfp - 44/plcc - 44 t able 1: p in d escriptions for qfp - 44/plcc - 44 qfp - 44 plcc - 44 name i/o function pwm3 o pwm channel 3 1 7 p1.5 i/o bit 5 of port 1 2 8 p1.6 i/o bit 6 of port 1 3 9 p1.7 i/o bit 7 of port 1 4 10 res i reset rxd i receive data 5 11 p3.0 i/o bit 0 of port 3 6 12 p4.3 i/o bit 3 of port 4 txd o transmit data & 7 13 p3.1 i/o b it 1 of port 3 #int0 i external interrupt 0 8 14 p3.2 i/o bit 2 of port 3 #int1 i external interrupt 1 9 15 p3.3 i/o bit 3 of port 3 t0 i timer 0 10 16 p3.4 i/o bit 4 of port 3 t1 i timer 1 & 3 11 17 p3.5 i/o bit 5 of port #wr o ext. memory write 12 18 p3.6 i/o bit 6 of port 3 #rd o ext. memory read 13 19 p3.7 i/o bit 7 of port 3 14 20 xtal2 o oscillator/crystal output 15 21 xtal1 i oscillator/crystal in 16 22 vss - ground 17 23 p4.0 i/o bit 0 of p ort 4 p2.0 i/o bit 0 of port 2 18 24 a8 o bit 8 of external memory address p2.1 i/o bit 1 of port 2 19 25 a9 o bit 9 of external memory address p2.2 i/o bit 2 of port 2 20 26 a10 o bit 10 of external memory address p2.3 i/o bit 3 of port 2 & 21 27 a11 o bit 11 of ex ternal memory address p2.4 i/o bit 4 of port 2 22 28 a12 o bit 12 of external memory address p2.5 i/o bit 5 of port 2 23 29 a13 o bit 13 of external memory address qfp - 44 plcc - 44 name i/o function p2.6 i/o bit 6 of port 2 24 30 a14 o bit 14 of external memory address p2.7 i/o bit 7 of port 2 25 31 a15 o bit 15 of external memory address 26 32 #psen o program store enable 27 33 ale o address latch enable 28 34 p4.1 i/o bit 1 of port 4 29 35 #ea i external access p0.7 i/o bit 7 of port 0 30 36 ad7 i/o data/address bit 7 of external memory p0.6 i/o bit 6 of port 0 31 37 ad6 i/o data/address bit 6 of external memory p0.5 i/o bit 5 of port 0 32 38 ad5 i/o data/address bit 5 of external memory p0.4 i /o bit 4 of port 0 33 39 ad4 i/o data/address bit 4 of external memory p0.3 i/o bit 3 of port 0 34 40 ad3 i/o data/address bit 3 of external memory p0.2 i/o bit 2 of port 0 35 41 ad2 i/o data/address bit 2 of external memory p0. 1 i/o bit 1 of port 0 & data 36 42 ad1 i/o address bit 1 of external memory p0.0 i/o bit 0 of port 0 & data 37 43 ad0 i/o address bit 0 of external memory 38 44 vdd - vcc 39 1 p4.2 i/o bit 2 of port 4 t2 i timer 2 clock out 40 2 p1.0 i/o bit 0 of port 1 t2ex i timer 2 control 41 3 p1.1 i/o bit 1 of port 1 pwm0 o pwm channel 0 42 4 p1.2 i/o bit 2 of port 1 pwm1 o pwm channel 1 43 5 p1.3 i/o bit 3 of port 1 pwm2 o pwm channel 2 44 6 p1.4 i/o bit 4 of port 1 44 11 12 22 23 33 32 31 30 29 28 27 26 25 24 34 vrs 51 c 1100 qfp - 44 p 2 . 6 / a 1 4 p 2 . 5 / a 1 3 # p s e n p 2 . 7 / a 1 5 p 4 . 1 a l e p 0 . 7 / a d 7 # e a p 0 . 5 / a d 5 p 0 . 6 / a d 6 p 0 . 4 / a d 4 # rd / p 3 . 7 # wr / p 3 . 6 xtal 1 xtal 2 p 4 . 0 vss p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 11 p 2 . 2 / a 10 p 2 . 4 / a 12 p 1 . 6 p w m 3 / p 1 . 5 r e s p 1 . 7 p 4 . 3 r x d / p 3 . 0 # i n t 0 / p 3 . 2 t x d / p 3 . 1 t 0 / p 3 . 4 # i n t 1 / p 3 . 3 t 1 / p 3 . 5 pwm 1 / p 1 . 3 pwm 2 / p 1 . 4 t 2 ex / p 1 . 1 pwm 0 / p 1 . 2 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / ad 0 vdd p 0 . 2 / ad 2 p 0 . 1 / ad 1 p 0 . 3 / ad 3 21 20 19 18 17 16 15 14 13 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 p w m 0 / p 1 . 2 p 1 . 6 pwm 3 / p 1 . 5 res p 1 . 7 p 4 . 3 rxd / p 3 . 0 # int 0 / p 3 . 2 txd / p 3 . 1 t 0 / p 3 . 4 # int 1 / p 3 . 3 t 1 / p 3 . 5 # r d / p 3 . 7 # w r / p 3 . 6 x t a l 1 x t a l 2 p 4 . 0 v s s p 2 . 1 / a 9 p 2 . 0 / a 8 p 2 . 3 / a 1 1 p 2 . 2 / a 1 0 p 2 . 4 / a 1 2 p 2 . 6 / a 14 p 2 . 5 / a 13 # psen p 2 . 7 / a 15 p 4 . 1 ale p 0 . 7 / ad 7 # ea p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 4 / ad 4 p w m 1 / p 1 . 3 p w m 2 / p 1 . 4 t 2 e x / p 1 . 1 p 4 . 2 t 2 / p 1 . 0 p 0 . 0 / a d 0 v d d p 0 . 2 / a d 2 p 0 . 1 / a d 1 p 0 . 3 / a d 3 1 6 7 17 18 28 29 39 40 2 3 4 5 8 9 10 13 12 11 15 14 16 19 20 21 22 23 24 26 25 27 30 33 32 31 35 34 37 36 38 41 44 43 42 vrs 51 c 1100 plcc - 44 p2.6/a14 p2.5/a13 #psen p2.7/a15 p4.1 ale p0.7/ad7 #ea p0.5/ad5 p0.6/ad6 p0.4/ad4
VRS51C1100 _______________________________________________________________________________________________ www.ramtro n.com page 3 of 50 vrs51c11 00 dip40 pin descriptions t able 2: VRS51C1100 p in d escriptions for dip40 package dip40 name i/o function t2 i timer 2 clock out 1 p1.0 i/o bit 0 of port 1 t2ex i timer 2 control 2 p1.1 i/o bit 1 of port 1 pwm0 o pwm channe l 0 3 p1.2 i/o bit 2 of port 1 pwm1 o pwm channel 1 4 p1.3 i/o bit 3 of port 1 pwm2 o pwm channel 2 5 p1.4 i/o bit 4 of port 1 pwm3 o pwm channel 3 6 p1.5 i/o bit 5 of port 1 7 p1.6 i/o bit 6 of port 1 8 p1.7 i/o bit 7 of port 1 9 reset i reset rxd i receive data 10 p3.0 i/o bit 0 of port 3 txd o transmit data & 11 p3.1 i/o bit 1 of port 3 #int0 i external interrupt 0 12 p3.2 i/o bit 2 of port 3 #int1 i external interrupt 1 13 p3.3 i/o bit 3 of port 3 t0 i timer 0 14 p3.4 i/o bi t 4 of port 3 t1 i timer 1 & 3 15 p3.5 i/o bit 5 of port #wr o ext. memory write 16 p3.6 i/o bit 6 of port 3 #rd o ext. memory read 17 p3.7 i/o bit 7 of port 3 18 xtal2 o oscillator/crystal output 19 xtal1 i oscillator/crystal in 20 vss - gro und t 2 / p 1 . 0 t 2 ex / p 1 . 1 pwm 0 / p 1 . 2 pwm 1 / p 1 . 3 pwm 2 / p 1 . 4 pwm 3 / p 1 . 5 p 1 . 6 p 1 . 7 reset rxd / p 3 . 0 txd / p 3 . 1 # int 0 / p 3 . 2 # int 1 / p 3 . 3 t 0 / p 3 . 4 t 1 / p 3 . 5 # wr / p 3 . 6 # rd / p 3 . 7 xtal 2 xtal 1 vss vrs 51 c 1100 dip - 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vdd p 0 . 0 / ad 0 p 0 . 1 / ad 1 p 0 . 2 / ad 2 p 0 . 3 / ad 3 p 0 . 4 / ad 4 p 0 . 5 / ad 5 p 0 . 6 / ad 6 p 0 . 7 / ad 7 # ea / vpp ale psen p 2 . 7 / a 15 p 2 . 6 / a 14 p 2 . 5 / a 13 p 2 . 4 / a 12 p 2 . 3 / a 11 p 2 . 2 / a 10 p 2 . 1 / a 9 p 2 . 0 / a 8 dip40 name i/o function p2.0 i/o bit 0 of port 2 21 a8 o bit 8 of external memory address p2.1 i/o bit 1 of port 2 22 a9 o bit 9 of external memory address p2.2 i/o bit 2 of port 2 23 a10 o bit 10 of ext ernal memory address p2.3 i/o bit 3 of port 2 & 24 a11 o bit 11 of external memory address p2.4 i/o bit 4 of port 2 25 a12 o bit 12 of external memory address p2.5 i/o bit 5 of port 2 26 a13 o bit 13 of external memory address p2.6 i/o bit 6 of port 2 27 a14 o bit 14 of external memory address p2.7 i/o bit 7 of port 2 28 a15 o bit 15 of external memory address 29 #psen o program store enable 30 ale o address latch enable 31 #ea / vpp i external access flash programming voltage input p0.7 i/o bit 7 of port 0 32 ad7 i/o data/address bit 7 of external memory p0.6 i/o bit 6 of port 0 33 ad6 i/o data/address bit 6 of external memory p0.5 i/o bit 5 of port 0 34 ad5 i/o data/address bit 5 of external memory p0.4 i/o bit 4 of por t 0 35 ad4 i/o data/address bit 4 of external memory p0.3 i/o bit 3 of port 0 36 ad3 i/o data/address bit 3 of external memory p0.2 i/o bit 2 of port 0 37 ad2 i/o data/address bit 2 of external memory p0. 1 i/o bit 1 of port 0 & data 38 ad1 i/o address bit 1 of external memory p0.0 i/o bit 0 of port 0 & data 39 ad0 i/o address bit 0 of external memory 40 vdd - supply input
VRS51C1100 _______________________________________________________________________________________________ www.ramtro n.com page 4 of 50 instruction set the following table describes the VRS51C1100 instruction set. the instructions are function and bi nary code compatible with industry standard 8051 s . t able 3: l egend for i nstruction s et t able symbol function a accumulator rn register r0 - r7 direct internal register address @ri internal register pointed to by r0 or r1 (except mov x) rel two's complement offset byte bit direct bit address #data 8 - bit constant #data 16 16 - bit constant addr 16 16 - bit destination address addr 11 11 - bit destination address t able 4: VRS51C1100 i nstruction s et mnemonic descript ion size (bytes) instr. cycles arithmetic instructions add a, rn add register to a 1 1 add a, direct add direct byte to a 2 1 add a, @ri add data memory to a 1 1 add a, #data add immediate to a 2 1 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 1 addc a, @ri add data memory to a with carry 1 1 addc a, #data add immediate to a with carry 2 1 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 1 subb a, @ri subtract data mem from a with borrow 1 1 subb a, #data subtract immediate from a with borrow 2 1 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 1 inc @ri increment data memory 1 1 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 1 dec @ri decrement data memory 1 1 inc dptr increment data pointer 1 2 mul ab multiply a by b 1 4 div ab divide a by b 1 4 da a decimal adjust a 1 1 logical instructions anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 1 anl a, @ri and data memory to a 1 1 anl a, #data and immediate to a 2 1 anl direct, a and a to direct byte 2 1 anl direct, #data and immediate data to direct byte 3 2 orl a, rn or regist er to a 1 1 orl a, direct or direct byte to a 2 1 orl a, @ri or data memory to a 1 1 orl a, #data or immediate to a 2 1 orl direct, a or a to direct byte 2 1 orl direct, #data or immediate data to direct byte 3 2 xrl a, rn exclusive - or register to a 1 1 xrl a, direct exclusive - or direct byte to a 2 1 xrl a, @ri exclusive - or data memory to a 1 1 xrl a, #data exclusive - or immediate to a 2 1 xrl direct, a exclusive - or a to direct byte 2 1 xrl direct, #data exclusive - or immediate to direct byte 3 2 clr a clear a 1 1 cpl a compliment a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 mnemonic description size (bytes) instr. cycles b oolean instruction clr c clear carry bit 1 1 clr bit clear bit 2 1 setb c set carry bit to 1 1 1 setb bit set bit to 1 2 1 cpl c complement carry bit 1 1 cpl bit complement bit 2 1 anl c,bit logical and between carry and bit 2 2 anl c,#bit logical and between carry and not bit 2 2 orl c,bit logical orl between carry and bit 2 2 orl c,#bit logical orl between carry and not bit 2 2 mov c,bit copy bit value into carry 2 1 mov bit,c copy carry value into bit 2 2 data transfer instructions mov a, r n move register to a 1 1 mov a, direct move direct byte to a 2 1 mov a, @ri move data memory to a 1 1 mov a, #data move immediate to a 2 1 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate t o register 2 1 mov direct, a move a to direct byte 2 1 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 2 mov direct, @ri move data memory to direct byte 2 2 mov direct, #data move immediate to direc t byte 3 2 mov @ri, a move a to data memory 1 1 mov @ri, direct move direct byte to data memory 2 2 mov @ri, #data move immediate to data memory 2 1 mov dptr, #data move immediate to data pointer 3 2 movc a, @a+dptr move code byte relative dptr to a 1 2 movc a, @a+pc move code byte relative pc to a 1 2 movx a, @ri move external data (a8) to a 1 2 movx a, @dptr move external data (a16) to a 1 2 movx @ri, a move a to external data (a8) 1 2 movx @dptr, a move a to external data (a16) 1 2 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange a and register 1 1 xch a, direct exchange a and direct byte 2 1 xch a, @ri exchange a and data memory 1 1 xchd a, @ri exchange a and data memory nibble 1 1 branching instructions acall addr 11 absolute call to subroutine 2 2 lcall addr 16 long call to subroutine 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr 11 absolute jump unconditional 2 2 ljmp addr 16 long jump unconditi onal 3 2 sjmp rel short jump (relative address) 2 2 jc rel jump on carry = 1 2 2 jnc rel jump on carry = 0 2 2 jb bit, rel jump on direct bit = 1 3 2 jnb bit, rel jump on direct bit = 0 3 2 jbc bit, rel jump on direct bit = 1 and clear 3 2 jmp @a+dp tr jump indirect relative dptr 1 2 jz rel jump on accumulator = 0 2 2 jnz rel jump on accumulator 1= 0 2 2 cjne a , direct, rel compare a, direct jne relative 3 2 cjne a, #d, rel compare a, immediate jne relative 3 2 cjne rn, #d, rel compare reg, immed iate jne relative 3 2 cjne @ri, #d, rel compare ind, immediate jne relative 3 2 djnz rn, rel decrement register, jnz relative 2 2 djnz direct, rel decrement direct byte, jnz relative 3 2 miscellaneous instruction nop no operation 1 1 rn: any of the register r0 to r7 @ri: indirect addressing using register r0 or r1 #data: immediate data provided with instruction #data16: immediate data included with instruction bit: address at the bit level rel: relative address to program counter from +127 to ? 128 addr11: 11 - bit address range addr16: 16 - bit address range #d: immediate data supplied with instruction
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 5 of 50 special function registers (sfr) addresses 80h to ffh of the sfr address space can be accessed in direct addressing mode only. the following table list s the VRS51C1100 special function registers . t able 5: s pecial f unction r egisters (sfr) sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value p0 80h - - - - - - - - 1111 1111b sp 81h - - - - - - - - 0000 01 11b dpl 82h - - - - - - - - 0000 0000b dph 83h - - - - - - - - 0000 0000b mpage 85h - - - - - - - - 0000 0000b dbank 86h bse - - - bs3 bs2 bs1 bs0 0000 0001b pcon 87h smod - - - gf1 gf0 pdown idle 0000 0000b tcon 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0 000 0010b tmod 89h gate1 c/t1 m1.1 m0.1 gate0 c/t0 m1.0 m0.0 0000 0000b tl0 8ah - - - - - - - - 0000 0000b tl1 8bh - - - - - - - - 0000 0000b th0 8ch - - - - - - - - 0000 0000b th1 8dh - - - - - - - - 0000 0000b p1 90h - - - - - - - - 1111 1111b wdt key 97h - - - - - - - - 0000 0000b scon 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 0000 0000b sbuf 99h - - - - - - - - 0111 1111b pwme 9bh - - pwm3e pwm2e pwm1e pwm0e - - 0000 0000b wdtctrl 9fh wdte - clear - - ps2 ps1 ps0 0000 0000b p2 a0h - - - - - - - - 1 111 1111b pwmc a3h - - - - - - pdck1 pdck0 0000 0000b pwmd0 a4h pwmd0.4 pwmd0.3 pwmd0.2 pwmd0.1 pwmd0.0 np0.2 np0.1 np0.0 0000 0000b pwmd1 a5h pwmd1.4 pwmd1.3 pwmd1.2 pwmd1.1 pwmd1.0 np1.2 np1.1 np1.0 0000 0000b pwmd2 a6h pwmd2.4 pwmd2.3 pwmd2.2 pwmd2. 1 pwmd2.0 np2.2 np2.1 np2.0 0000 0000b pwmd3 a7h pwmd3.4 pwmd3.3 pwmd3.2 pwmd3.1 pwmd3.0 np3.2 np3.1 np3.0 0000 0000b ie a8h ea - et2 es et1 ex1 et0 ex0 0000 0000b p3 b0h - - - - - - - - 1111 1011b ip b8h - - pt2 ps pt1 px1 pt0 px0 0000 0000b syscon b fh wdr - - - datafe iape xrame alei 0000 1010b t2con c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 0000 0000b rcap2l cah - - - - - - - - 0000 0000b rcap2h cbh - - - - - - - - 0000 0000b tl2 cch - - - - - - - - 0000 0000b th2 cdh 0000 0000b psw d0h cy ac f0 rs1 rs0 ov - p 0000 0001b p4 d8h - - - - p4.3 p4.2 p4.1 p4.0 ****1111b acc e0h - - - - - - - - b f0h - - - - - - - - 0000 0000b iapfadhi f4h fa15 fa14 fa13 fa12 fa11 fa10 fa9 fa8 0000 0000b iapfadlo f5h fa7 fa6 fa5 fa4 fa3 fa2 fa1 fa0 0 000 0000b iapfdata f6h fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 0000 0000b iapfctrl f7h iapstart fzone iapfct 1 iapfct 0 0000 0000b
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 6 of 50 VRS51C1100 program + data flash memory the VRS51C1100 includes 64k b of on - chip flash memory that can be used as program memo ry or as non - volatile data storage memory using the in - application programming feature (iap). the VRS51C1100 also includes 64k b of d ata storage flash memory that is also ia p programm able . isp boot program memory zone the upper portion of the VRS51C1100 fl ash program memory can be reserved to store an isp (in - system programmable) boot loader program. this boot program can be used to program the flash memory via the serial interface ( or via any other method ). by making use of the in - application programmin g (iap) feature . this allows the processor to load the program or data from an external device or system , and to program it into the flash memory ( s ee the VRS51C1100 iap feature section) . the size of the memory block reserved for the isp boot loader progr am (when activated) is adjustable from 512 to 4 k b b ytes in increments of 512 b ytes, using the isp page c onfig parameter. f igure 3: VRS51C1100 - isp p rogram size vs isp c onfig . v alue ispcfg=1 ispcfg=2 ispcfg=3 ispcfg=4 ispcfg=5 ispcfg=6 ispcfg=7 ispcfg=8 ffffh fe00h fc00h fa00h f000h f800h f600h f400h f200h 0000h isp program size = isp page config value x 512bytes programming the isp boo t program the isp boot program is programmed into the device using a parallel programmer, such as the versamcu - ppr , or a commercial parallel programmer that support s the VRS51C1100 . the flash memory reserved for the isp program is defined by the parallel p rogrammer software (isp page config) when the device is programmed. when programming the isp boot program into the VRS51C1100 , the ?lock bit? option should be activated to protect the isp f lash memory zone from being inadvertently erased , which can happe n when flash erase operations are performed under the control of the isp boot program , or to prevent the VRS51C1100 f lash memory from being read back using a parallel programmer. if an erase operation is performed using a parallel programmer, the entire f lash memory, including the isp boot program memory zone , will be erased. isp boot program start conditions setting the isp page configuration to a value other than 0 will cause the p rocessor to jump to the base address of the isp boot code when a hardwar e reset is performed ( provided that the value ffh is present at program address 0000h ) .
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 7 of 50 an alternate way to force the VRS51C1100 to jump to the isp b oot program is to maintain pin s p2.6 and p2.7 or pin p4.3 at a l ow logic level during a h ardware r ese t, a s shown in the diagram below: f igure 4: VRS51C1100 a lternate isp boot program access 10ms 10ms p2.7 p2.6 res or... p4.3 res 10ms 10ms t he isp boot program can also be accessed via the ljmp instruction. when the isp page configuration is set to 0 wh il e the device is being programmed with a parallel programmer, the isp boot feature will be disabled. VRS51C1100 ispv x firmware b oot p rogram a n isp boot loader program is available for the VRS51C1100 . (ispvx firmware, x = revision, see ramtron website for latest revision) that resides in locations f200h to ffffh in the upper 3.5k b of the VRS51C1100 program flash memory. the ispv x firmware enables in - system - programming of the VRS51C1100 on the final application pcb using the uart interface. the VRS51C1100 can be ordered with or without the ispvx bootloader firmware (see the ordering information section of this datasheet for part number information). see the following figure for a hardware configuration example. other configurations are also possible. f igu re 5: VRS51C1100 i nterface for i n - s ystem p rogramming r s 2 3 2 t r a n s c e i v e r vrs 51 c 1100 rxd txd res creset r s 2 3 2 i n t e r f . to pc 5 1 k 150 k pnp rreset ( with ispv 2 firmware ) visit the ramtron web site to download the ?versa ware isp? window??s application, which enables communication with the ispvx firmware. the ispvx bootloader firmware can also be programmed into the vrs51c1000 by the user. source code is included with the versa ware isp applic ation software. for more information on the ispv x f irmware, please consult the ? VRS51C1100 ispv x firmware user guide.pdf , ? available on the ramtron w eb site. note : the current ispv x f irmware and versa ware software does not allow VRS51C1100 data flash pr ogramming. future versions of both will provide support for VRS51C1100 data flash programming.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 8 of 50 VRS51C1100 iap feature the VRS51C1100 iap feature allows the processor to self - program its p rogram and d ata flash memory from within the user program. five s fr registers serve to control the iap operation. the description of these registers is provided below. system control register the s ystem c ontrol register controls the activation of the d ata flash and the e xpanded ram and serves to monitor the w atch d og t imer s tatus. t able 6: s ystem c ontrol r egister (syscon) ? sfr bf h 7 6 5 4 3 2 1 0 wdr unused dflashe iape xrame alei bit mnemonic description 7 wdr this is the w atch d og t imer reset bit. it will be set to 1 when the reset signal generated by wdt overflows. 6 unused - 5 unused - 4 unused - 3 dflashe data flash memory enable 0: data flash is disabled 1: data flash is enabled 2 iape iap function enable bit 0: iap is disabled 1: isp is enabled 1 xrame 768 byte on - chip enable bit 0 alei ale output inhibit bit, which is used to reduce emi. 0: ale active 1: ale activity is inhibited the wdr bit of the syscon register indicates whether the system has been reset due to the overflow of the w atch d og t imer. for this reason , users shou ld check the wdr bit whenever an unexpected reset occurs. setting the dflashe bit of the syscon register to 1 activate s the 64k b on - chip d ata flash memory , which is disabled by default. the iape bit is used to a ctivate the iap function. when set to 1 , the xrame bit enable s the expanded 768 b ytes of ram. bit 0 of this register is the ale output inhibit bit. setting this bit to 1 will inhibit the fosc/6hz clock signal output to the ale pin. iap flash address and data registers the iapfadhi and iapadlo registers are used to specify at which address the iap function will be performed. t able 7: iap f lash a ddress h igh (iapfadhi) - sfr f4 h 7 6 5 4 3 2 1 0 iapfadhi[15:8] t able 8: iap f lash a ddress l ow (iapfadlo) - sfr f5 h 7 6 5 4 3 2 1 0 iapfadlo[15:8] the iapfdata sfr register contains the d ata byte required to perform the iap function. t able 9: iap f lash d ata r egister (iapfdata) - sfr f6 h 7 6 5 4 3 2 1 0 iapfdata[7:0]
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 9 of 50 iap flash contr ol register the VRS51C1100 ?s iap function operation is controlled by the iap flash c ontrol register, iapfctrl. t able 10: iap f lash c ontrol r egister (iapfctrl) - sfr f7 h 7 6 5 4 3 2 1 0 iapfctrl[15:8] bit mnemonic description 7 iap start iap selected operation start sequence 6 unused - 5 fzone flash z one s elect for iap flash operations: 0: flash program zone 1: flash data zone 4 unused - 3 unused - 2 unused - 1 0 iapfct[1:0] flash memory iap function (see below) vrs51c11 00 iap operation s can be performed i n either the 64k b flash p rogram memory zone or the 64k b d ata flash memory z one. the fzone bit selects the area i n which the iap operations will be performed and acts as the 17 th bit of the 128k b f lash address. fzone = 0: iap functions target p rogram flash fzone = 1: iap functions target d ata flash setting the iapstart bit to 1 starts the execution of the iap command specified by the iapfct[1:0] bit s of the iap flash c ontrol register. if the iapstart bit s equal 0, no iap operations will be performed. the iap subsystem handles four different functions. the iap function perform ed is controlled by the iapfct bits , as shown below: t able 11: iap f unctions iapfct[1:0] bits value iap function 00 flash b yte program 01 flash erase protect 10 flash page erase 11 flash erase when activated, t he flash erase function will erase the entire VRS51C1100 flash memory except for the isp boot program , if the isp config bit s (lock) have been activated. be careful when performing flash erase under final application program control. n ote that for security reasons , the iapstart bit of the iapfctrl register is configured as read - only by default. t o set the iapstart to 1 , the following operation sequence must be per formed first : mov iapfdata,#55h mov iapfdata,#aah mov iapfdata,#55h once the start bit is set to 1, the iap subsystem will read the content s of the iap flash a ddress and d ata register s and hold the VRS51C1100 program counter at its current value until th e iap operation is complete. when the iap operation is complete, the iapstart bit will be cleared and the program will continue execut ing. iap byte program in the VRS51C1100 program flash the iap byte program function is used to program a byte into a spe cified p rogram memory location under the control of the iap feature. see t he following program example: iap_prog: mov iapfdata,#55h ;sequence to enable writing mov iapfdata,#0aah ; the iapstart bit mov iapfdata,#55h mov syscon,#04h ;enable iap functio n mov iapfadhi, fadrsh ;set msb of address to program mov iapfadlo,fadrsl ;set lsb of address to program mov iapfdata,fdata ;set data to program mov iapfctrl,#80h ;set the iap start bit + byte program ;**the program counter will stop un til the iap function is completed iap byte program in the VRS51C1100 data flash the iap byte program function can also be used to program a byte into a specified d ata flash memory location under the control of the iap feature. see the following program exa mple: iap_prog: mov iapfdata,#55h ;sequence to enable writing mov iapfdata,#0aah ; the iapstart bit mov iapfdata,#55h mov syscon,#0ch ;enable iap function + enable ;data flash mov iapfadhi, fadrsh ;set msb of address to program mov iapfadlo,fadrsl ; set lsb of address to program mov iapfdata,fdata ;set data to program mov iapfctrl,#a0h ;set the iap start bit + fzone bit ;**the program counter will stop until the iap function is completed
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 10 of 50 iap page erase function by using the iap fea ture, it is possible to perform a p age e rase of the VRS51C1100 p rogram or d ata flash memory (note that the memory area occupied by the isp boot program cannot be page erased) . each page is 512 b ytes in size. to perform a f lash page erase, the page address is specified by the xy (hex) value written into the iapfadhi register . (the value 00h must be written into the iapfadlo registers . ) if the ?y? portion of the iapfadhi register represents an even number, the page that will be erased corresponds to the r ange xy00h to x(y+1)ffh . if the ?y? portion of the iapfadhi register represents an odd number, the page that will be erased corresponds to the range x(y - 1)00h to xyffh . the following program example demonstrates how to erase the page corresponding to the address b000h - cfffh in the p rogram m emory zone: ;** erase flash program page located at address b000h to cfffh. pageerase: mov iapfdata,#55h ;sequence to enable writing mov iapfdata,#0aah ; the iapstart bit mov iapfdata,#55h mov syscon,#04h ;enable iap mov iapfadhi, #0b0h ;set msb of page address to erase mov iapfadlo,#00h ;set lsb of address = 00 mov iapfctrl,#82h ;set the iap start bit the following example shows how to erase the same page in the d ata flash memory zone: ;** erase flash data page located at address b000h to cfffh. pageerase: mov iapfdata,#55h ;sequence to enable writing mov iapfdata,#0aah ; the iapstart bit mov iapfdata,#55h mov syscon,#0ch ;enable iap + data flash mov iapfadhi, #0b0h ;set msb of page address to erase mov iapfadlo,#00h ;set lsb of address = 00 mov iapfctrl,#a2h ;set the iap start bit + fzone bit iap chip erase function the iap chip erase function will erase the entire flash memory content s with the exception of the isp boot pro gram area. running this function will also automatically unprotect the f lash memory. iap chip protect function when t he chip protect function is enabled, values read back from flash memory will be 00h. isp/aip operation durations the following table show s the duration of the isp/iap operations for an oscillator clock of 40mhz. operation max duration (fosc = 40mhz) byte program 30us page erase 10ms chip erase 3sec chip protect 400us all isp/iap operations require a supply voltage of 5v to be execute d properly. program status word register the psw register is a bit addressable register that contains the status flags (cy, ac, ov, p), user flag (f0) and register bank select bits (rs1, rs0) of the 8051 processor. t able 12: p rogram s t atus w ord r egister (psw) - sfr do h 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov - p bit mnemonic description 7 cy carry bit 6 ac auxiliary carry bit from bit 3 to 4. 5 f0 user definer flag 4 rs1 r0 - r7 registers bank select bit 0 3 rs0 r0 - r7 registers ban k select bit 1 2 ov overflow flag 1 - - 0 p parity flag rs1 rs0 active bank address 0 0 0 00h - 07h 0 1 1 08h - 0fh 1 0 2 10h - 17h 1 1 3 18 - 1fh
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 11 of 50 data pointer the VRS51C1100 has one 16 - bit data pointer. the dptr is accessed via two sfr addresses: dpl located at address 82h and dph located at address 83h. stack pointer the s tack p ointer (sp) is a register located at address 81h of the sfr register area whose value corresponds to the address of the last item that was put on the processor stack. each time new data is put on the sp, the value of the s tack p ointer is incremented. by default, the stack pointer value is 07h, but it is possible to program the processor stack pointer to point anywhere in the 00h to ffh range of ram memory. when a function call is performed or an interrupt is serviced, the 16 - bit return address ( 2 bytes) is stored on the stack. d ata can be placed manually on the s tack by using the push and pop functions. data memory the VRS51C1100 has 1k b of on - chip ram : 256 b ytes are con figured like the internal memory structure of a standard 8052 , while the remaining 768 b ytes can be accessed using external memory addressing ( movx). the VRS51C1100 also includes a large block of 64k b of d ata flash that is mapped on the processor?s externa l memory bus for r ead access. f igure 6: VRS51C1100 d ata m emory structure upper 128 bytes ram ( i ndirect addressing only ) lower 128 bytes ram sfr ( d irect addressing only ) expanded 768 bytes ( a ccessed by direct external addressing mode , using the movx instruction ) ( xrame = 1 ) 02 ffh 0000 h ffh 80 h 7 fh 00 h ffffh 0000 h if dflashe = 1 data flash mapped as external memory use movx to read if xrame = 1 and dflashe = 1 data flash mapped as external memory use movx to read 02 ffh by default , after reset the expanded ram area and the d ata flash areas are disabled. they are enabled by setting the xrame and th e dflashe bit s (respectively) of the syscon register located at address bfh in the sfr. the dflashe and xrame bits of the syscon register define which area the movx instruction will target: dflashe xrame movx <= 2ffh movx > 2ffh 0 0 ext. memory ext. memo ry 0 1 int. ram ext. memory 1 0 int. data flash int. data flash 1 1 int. ram int. data flash lower 128 bytes (00h to 7fh, bank 0 & bank 1) the lower 128 bytes of data memory (from 00h to 7fh) is summarized as follow s : o address range 00h to 7fh can be accessed in direct and indirect addressing modes o address range 00h to 1fh includes r0 - r7 register area s o address range 20h to 2fh is bit addressable o address range 30h to 7fh is not bit addressable and can be used for general - purpose storage upper 128 bytes (80h to ffh, bank 2 & bank 3) the upper 128 bytes of the data memory ranging from 80h to ffh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode. expanded ram access using the movx @dptr instruction (0000 - 02ff, bank4 - bank15) the 768 b ytes of expanded ram data memory occup ies addresses 0000h to 02ffh . this can be accessed using external direct addressing (i.e. the movx instruction) or bank mapping direct addressing. when indirect addressing executes the movx @dpt r instruction, if the address is larger than 02ffh and the d ata flash is disabled (dflashe=0), the VRS51C1100 will access off - chip memory in the external memory space using the external memory control signals . the mpage r egister ( e xtra read data pointer) the VRS51C1100 features a second data pointer called mpage, which is dedicated t o d ata flash and external ram read access using the movx @ri (i=0,1) instruction. the mpage register provides the high byte of the a ddress , while the content s of the ri regis ter provides the l ow b yte of the a ddress. the o peration of t he mpage register resembles th at of th e
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 12 of 50 movx @dptr instruction, but is limited as a read function. the mpage register default setting is 00h . t able 13: mpage register (mpage) - sfr 85 h 7 6 5 4 3 2 1 0 mpage[7:0] data bank control register the dbank register enable s the d ata b ank s elect function to map the entire content s of the ram memory in the range of 40h to 7fh for applications that require direct addressing of the expa nded ram content s . the d ata b ank s elect function is activated by setting the d ata b ank s elect enable bit (bse) to 1 . setting this bit to zero disables th e function. the lower nibble of this register control s the mapping of the entire 1k b bytes on - chip ram space into the 040h - 07fh range. t able 14: d ata b ank c ontrol r egister (dbank) ? sfr 86 h 7 6 5 4 3 2 1 0 bse unused bs3 bs2 bs1 bs0 bit mnemonic description 7 bse data bank select enable bit bse=1, data bank select enabled bse=0, data bank select disabled 6 unused - 5 unused - 4 unused - 3 bs3 2 bs2 1 bs1 0 bs0 allows the mapping of the 1k b ram into the 040h - 07fh ram space w indowed access to the entire 1k b of on - chip ram in the range of 40h - 7fh is described in the f ollowing table. t able 15: b ank mapping direct a ddressing mode bs3 bs2 bs1 bso 040h~07fh mapping address note 0 0 0 0 000h - 03fh lower 128 byte s ram 0 0 0 1 040h - 07fh lower 128 byte s ram 0 0 1 0 080h - 0bfh upper 128 byte s ram 0 0 1 1 0 c0h - 0ffh upper 128 byte s ram 0 1 0 0 0000h - 003fh on - chip expanded 768 byte s ram 0 1 0 1 0040h - 007fh on - chip expanded 768 byte s ram 0 1 1 0 0080h - 00bfh on - chip expanded 768 byte s ram 0 1 1 1 00c0h - 00ffh on - chip expanded 768 byte s ram 1 0 0 0 0100h - 013fh on - chip expanded 768 byte s ram 1 0 0 1 0140h - 017fh on - chip expanded 768 byte s ram 1 0 1 0 0180h - 01bfh on - chip expanded 768 byte s ram 1 0 1 1 01c0h - 01ffh on - chip expanded 768 byte s ram 1 1 0 0 0200h - 023fh on - chip expanded 768 byte s ram 1 1 0 1 0240h - 0 27fh on - chip expanded 768 byte s ram 1 1 1 0 0280h - 02bfh on - chip expanded 768 byte s ram 1 1 1 1 02c0h - 02ffh on - chip expanded 768 byte s ram example: user writes #55h to address 203h: mov dbank, #8ch ;set bank mapping 40h - 07fh to 0200h - 023fh mov a, # 55h ;store #55h to a mov 43h, a ;write #55h to 0203h ;address
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 13 of 50 power control register the VRS51C1100 provides two power saving modes: idle and power down, which are controlled by the pdown and idle bits of the pcon register at address 87h. t able 16: p ower c ontrol r egister (pcon) - sfr 87 h 7 6 5 4 3 2 1 0 unused rams1 rams0 bit mnemonic description 7 smod 1: double the baud rate of the serial port frequency that was generated by timer 1. 0: normal serial port baud rate genera ted by timer 1. 6 5 4 3 gf1 general purpose flag 2 gf0 general purpose flag 1 pdown power d own mode control bit 0 idle idle mode control bit in idle mode, the processor is stopped but the oscillator continues to run. the content of the ram, i/o state and sfr registers are maintained and the timer and external interrupts are left operational. the processor will be woken up when an external event, triggering an interrupt, occurs. in power down mode, the oscillator and the peripherals are d i sabled . the content s of the ram and the sfr registers, however, are maintained. the only way to exit from the power down mode is via a hardware r eset (note that the w atch d og t imer is stopped in power down ). when the VRS51C1100 is in power down, its curren t consumption drops to about 50ua. the smod bit of the pcon register controls the oscillator divisor applied to timer 1 when used as a baud rate generator for the uart. setting this bit to 1 doubl es the uart?s baud rate generator frequency.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 14 of 50 input/output ports the VRS51C1100 has 36 bi - directional lines grouped in to four 8 - bit i/o ports and one 4 - bit i/o port. these i/os can be individually configured as input s or output s . with the e xcept ion of the p0 i/os, which are of the open drain type, each i/o cons ists of a transistor connected to ground and a weak, transistor - based pull - up resistor . writing a 0 in a given i/o port bit register will activate the transistor connected to vss and bring the i/o to a low level. writing a 1 into a given i/o port bit re gister deactivates the transistor between the pin and ground. in this case , an internal weak pull - up resistor will bring the pin to a high level (except for port 0 , which is open - drain). to use a given i/o as an input, a 1 must be written into its associa ted port register bit. by default, upon reset all the i/os are configured as input s . the VRS51C1100 i/o ports are not designed to source current. structure of the p1, p2, p3 and p4 ports the following figure demonstrates the general structure of the p1, p 2 , p3 and p4 port i/o s. for these ports, the output stage is composed of a transistor (x1) and a transistor set configured as a weak pull - up. note that the figure below does not show the intermediary logic that connects the register?s output and the output stage because this logic varies with the auxiliary function of each port. f igure 7: g eneral s tructure of the o utput s tage of p1, p2, p3 and p4 d flip-flop q q ic pin read register internal bus write to register read pin vcc pull-up network x1 each line may be used independently as a logical input or output. when used as an input, the corresponding bit register must be high. this would correspond to #q=0 in figure 7 . the transistor would be off (open - circuited) and current would flow from the vcc to the pin, generating a logical high at the output. n ote that if an external device with a logical low value is connected to the pin, the current will flow out of the pin. the presence of the pull - up resistance , even when the i/o?s are configured as input s, means that a small current is likely to flow fr om the VRS51C1100 i/o?s pull - up resistors to the driving circuit when the inputs are driven l ow. for this reason, the VRS51C1100 i/o ports p1, p2, p3 and p4 are called ?quasi bi - directional?. structure of port 0 the internal structure of p0 is shown in the next figure. the auxiliary function of this port requires a particular logic. as opposed to the other ports, p0 is truly bi - directional. in other words, when used as an input, it is considered to be in a floating logical state (high impedance state). this arises from the absence of the internal pull - up resistance. the pull - up resistance is actually replaced by a transistor that is only used when the port is configured to access external memory/data bus (ea=0). when used as an i/o port, p0 acts as an open drain port and the use of an external pull - up resistor is likely to be required for most applications. f igure 8: p ort p0? s particular structu re d flip-flop q q ic pin read register internal bus write to register read pin x1 control address a0/a7 vcc when p0 is used as an external memory bus input (for a movx instruction, for example), the outputs of the register are automatically forced to 1.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 15 of 50 the bit addressable p0 register , located at address 80h , controls the p0 individual pin direction s when used as i/o s (see the following table) . t able 17: p ort 0 r egister (p0) - sfr 80 h 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 bit mnemonic description 7 p0.7 6 p0.6 5 p0.5 4 p0.4 3 p0.3 2 p0.2 1 p0.1 0 p0.0 for each bit of the p0 register correspond to an i/o line: 0: output transistor pull the line to 0v 1: the output transistor is blocked so the pull - up brings the i/o to 5v. port 2 port p2 is similar to p ort s 1 and 3 , the difference being that p2 is used to drive the a8 - a15 lines of the address bus wh en the ea line of VRS51C1100 is held low at reset time or when a movx instruction is executed. like the p 0, p 1 and p3 registers, the p2 register is bit addressable. t able 18: p ort 2 r egister (p2) - sfr a0 h 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 bit mnemonic description 7 p2.7 6 p2.6 5 p2.5 4 p2.4 3 p2.3 2 p2.2 1 p2.1 0 p2.0 for each bit of the p2 register correspond to an i/o line: 0: output transistor pull the line to 0v 1: the output transistor is blocked so the pull - up brings the i/o to 5v. port p0 and p2 as address and data bus the output stage may receive data from two sources : o the outputs of register p0 or the bus address itself multiplexed with the data bus for p0 o the outputs of the p2 register or the high byte (a8 through a15) of the bus address for the p2 port f igure 9: p2 p ort s tructure d flip-flop q q ic pin read register internal bus write to register read pin vcc pull-up network x1 control address when the ports are used as an address or data bus, special function registers p0 and p2 are disconnected from the output stage , t he 8 bits of the p0 register are forced to 1 and the content s of the p2 register remains constant. port 1 the p1 register controls the direction of the port 1 i/o pins. writing a 1 in to the p1.x bit (see the follow ing table) of the p1 register configures the bit as an output , presenting a logic 1 to the corresponding i/o pin or enables use of the i/o pin as an input. writing a 0 activates the output ?pull - down? transistor , which will force the corresponding i/o line to a logic l ow. t able 19: p ort 1 r egister (p2) - sfr 90 h 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 bit mnemonic description 7 p1.7 6 p1.6 5 p1.5 4 p1.4 3 p1.3 2 p1.2 1 p1.1 0 p1.0 for each bit of the p1 register correspond to an i/o line: 0: output transist or pull the line to 0v 1: the output transistor is blocked so the pull - up bring the i/o to 5v.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 16 of 50 auxiliary port 1 functions the port 1 i/o pins are shared with the pwm outputs, timer 2 ext and t2 inputs , as shown below: pin mnemonic function p1.0 t2 timer 2 counter input p1.1 t2ex timer 2 auxiliary input p1.2 p1.3 pwm0 pwm0 output p1.4 pwm1 pwm1 output p1.5 pwm2 pwm2 output p1.6 pwm3 pwm3 output p1.7 pwm4 pwm4 output port 3 the po rt 3 structure is similar that of port 1. t able 20: p ort 3 r egister (p3) - sfr b0 h 7 6 5 4 3 2 1 0 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 bit mnemonic description 7 p3.7 6 p3.6 5 p3.5 4 p3.4 3 p3.3 2 p3.2 1 p3.1 0 p3.0 for each bit of the p3 register correspond to an i/o lin e: 0: output transistor pull the line to 0v 1: the output transistor is blocked so the pull - up brings the i/o to 5v. to configure p3 pins as input or use alternate p3 function the corresponding bit must be set to 1. auxiliary p3 port functions the port 3 i/o pins are shared with the uart interface, int0 and int1 interrupts, timer 0 and timer 1 inputs and the #wr and #rd lines when external memory access es are performed. f igure 10: p3 p ort s tructure d flip-flop q q ic pin read register internal bus write to register read pin x1 vcc auxiliary function: input auxiliary function: output the following table describes the auxiliary function s of the port 3 i/o pins. t able 21: p3 a uxiliary f unction t able pin mnemonic function p3.0 rxd serial port: rec eive data in asynchronous mode. input and output data in synchronous mode. p3.1 txd serial port: transmit data in asynchronous mode. output clock value in synchronous mode. p3.2 int0 external interrupt 0 timer 0 control input p3.3 int1 external interr upt 1 timer 1 control input p3.4 t0 timer 0 counter input p3.5 t1 timer 1 counter input p3.6 wr write signal for external memory p3.7 rd read signal for external memory
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 17 of 50 port 4 port 4 has four related i/o pins and its port address is located at 0d8 h. t able 22: p ort 4 (p4) - sfr d8 h 7 6 5 4 3 2 1 0 unused p4.3 p4.2 p4.1 p4.0 bit mnemonic description 7 unused - 6 unused - 5 unused - 4 unused - 3 p4.3 2 p4.2 1 p4.1 0 p4.0 used to output the setting to pins p4.3, p4.2, p4.1, p4.0 respectively. software port control some instructions allow the user to read the logic state of the output pin, while others allow the user to read the content s of the associated port register. these instructions are called read - modify - writ e instructions. a list of these instructions are found in the following table. upon execution of these instructions, the content of the port register (at least 1 bit) is modified. the other read instructions take the present state of the input s into acco unt. for example, instruction anl p3,#01h obtains the value in the p3 register; performs the desired logic operation with the constant 01h; and recopies the result into the p3 register. when users want to take the present state of the inputs into account, they must first read these states and perform an and operation between the read value and the constant. mov a, p3; state of the inputs in the accumulator anl a, #01; and operation between p3 and 01h when the port is used as an output, the register contai ns information on the state of the output pins. measuring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. the functions shown next take the value of the regis ter rather than that of the pin. t able 23: l ist of i nstructions that r ead and m odify the p ort u sing r egister v alues instruction function anl logical and ex: anl p0, a orl logical or ex: orl p2, #01110000b xrl exclusive or ex: xrl p1 , a jbc jump if the bit of the port is set to 0 cpl complement one bit of the port inc increment the port register by 1 dec decrement the port register by 1 djnz decrement by 1 and jump if the result is not equal to 0 mov p.,c copy the held bit c to the port clr p.x set the port bit to 0 setb p.x set the port bit to 1 port operation timing writing to a port (output) when an operation results in a modification of the content in a port register, the new value is placed at the output of the d flip - flop during the last machine cycle that the instruction needed to execute. reading a port (input) t o be sampled, the signal duration present on the i/o inputs must be longer than fosc/12.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 18 of 50 i/o ports driving capability the maximum allowable continuous c urrent that the device can sink on an i/o port is described in the following table: maximum sink current on one given i/o 10ma maximum total sink current for p0 26ma maximum total sink current for p1, 2, 3 15ma maximum total sink current on all i/o 71m a it is not recommended to exceed the sink current s outlined in the above table. doing so will likely make the low - level output voltage exceed device specification s and affect device reliability. the VRS51C1100 i/o ports are not designed to source curre nt. VRS51C1100 timers the VRS51C1100 includes three 16 - bit timers: timer 0, timer 1 and timer 2. the timers can operate in two modes: o event counting mode o timer mode when operating in event counting mode, the counter is incremented each time an externa l event, such as a transition in the logical state of the t imer input (t0, t1, t2 input), is detected. when operating in t imer mode, the counter is incremented by the microcontroller?s system clock (fosc/12) or by a divided version of it. timer 0 and time r 1 timers 0 and 1 have four m odes of operation. these m odes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. timer 1 can also be used as a baud rate generator to generate c ommunication frequencies for the serial interface. timer s 1 and 0 are configured by the tmod and tcon registers. t able 24: t imer m ode c ontrol r egister (tmod) ? sfr 89 h 7 6 5 4 3 2 1 0 gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 bit mnemonic description 7 gate1 1: enables external gate control (pin int1 for counter 1). when int1 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge on the t1in input pin. 6 c/t1 selects timer or counter op eration (timer 1). 1 = a counter operation is performed 0 = the corresponding register will function as a timer. 5 t1m1 4 t1m0 selects the operating mode of timer/counter 1 3 gate0 if set, enables external gate control (pin int0 for counter 0). when int0 is high, and trx bit is set (see tcon register), a counter is incremented every falling edge on the t0in input pin. 2 c/t0 selects timer or counter operation (timer 0). 1 = a counter operation is performed 0 = the corresponding register will functio n as a timer. 1 t0m1 0 t0m0 selects the operating mode of timer/counter 0. the table below summarizes the four modes of operation of t imers 0 and 1. the timer operating mode is selected by bits t1m1/t1m0 and t0m1/t0m0 of the tmod register. t able 25: t imer /c ounter m ode d escription s ummary m1 m0 mode function 0 0 mode 0 13 - bit counter 0 1 mode 1 16 - bit counter 1 0 mode 2 8 - bit auto - reload counter/timer. the reload value is kept in th0 or th1, while tl0 or tl1 is incremented ev ery machine cycle. when tlx overflows, the value of thx is copied to tlx. 1 1 mode 3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 19 of 50 timer 0, timer 1 counter / timer functions timing function when timer 1 or timer 0 is configured to operate as a t imer, its value is automatically incremented at every machine cycle. once the t imer value rolls over, a flag is raised and the counter acquires a value of zero. the overflow flags (tf0 and tf1) are located in the tcon register. the tr0 and tr1 bit s o f the tcon register gate the corresponding timer operation. in order for the t imer to run, the corresponding trx bit must be set to 1. the it0 and it1 bits of the tcon register control the event that will trigger an e xternal i nterrupt as follow s : it0 = 0 : the int0, if enabled, occurs if a l ow l evel is present on p3.2 it0 = 1: the int0, if enabled, occurs if a h igh to l ow transition is detected on p3.2 it1 = 0: the int1, if enabled, occurs if a l ow l evel is present on p3.3 it1 = 1: the int1, if enabled, occurs if a h igh to l ow transition is detected on p3.3 the ie0 and ie1 bit s of the tcon register are e xternal flags that indicate whether a transition has been detected on the int0 and int1 interrupt pins , respectively. if the external interrupt is conf igured as edge sensitive, the corresponding ie0 and ie1 flag s are automatically cleared when the corresponding interrupt is serviced. i f the external interrupt is configured as level sensitive, the corresponding flag must be cleared by the software. t a ble 26: t imer 0 and 1 c ontrol r egister (tcon) ? sfr 88 h 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit mnemonic description 7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware on timer/ counter overflow. cleared by hardware when processor vectors to interrupt routine. 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on or off. 3 ie1 interrupt edge flag. set by hardware when external interrupt edge is detected. cleared when interrupt proc essed. 2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. 1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge is detected. cleared when interrupt processed. 0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. counting function when operating as a counter, the t imer?s register is incremented at every falling edge of the t0 and t1 signals located at the input of the timer. when the sampling circuit sees a high immediately followed by a low in the next machine cycle, the counter is incremented. two machine cycles are required to detect and record an event. in order to be properly sampled, the duration of the event present ed to the t imer input should be greater than 1/24 of the oscillator frequency. timer 0 / timer 1 operating modes the user may change the operating mode by setting the m1 and m0 bits of the tmod sfr.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 20 of 50 mode 0 a schematic representation of this mode of operation is presented in the figure below. in mode 0, the t imer operates as a 13 - bit counter made up of 5 lsb s of the tlx register and the 8 upper bits of the thx register. when an overflow causes the value of the register to rollover to 0, the tfx interrupt signal goes to 1. the count value is validated as soon as trx goes to 1 and the gate bit is 0, or when intx is 1. f igure 11: t imer /c ounter 1 m ode 0: 13 - b it c ounter fosc 12 t1/t0 pin c/t1 / c/t0 =0 c/t1 / ct0 =1 tr1/tr0 gate1 / gate0 int1 / int0 pin 0 1 0 7 4 mode 0 mode 1 0 7 tl1 / tl0 tf1 / tf0 int th1 / th0 clk control m ode 1 mode 1 is almost identical to mode 0 , the difference being that in mode 1, the counter/timer uses the full 16 - bits of the t imer. mode 2 in this mode, the register of the t imer is configured as an 8 - bit automatically re - loadable c ounter/ t imer. in mo de 2, the lower byte tlx is used as the counter. in the event of a counter overflow, the tfx flag is set to 1 and the value contained in thx, which is preset by software, is reloaded into the tlx counter. the value of thx remains unchanged. f igure 12: t imer /c ounter 1 m ode 2: 8 - bit a utomatic r eload 12 t1 / t0 pin c/t1 / c/t0 = 1 tr1 / tr0 gate1 / gate0 0 1 0 7 th1 / th0 fosc tf1 / tf0 int 0 7 int1 / int0 pin tl1 / tl0 control reload c/t1 / c/t0 = 1 mode 3 in mode 3 , timer 1 is blocked as if its control bit, tr1, was set to 0. in this mode, timer 0?s registers , tl0 and th0 , are configured as two separate 8 - bit counters. t he tl0 counter uses timer 0?s control bits ( c/t, gate, tr0, int0 , tf0 ), and the th0 counter is held in t imer m ode (counting machine cycles) and gains control over tr1 and tf1 from timer 1. at this point, th0 controls the timer 1 interrupt . f igure 13: t imer /c ounter 0 m ode 3 fosc 12 t0pin c/t =0 c/t =1 tr0 gate int0 pin 0 1 0 7 tl0 tf0 clk control interrupt 0 7 th0 tf1 clk control interrupt tr1
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 21 of 50 timer 2 timer 2 of the VRS51C1100 is a 16 - bit t imer/ c ounter and is s imilar to t imers 0 and 1 in that it can operate as either an event counter or a timer. th is is co ntrolled by the c/t2 bit in the t2con special function register. timer 2 has three operating modes: auto - load , capture, and baud rate generator. the se modes are selected via the t2con. the following table describes the t2con special function register bits . t able 27: t imer 2 c ontrol r egister (t2con) ? sfr c8 h 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 bit mnemonic description 7 tf2 timer 2 overflow flag: set by an overflow of timer 2 and must be cleared by software. tf 2 will not be set when either rclk =1 or tclk =1. 6 exf2 timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on t2ex and exen2=1. when timer 2 is enabled, exf=1 will cause the cpu to vector to th e timer 2 interrupt routine. note that exf2 must be cleared by software. 5 rclk serial port receive clock source. 1: causes serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. 0: causes timer 1 overflow to be used for the s erial port receive clock. 4 tclk serial port transmit clock. 1: causes serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. 0: causes timer 1 overflow to be used for the serial port transmit clock. 3 exen2 timer 2 externa l mode enable. 1: allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. 0: causes timer 2 to ignore events at t2ex. 2 tr2 start/stop control for timer 2. 1: start timer 2 0: stop timer 2 1 c/t2 timer or counter select (timer 2) 1: external event counter falling edge triggered. 0: internal timer (osc/12) 0 cp/rl2 capture/reload select. 1: capture of timer 2 value into rcap2h, rcap2l is performed if exen2=1 and a negat ive transitions occurs on the t2ex pin. the capture mode requires rclk and tclk to be 0. 0: auto - reload reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2=1. when either rck =1 or tclk =1, this bit is ignored and t he timer is forced to auto - reload on timer 2 overflow. the timer 2 mode selection bits and their functions are described in the following table : t able 28: t imer 2 m ode s election b its rclk + tclk cp/rl2 tr2 mode 0 0 1 16 - bit auto - rel oad mode 0 1 1 16 - bit capture mode 1 x 1 baud rate generator mode x x 0 timer 2 stops the details of each mode are described in the following sections . timer 2 capture mode in c apture m ode , the exen2 bit of the t2con register controls whether an e xternal transition on the t2ex pin will trigger the capture of the timer value. when exen2 = 0, the timer 2 acts as a 16 - bit timer / counter, which, upon overflowing, will set the tf2 bit (timer 2 overflow bit). this overflow can be used to generate an in terrupt. f igure 14: t imer 2 in c apture m ode f osc 12 timer counter c/t2 0 1 t2 pin tr2 t2ex pin 0 7 0 7 0 7 0 7 timer 2 interrupt exf2 exen2 rcap2l rcap2h tl2 th2 tf2 when exen2 = 1, the above still applies , however, i n addition, it is possible to allow a 1 to 0 transition at the t2ex input to cause the current value stored in the timer 2 registers (tl2 and th2) to be captured into
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 22 of 50 the rcap2l and rcap2h registers. furthermore, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. note that both exf2 and tf2 share the same i nterrupt vector. timer 2 auto - reload mode in this mode, there are also two options controlled by the exen2 bit in the t2con register . if exen2 = 0, when timer 2 rolls over, it not only sets tf2, but also causes the timer 2 registers to be reloaded with t he 16 - bit value in the rcap2l and rcap2h registers previously initialised. in this mode, timer 2 can be used as a baud rate generator source for the serial port. if exen2=1, then timer 2 still performs the above operation, but a 1 to 0 transition at the e xternal t2ex input will also trigger an anticipated reload of timer 2 with the value stored in rcap2l, rcap2h and set exf2. f igure 15: t imer 2 in auto - reload mode f osc 12 timer counter c/t2 0 1 t2 pin tr2 t2ex pin 0 7 0 7 0 7 0 7 timer 2 interrupt exf2 exen2 rcap2l rcap2h tl2 th2 tf2 timer 2 baud rate generator mode timer 2 can be used for uart baud rate generation . this m ode is activated when rclk is set to 1 and/or tclk is set to 1. this m ode is described further in the serial port section. f igure 16: t imer 2 in automatic b aud g enerator m ode f osc 2 timer counter c/t2 0 1 t2 pin tr2 t2ex pin 0 7 0 7 0 7 0 7 exf2 exen2 rcap2l rcap2h tl2 th2 2 16 16 smod 0 1 timer 1 overflow 0 1 0 1 tclk rclk tx clock rx clock timer 2 interrupt request uart serial port the serial port on the VRS51C1100 can operate in full duplex ( it can transmit and receive data simultaneously. ) this occurs at the same speed if one timer is assigned as the clock source for both transmission and reception, and at different speeds if transmission and reception are each controlled by their own timer. the VRS51C1100 serial port includes a double buffer for the receiver , which allows reception of a byte even if the previously received byte has not b een retrieved from the receive register by the processor. however, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. the sbuf register provides access to th e transmit and receive registers of the serial port. reading from the sbuf register will access the receive register, while a write to the sbuf loads the transmit register.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 23 of 50 serial port control register the scon (serial port control) register contains contr ol and status information, and includes the 9 th data bit for transmit/receive (tb8/rb8 if required), mode selection bits and serial port interrupt bits (ti and ri ). t able 29: s erial p ort c ontrol r egister (scon) ? sfr 98 h 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri bit mnemonic description 7 sm0 bit to select mode of operation (see table below) 6 sm1 bit to select mode of operation (see table below) 5 sm2 multiprocessor communication is possible in modes 2 and 3. in modes 2 or 3 if sm2 is set to 1, ri will not be activated if the received 9 th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. 4 ren serial reception enable bit this bit must be set by software and c leared by software. 1: serial reception enabled 0: serial reception disabled 3 tb8 9 th data bit transmitted in modes 2 and 3 this bit must be set by software and cleared by software. 2 rb8 9 th data bit received in m odes 2 and 3. in mode 1, if sm2 = 0, r b8 is the stop bit that was received. in mode 0, this bit is not used. this bit must be cleared by software. 1 ti transmission interrupt flag. automatically set to 1 when: the 8 th bit has been sent in mode 0. automatically set to 1 when the stop bit has been sent in the other modes. this bit must be cleared by software. 0 ri reception interrupt flag automatically set to 1 when: the 8 th bit has been received in mode 0. automatically set to 1 when the stop bit has been sent in the other modes (see sm2 ex ception). this bit must be cleared by software. t able 30: s erial p ort m odes of o peration sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 0 1 1 8 - bit uart variable 1 0 2 9 - bit uart f osc /64 or f osc /32 1 1 3 9 - bit uart variable uart operating modes the VRS51C1100 ?s serial port can operate in four different m odes. in all four m odes, a transmission is initiated by an instruction that uses the sbuf register as a destination register. in mode 0, reception is initiat ed by setting ri to 0 and ren to 1. an incoming start bit initiates reception in the other modes , provided that ren is set to 1. the following paragraphs describe the se four m odes. uart operation in mode 0 in this m ode, the serial data exits and enters t hrough the rxd pin. txd is used to output the shift clock. the signal is composed of 8 data bits starting with the lsb. the baud rate in this mode is 1/12 the oscillator frequency. f igure 17: s erial p ort m ode 0 b lock d iagram txd p3.1 internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock shift send rx control unit ri ti 1 1 1 1 1 1 1 0 rx clock start shift receive shift register sbuf internal bus read sbuf ren ri rxd p3.0 input function rxd p3.0 shift clock fosc/12 serial port interrupt shift rxd p3.0
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 24 of 50 uart transmission in mode 0 any instruction that uses sbuf as a destination register may initiate a transmission. the ?write to sbuf? signal also loads a 1 into the 9 th position of the transmit shift register and informs the tx cont rol block to begin a transmission. the internal timing is such that one full machine cycle will elapse between a write to sbuf instruction and the activation of send. the send signal enables the output of the shift register to the alternate output functio n line of p3.0 and enables shift clock to the alternate output function line of p3.1. at every machine cycle in which send is active, the contents of the transmit shift register are shifted to the right by one position. zeros come in from the left as dat a bits shift out to the right. the tx control block sends its final shift and deactivates send while setting t1 after one condition is fulfilled: when the msb of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9 th position is just to the left of the msb; and all positions to the left of that contain zeros. once these conditions are met, the deactivation of send and the setting of t1 occur at t1 of the 10 th machine cycle after the ?write to sbuf? pulse. uart reception in mode 0 when ren and r1 are set to 1 and 0 , respectively, reception is initiated. the bits 11111110 are written to the receive shift register at the end of the next machine cycle by the rx control unit. in the following phase, the rx con trol unit will activate receive. the contents of the receive shift register are shifted one position to the left at the end of every machine cycle during which receive is active. the value that comes in from the right is the value that was sampled at the p3.0 pin. 1?s are shifted out to the left as data bits are shifted in from the right. the rx control block is flagged to do one last shift and load the sbuf when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. uart operation in mode 1 in a mode 1 operation , 10 bits are transmitted (through txd) or received (through rxd). the transactions are composed of: a start bit (low); 8 data bits (lsb first) and a stop bit (high). the reception is co mpleted once the stop bit sets the rb8 flag in the scon register. either timer 1 or timer 2 controls the baud rate in this mode. the following diagram demonstrates the serial port structure when configured in mode 1. f igure 18: s er ial p ort m ode 1 and 3 b lock d iagram internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock data send rx control unit ri ti rx clock start shift 9-bit shift register sbuf internal bus read sbuf load sbuf serial port interrupt shift bit detector 16 16 1-0 transition detector rxd 2 timer 2 overflow timer 1 overflow rclk tclk smod 0 1 0 1 0 1 load sbuf shift txd
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 25 of 50 uart transmission in mode 1 transmission in this mode is initiated by any instruction that makes use of sbuf as a destination register. the 9 th bit position of the transmit shift register is loaded by the ?write to sbuf? signal. this event also flags /informs the tx c ontrol u nit that a transmission has been requested. it is after the next rollover in the divide - by - 16 counter when transmission actually begins. it follows that the bit times are synchronized to the divide - by - 16 counter and not to the ?write to sbuf? signal. when a transmission begins, it places the s tart bit at txd. data transmission is activated one bit time later. this activation enables the output bit of the transmit shift re gister to txd. one bit time after that, the first shift pulse occurs. in this m ode, zeros are clocked in from the left as data bits are shifted out to the right. when the most significant bit of the data byte is at the output position of the shift registe r, the 1 that was initially loaded into the 9 th position is to the immediate left of the msb and all positions to the left of that contain zeros. this condition flags the tx c ontrol u nit to shift one more time. uart reception in mode 1 a one to zero trans ition at pin rxd will initiate reception. it is for this reason that rxd is sampled at a rate of 16 multiplied by the baud rate that has been established. when a transition is detected, 1ffh is written into the input shift register and the divide - by - 16 cou nter is immediately reset. the divide - by - 16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. in total, there are 16 states in the counter. during the 7 th , 8 th and 9 th counter states of each bit time , the bit detector samples the value of rxd. the accepted value is the one seen in at least two of the three samples. the purpose of doing this is for noise rejection. if the value accepted during the first bit time is not zero, the receive circuits are reset and th e unit goes back to searching for another one to zero transition. all false start bits are rejected by doing this. if the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. for a recei ve operation, the data bits come in from the right as 1?s shift out on the left. as soon as the start bit arrives at the leftmost position in the shift register, (9 - bit register), it tells the uart?s receive controller block to perform one last shift opera tion: to set ri and to load sbuf and rb8. the signal to load sbuf and rb8, and to set ri will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: o either sm2 = 0 or the received stop bit = 1 o ri = 0 if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf and ri is activated. if one of these conditions is not met, the received frame is completely lost. at this time, whether the above conditions are met or not, the unit r eturns to searching for a one to zero transition in rxd. uart operation in mode 2 in mode 2 a total of 11 bits are transmitted (through txd) or received (through rxd). the transactions are composed of: a start bit ( l ow), 8 data bits (lsb first), a program mable 9 th data bit and a stop bit ( h igh). for transmission, the 9 th data bit comes from the tb8 bit of scon. for example, the parity bit p in the psw could be moved into tb8. in the case of receive, the 9 th data bit is automatically written into rb8 of the scon register.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 26 of 50 in mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. f igure 19: s erial p ort m ode 2 b lock d iagram internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock data send rx control unit ri ti rx clock control start shift 9-bit shift register sbuf internal bus read sbuf load sbuf serial port interrupt shift bit detector 16 16 1-0 transition detector rxd 2 fosc/2 smod 0 1 load sbuf shift txd stop sample uart operation in mode 3 in mode 3, 11 bits ar e transmitted (through txd) or received (through rxd). the transactions are composed of: a start bit ( l ow), 8 data bits (lsb first), a programmable 9 th data bit and a stop bit ( h igh). mode 3 is identical to mode 2 in all respects but one , the baud rate. e ither timer 1 or timer 2 generates the baud rate in mode 3. f igure 20: s erial p ort m ode 3 b lock d iagram internal bus sbuf d s q zero detector clk 1 write to sbuf tx control unit start tx clock data send rx control unit ri ti rx clock start shift 9-bit shift register sbuf internal bus read sbuf load sbuf serial port interrupt shift bit detector 16 16 1-0 transition detector rxd 2 timer 2 overflow timer 1 overflow rclk tclk smod 0 1 0 1 0 1 load sbuf shift txd sample
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 27 of 50 uart in mode 2 and 3: additional information as mentioned previously , for an operation in m odes 2 and 3, 11 bits are transmitted (through txd) or received (through rxd). the signal is comprise d of: a logical low start bit, 8 data bits (lsb first), a programmable 9 th data bit and a logical high stop bit. on transmit, (tb8 in scon) can be assigned t he value of 0 or 1. on receive , the 9 th data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from either timer 1 or timer 2 depending on the states of tclk and rclk. uart transmission in mode 2 and mode 3 the transmission is initiated by any instruction that makes use of sbuf as the destination register. the 9 th bit position of the transmit shift register is loaded by the ?write to sbuf? signa l. this event also informs the uart transmission control unit that a transmission has been requested. after the next rollover in the divide - by - 16 counter, a transmission actually starts at the beginning of the machine cycle. it follows that the bit times a re synchronized to the divide - by - 16 counter and not to the ?write to sbuf? signal, as in the previous mode. transmissions begin when the send signal is activated, which places the start bit on the txd pin. data is activated one bit time later. this activa tion enables the output bit of the transmit shift register to the txd pin. the first shift pulse occurs one bit time after that. the first shift clocks a stop bit (1) into the 9 th bit position of the shift register on txd. thereafter, only zeros are clock ed in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition sig nals to the tx control unit to shift one more time and set ti, while deactivating send. this occurs at the 11 th divide - by - 16 rollover after ?write to sbuf?. uart reception in mode 2 and mode 3 one to zero transitions on the rxd pin initiate reception. fo r this reason the rxd is sampled at a rate of 16 multiplied by the established baud rate . .when a transition is detected, the 1ffh is written into the input shift register and the divide - by - 16 counter is immediately reset. during the 7 th , 8 th and 9 th count er states of each bit time , the bit detector samples the value of rxd. the accepted value is the one seen in at least two of the three samples. if the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes ba ck to searching for another one to zero transition. if the s tart bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. for a receive operation, the data bits come in from the right as 1?s shift out on the left. as soon as the s tart bit arrives at the leftmost position in the shift register (9 - bit register), it informs the rx control block to do one more shift, to set ri and to load sbuf and rb8. the signal to set ri and to load sbuf and rb8 will be generated if, and only if, the following conditions are satisfied when the final shift pulse is generated: - either sm2 = 0 or the received 9 th bit equal 1 - ri = 0 if both conditions are met, the 9 th data bit received goes into rb8, and the first 8 dat a bits go into sbuf. if one of these conditions is not met, the received frame is completely lost. one bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the rxd input. please note t hat the value of the received s top bit is unrelated to sbuf, rb8 or ri.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 28 of 50 uart baud rates in mode 0, the baud rate is fixed and can be represented by the following formula: in mode 2, the baud rate depends on the value of the smod bit in the pcon sfr. from the formula below, we can see that if smod = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. the timer 1 and/or timer 2 overflow rate determines the baud rates in modes 1 and 3. generating uart baud rate with tim er 1 when timer 1 functions as a baud rate generator, the baud rate in m odes 1 and 3 is determined by the timer 1 overflow rate. timer 1 must be configured as an 8 - bit timer (tl1) in auto - reload mode with a th1 value when an overflow occurs (mod e 2). in this application, the timer 1 interrupt should be disabled. the two following formulas can be used to calculate the baud rate and the reload value written in to the th1 register. the value to write into the th1 register is defined by the f ollowing formula: generating uart baud rates with timer 2 timer 2 is often preferred to generate the baud rate, as it can be easily configured to operate as a 16 - bit timer with auto - reload . this enables far better resolution than using timer 1 in 8 - bit auto - reload mode. the baud rate using timer 2 is defined as: the timer can be configured as either a timer or a counter in any of its three running modes. in typical applications, it is configured as a timer (c/t2 is set to 0). to make tim er 2 operate as a baud rate generator, the tclk and rclk bits of the t2con register must be set to 1. the baud rate generator mode is similar to the auto - reload mode in that an overflow in th2 causes the timer 2 registers to be reloaded with the 16 - bit va lue in registers rcap2h and rcap2l, which are preset by the software. however, when timer 2 is configured as a baud rate generator, its clock source is osc/2. mode 0 baud rate = oscillator frequency 12 mode 2 baud rate = 2 smod x (oscillator frequency) 64 mode 1,3 baud rate = 2 smod x fosc 32 x 12(256 ? th1) th1 = 256 - 2 smod x fosc 32 x 12x (baud rate) mode 1,3 baud rate = 2 smod x timer 1 overflow rate 32 mode 1,3 baud rate = timer 2 overflow rate 16
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 29 of 50 the following formula can be used to calculate the baud rate in modes 1 and 3 using timer 2: the formula below is used to define the reload value written into the rcap2h, rcap2l registers to achieve a given baud rate. in the above formula, rcap2h and rcap2l are the content s of rcap2h and rcap2l taken as a 16 - bit unsigned integer. note that a rollover in th2 does not set tf2 and will not generate an interrupt. as such , the timer 2 interrupt does not have to be disabled when timer 2 is configured in baud rate generator mode. furthermore, when timer 2 is configured as a uart baud ra te generator and is running (tr2 is set to 1), the user should not try to perform read or write operations to the th2 / tl2 , rcap2h and rcap2l registers . modes 1, 3 baud rate = oscillator frequency 32x[65536 ? (rcap2h, rcap2l)] (rcap2h, rcap2l) = 65536 - fosc 32x[baud rate]
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 30 of 50 timer 1 reload value in modes 1 & 3 for uart baud rate the following table provides examples of the timer 1, 8 - bit reload value when used as a uart b aud r ate generator and the smod bit of the pcon register is set to 1 : 22.184mhz 16.000mhz 14.745mhz 12.000mhz 11.059mhz 8.000mhz 3.57mhz 115200bps ffh - - - - - - 57600bps feh - - - ffh - - 38400bps fdh - feh - - - - 31250bps - - - feh - - - 19200bps fah - fch - fdh - - 9600bps f4h - f8h - fah - - 2400bps d0h ddh e0h e6h e8h - - 1200bps a0h bbh c0h cch d0h ddh - 300bps - - 00h 30h 40h 75h c2h timer 2 reload value i n modes 1 & 3 for uart baud rate the following are examples of [rcap2h, rcap2l] reload values for timer 2 when it is used as a baud rate generator for the VRS51C1100 uart : 22.184mhz 16.000mhz 14.745mhz 12.000mhz 11.059mhz 8.000mhz 3.57mhz 230400bps ff fdh - fffeh - - - - 115200bps fffah - fffch - fffdh - - 57600bps fff4h - fff8h - fffah - - 38400bps ffeeh fff3h fff4h - fff7h - - 31250bps ffeah fff0h fff1h fff4h fff5h fff8h - 19200bps ffdch ffe6h ffe8h - ffeeh fff3h 9600bps ffb8h ffcch ffd0h ffd9h ffdch ffe6h - 2400bps fee0h ff30h ff40h ff64h ff70h ff98h ffd1h 1200bps fdc0h fe5fh fe80h fec7h fee0h ff30h ffa3h 300bps f700h f97dh fa00h fb1eh fb80h fcbeh fe8bh uart initialization in mode 3 using timer 1 ;*** intialize the uart @ 9600bps, fosc= 11.0592mhz iniser0t1i: mov a,t2con ;retrieve current value of t2con anl a,#11001111b ;rclk & tclk bit = 0 - > to use timer1 mov t2con,a ;baud rate generator source for uart mov pcon,#80h ;set the smod bit to 1 mov tl1,#0fah ;config timer1 at 8bit with auto - reload mov th1,#0fah ;calculate the timer 1 reload value ;th1 = [(2^smod) * fosc] / (32 * 12 * fcomm) ;th1 for 9600bps @ 11.059mhz = fah mov scon,#05ah ;config scon_0 mode_1 mov tmod,#00100000b ;config timer 1 in mode 2, 8b it ; + auto reload mov tcon,#01000000b ;start timer1 clr scon.0 ;clear uart rx, tx flags clr scon.1 mov sbuf,#data ;send one byte on the serial port uart initialization in mode 3, using timer 2 ;*** intiali ze the uart @57600bps, fosc=11.0592mhz iniser0t2i: mov scon,#05ah ;config scon_0 mode_1, ;calculate reload value with t2 ;rcap2h,rcap2l = 65536 - [ fosc / (32*fcomm)] mov rcap2h,#0ffh ;reload value 57600bps, 11.059mhz =fffah mov rcap2l,# 0dch ; mov t2con,#034h ;serial port0, timer2 reload start clr scon.0 ;clear uart rx, tx flags clr scon.1 mov sbuf,#data ;send one byte on the serial port
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 3 1 of 50 interrupts the VRS51C1100 has 8 interrupt sources (9 if the wdt is include d ) and 7 interrupt vectors (including reset) used for handl ing . the interrupt s are enabled via the ie register shown below: t able 31: ie i nterrupt e nable r egister ? sfr a8 h 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 bit mnemonic descrip tion 7 ea disables all interrupts 0: no interrupt acknowledgment 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit. 6 - reserved 5 et2 timer 2 interrupt enable bit 4 es serial port interrupt enable bit 3 et1 timer 1 interrupt enable bit 2 ex1 external interrupt 1 enable bit 1 et0 timer 0 interrupt enable bit 0 ex0 external interrupt 0 enable bit the following figure illustrates the various interrupt sources on the VRS51C1100 . f igure 21: i nterrupt s ources ie0 it0 int0 tf0 ie1 it1 int1 tf1 t1 ri tf2 exf2 interrupt sources interrupt vectors the table below specifies each interrupt source, its flag and its vector address. t able 32: i nterrupt v ector a ddress interrupt source flag vector address reset (+ wdt) wdr 0000h* int0 ie0 0003h timer 0 tf0 000bh int1 ie1 0013h timer 1 tf1 001bh serial port ri+ti 0023h timer 2 tf2+exf2 002bh *if location 0000h = ffh, the pc jump to the isp program. external interrupts the VRS51C1100 has two external interrupt inputs ( int0 and int1 ) . these interrupt lines are shared with the p3.2 and p3.3 i/os . b its it0 and it1 of the tcon register determine whether the external interrupts are level or edge sensitive. if itx = 1, the interrupt will be raised when a 1 - > 0 transition occurs at the interrupt pin. the duration of the transition must be at least equal to 12 oscillator cycles. if itx = 0, the interrupt will occur when a logic low condition is present on the interrupt pin. the state of the external inte rrupt, when enabled, can be monitored using the flags, ie0 and ie1 of the tcon register and will be set when the interrupt condition occurs. in the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared whe n the interrupt is serviced. if the interrupt is configured as level sensitive, the interrupt flag must be cleared by the software.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 32 of 50 timer 0 and timer 1 interrupt both timer 0 and timer 1 can be configured to generate an interrupt when a rollover of the t imer/counter occurs (except timer 0 in mode 3). the tf0 and tf1 flags serve to monitor timer overflow occurring in timer 0 and timer 1. these interrupt flags are automatically cleared when the interrupt is serviced. timer 2 interrupt a timer 2 interrupt can occur if tf2 and/or exf2 flags are set to 1 and if the timer 2 interrupt is enabled. the tf2 flag is set when a rollover of the timer 2 counter/timer occurs. the exf2 flag can be set by a 1 to 0 transition on the t2ex pin by the software. note that neither flag is cleared by the hardware upon execution of the interrupt service routine. the service routine may have to determine whether it was tf2 or exf2 that generated the interrupt. these flag bits will have to be cleared by the software. every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. in other words, pending interrupts can be cancelled and interrupts can be generated by the software. serial po rt interrupt the serial port can generate an interrupt upon byte reception or once the byte transmission is completed. th e se two conditions share the same interrupt vector and it is up to the user - developed interrupt service routine software to determine the cause of the interrupt by examining serial interrupt flags ri and ti . note that neither of these flags is cleared by the hardware upon execution of the interrupt service routine. the software must clear these flags. execution of an interrupt when th e processor receives an interrupt request, an automatic jump to the desired subroutine occurs. this jump is similar to executing a branch to a subroutine instruction: the processor automatically saves the address of the next instruction on the stack. an in ternal flag is set to indicate that an interrupt is taking place, and then the jump instruction is executed. an interrupt subroutine must always end with the reti instruction. this instruction allows users to retrieve the return address placed on the stack . the reti instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. interrupt enable and interrupt priority when the VRS51C1100 is initialized, all interrupt sources are inhibited by the bit s of the ie register being reset to 0. it is necessary to start by enabling the interrupt sources that the application requires.this is achieved by setting bits in the ie register, as discussed previously. this register is part of the bit addressable inte rnal ram. for this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. all interrupts can be inhibited by setting ea to 0. the order in which interrupts are serviced is shown in the following table: t able 33: i nterrupt p riority interrupt source reset + wdt (highest priority) ie0 tf0 ie1 tf1 ri+ti tf2+exf2 (lowest priority)
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 33 of 50 modifying the order of priority the VRS51C1100 allows the user to modify the natural priority of the interrupts. the order can be m odif ied by programming the bits in the ip (interrupt priority) register. when any bit in this register is set to 1, it gives the corresponding source priority over interrupts coming from sources tha t don?t have their corresponding ip bit s set to 1. the ip register is represented in the table below. t able 34: ip i nterrupt p riority r egister ? sfr b8 h 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 bit mnemonic description 7 - 6 - 5 pt2 gives timer 2 interrupt higher priority 4 ps gives serial port interrupt higher priority 3 pt1 gives timer 1 interrupt higher priority 2 px1 gives int1 interrupt higher priority 1 pt0 gives timer 0 interrupt higher priority 0 px0 gives int0 interrupt higher priority the watch d og timer the VRS51C1100 w atch d og t imer (wdt) is a 16 - bit free - running counter operating from an independent 250khz internal rc oscillator. the overflow of the w atch d og t imer counter will reset the processor. the wd t is a useful safety measure for systems that are susceptible to noise, power glitches and other conditions that can cause the software to go into infinite dead loops or runaways ; the wdt provides a recovery mechanism from abnormal software conditions. wa tch d og timer registers the configuration and use of the VRS51C1100 w atch d og t imer is handled by three registers: wdtkey, wdtctrl and syscon. the wdtkey register ensure s that the w atch d og t imer is not inadvertently reset in case of program malfunction. t able 35: w atch d og t imer k ey register : wdtkey ? sfr 97 h 7 6 5 4 3 2 1 0 wdtkey7:0 bit mnemonic description 7:0 wdtkey watch dog key the wdtctrl register is , by default , configured as a read - only register. to modify its conte nts, two consecutive write operations to the wdtkey register must be performed: mov wdtkey,#01eh mov wdtkey,#0e1h once the configuration or wdt reset operation is complete, the wdtctrl register can be restored to r ead - o nly by writing the following sequ ence into the wdtkey register: mov wdtkey,#0e1h mov wdtkey,#01eh once the wdt operation is activated, the user software must clear it periodically. if the wdt is not cleared, its overflow will trigger a reset of the VRS51C1100 . t able 36: w atch d og t imer c ontrol (wdtctrl) ? sfr 9f h 7 6 5 4 3 2 1 0 wdte unused wdt clr unused wdt ps2 wdt ps1 wdt ps0 bit mnemonic description 7 wdte watch d og timer enable bit 0: watch d og timer is disabled 1: watch d og timer is enabled 6 unused - 5 wdtcl r watch d og timer counter clear bit [4:3] unused - 2 wdtps2 clock source divider bit 2 1 wdtps1 clock source divider bit 1 0 wdtps0 clock source divider bit 0 the wdt timeout delay can be adjusted by configuring the clock divider input on the wdt?s ti me base source clock. to select the divider value, the [wdtps2~wdtps0] bits of the wdt c ontrol r egister should be set accordingly. the following table provides the approximate timeout period s associated with different values of the wdtpsx bits of the w atc h d og t imer r egister.
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 34 of 50 t able 37: wdt t imeout p eriod at wdtps [2:0] wdt period 000 2.05ms 001 4.10ms 010 8.19ms 011 16.38ms 100 32.77ms 101 65.54ms 110 131.07ms 111 262.14ms to enable the wdt, the user must set bit 7 (wdte) o f the wdtctrl register to 1. t he 16 - bit counter will start to count using the internal 250khz oscillator as a clock source, divided according to the value of the wdtps2~wdtps0 bits. to c lear the wdt , set the wdtclr bit of the wdtctrl to 1. this action wi ll clear the contents of the 16 - bit counter and force it to restart. i f the w atch d og t imer overflows, it will reset the processor , the wdr bit (7) of syscon register will be set to 1 and the wdte bit will be cleared to 0. the user should check the wdr bi t if an unexpected reset has taken place. if the wdr bit is set, the p rocessor r eset was caused by the watchdog tim er. wdt i nitialization example the following program example demonstrates the watchdog timer initialization sequence and the routine to peri odically clear it. ;*** variable definition *** cptr equ 020h portval equ 00h ;*** program start here **** org 0000h ljmp start ;*** main program start *** org 0100h ;*** check if reset was caused by the watchdog timer start: mov a,syscon anl a,#80h jnz wdtreset ;wdt bit set - > we got a wdt reset initwdt: mov wdtkey,#01eh ;unlock the wdtctrl reg access in mov wdtkey,#0e1h ;writing mode mov wdtctrl,#10000010b ;config the watchdog timer ;bit 7 - wdten= 1 watchdog timer enable ;bit 6 - unused ;bit 5 - wdtclr=1 watchdog clear ;bit 4:3 - unused ;bit 2:0 - wdtclk=010 - wdt timeout = 8ms mov wdtkey,#0e1h ;lock the wdtctrl access in writing mov wdtkey,#01eh mov portval,#00h ;init p ort value to 00h wdtreset: nop ;if the wdt cause the reset init portval mov a,portval ;toggle p1 value cpl a mov portval,a mov p1,a ;*** sequence to clear the watchdog timer (same as config) loop: ;mov wdtkey,#01eh ;unloc k the wdtctrl reg access in ;writing mode ;mov wdtkey,#0e1h ;mov wdtctrl,#10100010b ;config the wdt timer ;bit 7 - wdten=1 wdt enable ;bit 6 - unused ;bit 5 - wdtclr=1 wdt clear ;bit 4:3 - unused ;bit 2:0 - wdtclk=010 - wdt ti meout = 8ms ;mov wdtkey,#0e1h ;lock the wdtctrl access in writing ;mov wdtkey,#01eh (?) ljmp loop
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 35 of 50 pulse width modulation (pwm) the pulse width modulation (pwm) module consists of four o utputs. each output uses an 8 - bit pwm data registe r (pwmd) to set the number of continuous pulses within a pwm frame cycle. pwm function description: each 8 - bit pwm output incorporates an 8 - bit register that consists of a 5 - bit pwm (5 msbs) and a 3 - bit (lsbs) narrow pulse gen erator (np). the 5 - bit pwm de termines the duty cycle of the output. the 3 - bit npx generates and inserts narrow pulses among the pwm frame made of 8 cycles. the number of pulses generated is equal to the number programmed in to the 3 - bit np. the np is used to generate an equivalent 8 - bit resolution pwm - type dac with a reasonably high repetition rate through a 5 - bit pwm clock speed. the pdck[1:0] settings of the pwmc (a3h) register are used to derive the pwm clock from fosc. the pwm output cycle frame repetition rate (frequ ency) is calculated using the following formula: pwm output enable register t able 38: pwm o utput e nable r egister (pwme) ? sfr 9b h 7 6 5 4 -- pwm3e pwm2e 3 2 1 0 pwm1e pwm0e - bit mnemonic description 7:6 - 5 pwm3e 4 pwm2e 3 pwm1e 2 pwm0e when bit is set to one, the corresponding pwm pin is active as a pwm function. when the bit is cleared, the corresponding pwm pin is active as an i/o pin. these five bits are cleared upon reset. 1:0 - pwm regist ers - pwm control register the table below describes the pwm control register . t able 39: pwm c ontrol r egister (pwmc) ? sfr a3 h 7 6 5 4 3 2 1 0 unused pdck1 pdck0 bit mnemonic description [7:2] unused - 1 pdck1 input clock freque ncy divider bit 1 0 pdck0 input clock frequency divider bit 0 the following table describes the relationship between the values of pdck1/pdck0 and the value of the divider. numerical values of the corresponding frequencies are also provided. pdck1 pdck o divider pwm clock, fosc=20mhz pwm clock, fosc=24mhz 0 0 2 10mhz 12mhz 0 1 4 5mhz 6mhz 1 0 8 2.5mhz 3mhz 1 1 16 1.25mhz 1.5mhz pwm clock = f osc 2 (pdck [1:0] +1) pwm clock = f osc 32 x 2 (pdck [1:0] +1)
VRS51C1100 _____________________________________________________________ _________________________________ www.ramtron.com page 36 of 50 pwm data registers the following tables describe the pwm data r egisters. the pwmdx bits hold the content of the pwm data regist er and determine the duty cycle of the pwm output waveform s . the npx[2:0] bits will insert narrow pulses in to the 8 - pwm - cycle frame. t able 40: pwm d ata r egister 0 (pwmd0) ? sfr a4 h 7 6 5 4 pwmd0.4 pwmd0.3 pwmd0.2 pwmd0.1 3 2 1 0 pwmd0.0 np0.2 np0.1 np0.0 bit mnemonic description 7 pwmd0.4 contents of pwm data register 0 bit 4 6 pwmd0.3 contents of pwm data register 0 bit 3 5 pwmd0.2 contents of pwm data register 0 bit 2 4 pwmd0.1 contents of pwm data register 0 bi t 1 3 pwmd0.0 contents of pwm data register 0 bit 0 2 np0.2 1 np0.1 0 np0.0 inserts narrow pulses in a 8 - pwm - cycle frame t able 41: pwm d ata r egister 1 (pwmd1) ? sfr a5 h 7 6 5 4 pwmd1.4 pwmd1.3 pwmd1.2 pwmd1.1 3 2 1 0 pwm d1.0 np1.2 np1.1 np1.0 bit mnemonic description 7 pwmd1.4 contents of pwm data register 1 bit 4 6 pwmd1.3 contents of pwm data register 1 bit 3 5 pwmd1.2 contents of pwm data register 1 bit 2 4 pwmd1.1 contents of pwm data register 1 bit 1 3 pwmd1 .0 contents of pwm data register 1 bit 0 2 np1.2 1 np1.1 0 np1.0 inserts narrow pulses in a 8 - pwm - cycle frame t able 42: pwm d ata r egister 2 (pwmd2) ? sfr a6 h 7 6 5 4 pwmd2.4 pwmd2.3 pwmd2.2 pwmd2.1 3 2 1 0 pwmd2.0 np2.2 n p2.1 np2.0 bit mnemonic description 7 pwmd2.4 contents of pwm data register 2 bit 4 6 pwmd2.3 contents of pwm data register 2 bit 3 5 pwmd2.2 contents of pwm data register 2 bit 2 4 pwmd2.1 contents of pwm data register 2 bit 1 3 pwmd2.0 contents of pwm data register 2 bit 0 2 np2.2 1 np2.1 0 np2.0 inserts narrow pulses in a 8 - pwm - cycle frame t able 43: pwm d ata r egister 3 (pwmd3) ? sfr a7 h 7 6 5 4 pwmd3.4 pwmd3.3 pwmd3.2 pwmd3.1 3 2 1 0 pwmd3.0 np3.2 np3.1 np3.0 bit mnemonic description 7 pwmd3.4 contents of pwm data register 3 bit 4 6 pwmd3.3 contents of pwm data register 3 bit 3 5 pwmd3.2 contents of pwm data register 3 bit 2 4 pwmd3.1 contents of pwm data register 3 bit 1 3 pwmd3.0 contents of pwm data register 3 bit 0 2 np3.2 1 np3.1 inserts narrow pulses in a 8 - pwm - cycle frame the table below shows the number of pwm cycles inserted in to an 8 - cycle frame when we vary the np number . np[2:0] number of pwm cycles inserted in an 8 - cycle frame 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 37 of 50 example of pwm timing diagram mov pwmd0 #83h ; pwmd04:0]=10h (=16t high, 16t low), np02:0] = 3 mov pwme, #08h ; enable p1.3 as pwm output pin f igure 22: pwm t iming d iagra m 32t 32t 32t 32t 32t 32t 32t 32t 1t 1t 1t 16 16 16 16 16 1st cycle frame 2nd cycle frame 3rd cycle frame 4th cycle frame 5th cycle frame 6th cycle frame 7th cycle frame 8th cycle frame (narrow pulse inserted by np0[2:0]=3) pwm clock= 1/t= fosc / 2^(pdiv+1) the spwm output cycle frame frequency = spwm clock/32 = [fosc/2^(pdiv+1)]/32 if fosc = 20mhz, pdck[1:0] of pwmc = #03h, then pwm clock = 20mhz/2^4 = 20mhz/16 = 1.25mhz. pwm output cycle frame frequency = (20mhz/2^4)/32 = 39.1 khz.
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 38 of 50 crystal consideration the crystal connected to the VRS51C1100 osc illator input should be of a parallel type, operating in fundamental mode. the following table provides suggested capacitor and resistor feedback values for different operating frequencies. valid for VRS51C1100 xtal 3mhz 6mhz 9mhz 12mhz c1 30 pf 30 pf 30 pf 30 pf c2 30 pf 30 pf 30 pf 30 pf r open open open open xtal 16mhz 25mhz 33mhz 40mhz c1 30 pf 15 pf 5 pf 2 pf c2 30 pf 15 pf 5 pf 2 pf r open 62ko 6.8k o 4.7ko note: oscillator circuits may differ with different crystals or ceramic resonators in higher oscillat or frequenc ies . crystals or ceramic resonator characteristics vary from one manufacturer to the other. the user should review the technical literature supplied with specific crystal or ceramic resonator s or contact the manufacturer to select the appropriate values for external components. vrs 51 c 1100 xtal 1 xtal 2 xtal r c 1 c 2
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 39 of 50 operating conditions t able 44: o perating c onditions symbol description min. typ. max. unit remarks ta operating temperature - 40 25 +85 oc am bient temperature under bias ts storage temperature - 55 25 155 oc vcc5 supply voltage 4.5 5.0 5.5 v fosc 40 oscillator frequency 3.0 - 40 mhz for 5v application dc characteristics t able 45: dc c haracteristics symbol parameter valid min. max. unit test conditions vil1 input low voltage port 0 ,1,2,3,4,#ea - 0.5 1.0 v vcc=5v vil2 input low voltage res, xtal1 0 0 . 8 v vcc=5v vih1 input high voltage port 0,1,2,3,4,#ea 2.0 vcc+0.5 v vcc=5v vi h2 input high voltage res, xtal1 70% vcc vcc+0.5 v vcc=5v vol1 output low voltage port 0, ale, #psen 0.45 v iol=3.2ma vol2 output low voltage port 1,2,3,4 0.45 v iol=1.6ma 2.4 v ioh= - 800ua voh1 output high voltage port 0 90%vcc v ioh= - 80ua 2.4 v ioh= - 60ua voh2 output high voltage port 1,2,3,4, ale,#psen 90% vcc v ioh= - 10ua iil logical 0 input current port 1,2,3,4 - 75 ua vin=0.45v itl logical transition current port 1,2,3,4 - 650 ua vin=2.ov ili input leakage current port 0, #ea + 10 ua 0.45v VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 40 of 50 ac characteristics t able 46: ac c haracteristics fosc 16 variable fosc symbol parameter valid cycle min. type max. min. type max. unit t lhll ale pulse width rd/wrt 115 2xt - 10 ns t avll address valid to ale low rd/wrt 43 t - 20 ns t llax address hold after ale low rd/wrt 53 t - 10 ns t lliv ale low to valid instruction in rd 240 4xt - 10 ns t llpl ale low to #psen low rd 53 t - 10 ns t plph #psen pulse width rd 173 3xt - 15 ns t pliv #psen low to valid instruction in rd 177 3xt - 10 ns t pxix instruction hold after #psen rd 0 0 ns t pxiz instruction fl oat after #psen rd 87 t + 25 ns t avi v address to valid instruction in rd 292 5xt - 20 ns t plaz #psen low to address float rd 10 10 ns t rlrh #rd pulse width rd 365 6xt - 10 ns t wlwh #wr pulse width wrt 365 6xt - 10 ns t r ldv #rd low to valid data in rd 302 5xt - 10 ns t rhdx data hold after #rd rd 0 0 ns t rhdz data float after #rd rd 145 2xt + 20 ns t lldv ale low to valid data in rd 590 8xt - 10 ns t avdv address to valid data in rd 542 9xt - 20 ns t llyl ale low to #wr high or #rd low rd/wrt 178 197 3xt - 10 3xt + 10 ns t avyl address valid to #wr or #rd low rd/wrt 230 4xt - 20 ns t qvwh data valid to #wr high wrt 403 7xt - 35 ns t qvwx data valid to #wr transition wrt 38 t - 25 ns t whqx data hold after #wr wrt 73 t + 10 ns t rlaz #rd low to address float rd 5 ns t yalh #w r or #rd high to ale high rd/wrt 53 72 t - 10 t+10 ns t chcl clock fall time ns t clcx clock low time ns t clch clock ri se time ns t chcx clock high time ns t,tc lcl clock period 63 1/fosc ns
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 41 of 50 data memory read cycle timing the following timing diagram provides data memory read cycle timing information . f igure 24: d ata m emor y r ead c ycle t iming t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 osc ale #psen #rd port2 port0 address a15-a8 inst in a7-a0 float data in float address or float 7 8 1 2 5 3 3 4 6 float
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 42 of 50 program memory read cycle timing the following timing diagram provides program memory read cycle timing information . f igure 25: p rogram m emory r ead c ycle t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 osc ale #psen #rd,#wr port2 port0 float a7-a0 float float float float a7-a0 inst in inst in address a15-a8 address a15-a8 1 2 5 7 3 3 4 6 8
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 43 of 50 data memory write cycle timing the following timing diagram provides data memory write cycle timing information . f igure 26: d ata m emory w rite c ycle t iming t12 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t1 t2 t3 osc ale #psen #wr port2 port0 address a15-a8 inst in a7-a0 data out address or float 1 5 float 2 2 3 6 4
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 44 of 50 i/o ports timing the following timi ng diagram provides port timing information . f igure 27: i/o p orts t iming t7 t8 t9 t10 t11 t12 t1 t2 t3 t4 t5 t6 t7 t8 sampled sampled sampled current data next data x1 inputs p0,p1 inputs p2,p3 output by mov px, src rxd at serial port shift clock mode 0
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 45 of 50 timing requirement of the external clock (vss = 0v is assumed) f igure 28: t iming r equirement of e xternal c lock (vss= 0.0v is assumed ) tclcl tchcx tclch tchcl tclcx 70% vdd 20% vdd-0.1v vdd - 0.5v 0.45v external program memory read cycle the following timing diagram provides external program memory read cycle timing information . f igure 29: e xternal p rogram m emory r ead c ycle tplph tpxix tpxiz instruction in a0-a7 a8-a15 p2.0-p2.7 or ab-a15 from dph a0-a7 tllpl tlhll tavll tllax tplaz tpliv taviv #psen ale port 0 port2
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 46 of 50 external data memory read cycle the following timing diagram provides external data memory read cycle timing information . f igure 30: e xternal d ata m emory r ead c ycle tlldv tllyl trlrh trlaz a0-a7 from ri or dpl tavll tllax tavyl tavdv p2.0-p2.7 or a8 -a15 from dph a8-a15 from pch data in trhdx trhdz a0-a7 from pcl instrl in trldv tyhlh #psen ale #rd port 0 port 2
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 47 of 50 external data memory write cycle the following timing diagram provides external data memory write cycle timing information . f igure 31: e xternal d ata m emory w rite c ycle #psen twlwh tllyl tlhll tavll tllax tqvwx tqvwh twhqx tyhlh tavyl ale #wr port 0 port 2 p2.0-p2.7 or a8-a15 from dph data out a0-a7 from ri or dpl a8-a15 from pch a0-a7 from pcl instrl in .
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 48 of 50 plastic chip carrier ( plcc - 44 ) vrs 51 c 1100 plcc - 44 d hd e he gd e c b1 b note: 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inch 4. general appearance spec should be based on final visual inspection spec. ge y a2 a1 a l t able 47: d imensions of plcc - 44 c hip c arrier dimension in inch dimension in mm symbol minimal/maximal minimal/maximal a - /0.185 - /4.70 al 0.020/ - 0 .51/ a2 0.145/0.155 3.68/3.94 bl 0.026/0.032 0.66/0.81 b 0.016/0.022 0.41/0.56 c 0.008/0.014 0.20/0.36 d 0.648/0.658 16.46/16.71 e 0.648/0.658 16.46/16.71 e 0.050 bsc 1.27 bsc gd 0.590/0.630 14.99/16.00 ge 0.590/0.630 14.99/16.00 hd 0.680/0.7 00 17.27/17.78 he 0.680/0.700 17.27/17.78 l 0.090/0.110 2.29/2.79 ? - /0.004 - /0.10 ?y / /
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 49 of 50 plastic quad flat package (qfp - 44 ) vrs 51 c 1100 qfp - 44 e 2 e 1 e d 2 d 1 d e seating plane c e1 note: 1. dimensions d1 and e1 do not include mold protrusion. 2. allo wance protrusion is 0.25mm per side. 3. dimensions d1 and e1 do not include mold mismatch and are determined datum plane. 4. dimension b does not include dambar protrusion. 5. allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximu m material condition. dambar cannot be located on the lower radius of the lead foot. l c l1 s s b a a1 a2 t able 48: d imensions of qfp - 44 c hip c arrier dimension in in. dimension in mm symbol minimal/maximal minimal/maximal a - /0.100 - /2.55 al 0.006/0.014 0.15/0.35 a2 0.071 / 0.087 1.80/2.20 b 0.012/0.018 0.30/0.45 c 0.004 / 0.009 0.09/0.20 d 0.520 bsc 13.20 bsc d1 0.394 bsc 10.00 bsc d2 0.315 8.00 e 0.520 bsc 13.20 bsc e1 0.394 bsc 10.00 bsc e2 0.315 8.00 e 0.031 bsc 0.80 bsc l 0.029 / 0.041 0.73/1.03 l1 0.063 1.60 r1 0.005/ - 0.13/ - r2 0.005/0.012 0.13/0.30 s 0.008/ - 0.20/ - 0 0 /7 as left ? 1 0 / - as left ? 2 10 ref as left ? 3 7 ref as left ?c 0.004 0.10 3 gage plane 0.25mm r1 2 r2
VRS51C1100 ______________________________________________________________________________________________ www.ramtron.com page 50 of 50 ordering information device number structure VRS51C1100 ordering options (no ispv2 firmware preprogrammed) device number flash size ram size package option voltage temperature frequency VRS51C1100 - 40 - l 64kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - q 64kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - p 64kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - lg 64 kb 1 kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - qg 64kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - pg 64kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 ordering options (with ispv2 firmware preprogrammed) device number flash size ram size package option voltage temperature frequenc y VRS51C1100 - 40 - l - ispv2 64kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - q - ispv2 64kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - p - ispv2 64kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - lg - ispv2 64 kb 1kb plcc - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - qg - ispv2 64kb 1kb qfp - 44 4.5v to 5.5v - 40c to +85c 40mhz VRS51C1100 - 40 - pg - ispv2 64kb 1kb dip - 40 4.5v to 5.5v - 40c to +85c 40mhz disclaimers right to make change - ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. customers should obtain the most current and relevant infor mation before placing orders. use in applications - ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representa tions or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. customers are responsible for product design and applications using ramtron parts. ramtron assumes no liability for applicat ions assistance or customer product design. life support ? ramtron products are not designed for use in life support systems or devices. ramtron customers using or selling goal products for use in such applications do so at their own risk and agree to full y indemnify ramtron for any damages resulting from such applications.

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