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ds04-21370-2e fujitsu semiconductor data sheet assp fractional-n pll frequency synthesizer mb15f88ul n n n n description the fujitsu mb15f88ul is fractional-n phase locked loop (pll) frequency synthesizer with fast lock up function. the fractional-n pll operating up to 2600 mhz and the integer pll operating up to 1200 mhz are integrated on one chip. the mb15f88ul is used as charge pump which is well-balanced output current with 1.5 ma and 6 ma selectable by serial data, direct power save control and digital lock detector. in addition, the mb15f88ul adopts a new architecture to achieve fast lock. the new package (thin bump chip carrier20) decreases a mount area of the mb15f88ul more than 30 % comparing with the former b.c.c.16 (for dual pll, mb15f08sl) . the mb15f88ul is ideally suited for wireless mobile communications, such as w-cdma. n n n n features ? high frequency operation : rx synthesizer : 2600 mhz max tx synthesizer : 1200 mhz max ? low power supply voltage : v cc = 2.7 v to 3.6 v ? ultra low power supply current : i cc = 6.0 ma typ ( v cc = vp = 3.0 v, ta = + 25 c, sw = 0 in tx and rx locking state) ? 23-bit shift register input control (continued) n n n n packages 20-pin, plastic tssop 20-pad, plastic bcc (fpt-20p-m06) (lcc-20p-m05)
mb15f88ul 2 (continued) ? direct power saving function : power supply current in power saving mode typ 0.1 m a (v cc = vp = 3.0 v, ta = + 25 c) , max 10 m a (v cc = vp = 3.0 v) ? fractional function : selectable modulo 5 or 8/acheiving fast lock and low phase noise (implemented in rx) ? dual modulus prescaler : 2600 mhz prescaler (32/33 fixed) /1200 mhz prescaler (16/17 or 32/33) ? serial input 14-bit programmable reference divider : r = 8 to 16,383 ? serial input programmable divider consisting of : rx section - binary 5-bit swallow counter : 0 to 31 - binary 10-bit programmable counter : 34 to 1,023 - binary 4-bit fractional counter numerator : 0 to 15 tx section - binary 5-bit swallow counter : 0 to 31 - binary 11-bit programmable counter : 3 to 2,047 ? on-chip phase comparator for fast lock and low noise ? operating temperature : ta = - 40 c to + 85 c ? small package bump chip carrier.0 (3.4 mm 3.6 mm 0.6 mm) n n n n pin assignments (bcc-20) top view (lcc-20p-m05) (tssop-20) top view (fpt-20p-m06) osc in gnd fin tx xfin tx gnd tx v cctx ps tx vp tx d otx ld/fout clock data le fin rx xfin rx gnd rx v ccrx ps rx vp rx d orx 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd clock d otx 1 2 3 4 5 678 9 10 11 12 13 14 15 16 19 18 17 20 gnd tx gnd rx v cctx vp tx le fin rx fin tx v ccrx ps rx ps tx xfin rx xfin tx osc in data ld/fout d orx vp rx
mb15f88ul 3 n n n n pin description pin no. pin name i/o descriptions tssop bcc 119osc in i the programmable reference divider input pin. tcxo should be connected with an ac coupling capacitor. 220gnd ? ground pin for osc input buffer and the shift register circuit. 31fin tx i prescaler input pin for the tx-pll. connection to an external vco should be ac coupling. 42xfin tx i prescaler complimentary input pin for the tx-pll section. this pin should be grounded via a capacitor. 53gnd tx ? ground pin for the tx-pll section. 64v cctx ? power supply voltage input pin for the tx-pll section (except for the charge pump circuit) , the shift register and the oscillator input buffer. when power is off, latched data of tx-pll is lost. 75ps tx i power saving mode control pin for the tx-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps tx = h ; normal mode, ps tx = l ; power saving mode 86vp tx ? power supply voltage input pin for the tx-pll charge pump. 97do tx o charge pump output pin for the tx-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 10 8 ld/fout o look detect signal output (ld) /phase comparator monitoring output (fout) pins. the output signal is selected by an lds bit in a serial data. lds bit = h ; outputs fout signal, lds bit = l ; outputs ld signal 11 9 do rx o charge pump output pin for the rx-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 12 10 vp rx ? power supply voltage input pin for the rx-pll charge pump. 13 11 ps rx i power saving mode control pin for the rx-pll section. this pin must be set at l when the power supply is started up. (open is prohibited. ) ps rx = h ; normal mode, ps rx = l ; power saving mode 14 12 v ccrx ? power supply voltage input pin for the rx-pll section (except for the charge pump circuit) . 15 13 gnd rx ? ground pin for the rx-pll section. 16 14 xfin rx i prescaler complimentary input pin for the rx-pll section. this pin should be grounded via a capacitor. 17 15 fin rx i prescaler input pin for the rx-pll. connection to an external vco should be ac coupling. 18 16 le i load enable signal input pin (with the schmitt trigger circuit.) on a rising edge of load enable, data in the shift register is transferred to the cor- responding latch according to the control bit in a serial data. 19 17 data i serial data input pin (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (tx-ref counter, tx-prog. counter, rx-ref. counter, rx-prog. counter) according to the control bit in a serial data. 20 18 clock i clock input pin for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a rising edge of the clock.
mb15f88ul 4 n n n n block diagram 7 3 4 1 17 11 10 16 13 18 19 20 12 15 14 2 9 8 5 6 ps tx fin tx xfin tx osc in (5) (7) (8) (9) (18) (17) (16) (11) (14) (15) (1) (2) (19) power saving tx-pll prescaler (tx-pll) 16/17, 32/33 5-bit latch 11-bit latch binary 14-bit pro- grammable ref. counter (tx-pll) binary 11-bit programmable counter (tx-pll) vcc tx gnd tx vp tx (4) (3) (6) (10) (13) (12) (20) fp tx phase comp. (tx-pll) charge pump (tx-pll) do tx ld/fout 14-bit latch binary 5-bit swallow counter (tx-pll) lds t1 t2 swc fcc csc 6-bit latch lock det. (tx-pll) ld tx slector ld tx ld rx fr tx fr rx fp tx fp rx or lock det. (rx-pll) phase comp. (rx-pll) charge pump (rx-pll) do rx sc (rx-pll) sc1 sc2 vp rx gnd rx gnd vcc rx clock data le ps rx xfin rx fin rx schmitt circuit schmitt circuit schmitt circuit c n 1 c n 2 c n 3 23-bit shift register latch selector power saving rx-pll prescaler (rx-pll) 32/33 md2 binary 5-bit swallow counter (rx-pll) binary 10-bit programmable counter (rx-pll) 5-bit latch 10-bit latch md1 f 1 f 2 f 3 f 4 4-bit latch fractional counter 5, 8 fr rx fp rx fr rx fp rx selector sc1 qm sc2 swf fcf csf 6-bit latch 14-bit latch binary 14-bit pro- grammable ref. counter (rx-pll) or o : tssop 20 ( ) : bcc 20
mb15f88ul 5 n n n n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max power supply voltage v cc - 0.5 + 4.0 v vp v cc + 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld/fout v o gnd v cc v d o v do gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit remark min typ max power supply voltage v cc 2.7 3.0 3.6 v v ccrx = v cctx vp v cc 3.0 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f88ul 6 * n n n n electrical characteristics (v cc = 2.7 v to 3.6 v, ta = - 40 c to + 85 c) (continued) parameter symbol condition value unit min typ max power supply current i cctx * 1 fin tx = 910 mhz, sw c = 0, v cctx = vp tx = 3.0 v 1.3 2.0 2.8 ma i ccrx * 1 fin rx = 2500 mhz, v ccrx = vp rx = 3.0 v 2.6 4.0 5.6 ma power saving current i pstx ps = l ? 0.1 * 2 10 m a i psrx ps = l ? 0.1 * 2 10 m a operating frequency fin tx * 3 fin tx tx pll 100 ? 1200 mhz fin rx * 3 fin rx rx pll 1700 ? 2600 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin tx pfin tx tx pll, 50 w system - 15 ?+ 2dbm fin rx pfin rx rx pll, 50 w system - 15 ?+ 2dbm osc in v osc ? 0.5 ? v cc vp-p h level input voltage data, clock, le v ih schmitt triger input 0.7v cc + 0.4 ?? v l level input voltage v il schmitt triger input ?? 0.3v cc - 0.4 h level input voltage ps tx ps rx v ih ? 0.7v cc ?? v l level input voltage v il ??? 0.3v cc h level input current data, clock, le, ps tx , ps rx i ih * 4 ?- 1.0 ?+ 1.0 m a l level input current i il * 4 ?- 1.0 ?+ 1.0 h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il * 4 ?- 100 ? 0 h level output voltage ld/ fout v oh v cc = vp = 3.0 v, i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 3.0 v, i ol = 1 ma ?? 0.4 h level output voltage do tx do rx v doh v cc = vp = 3.0 v, i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 3.0 v, i dol = 0.5 ma ?? 0.4 high impedance cutoff current do tx do rx i off v cc = vp = 3.0 v, v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/ fout i oh * 4 v cc = vp = 3.0 v ??- 1.0 ma l level output current i ol * 4 v cc = vp = 3.0 v 1.0 ??
mb15f88ul 7 (continued) (v cc = 2.7 v to 3.6 v, ta = - 40 c to + 85 c) *1 : conditions ; fosc = 13 mhz, ta = + 25 c in locking state. *2 : v cctx = vp tx = v ccrx = vp rx = 3.0 v, fosc = 13 mhz, ta = + 25 c, in power saving mode. *3 : ac coupling. 1000 pf capacitor is connected. *4 : the symbol C (minus) means direction of current flow. *5 : v cc = vp = 3.0 v, ta = + 25 c (||i 3 | - |i 4 ||) / [ (|i 3 | + |i 4 |) / 2] 100 ( % ) *6 : v cc = vp = 3.0 v, ta = + 25 c [ (||i 2 | - |i 1 ||) / 2] / [ (|i 1 | + |i 2 |) / 2] 100 ( % ) (applied to each l dol and l doh ) *7 : v cc = vp = 3.0 v, ta = + 25 c[ (||i do ( + 85 c) | - |i do (C40 c) ||) / 2] / [ (|i do ( + 85 c) | + |i do (C40 c) |) / 2] 100 ( % ) (applied to each i dol and i doh ) parameter symbol condition value unit min typ max h level output current do tx do rx i doh * 4 v cc = vp = 3.0 v, v doh = vp / 2, ta = + 25 c cs bit = h - 8.2 - 6.0 - 4.1 ma cs bit = l - 2.2 - 1.5 - 0.8 ma l level output current i dol v cc = vp = 3.0 v, v dol = vp / 2, ta = + 25 c cs bit = h 4.1 6.0 8.2 ma cs bit = l 0.8 1.5 2.2 ma charge pump current rate i dol /i doh i domt * 5 v do = vp / 2 ? 3 ?% vs v do i dovd * 6 0.5 v v do vp - 0.5 v ? 10 ?% vs ta i dota * 7 - 40 c ta + 85 c, v do = vp / 2 ? 5 ?% i dol i 1 i 3 i 2 i 1 i 4 i 2 0.5 vp/2 vp - 0.5 vp i doh output voltage (v)
mb15f88ul 8 n n n n functional description 1. serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of tx/rx-pll sections and programmable reference dividers of tx/rx-pll sections are controlled individually. serial data of binary code is entered through data pin. on a rising edge of clock, one bit of serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. note : cn3 = 1 is prohibited (1) serial data format the programmable reference counter for the tx-pll the programmable counter and the swallow counter for the tx-pll the programmable reference counter for the rx-pll the programmable counter and the swallow counter for the rx-pll cn1 01 0 1 cn2 00 1 1 cn3 00 0 0 note: data input with msb first. 1234567891011121314151617181920212223 000r c 1r c 2r c 3r c 4r c 5r c 6r c 7r c 8r c 9r c 10 r c 11 r c 12 r c 13 r c 14 lds t1 t2 sw c fc c cs c 100a c 1a c 2a c 3a c 4a c 50 0n c 1n c 2n c 3n c 4n c 5n c 6n c 7n c 8n c 9n c 10 n c 11 x x 010r f 1r f 2r f 3r f 4r f 5r f 6r f 7r f 8r f 9r f 10 r f 11 r f 12 r f 13 r f 14qmsc1sc21fc f cs f 110a f 1a f 2a f 3a f 4a f 5n f 1n f 2n f 3n f 4n f 5n f 6n f 7n f 8n f 9n f 10 f1 f2 f3 f4 0 r c 1 to r c 14 : divide ratio setting bits for the reference counter of the tx (8 to 16383) a c 1 to a c 5 : divide ratio setting bits for the swallow counter of the tx (0 to 31, a < n) n c 1 to n c 11 : divide ratio setting bits for the programmable counter of the tx (3 to 2047) lds, t1, t2 : select bits for the lock detect output or a monitoring phase comparison frequency sw c : divide ratio setting for the prescaler of the tx fc c : phase control bit for the phase detector of the tx cs c : charge pump current select bit of the tx r f 1 to r f 14 : divide ratio setting bits for the reference counter of the rx (8 to 16383) a f 1 to a f 5 : divide ratio setting bits for the swallow counter of the rx (0 to 31, a < n - 2) n f 1 to n f 10 : divide ratio setting bits for the programmable counter of the rx (34 to 1023) f1 to f4 : fractional-n increment setting bit for the fractional accumulator (0 to 15, f < q) qm : fractional-n modulus selection bit. 1 modulus = 8, 0 modulus = 5 sc1, sc2 : spurious cancel set bit of the rx. fc f : phase control bit for the phase detector of the rx. cs f : charge pump current select bit of the rx x : dummy bit (set 0 or 1) lsb msb direction of data shift control bit (cn3) control bit (cn2) control bit (cn1)
mb15f88ul 9 (2) data setting rx synthesizer data setting (fractional-n) the divide ratio can be calculated using the following equation : f vcorx = n total fosc ? r n total = p n + a + f / q (a < n - 2, f < q) binary 14 - bit programmable reference counter data setting (r f 1 to r f 14) note : divide ratio less than 8 is prohibited. fractional-n incremant of the fractional accumulator data setting ( f1 to f4 ) note : f < q, f5 = 0 fractional-n modulo data setting ( q ) divide ratio (r) r f 14 r f 13 r f 12 r f 11 r f 10 r f 9r f 8r f 7r f 6r f 5r f 4r f 3r f 2r f 1 8 00000000001000 9 00000000001001 ? ?????????????? 52 00000000110100 ? ?????????????? 16383 11111111111111 setting value(f) f4 f3 f2 f1 0 0000 1 0001 2 0010 ? ???? 151111 qm modulo-q 05 18 f vcorx : output frequency of external voltage controlled oscillator (vco) n total : total division ratio from prescaler input to the phase detector input fosc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14 bit referance counter (8 to 16383) p : preset divide ratio of modulus prescaler (32 fixed) n : preset divide ratio of binary 10 bit programmable counter (34 to 1023) a : preset divide ratio of binary 5 bit swallow counter (0 to 31) f : a numerator of fractional-n (0 to 15) q : a denominator of fractional-n qm bit = 1 modulo 8, qm bit = 0 modulo 5
mb15f88ul 10 binary 10 - bit programable counter data setting ( n f 1 to n f 10 ) note : divide ratio less than 34 is prohibited. binary 5-bit swallow counter data setting (a f 1 to a f 5) note : a < n - 2 spurious cancel bit setting note : the bits set how much the amount of spurious cancel. if the large is selected, a spurious is tended to become small. phase comparator phase switching data setting notes : z = high-z depending upon the vco and lpf polarity, fc bit should be set. charge pump current select bit setting divide ratio (n) n f 10 n f 9n f 8n f 7n f 6n f 5n f 4n f 3n f 2n f 1 34 0000100010 35 0000100011 ? ?????????? 64 0001000000 ? ?????????? 1023 1 1 11111111 divide ratio (a) a f 5a f 4a f 3a f 2a f 1 0 00000 1 00001 2 00010 ? ????? 31 11111 spurious cancel amount sc1 sc2 large 0 0 midium 0 1 small 1 0 fc f = = = = 1 fc f = = = = 0 d o d o fr > fp h l fr < fp l h fr = fp z z vco polarity 1 2 cs f current value 1 6.0 ma 0 1.5 ma
mb15f88ul 11 tx synthesizer data setting (integer) the divide ratio can be calculated using the following equation : f vcotx = [ (p n) + a] fosc ? r (a < n) binary 14-bit programmable reference counter data setting (r c 1 to r c 14) note : divide ratio less than 8 is prohibited. binary 11-bit programmable counter data setting (n c 1 to n c 11) note : divide ratio less than 3 is prohibited. binary 5-bit swallow counter data setting (a c 1 to a c 5) note : a < n, a c 6 to a c 7 = 0 prescaler data setting (sw c ) divide ratio (r) r c 14 r c 13 r c 12 r c 11 r c 10 r c 9r c 8r c 7r c 6r c 5r c 4r c 3r c 2r c 1 8 00000000001000 9 00000000001001 ? ?????????????? 16383 11111111111111 divide ratio (n) n c 11 n c 10 n c 9n c 8n c 7n c 6n c 5n c 4n c 3n c 2n c 1 3 00000000011 4 00000000100 ? ??????????? 2047 1 1 1 1 1 1 1 1 1 1 1 divide ratio (a) a c 5a c 4a c 3a c 2a c 1 0 00000 1 00001 2 00010 ? ????? 31 11111 sw c prescaler divide ratio 116/17 032/33 f vcotx : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of modulus prescaler (16 or 32) n : preset divide ratio of binary 11 bit programmable counter (3 to 2047) a : preset divide ratio of binary 5 bit swallow counter (0 to 31) fosc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14 bit reference counter (8 to 16383)
mb15f88ul 12 phase comparator phase switching data setting notes : z = high-z depending upon the vco and lpf polarity, fc bit should be set. charge pump current select data setting (cs c ) common setting ld/fout output select data setting fc bit setting when designing a synthesizer, the fc bit setting depends on the vco and lpf characteristics fc c = = = = 1 fc c = = = = 0 d o d o fr > fp h l fr < fp l h fr = fp z z vco polarity 1 2 cs c do current 1 6.0 ma 0 1.5 ma ld/fout lds t1 t2 ld output 0 ?? fout output fr tx 100 fr rx 110 fp tx 101 fp rx 111 (1) (2) lpf output voltage max. vco output frequency high when the lpf and vco characteristics are similar to (1) , fc : h. when the vco characteristics are similar to (2) , fc : l.
mb15f88ul 13 2. power saving mode (intermittent mode control) ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters the power saving mode, reducing the current consumption. see electrical characteristics for the specific value. the phase detector output, do, becomes high impedance. for the single pll, the lock detector, ld, remains high, indicating a locked condition. for the dual pll, the lock detector, ld, is shown in phase detector output waveform the ld output logic table . setting the ps pin high releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes : when power (v cc ) is first applied, the device must be in standby mode and ps = low, for at least 1 m s. ps pin must be set l for power on. ps pin status h normal mode l power saving mode on off v cc clock data le ps (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps = l (power saving mode) at power on (2) set serial data 1 m s after power supply remains stable (v cc 3 2.2 v) . (3) release power saving mode (ps : l ? h) 100 ns after setting serial data.
mb15f88ul 14 3. serial data input timing lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data 2nd data control bit invalid data on the rising edge of the clock, one bit of data is tranferred into shift register. note : le should be l when the data is transferred into the shift register. parameter min typ max unit parameter min typ max unit t 1 20 ?? ns t 5 100 ?? ns t 2 20 ?? ns t 6 20 ?? ns t 3 30 ?? ns t 7 100 ?? ns t 4 30 ?? ns
mb15f88ul 15 n n n n phase detector output waveform fr tx/rx fp tx/rx ld d otx/rx t wu t wl d otx/rx (fc bit = high) (fc bit = low) z h l z l h ld output logic table tx-pll section rx-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l notes : phase error detection range = - 2 p to + 2 p pulses on do tx/rx signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu 3 2/fosc : i.e. t wu 3 153.8 ns when fosc = 13 mhz t wu 4/fosc : i.e. t wl 307.6 ns when fosc = 13 mhz
mb15f88ul 16 n n n n test circuit (for measuring input sensitivity fin/osc in ) mb15f88ul s.g p.g s.g fout oscilloscope 1000 pf 50 w vp tx v cctx 0.1 m f 0.1 m f 1000 pf 1000 pf 50 w ld/fout d orx vp rx ps rx v ccrx gnd rx xfin rx fin rx le data clock d otx vp tx ps tx v cctx gnd tx xfin tx fin tx gnd osc in controller (divide ratio setting) 1000 pf 50 w 1000 pf vp rx v ccrx 0.1 m f 0.1 m f 11 12 13 14 15 16 17 18 19 20 10987654321 note : tssop-20
mb15f88ul 17 n n n n typical characteristics 1. fin input sensitivity 10.0 0.0 - 10.0 - 20.0 - 30.0 - 40.0 - 50.0 - 60.0 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 spec v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec ta = + 25 c 10.0 0.0 - 10.0 - 20.0 - 30.0 - 40.0 - 50.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 spec v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec ta = + 25 c rx-pll input sensitivity vs input frequency fin rx (mhz) pfin rx (dbm) tx-pll input sensitivity vs input frequency fin tx (mhz) pfin tx (dbm)
mb15f88ul 18 2. osc in input sensitivity spec 10 0 - 10 - 20 - 30 - 40 - 50 - 60 0 100 160 200 260 300 20 40 60 80 120 140 180 220 240 280 320 v cc = 3.6 v v cc = 2.7 v v cc = 3.0 v spec ta = + 25 c input sensitivity vs input frequency f osc (mhz) p osc (dbm)
mb15f88ul 19 3. rx-pll do output current ? 1.5 ma mode ? 6.0 ma mode charge pump output current i do (ma) i do - v do charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) v cc = vp = 3.0 v 10.0 0 - 10.0 3.0 0.0 ta = + 25 ?c v cc = vp = 3.0 v 10.0 0 - 10.0 3.0 0.0 ta = + 25?c charge pump output voltage v do (v) charge pump output voltage v do (v)
mb15f88ul 20 4. tx-pll do output current ? 1.5 ma mode ? 6.0 ma mode i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) 10.0 0 - 10.0 3.0 1.0 ta : + 25 c v cc = vp = 3.0 v 2.0 0.0 10.0 0 - 10.0 3.0 1.0 ta : + 25 c v cc = vp = 3.0 v 2.0 0.0
mb15f88ul 21 5. fin input impedance 45.859 w - 188.77 w 1 ghz 25.48 w - 103.67 w 1.7 ghz 22.152 w - 83.391 w 2 ghz 1 : 2 : 3 : start 1 000.000 000 mhz stop 2 600.000 000 mhz 4 : 17.994 w- 52.029 w 1.1765 pf 2 600.000 000 mhz 1 3 2 4 926.38 w - 970.56 w 100 mhz 120.58 w - 429.81 w 400 mhz 45.984 w - 220.31 w 800 mhz 1 : 2 : 3 : start 100.000 000 mhz stop 1 200.000 000 mhz 4 : 29.164 w- 143.77 w 922.54 ff 1 200.000 000 mhz 1 3 2 4 fin rx input impedance fin tx input impedance
mb15f88ul 22 6. osc in input impedance 1 2 4 3 15.032 k w - 10.537 k w 3 mhz 1.2688 k w - 5.2405 k w 20 mhz 352.88 w - 2.6899 k w 40 mhz 1 : 2 : 3 : 4 : 081.06 w- 1.0784 k w 1.4758 pf 100.000 000 mhz start 3.000 000 mhz stop 100.000 000 mhz osc in input impedance
mb15f88ul 23 n n n n reference information ( for lock - up time , phase noise and reference leakage ) (continued) s.g. osc in fin vco d o lpf test circuit spec trum analyzer 15 k w 820 pf 24 k w 82 pf 22 pf f vco = 2490 mhz v cc = vp = 3.0 v k v = 52 mhz/v v vco = 2.5 v fr = 1 mhz ta = + 25 c f osc = 13 mhz cp : 1.5 ma mode lpf q = 5 ? pll reference leakage ? pll phase noise atten 10 db rl 0 dbm center 2.490008 ghz rbw 3.0 khz vbw 3.0 khz span 1.000 mhz swp 280 ms d mkr - 67.17 db 200 khz vavg 30 10 db/ d mkr 200 khz - 67.17 db * d s atten 10 db rl 0 dbm center 2.49000668 ghz rbw 100 hz vbw 100 hz span 10.00 khz swp 802 ms d mkr - 60.16 db 1.00 khz vavg 19 10 db/ d mkr 1.00 khz - 60.16 db d s
mb15f88ul 24 (continued) 2.550012000 ghz 2.550008000 ghz 2.550004000 ghz - 1.933 ms 567 m s 500.0 m s/div 3.067 ms 2.490011750 ghz 2.490007750 ghz 2.490003750 ghz - 1.933 ms 567 m s 500.0 m s/div 3.067 ms pll lock up time 2490 mhz ? 2550 mhz within 1 khz lch ? hch 144 m s pll lock up time 2550 mhz ? 2490 mhz within 1 khz hch ? lch 133 m s
mb15f88ul 25 n n n n application example 0.1 m f 18 17 20 19 16 15 14 13 12 11 34 12 5678910 1000 pf 1000 pf output 3.0 v mb15f88ul 1000 pf 1000 pf 1000 pf 3.0 v 0.1 m f 0.1 m f output lock det. vco lpf vco lpf tcxo d orx ps rx vp rx xfin rx gnd rx v ccrx fin rx le data clock d otx ps tx vp tx ld/fout v cctx fin tx xfin tx gnd tx osc in gnd 3.0 v 0.1 m f 3.0 v from controller notes : clock, data, le : schmit trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input) . tssop-20
mb15f88ul 26 n n n n usage precautions (1) v ccrx , vp rx , v cctx and vp tx must be equal voltage. even if either rx-pll or tx-pll is not used, power must be supplied to v ccrx , vp rx , v cctx and vp tx to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions : -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. n n n n ordering information part number package remarks mb15f88ulpft 20-pin plastic tssop (fpt-20p-m06) MB15F88ULPVA 20-pad plastic bcc (lcc-20p-m05)
mb15f88ul 27 n n n n package dimensions (continued) 20-pin plastic tssop (fpt-20p-m06) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm ( inches ) note : the values in parentheses are reference values. c 2003 fujitsu limited f20026s-c-3-3 6.500.10(.256.004) 4.400.10 6.400.20 (.252.008) (.173.004) 0.10(.004) 0.65(.026) 0.240.08 (.009.003) 1 10 20 11 "a" 0.170.05 (.007.002) m 0.13(.005) details of "a" part 0~8 ? (.024.006) 0.600.15 (0.50(.020)) 0.25(.010) (.041.002) 1.050.05 (mounting height) 0.07 +0.03 C0.07 +.001 C.003 .003 (stand off) lead no. index * 1 * 2
mb15f88ul 28 (continued) 20-pad plastic bcc (lcc-20p-m05) dimensions in mm ( inches ) note : the values in parentheses are reference values. c 2001 fujitsu limited c20056s-c-2-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.55?.05 0.075?.025 (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) (.003?001) (mounting height) (.022?002)
mb15f88ul fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0306 ? fujitsu limited printed in japan

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