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d a t a sh eet product speci?cation supersedes data of 1995 aug 28 file under integrated circuits, ic01 1996 jul 17 integrated circuits TDA1373H general digital input (gdin)
1996 jul 17 2 philips semiconductors product speci?cation general digital input (gdin) TDA1373H features four operating modes: C sample rate conversion (src) mode C ad/da mode C slave-vco mode C slave-vcxo mode full digital sample rate conversion over a wide range of input sample rates fast and automatic detection and locking to the input sample rate with continuous tracking digital phase-locked loop (pll) with adaptive bandwidth which removes jitter on the digital audio input audio outputs (soft) muted during loop acquisition full linear phase processing based on all-fir filtering integrated full digital iec 958 demodulator for digital input signals (aes/ebu or spdif format) with intelligent error handling extended input sample frequency range iec 958 channel status (cs) and user channel (uc) outputs on-chip cs and/or uc demodulation and buffering (consumer and professional format) dedicated subcode processing for compact disc (cd) final output quantization to 16, 18 or 20 bits with optional in-audio-band noise shaping bitstream input and output for coupling with 1-bit analog-to-digital conversion (adc) and digital-to-analog conversion (dac) i 2 s and japanese serial input formats supported for src and dac functions i 2 s and japanese serial output formats supported for src and adc functions i 2 s and japanese 4 oversampled serial output available for src and adc functions 8-bit digital gain/attenuation control switchable digital signal processor (dsp)-interface (i 2 s input and output) for additional audio processing additional clock outputs available at 768, 384, 256 and 128f so 3-line serial microcontroller interface, compatible with the philips cd i.c. protocol (hcl) 5 v power supply 0.7 m m double metal complementary metal oxide semiconductor (cmos) src thd + n: C - 113 db over the 0 to 20 khz band (1 khz, 20 bits input and output) (see fig.3) C - 95 db over the 0 to 20 khz band (1 khz, 16 bits input and output) pass band ripple smaller than 0.004 db for up-sampling and down-sampling filters stop band suppression: C selectable between 70 db and 50 db for 64 up-sampling filters C 80 db for 128 down-sampling filters microcontroller operated and stand-alone mode. applications professional audio equipment for: C mixing C recording C editing C broadcasting cd-recordable (cd-r) digital speaker systems (dss) digital compact cassette recorders (dcc) digital audio tape (dat) and md recorders digital amplifiers jitter killers.
1996 jul 17 3 philips semiconductors product speci?cation general digital input (gdin) TDA1373H general description the TDA1373H is a general digital input (gdin) device for audio signals which is able to perform a high-quality sample rate conversion of digital audio signals ( src mode ). the device reads several serial input formats and signals in the iec 958 digital audio format (also known as aes/ebu or spdif signals). for this purpose a full audio digital input circuit (adic) is present in the device. an internal digital pll results in extensive jitter removal from incoming digital audio signals without any analog loop electronics. the standard 20 bit output word length can be limited to 16 or 18 bits by means of in-audio-band noise shaping. the gdin digital filters can also be reused for bitstream adc and dac conversion ( ad/da mode ). the internal digital pll can be reconfigured to operate the gdin in a slave mode, where the output sample frequency of the device is locked to the incoming sample rate ( slave-vco and slave-vcxo modes). the combination of an adic function, sample rate conversion and bitstream adc and dac results in a device with a highly versatile functionality and large replacement value in consumer and professional audio sets. quick reference data all inputs and outputs cmos compatible; unless otherwise speci?ed. ordering information symbol parameter conditions min. typ. max. unit supply v dd supply voltage f so > 44.1 khz 4.75 5 5.5 v f so 44.1 khz 4.5 5 5.5 v i dd(tot) total supply current f so = 44.1 khz - 155 - ma p tot total power dissipation f so = 44.1 khz - 775 - mw f so = 49 khz; v dd = 5.5 v - 1030 - mw iec 958 input di1s (high-sensitivity iec input) v i(p-p) ac input voltage (peak-to-peak value) 0.2 - v dd v clock and timing f so(max) maximum output sample frequency v dd = 4.75 v 49 55 - khz temperature t amb operating ambient temperature 0 70 c type number package name description version TDA1373H qfp64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 20 2.7 mm; high stand-off height sot319-1
1996 jul 17 4 philips semiconductors product speci?cation general digital input (gdin) TDA1373H block diagram fig.1 block diagram. switches mm1 and mm0 are controlled indirectly via the mode selection. all other switches can be controlled directly by the user. handbook, full pagewidth mlc334 - 2 adic (iec 958 decoder) data slicer 4 x up- sampling 44 37 48 43 62 63 1 mu em lock sa di1d di1o channel status extraction user channel extraction phase detector loop filter hold vco general control clock shop crystal oscillator 768f so 384f so 256f so 128f so 23 27 28 30 31 22 21 19 20 46 45 47 35 36 34 52 39 14 32 7 clo4 clo3 clo2 clo1 cli xtlo xtli da v dda4 v ssa4 ld cl cen cus bs ddd v 11 ddd v ddd v ddd v ddd v ddd v micro- controller interface/ stand-alone control 16 x up- sampling variable hold fifo and gain i s out 2 i s in 2 i s out 2 i s out 2 in-band noise shaper 32 x down- sampling 4 x down- sampling 64f so hold attenuator bitstream digital filter dac output 8 ssd v 33 ssd v 40 ssd v 53 ssd v 26 ssd v 29 ssd v 58 ssd v 61 ssd v 64 ssd v 12 ssd v 13 24 ssd v 17 ssd v ssd v TDA1373H 60 di2c 59 di2w 57 di2d 54 fow 56 foc 55 fod 4 ail 5 air 38 rst 42 tst1 41 tst2 stereo fos di2 3 di1s 2 dda1 v ssa1 v 25 fsl 10 do2d 16 do2w 6 do2c 50 do1d 49 do1w 51 do1c 9 aol1 15 aor1 18 cld aos dni dso ins do2 mm0 di2 di1 mm1 u pv c ws po
1996 jul 17 5 philips semiconductors product speci?cation general digital input (gdin) TDA1373H pinning symbol pin description type di1s 1 iec 958 digital audio input s (200 mv peak-to-peak value) e036a v ssa1 2 iec 958 slicer analog ground e038a v dda1 3 iec 958 slicer analog supply voltage e037a ail 4 bitstream audio input left hpp01 air 5 bitstream audio input right hpp01 do2c 6 serial digital audio output 2; bit clock output (192f so ) opf40 v ddd 7 digital supply voltage; note 1 - v ssd 8 digital ground; note 2 - aol1 9 bitstream audio output left opf40 do2d 10 dlo = 0; serial digital audio output 2; data; dlo = 1; bitstream audio output left inverted ( aol1); note 3 opf40 v ddd 11 digital supply voltage; note 1 - v ssd 12 digital ground; note 2 - v ssd 13 digital ground; note 2 - v ddd 14 digital supply voltage; note 1 - aor1 15 bitstream audio output right opf40 do2w 16 dlo = 0; serial digital audio output 2; word select output (4f so ); dlo = 1; bitstream audio output right inverted ( aor1); note 3 opf40 v ssd 17 digital ground; note 2 - cld 18 bitstream dac clock (192 or 128f so ) opf43 v dda4 19 oscillator analog supply voltage e037a v ssa4 20 oscillator analog ground e038a xtli 21 crystal input 768f so osx01 xtlo 22 crystal output osx01 cli 23 external vco input (slave-vco mode only) hpp01 v ssd 24 digital ground; note 2 - fsl 25 sa = 0 (microcontroller operated) external vco output (slave modes only); sa = 1 (stand-alone control) di11 control line; note 4 hof21 v ssd 26 digital ground; note 2 - clo1 27 clock output 768f so opf40 clo2 28 clock output 384f so opf40 v ssd 29 digital ground; note 2 - clo3 30 clock output 256f so opf40 clo4 31 clock output 128f so ; opf40 v ddd 32 digital supply voltage; note 1 - v ssd 33 digital ground; note 2 - bs 34 block sync; channel status/user channel/cd subcode opf40 cen 35 data enable; channel status/user channel/cd subcode opf40 cus 36 data bit; channel status/user channel/cd subcode opf40 em 37 iec 958 source pre-emphasis ?ag opf20
1996 jul 17 6 philips semiconductors product speci?cation general digital input (gdin) TDA1373H notes 1. all v ddd pins are internally connected. 2. all v ssd pins are internally connected. 3. dlo is a command flag from register 4 (see section command registers). 4. sa is the stand-alone/microcontroller operated pin (pin 43). di11, nsd, di2, qu1, qu0 and ms0 are command flags to control the operation of the device. for more information see section controlling the gdin. rst 38 power-on reset input (active low) hpp07 v ddd 39 digital supply voltage; note 1 - v ssd 40 digital ground; note 2 - tst2 41 test pin 2 (low for normal operation) hpp01 tst1 42 test pin 1 (low for normal operation) hpp01 sa 43 stand-alone/microcontroller operated selection; sa = 1 for stand-alone operation hpp01 mu 44 mute ?ag (active high) opf40 ld 45 sa = 0 (microcontroller operated) microcontroller interface; load (read/write); sa = 1 (stand-alone control) nsd control line; note 4 hpp01 da 46 sa = 0 (microcontroller operated) microcontroller interface (data); sa = 1 (stand-alone control) di2 control line; note 4 hof41 cl 47 sa = 0 (microcontroller operated) microcontroller interface (clock); sa = 1 (stand-alone control) qu1/qu0 control line; note 4 hpp01 lock 48 adic lock ?ag (active high) opf40 do1w 49 serial digital audio output 1; word select input/output (f so ) hof41 do1d 50 serial digital audio output 1; data opf43 do1c 51 serial digital audio output 1; bit clock input/output (48f so ) hof41 v ddd 52 digital supply voltage; note 1 - v ssd 53 digital ground; note 2 - fow 54 serial digital audio feature output; word select opf43 fod 55 serial digital audio feature output; data opf43 foc 56 serial digital audio feature output; bit clock (64f so ) opf43 di2d 57 serial digital audio input 2; data hpp01 v ssd 58 digital ground; note 2 - di2w 59 serial digital audio input 2; word select hof21 di2c 60 serial digital audio input 2; bit clock output hof21 v ssd 61 digital ground; note 2 - di1d 62 sa = 0 (microcontroller operated) iec 958 digital audio input d (cmos level); sa = 1 (stand-alone control) mso control line; note 4 hpp01 di1o 63 iec 958 digital audio input o (cmos level) hpp01 v ssd 64 digital ground; note 2 - symbol pin description type
1996 jul 17 7 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 20 21 22 24 25 26 27 28 29 30 31 32 23 64 63 62 60 59 58 57 56 55 54 53 52 61 mlb955 - 2 TDA1373H mu em lock sa di1o di1d clo4 clo3 clo2 clo1 cli xtlo xtli da ld cl cen cus bs ddd v ddd v ddd v ddd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssa4 v ssd v di2c di2w di2d fow foc fod ail air rst tst1 tst2 di1s dda1 v ddd v dda4 v ddd v ssa1 v fsl do2d do2w do2c do1d do1w do1c aol1 aor1 cld fig.2 pin configuration.
1996 jul 17 8 philips semiconductors product speci?cation general digital input (gdin) TDA1373H functional description operating modes s ample r ate c onversion (src) mode the output sample rate is determined by a crystal and can be chosen up to 49 khz. the range of input sample rates for a given output sample rate is given in table 1. a pitch variation (varispeed) of 12% around the nominal input sample rate can be tracked. table 1 input sample rates output sample rate (khz) i 2 s input (khz) 0.3 to 1.7f so iec 958 input (khz) 0.35 to 1.45f so 48 13 to 83 16 to 68 44.1 12 to 76 15 to 62 32 9to55 12to45 data path (see fig.4) the input signal at sample frequency f si comes in via one of the di1 inputs (iec 958) or via the serial input di2x. the signal passes through the fifo/gain part and is interpolated in the up-sampling filters. the actual sample rate conversion takes place in the variable hold block. the down-sampling filters decimate the sample frequency to f so and after in-band noise shaping, the output signal is present at serial output do1. additionally the converted signal is available at the analog bitstream outputs aol, aor and at the serial digital output do2 (4f so ). handbook, full pagewidth 160 60 10 5 mlb956 10 4 10 3 10 2 10 140 120 100 80 thd n (db) f (hz) fig.3 total harmonic distortion plus noise as a function of frequency. measurement done with audio precision. src mode; 48 to 44.1 khz; 20-bit output.
1996 jul 17 9 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth mlc335 adic (iec 958 decoder) fifo & gain 4 x and 16 x up-sampling 32 x and 4 x down- sampling in-band noise shaper bitstream digital filter hold clock shop microcontroller interface general control digital pll cs and uc extraction do1c do1d do1w do2c do2d do2w aol aor foc fod fow tst2 tst1 cli xtli xtlo lock em cus cen bs fsl cld main path. example of additional path. clo4 clo3 clo2 clo1 rst sa mu da ld cl di1s di1o di1d ail air di2c di2d di2w TDA1373H 768f so bitstream dac e.g. tda1547 analog output digital output f so i s 2 digital input f si aes/ebu or i s 2 TDA1373H aos ins do2 dso di2 fos di1 dni variable hold fig.4 standard data path in the src mode.
1996 jul 17 10 philips semiconductors product speci?cation general digital input (gdin) TDA1373H slave-vco and slave-vcxo modes in the slave-vco and slave-vcxo modes, the gdin can pass an exact copy of the incoming samples to the output, e.g. for storage on a digital medium such as cd-r. the output sample rate tracks any input sample rate within the frequency range of the external vc(x)o (f so =f si ). in the slave-vco mode a pitch variation of 12.5% around the nominal sample frequency can be tolerated. data path (see fig.5) the signal at input sample frequency f si comes in via one of the di1 inputs (iec 958). the adic signal passes through the fifo/gain block and can be fed through the in-band noise shaper to the serial output do1. additionally, the signal is present at do2 (4f so ) and at the bitstream outputs aol and aor. exact copies for digital use (e.g. write to a disk) from the input signal can be retrieved at output fo (this signal might be affected by jitter since it has not passed through the fifo/gain block). by means of data path switch dso, this direct output of the adic block can also be fed to output do1. note that in this event the do1 serial format becomes equal to the fo format (see table 3). ad/da mode in this mode, the gdin supports an economic realization of analog-to-digital and digital-to-analog conversion, in accordance with the bitstream principle. this requires a bitstream sigma-delta modulator and a bitstream dac, since the up-sampling and down-sampling filters of the sample rate convertor are reused. adc and dac can be simultaneously performed. data path da conversion (see fig.6) the signal at sample frequency f so comes in via serial input di2x or via one of the di1 inputs (iec 958). the signal passes through the fifo/gain part and is interpolated in the up-sampling filters. a bitstream digital filter converts this signal into a bitstream signal at outputs aol and aor, after which it can be filtered by a bitstream dac like the tda1547. data path ad conversion (see fig.6) the bitstream signal from the sigma-delta modulator enters the gdin at inputs ail and air. the down-sampling filters decimate this signal to f so and after in-band noise shaping (selectable), the output signal is present at serial output do1.
1996 jul 17 11 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth mlc336 adic (iec 958 decoder) fifo & gain 4 x and 16 x up-sampling 32 x and 4 x down- sampling in-band noise shaper bitstream digital filter hold clock shop microcontroller interface general control digital pll cs and uc extraction variable hold do1c do1d do1w do2c do2d do2w aol aor foc fod fow tst2 tst1 cli xtli xtlo lock em cus cen bs fsl cld main path. example of additional path. clo4 clo3 clo2 clo1 rst sa mu da ld cl ail air di2c di2d di2w TDA1373H TDA1373H bitstream dac e.g.tda1547 analog output digital output f si i s 2 digital input f si aes/ebu or i s 2 vco 768f so TDA1373H bitstream dac e.g.tda1547 analog output digital output f si i s 2 digital input f si aes/ebu or i s 2 aos do2 dso dni di2 fos di1s di1o di1d di1 ins fig.5 standard data path in the slave-vco and slave-vcxo modes.
1996 jul 17 12 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth mlc337 adic (iec 958 decoder) fifo & gain 4 x and 16 x up-sampling 32 x and 4 x down- sampling in-band noise shaper bitstream digital filter hold clock shop microcontroller interface general control digital pll cs and uc extraction variable hold do1c do1d do1w do2c do2d do2w aol aor foc fod fow tst2 tst1 cli xtli xtlo lock em cus cen bs fsl cld main path. example of additional path. clo4 clo3 clo2 clo1 rst sa mu da ld cl ail air di2c di2d di2w TDA1373H 768f so bitstream dac e.g. tda1547 analog output digital output f so i s 2 digital input f so aes/ebu or i s 2 TDA1373H ad in da in ad out da out aos do2 dso ins dni di2 fos analog input bitstream adc e.g. saa7360 di1s di1o di1d di1 fig.6 standard data paths in the ad/da mode.
1996 jul 17 13 philips semiconductors product speci?cation general digital input (gdin) TDA1373H description of functional blocks iec 958 audio digital input circuit the TDA1373H has three iec 958 inputs: 1. di1s. 2. di1o. 3. di1d. di1s accepts iec 958 line signals (minimum 200 mv peak-to-peak value and maximum 5 v peak-to-peak value), di1o and di1d accept only cmos level signals. the input sample rate range that can be handled depends on the output sample frequency (f so ) of the device. the maximum useful word length of the incoming samples is 20 bits. the internal adic retrieves the stereo audio samples, the v, u, c and p data bits, the adic word clock and the bit clock from the selected iec 958 input signal. the digital adic locks in less than 1 ms for a 44.1 khz input signal. during this lock-in time the word clock is stopped and the audio bits are muted. the validity flag (va), pre-emphasis flag and pin (em), lock flag (lck) and lock pin (lock) are available to check the status of the adic. this validity flag is an or-ing of the incoming validity (v) bit and the own error detection of the adic. the actions which take place in case of detected errors are listed in table 2. table 2 error concealment in the iec 958 decoder error action data action word clock validity (v-bit) error pass sample no action parity (p-bit) error repeat last correct sample number of data bits 1 32 missing pre-amble(s) extra pre-amble(s) more than 4 pre-ambles missing or extra mute output; restart stop adic word clock s erial digital inputs di2w, di2d and di2c the serial digital input di2 can be used as standard input instead of the di1 iec 958 input or can be used together with the fo-output to switch a dsp ic in the input data path. a third possibility is to use di2 as direct input to the gdin bitstream digital filter. in that case the di2 input signal should be 4 oversampled externally. the serial formats supported are shown in fig.7 and table 3. table 3 serial input and output formats (see note 1) note 1. s = slave; m = master. input output f ws f bck i 2 s japanes e 16-bit japanese 18-bit japanese 20-bit 3-state control bits di2 f si 128f si s s s s no di2, di21 and di22 4f so 192f so m s s s no di2 do1 f so 48f so mm m - yes do1s, do11 and do12 128f so s -- do2 4f so 192f so mm m - no do2, do21 and do22 fo f si 64f so m -- - yes fo and fo1
1996 jul 17 14 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth data bck ws left right lsb msb lsb msb data (d) bck (c) ws (w) right right left left t hws t suws t lb t hb t r t f t bck t sudat t hdat lsb msb data bck ws left right mlb960 msb lsb msb data (d) bck (c) ws (w) right left t hws t suws t lb t hb t r t f t bck t sudat t hdat lsb msb lsb fig.7 timing diagram for the serial input and output formats. a. i 2 s input format. b. japanese input format. a. b.
1996 jul 17 15 philips semiconductors product speci?cation general digital input (gdin) TDA1373H s erial digital outputs do1w, do1d and do1c depending on the operating mode and data path switching, do1 can contain the output of the in-band noise shaper or can be directly connected to the output of the internal adic. the supported serial formats and modes of this interface are given in table 3. in case the gdin goes out-of-lock the output data is muted and if the output is configured as master transmitter, the word clock slips half a word clock period. if this is undesirable, use the serial output as a slave transmitter. s erial digital outputs do2w, do2d and do2c the additional digital audio output do2 operates at 4f so . do2 can contain data of the up-sampling (not in src mode) or down-sampling filters. the formats supported are shown in table 3. s erial feature outputs fow, fod and foc the internal adic output is directly available in i 2 s format at this output. this makes it possible to switch a dsp featuring ic in the data path before src (at f si ). see table 3 for the formats supported. handbook, full pagewidth ail and air data foc, clo4 and do2c clock t cy t f t r mlb961 cld clock aol1, aol2, aor1 and aor2 data t cl t ch t d2 t d3 v 1 v dd 1.0 v t d1 fig.8 timing diagram for the bitstream inputs and outputs. b itstream inputs ail and air the bitstream input receives data at 128f so from a 1-bit sigma-delta modulator. possible bitstream inputs at 64f so are held twice. the timing diagram for the bitstream inputs and outputs is given in fig.8. b itstream outputs aol1 and aor1 the bitstream output generates a 128 (src and slave modes) or 192 (ad/da mode) times oversampled bitstream and can be connected to a bitstream dac (e.g. tda1547) for high-quality dac. it is also possible to get the inverted bitstream signals on the complementary bitstream outputs aol1 (pin do2d) and aor1 (pin do2w) by setting the dlo control bit. by using a simple low-pass filter, this symmetrical bitstream output can be used to make an inexpensive analog monitor output. in that event the serial digital output do2 cannot be used.
1996 jul 17 16 philips semiconductors product speci?cation general digital input (gdin) TDA1373H f irst -i n f irst -o ut (fifo) the incoming samples are buffered in a fifo. the depth of this fifo determines the transients that can be allowed in the input frequency, as they may occur during pitch control. the fifo has a depth of 8 samples, which makes gdin support a tracking speed of up to 4 khz/ms. fifo overflow detection is provided to detect out-of-lock situations. g ain c ontrol at the begin of the data path, the signal level can be controlled over a gain/attenuation range from 2 to 0 with a step size of 2e-7. this gain control can be used for volume control, gain correction and fade-in or fade-out. for normal operation, the gain level should be set to 1-2e-7 ( - 0.068 db) to avoid pass band ripple clipping in the digital filters. whenever a new gain value is set, the gain level is increased or decreased by one step per input sample until the new entered value is reached. setting the mmu control bit forces the gdin to start a soft muting. the gain is decreased, by one step per input sample, to zero. clearing the mmu bit will increase the gain back to its original value. only those outputs, for which the signal passes through the gain control part, are muted. 64 up - sampling filter a 64 (4 and 16 ) oversampling filter is incorporated in the gdin for the src process. this filter can also be used as the up-sampling filter for a bitstream digital-to-analog conversion in the ad/da mode, in combination with the bitstream digital filter and bitstream dac (e.g. tda1547). two filter characteristics can be chosen by the control bit ss (see table 4). the 50 db stop band suppression mode is especially suited for 32 khz input sources like digital satellite radio (dsr), where a very narrow transition band is required to obtain 0 to 15 khz pass band. table 4 filter characteristics 64 up-sampling ?lter ss pass band stop band 0 0 to 0.45351f si 0.004 db 0.54648f si to 1f si - 70 db 1 0 to 0.46875f si 0.004 db 0.53125f si to 1f si - 50 db v ariable hold in src mode, the variable hold is the interface between the 64 up-sampling filters (64f si ) and the 128 down-sampling filters (128f so ). in slave and ad/da modes, the variable hold holds each sample twice from 64f si to 128f si (f si =f so ). 128 down - sampling filter (see fig.10) after src, a 128 (32 +4 ) down-sampling filter decimates the signal to f so . in the ad/da mode, this filter is used as the adc down-sampling filter for a bitstream sigma-delta modulator. the stop band suppression is 80 db from 0.54648f so (e.g. 24.1 khz at f so = 44.1 khz).
1996 jul 17 17 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth 100 0 100 0 20406080 mlb962 80 60 40 20 f (khz) stop band suppression (db) fig.9 filter characteristic 64 up-sampling filter. ss = 0; 70 db stop band suppression. handbook, full pagewidth 100 0 100 0 20406080 mlb963 80 60 40 20 f (khz) stop band suppression (db) fig.10 filter characteristic 128 down-sampling filter.
1996 jul 17 18 philips semiconductors product speci?cation general digital input (gdin) TDA1373H i n - band n oise s haping (ins) the standard 20-bit output word length can be reduced to 16 or 18 bits to match digital consumer equipment. normally 16 bit output re-quantization at audio-band sample rates drops the signal-to-noise ratio (s/n) inevitably to 95 db, because of the re-quantization noise at - 98 db. it is possible however to shape the re-quantization noise in a psycho-acoustical way. this reduces the re-quantization noise at the frequencies where the human ear is most sensitive and stores the bulk of re-quantization noise at high frequencies, where the human ear is quite insensitive. the in-band noise shaping function (to 16 or 18 bits) results in a subjective quality improvement of about 2 bits below the actual quantization level. it is also possible to re-quantize the 20 bit output to 16 bits without noise shaping but by a simple rounding operation. table 5 gives an overview of the 4 possible settings. table 5 selectable output word lengths note 1. ins = in-band noise shaping. b itstream digital filter the bitstream digital filter generates a bitstream signal which should be filtered by a bitstream dac (e.g. tda1547) to become a high-quality analog signal. the input for this block can be selected from the output of the up-sample path or directly from serial input di2. in this case, the input signal applied to di2 should be externally oversampled to 4f so and further oversampling will be carried out by the hold function. the bitstream signal has a frequency of 128f so (src and slave modes) or 192f so (ad/da mode). to prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit nsd. d igital pll the digital pll controls the variable hold function which steers the actual src process. an adaptive loop filter qu1 qu0 word length 0 0 16 bit (rounded) 0 1 20 bit 1 0 16 bit ins (1) 1 1 18 bit ins (1) allows fast locking to the input frequency and a small bandwidth during steady-state. at start-up, the bandwidth of the 3-step digital loop filter is gradually reduced to 0.5 hz. a difference frequency of 1 hz is reached within 512 input samples (10 ms at 44.1 khz), which allows to start the src. at this moment the outputs are de-muted, indicated at pin mu and status flag mut. the fifo position is continuously monitored to control the adaptive loop filter. the loop filter switches back to a fast state when the fifo tends to drift, e.g. during pitch control on the input signal. it is possible to fix the loop filter in one of the three states. in the adaptive mode, the actual state can be monitored by the microcontroller (st1 and st0). in src mode, the microcontroller can retrieve the exact input sample frequency via the status registers sts3 and sts4. table 6 pll operation modes in both slave modes, a pulse modulated signal at pin fsl is present to control the external vc(x)o. in slave-vco mode, cli is the clock input of the gdin and in slave-vcxo mode xtli is the clock input. an external 1000 hz low-pass filter retrieves the control voltage for the vc(x)o. to get the loop characteristics as described above, the centre frequency of the vco should be at 1 2 v dd and the sensitivity should be: hz/v. the maximum vco frequency range is: (768 0.3)f so(c) < 768f si (=f so ) < (768 1.7)f so(c) (49 khz). iec 958 c hannel status and user channel extractor (cup) the internal adic retrieves also the channel status (cs) and user channel (uc) bits from the iec 958 signal. the c/u processing function block can be programmed for 4 different functions (see table 7). lc1 lc0 pll operation pll bandwidth (hz) 0 0 adaptive 500, 50 or 0.5 0 1 state 1 ?xed 500 1 0 state 2 ?xed 50 1 1 state 3 ?xed 0.5 g v 768f so c () 1 2 -- - v dd ------------------------ - =
1996 jul 17 19 philips semiconductors product speci?cation general digital input (gdin) TDA1373H table 7 overview of selectable cup functions note 1. x = dont care. sm1 sm0 lr (1) cup function ram buffer 0 1 0 extract full c-block left (192 bits/block) 80h to 97h 0 1 1 extract full c-block right (192 bits/block) 80h to 97h 1 0 x extract full u-block (384 bits/block) 80h to afh 0 0 x decode cd-subcode q-information (80 bits/cd frame) from u-bits 80h to 89h the extracted or decoded information can be read in three ways: from the internal ram buffer by a microcontroller (see section the ram buffer) at the output pins cus, bs and cen (see fig.11) in status registers sts5 and sts6 (permanent 16 consumer mode c-bits, see table 9). during cd subcode q extraction, a 16-bit crc is done over the q-channel (crc flag). this flag is only meaningful when the adic is locked (lck flag). t he ram buffer a double ram buffer is present in the device. while reading one buffer, the other buffer is filled with the new incoming data. the ram buffer can be read in two ways: 1. interrupt protocol (uip = 0). 2. user request protocol (uip = 1). interrupt protocol (uip = 0) a c-block, a u-block or cd subcode frame is read in the time between two block sync (output pin bs) pulses, which can be used as the interrupt for a microcontroller. at a sample rate of 44.1 khz, the microcontroller must be able to read a c-block or u-block within cd subcode frames are received at a data rate of 75 hz or 13.3 ms/frame. user request protocol (uip = 1) the microcontroller requests for a c, u and cd-q block or frame, which will then become available at the next block preamble, indicated by bs. the information is not updated until the next user request, which means the microcontroller can take any time to read the information. the cd subcode crc check flag always shows the crc over the last received cd subcode q frame and is not stored with the present q frame in the buffer. figure 12 shows the user request read procedure. 192 44100 ---------------- 4.35 ms. =
1996 jul 17 20 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth mlb964 left cs0 or uc0 right cs0 or uc1 left cs191 or uc382 right cs191 or uc 383 t cybs t subc t hbc t succ t hcc t lcen t cycen cus cen bs t cycen t succ(cd) t hcc(cd) t hcen(cd) t cybs(cd) t subc(cd) t hbs(cd) cus cen bs q1 r1 s1 q98 q1 r1 s1 fig.11 timing of the cus, cen and bs output pins. a. channel status (cs) or user channel (uc) extraction. b. cd subcode demodulation. a. b.
1996 jul 17 21 philips semiconductors product speci?cation general digital input (gdin) TDA1373H handbook, full pagewidth mlb965 block sync or cd subcode frame sync (bs) buffer contents valid (bcv) set buffer free (sbf) microcontroller data communication (ld, cl, da) ok, buffer valid set buffer free again buffer completely read start to read buffer request to read (hold buffer) fig.12 c, u and cd-q user request procedure. t he microcontroller interface / stand - alone control block if pin sa is low, a microcontroller controls and monitors the operation of the gdin and reads c, u and cd-q information. a 3-line bidirectional serial interface with data (da), load (ld) and clock (cl) line is present. for both a write and read operation the microcontroller generates the clock and load signals. a single byte is written by setting the ld signal active high during transmission of the serial data. at the rising edge of the serial clock, the gdin clocks in the serial data. at the end of the 8-bit data word a load pulse should be given to enable the internal serial-to-parallel conversion. write operations are always two-byte operations. first, the register address is sent to the gdin, then the corresponding data is send (see fig.13): 1. write address. 2. write data byte. a single byte read-operation is initialized by pulling ld low. when the serial clock is started, the gdin will transmit serial data on the da line. the information is read by the microcontroller at the rising edges of the clock cl. read operations are at least two-byte operations with multi-byte reads possible. the address is sent to the gdin and then one or more bytes are read from the gdin with each additional byte coming from an incrementally higher address: 1. write address. 2. read data byte. 3. read data byte. 4. read data byte. 5. etc. multi-read operations continue to cycle through the given register address range until the read operation is completed. if pin sa is high, the gdin can operate without an external microcontroller. in this event, only the src mode and the ad/da mode can be selected. a number of pins are reconfigured to control some of the internal switches of the device. for more information see chapter pinning and section controlling the gdin.
1996 jul 17 22 philips semiconductors product speci?cation general digital input (gdin) TDA1373H table 8 TDA1373H memory map register address range register name type 00h to 05h cmd1 to cmd6 command; read/write 40h to 45h sts1 to sts6 status; read 80h to 97h ram buffer; c-block read 80h to afh ram buffer; u-block read 80h to 89h ram buffer; cd-q frame read handbook, full pagewidth mlb966 7070 7070 t hdc t sudc t cy t hcl t lcl t hlc t sulc t ld1 t hld t sulc t sudc t hdc cl ld da cl ld da fig.13 timing for the microcontroller read and write operations. a. a complete write operation. b. a complete read operation. a. b.
1996 jul 17 23 philips semiconductors product speci?cation general digital input (gdin) TDA1373H controlling the gdin m icrocontroller operated status registers table 9 status registers notes 1. only valid when the internal adic is in lock (bit 3 of register sts1; lck = 1). register bit flag description explanation sts1 (40h) gdin status information 7 - reserved - 6 - reserved - 5 - reserved - 4 - reserved - 3 lck internal adic lock status 0 = not locked; 1 = locked 2 crc cd-q channel; crc check (1) 0 = ok; 1 = error 1 va validity bit (2) 0 = valid; 1 = not valid 0 bcv ram buffer contents 0 = valid; 1 = not valid sts2 (41h) gdin status information 7 - reserved - 6 - reserved - 5 - reserved - 4 - reserved - 3 - reserved - 2 and 1 st1 and st0 pll operating status (3) 00 = reserved; 01 = state 1; 10 = state 2; 11 = state 3 0 mut mute status (4) 0 = mute off; 1 = mute on sts3 (42h) 7 to 0 lf15 to lf8 lf15 to lf0: input sample rate (5) f si =f so (1 - (0.75 lf15 to lf0)) sts4 (43h) 7 to 0 lf7 to lf0 sts5 (44h) (6) aes/ebu channel status 7 and 6 ca1 and ca0 clock accuracy 00 = level 2; 01 = level 1; 10 = level 3; 11 = reserved 5 and 4 fs1 and fs0 input sample rate 00 = 44.1 khz; 01 = reserved; 10 = 48 khz; 11 = 32 khz 3 em pre-emphasis 0 = off; 1 = on 2 cpy copyright protection 0 = yes; 1 = no 1 an audio or data 0 = audio; 1 = data 0 cpf consumer or professional use 0 = consumer; 1 = professional sts6 (45h) (6) aes/ebu channel status 7 cat7 cat7 to cat0: category code some examples: 00000000 = general 10000000 = cd 1100001l = dcc 1100000l = dat 0100100l = mixer 0101100l = src 1001000l = md 6cat6 5cat5 4cat4 3cat3 2cat2 1cat1 0cat0 (7)
1996 jul 17 24 philips semiconductors product speci?cation general digital input (gdin) TDA1373H 2. va = iec 958 v-bit or adic error detector. 3. only valid when the digital pll works in adaptive mode. 4. after approximately 512 stereo input samples (approximately 10 ms when f si = 44.1 khz). 5. only valid in src mode. lf15 to lf0 are in twos complement notation. 6. only valid when iec 958 input format is consumer (bit 0 of register sts5; cpf = 0). when the input format is professional (cpf = 1) the sts5 and sts6 registers contain the first 16 bits of c-block. 7. generation status (l-bit). command registers table 10 command registers register bit flag description explanation cmd1 (00h) adic control 7 and 6 di12 and di11 adic input selector 00 = di1s; 01 = di1o; 10 = di1d; 11 = reserved 5 uip user interface protocol 0 = interrupt; 1 = user requirement 4 sbf set internal ram buffer free 0 = hold buffer; 1 = set buffer free 3 and 2 sm1 and sm0 channel decoding 00 = cd-q; 01 = c-block; 10 = u-block; 11 = reserved 1 lrs c-block left/right selector 0 = left; 1 = right 0 dba ram buffer mode 0 = normal; 1 = test cmd2 (01h) loop and mode control 7 - reserved - 6 - reserved - 5 and 4 lc1 and lc0 pll control; note 1 00 = adaptive; 01 = state 1 ?xed; 10 = state 2 ?xed; 11 = state 3 ?xed 3 and 2 ms1 and ms0 mode selector; notes 1 and 2 00 = src mode; 01 = ad/da mode; 10 = slave-vcxo mode; 11 = slave-vco mode 1 rtr enable 3-state outputs; note 3 0 = 3-state; 1 = enabled 0 mrs reset (hardware reset); note 4 0 = no reset; 1 = reset cmd3 (02h) data path (5) 7 dso do1 output selector 0 = ins; 1 = adic 6 - reserved - 5 fos fo output selector 0 = adic; 1 = 128 ?lter 4 di2 fifo input selector 0 = fow, fod and foc; 1 = di2w, di2d and di2c 3 dni input selector 128 ?lter 0 = variable hold; 1 = ail/air 2 ins in-band noise shaper input selector 0 = output 128 down; 1 = output fifo/gain 1 aos bitstream digital ?lter input selector 0 = variable hold; 1 = di2w, di2d and di2c 0 do2 do2 output selector 0 = 128 down; 1 = 64 up
1996 jul 17 25 philips semiconductors product speci?cation general digital input (gdin) TDA1373H notes 1. in the slave-vcxo mode, the pll should be fixed in state 2 until locked. 2. a mode change will always invoke a restart of the gdin. 3. at power-on the do1 and fo outputs are 3-state to avoid i 2 s bus conflicts. this bit overrides the serial i/o control bits. 4. a mrs or hardware reset clears all command registers, also the mrs flag itself. 5. see section data path switching for possible settings of the data path switches in the different modes. 6. set all reserved flags to 0. 7. setting mmu starts a soft-mute from current gain value to 0 by 1 128 per input sample. clearing mmu starts the inverse process from 0 to current gain value. 8. to prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit nsd. 9. set this bit for 32 khz input sources. 10. use 01111111 for normal operation to avoid pass band ripple clipping. cmd4 (03h) control 7 - reserved - 6 - reserved - 5 mmu soft mute function; note 7 0 = off; 1 = on 4 and 3 qu1 and qu0 in-band noise shaper 00 = 16-bit; 01 = 20-bit; 10 = 16-bit ins; 11 = 18-bit ins 2 nsd dither bitstream digital ?lter; note 8 0 = off; 1 = on 1 dlo symmetrical bitstream output 0 = off; 1 = on 0 ssp stop band suppression 64 ?lter; note 9 0 = 70 db; 1 = 50 db cmd5 (04h) input/output formats 7 and 6 di22 and di21 serial format di2 input 00 = i 2 s; 01 = japanese 16-bit; 10 = japanese 18-bit; 11 = japanese 20-bit 5 and 4 do22 and do21 serial format do2 output 00 = i 2 s; 01 = japanese 16-bit; 10 = japanese 18-bit; 11 = reserved 3 and 2 do12 and do11 serial format do1 output 00 = i 2 s; 01 = japanese 16-bit; 10 = japanese 18-bit; 11 = 3-stated 1 do1m do1 master/slave selector 0 = master; 1 = slave 0 fot fo output 3-state selector 0 = i 2 s; 1 = 3-stated cmd6 (05h) 7 gain7 gain7 to gain0: gain of the gcm block (10) ; maximum = 2; step = 1 128 some examples: 11111111 = 2 (maximum) 10000000 = 1 01111111 = 0.992 00000001 = 0.0078 6 gain6 5 gain5 4 gain4 3 gain3 2 gain2 1 gain1 0 gain0 register bit flag description explanation
1996 jul 17 26 philips semiconductors product speci?cation general digital input (gdin) TDA1373H data path switching all data path switches are freely controllable, although not all combinations make sense in the different operating modes. table 11 shows the preferred settings of the cmd3 control register. table 11 preferred settings of the cmd3 control register notes 1. level 0 or 1 indicates to set the flag in this position. a = application dependent. 2. when the output of the internal adic is fed directly to do1 or fo, the serial output format is i 2 s, the word select jitters (by one 384f so clock cycle) and the number of bit clocks per word select is not fixed. s tand - alone control when pin sa is high, the gdin operates under stand-alone control. some basic settings can be controlled in this event by changing the level at the control pins. table 12 shows which command bits are pin-controllable during stand-alone operation. the command bits which are not pin-controllable are automatically set to their appropriate value in accordance with the selected mode (src or ad/da). all control bits not shown get the value 0 in the event of stand-alone control. table 12 command registers notes 1. when the device operates in stand-alone control, only the src mode and ad/da mode are available. 2. this means that all 3-state outputs are permanently enabled during stand-alone operation. register bit flag data path switch src (1) slave (1) ad/da (1) cmd3 (02h) data path 7 dso do1 output selector; note 2 0 a a 6 - reserved --- 5 fos fo output selector; note 2 a a a 4 di2 fifo input selector a a a 3 dni input selector 128 ?lter 0 1 1 2 - reserved --- 1 aos aol and aor output selector a a a 0 do2 do2 output selector 0 a a register flag pin description explanation cmd1 (00h) adic control di11 fsl adic input selector 0 = di1s; 1 = di1o cmd2 (01h) loop and mode control ms0 di1d mode selector; note 1 0 = src mode; 1 = ad/da mode rtr - enable 3-state outputs; note 2 rtr is always 1 in stand-alone mode cmd3 (02h) data path di2 da fifo input selector 0 = fow, fod and foc; 1 = di2w, di2d and di2c dni - input selector 128 ?lter src mode = 0: variable hold; ad/da mode = 1: ail/air cmd4 (03h) control qu0/qu1 cl in-band noise shaper 0 = 20 bit; 1 = 16 bit ins nsd ld dither bitstream digital 0 = off; 1 = on cmd6 (05h) gain - gain of the fifo/gain block gain = 01111111 = 0.992
1996 jul 17 27 philips semiconductors product speci?cation general digital input (gdin) TDA1373H limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model (hbm): c = 100 pf; r = 1.5 k w ; 3 zaps positive and 3 zaps negative. 2. machine model (mm): c = 200 pf; l = 2.5 m h; r = 25 w ; 3 zaps positive and 3 zaps negative. thermal characteristics symbol parameter conditions min. typ. max. unit v dd supply voltage - 0.5 - +6.5 v i dd supply current -- 200 ma v i input voltage - 0.5 - v dd + 0.5 v i i(max) maximum input current -- 10 ma i o(max) maximum output current -- 10 ma p tot total power dissipation - 1030 - mw t stg storage temperature - 65 - +150 c t amb operating ambient temperature 0 - +70 c v es electrostatic handling hbm; note 1 - 3000 - +3000 v mm; note 2 - 300 - +300 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 46 k/w
1996 jul 17 28 philips semiconductors product speci?cation general digital input (gdin) TDA1373H characteristics v dd =5v 10%; t amb = 0 to +70 c; c l = 50 pf; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd supply voltage - 0.5 - 6.5 v i ddd digital supply current - 148 180 ma i dda1 analog supply current iec 958 data slicer - 0.65 1 ma i dda4 analog supply current clock oscillator - 46ma p tot total power dissipation f so = 44.1 khz - 775 - mw i q(tot) total quiescent supply current t amb =25 c; note 2 -- 10 m a dc characteristics i nput pins type hpp01 (ail, air, cli, tst2, tst1, sa, ld, cl, di2d, di1d and di1o) v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v ? i il ? input leakage current -- 1.0 m a i nput pin type hpp07 (s chmitt - trigger ; rst) v il low level input voltage -- 0.2v dd v v ih high level input voltage 0.8v dd -- v v hys hysteresis voltage - 0.33v dd - v ? i il ? input leakage current -- 1.0 m a i nput pin di1s (iec 958 input ) v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v i i input current -- 1.9 ma o utput pins type opf40 (do2c, aol1, do2d, aor1, do2w, clo1, clo2, clo3, clo4, bs, cen, cus, mu and lock; 4 ma outputs ) v ol low level output voltage -- 0.5 v v oh high level output voltage v dd - 0.5 -- v o utput pin type opf20 (em; 2 ma output ) v ol low level output voltage -- 0.5 v v oh high level output voltage v dd - 0.5 -- v o utput pins type opf43 (cld, do1d, fow, fod and foc; 4 ma 3- state outputs ) v ol low level output voltage -- 0.5 v v oh high level output voltage v dd - 0.5 -- v i oz 3-state leakage current -- 5.0 m a
1996 jul 17 29 philips semiconductors product speci?cation general digital input (gdin) TDA1373H i nput / output pins type hof21 (fsl, di2w and di2c; 2 ma outputs ) v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v ? i oz ? 3-state leakage current -- 5.0 m a v ol low level output voltage -- 0.5 v v oh high level output voltage v dd - 0.5 -- v i nput / output pins type hof41 (da, do1w and do1c; 4 ma outputs ) v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v ? i oz ? 3-state leakage current -- 5.0 m a v ol low level output voltage -- 0.5 v v oh high level output voltage v dd - 0.5 -- v characteristics per block and pin; note 1 i nput pins type hpp01 and hpp07 c i input capacitance - 10 - pf t r rise time (unless otherwise speci?ed) -- t cy ns t f fall time (unless otherwise speci?ed) -- t cy ns o utput pins type opf40 and opf43 t r rise time (unless otherwise speci?ed) - 510ns t f fall time (unless otherwise speci?ed) - 510ns c rystal oscillator g m mutual conductance 0.007821 - 0.03913 ma/v z o output impedance 405 - 3200 w ? i il ? input leakage current -- 1.0 m a c i input capacitance - 3.1 - pf c o output capacitance -- 18 pf v il low level input voltage -- 0.3v dd v v ih high level input voltage 0.7v dd -- v iec 958 interface ( for timing see s ection 13 of reference 1 in c hapter references) v i(p-p) ac input voltage (peak-to-peak value) 0.2 - v dd v c i input capacitance - 25 - pf symbol parameter conditions min. typ. max. unit
1996 jul 17 30 philips semiconductors product speci?cation general digital input (gdin) TDA1373H s erial input interfaces (see fig.7) t r rise time (unless otherwise speci?ed) -- 25 ns t f fall time (unless otherwise speci?ed) -- 25 ns t sudat set-up time data (d) to clock (c) t cy -- ns t hdat hold time data (d) to clock (c) 0 -- ns t suws set-up time word select (w) to clock (c) t cy -- ns t hws hold time word select (w) to clock (c) 0 -- ns t bck clock period time see table 3 - 1/f bck - ns t hb bit clock high time t cy -- ns t lb bit clock low time t cy -- ns s erial output interfaces t r rise time (unless otherwise speci?ed) -- 10 ns t f fall time (unless otherwise speci?ed) -- 10 ns t sudat set-up time data (d) to clock (c) 0.5t bck -- ns t hdat hold time data (d) to clock (c) t cy -- ns t suws set-up time word select (w) to clock (c) 0.5t bck -- ns t hws hold time word select (w) to clock (c) t cy -- ns t bck clock period time see table 3 - 1/f bck - ns t hb bit clock high time 0.4t bck -- ns t lb bit clock low time 0.4t bck -- ns b itstream inputs ail and air (see fig.8) t d1 delay time after high-to-low clock transition -- 100 ns b itstream outputs aol1, aor1 and cld (see fig.8) t r data output rise time - 10 15 ns t f data output fall time - 10 15 ns t su data output set-up time 0 -- ns t h data output hold time 25 -- ns t r clock output rise time - 510ns t f clock output fall time - 510ns t ch clock output high time 40 -- ns t cl clock output low time 40 -- ns symbol parameter conditions min. typ. max. unit
1996 jul 17 31 philips semiconductors product speci?cation general digital input (gdin) TDA1373H m icrocontroller interface (see fig.13) t cycl cl cycle time 6t cy -- ns t hcl cl high time 3t cy -- ns t lcl cl low time 3t cy -- ns t sulc set-up time ld to cl write operation 9t cy -- ns t hlc hold time ld to cl write operation 3t cy -- ns t ld1 write pulse period ld 3t cy -- ns t cyld ld cycle time read operation 3t cy -- ns t hlc hold time ld to cl read operation 3t cy -- ns t ld2 read enable ld pulse period 6t cy -- ns t sudc set-up time da to cl write operation t cy -- ns t hdc hold time da to cl write operation 3t cy -- ns t sudc set-up time da to cl read operation t cy -- ns t hdc hold time da to cl read operation 3t cy -- ns o utput pins cus, cen and bs (see fig.11) channel status or channel mode t cybs bs cycle time -- ms t cen cen enable time - 1 2 f si -m s t lcen cen low time 1.5 --m s t subc set-up time bs to cen 1.5 --m s t hbc hold time bs to cen 8 --m s t succ set-up time cus to cen 1.5 --m s t hcc hold time cus to cen 8 --m s cd-q subcode demodulation mode t cybs(cd) frame sync bs cycle time - 13.3 - ms t hbs(cd) frame sync bs high time - 408 -m s t cen cen enable time - 136 -m s t hcen(cd) cen enable high time - 1 2 f si - ms t subscen set-up time bs to cen 8 --m s t succ(cd) set-up time cus to cen 1.5 --m s t hcc(cd) hold time cus to cen 8 --m s symbol parameter conditions min. typ. max. unit 192 1 f si -----
1996 jul 17 32 philips semiconductors product speci?cation general digital input (gdin) TDA1373H notes 1. most timing specifications are referenced to the system clock t cy = 1 384 f so . 2. the (i dd ) quiescent current is checked on as much active gate area as possible, therefore outputs are chosen reference. each output is i dd tested in high and low state. the minimum number of test vectors on which i dd quiescent current is tested is 2 and the maximum is n + 1 (n = number of outputs). these test vectors also define fixed conditions in the core. i dd quiescent current test is not allowed on test vectors which may result in additional quiescent current caused by pull-up/down resistors, i/os, internal bus-structures, etc. in total this i dd quiescent current test contributes highly to the (functional) fault coverage. quality specification general quality in accordance with snw-fq-611 part e and can be found in the quality reference handbook (order number 9398 510 63011). references 1. digital audio interface , first edition 1989-03 international standard iec 958 . 2. i 2 s bus specification , release 2-86, philips export b.v. (order number 9398 332 10011). r eset t pwres reset pulse width 10t cy -- ns t ires internal reset time after reset pulse -- 40t cy ns symbol parameter conditions min. typ. max. unit
1996 jul 17 33 philips semiconductors product speci?cation general digital input (gdin) TDA1373H test diagram handbook, full pagewidth mlb967 - 1 v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd v ssd 64 61 58 29 26 53 40 33 8 v ddd 52 v ddd 39 v ddd 32 v ddd 7 c10 100 nf c11 100 nf c12 6 v c13 6 v v cc v cc l4 l3 v cc l2 v cc l1 c9 100 nf c8 100 nf c14 6 v c15 6 v clo 18 aor1 15 aol1 9 do1c 51 do1w 49 do1d 50 do2c 6 do2w 16 do2d 10 fsl 25 17 24 20 19 v dda4 v ssa4 v ssd v ssd c5 100 nf 6 v c6 r9 v cc clo4 31 clo3 30 clo2 28 clo1 27 cli 23 xtlo 22 xtli 21 da 46 ld 45 cl 47 lock 48 cen 35 cus 36 bs 34 rst 38 r2 c16 22 pf c17 22 pf l5 c1 1 nf y1 768f s 4 3 2 1 jp1 r3 10 k w 100 k w 4.7 w 75 w 4.7 w 4.7 w 4.7 w 47 m f 47 m f 47 m f 47 m f 47 m f 47 m f 47 m f 47 m f 2.2 m h v cc c7 10 m f c2 100 nf di2c 60 di2w 59 di2d 57 foc 56 fow 54 fod 55 mu 44 em 37 sa 43 di1o 63 di1d 62 di1s 1 3 2 11 14 12 13 ail 4 air 5 tst1 42 tst2 41 v ssd v ssd v ddd v ddd v ssa1 v dda1 TDA1373H c19 100 nf c20 100 nf c22 c23 6 v 6 v r6 v cc r5 v cc r4 v cc c18 100 nf c21 6 v r1 c3 100 nf c4 100 pf j1 rca 10 k w 10 k w 1 3 5 7 9 11 13 15 17 19 21 23 27 29 31 33 35 37 39 25 do1d do1w do1c di2d di2w di2c ail air aol1 aol2 aor1 aor2 cld xtin sda in 2 4 6 8 10 12 14 16 18 20 22 24 28 30 32 34 36 38 40 26 jp2 ground supply voltage do2d do2w r7 r8 fig.14 test diagram for the TDA1373H.
1996 jul 17 34 philips semiconductors product speci?cation general digital input (gdin) TDA1373H package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.36 0.10 2.87 2.57 0.25 0.50 0.35 0.25 0.13 14.1 13.9 1 18.2 17.6 1.43 1.23 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-1 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d b p e q e a 1 a l p q detail x l (a ) 3 b 19 y c d h b p e h a 2 v m b d z d a z e e v m a w m 1 64 52 51 33 32 20 x w m 0 5 10 mm scale pin 1 index 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height qfp64: plastic quad flat package; sot319-1 a max. 3.3
1996 jul 17 35 philips semiconductors product speci?cation general digital input (gdin) TDA1373H soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jul 17 36 philips semiconductors product speci?cation general digital input (gdin) TDA1373H definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 jul 17 37 philips semiconductors product speci?cation general digital input (gdin) TDA1373H notes
1996 jul 17 38 philips semiconductors product speci?cation general digital input (gdin) TDA1373H notes
1996 jul 17 39 philips semiconductors product speci?cation general digital input (gdin) TDA1373H notes
internet: http://www.semiconductors.philips.com/ps/ (1) TDA1373H_3 june 26, 1996 11:51 am philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca50 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 83749, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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