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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8345 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 250 mhz?000 mhz quadrature modulator functional block diagram 16 qbbp qbbn 15 com3 14 com3 13 vps2 12 vout 11 com2 10 com3 9 1 ibbp 2 ibbn 3 com3 4 com1 5 loin 6 loip 7 vps1 8 enbl bias + phase splitter ad8345 features 250 mhzC1000 mhz operating frequency +2.5 dbm p1 db @ 800 mhz C155 dbm/hz noise floor 0.5 degree rms phase error (is95) 0.2 db amplitude balance single 2.7 vC5.5 v supply pin-compatible with ad8346 16-lead exposed paddle tssop package applications cellular communication systems w-cdma/cdma/gsm/pcs/ism transceivers fixed broadband access systems lmds/mmds wireless lan wireless local loop digital tv/catv modulators single sideband upconverter product description the ad8345 is a silicon rfic quadrature modulator, designed for use from 250 mhz to 1000 mhz. its excellent phase accu- racy and amplitude balance enable the high performance direct modulation of an if carrier. the ad8345 accurately splits the external lo signal into two quadrature components through the polyphase phase-splitter network. the two i and q lo components are mixed with the baseband i and q differential input signals. finally, the outputs of the two mixers are combined in the output stage to provide a single-ended 50 ? drive at vout. applications the ad8345 modulator can be used as the if transmit modu- lator in digital communication systems such as gsm and pcs transceivers. it can also directly modulate an lo signal to produce qpsk and various qam formats for 900 mhz com- munication systems as well as digital tv and catv systems. additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution. the ad8345 modulator is supplied in a 16-lead tssop pack- age with exposed paddle. its performance is specified over a ?0 c to +85 c temperature range. this device is fabricated on analog devices?advanced silicon bipolar process.
rev. 0 C2C ad8345?pecifications (v s = 5 v; lo= ? dbm @ 800 mhz, 50 source and load impedances, i and q inputs 0.7 v 0.3 v on each side for a 1.2 v p-p differential input, i and q inputs driven in quadrature @ 1 mhz baseband frequency. t a = 25 c, unless otherwise noted.) parameters conditions min typ max unit rf output operating frequency 1 250 1000 mhz output power 3 1 +2 dbm output p1 db 2.5 dbm noise floor 20 mhz offset from lo, all bb ?55 dbm/hz inputs at 0.7 v quadrature error (cdma is95 setup, refer to figure 13) 0.5 degree rms i/q amplitude balance (cdma is95 setup, refer to figure 13) 0.2 db lo leakage ?2 ?3 dbm sideband rejection ?2 ?4 dbc third order distortion ?2 dbc second order distortion ?0 dbc equivalent output ip3 25 dbm equivalent output ip2 59 dbm output return loss (s22) ?0 db response to cdma is95 (refer to figure 13) baseband signals acpr ?2 dbc evm 1.3 % rho 0.9995 lo input lo drive level ?0 2 0 dbm loip input return loss (s11) 2 no termination on loip, loin at ? db ac ground 50 ? terminating resistor, differential ? db drive via balun baseband inputs input bias current 10 a input capacitance 2pf dc common level 0.6 0.7 0.8 v bandwidth (3 db) full power (0.7 v 0.3 v on each 80 mhz input, refer to tpc 2) enable turn-on enable high to output within 0.5 db of 2.5 s final value turn-off enable low to supply current dropping 1.5 s below 2 ma enbl high threshold (logic 1) +v s /2 v enbl low threshold (logic 0) +v s /2 v power supplies voltage 2.7 5.5 v current active 50 65 78 ma current standby 70 a notes 1 for information on operation below 250 mhz, see figure 4. 2 see lo drive section for more details on input matching. specifications subject to change without notice. rev. 0 ad8345 C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8345 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * supply voltage vps1, vps2 . . . . . . . . . . . . . . . . . . . . . 5.5 v input power loip, loin (re 50 ? ) . . . . . . . . . . . . . 10 dbm ibbp, ibbn, qbbp, qbbn . . . . . . . . . . . . . . . . . 0 v, 2.5 v internal power dissipation . . . . . . . . . . . . . . . . . . . . 500 mw ja (exposed paddle soldered down) . . . . . . . . . . . . 30 c/w ja (exposed paddle not soldered down) . . . . . . . . . 95 c/w maximum junction temperature . . . . . . . . . . . . . . . . 150 c operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration 16 15 14 13 12 11 10 9 qbbp qbbn com3 com3 vps2 vout com2 com3 1 2 3 4 5 6 7 8 ibbp ibbn com3 com1 loin loip vps1 enbl ad8345 top view (not to scale) ordering guide model temperature range package description package option ad8345are ?0 c to +85 c tube (16-lead tssop with exposed pad) re-16 ad8345are-reel 13" tape and reel ad8345are-reel7 7" tape and reel ad8345-eval evaluation board rev. 0 ad8345 C4C pin function descriptions equivalent pin no. mnemonic function circuit 1, 2 ibbp, ibbn i channel baseband differential input pins. these high impedance inputs should circuit a be dc biased to approximately 0.7 v. nominal characterized ac swing is 0.6 v p-p on each pin (0.4 v to 1 v). this gives a differential drive of 1.2 v p-p. inputs are not self-biasing so external biasing circuitry must be used in ac-coupled applications. 3, 9, 13, 14 com3 ground pin for input v-to-i converters and mixer core. 4 com1 ground pin for the lo phase-splitter and lo buffers. 5, 6 loin, loip differential lo drive pins. internal dc bias (approximately 1.8 v @ v s = 5 v) circuit b is supplied. pins must be ac-coupled. single-ended or differe ntial drive is permissible. 7 vps1 power supply pin for the bias cell and lo buffers. this pin should be decoupled using local 1000 pf and 0.01 f capacitors. 8 enbl enable pin. a high level enables the device; a low level puts the device in sleep mode. circuit c 10 com2 ground pin for the output stage of output amplifier. 11 vout 50 ? dc-coupled rf output. pin should be ac-coupled. circuit d 12 vps2 power supply pin for baseband input voltage to current converters and mixer core. this pin should be decoupled using local 1000 pf and 0.01 f capacitors. 15, 16 qbbn, qbbp q channel baseband differential input pins. inputs should be dc biased to circuit a approximately 0.7 v. nominal characterized ac swing is 0.6 v p-p on each pin (0.4 v to 1 v). this gives a differential drive level of 1.2 v p-p. inputs are not self-biasing so external biasing circuitry must be used in ac-coupled applications. equivalent circuits input current mirror to mixer core buffer vps2 circuit a phase splitter continues loin vps1 loip circuit b enbl 100k vps2 100k 100k to bias for startup/ shutdown circuit c 40 40 vps2 vout circuit d figure 1. equivalent circuits rev. 0 ad8345 C5C typical performance characteristics lo frequency ?mhz 0 250 ssb power ?dbm ? ? ? ? ?0 ?2 ?4 ?6 ?8 ?0 300 350 400 450 500 550 600 650 700 750 800 850 900 9501000 v s = 2.7v, differential input = 200mv p-p v s = 5v, differential input = 1.2v p-p tpc 1. single sideband (ssb) output power (p out ) vs. lo frequency (f lo ). (i and q inputs driven in quadrature at baseband frequency (f bb ) = 1 mhz; t a = 25 c) baseband frequency mhz 0.1 output power variation db 5.5 1 10 100 v s = 2.7v, 5v differential input = 200mv p-p v s = 5v, differential input = 1.2v p-p 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 tpc 2. i and q input bandwidth. (t a = 25 c, f lo = 800 mhz, lo level = C2 dbm, i and q inputs driven in quadrature) temperature c 40 ssb power dbm 26 040 80 v s = 5v, differential input = 1.2v p-p v s = 2.7v, differential input = 200mv p-p 24 22 20 18 16 14 12 10 8 6 4 2 0 20 20 60 tpc 3. ssb p out vs. temperature. (f lo = 800 mhz, lo level = C2 dbm, f bb = 1 mhz, i and q inputs driven in quadrature) lo frequency mhz 250 ssb output p1db dbm 500 800 t a = +85 c 16 14 12 10 8 6 4 2 0 350 650 950 300 400 450 550 600 700 750 850 900 1000 t a = 40 c t a = +25 c tpc 4. ssb output 1 db compression point (op 1 db) vs. f lo . (v s = 2.7 v, lo level = C2 dbm, i and q inputs driven in quadrature, f bb = 1 mhz) lo frequency mhz 250 ssb output p1db dbm 500 800 t a = +85 c 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 350 650 950 300 400 450 550 600 700 750 850 900 1000 t a = 40 c t a = +25 c 4.0 tpc 5. ssb output 1 db compression point (op 1 db) vs. f lo . (v s = 5 v, lo level = C2 dbm, i and q inputs driven in quadrature, f bb = 1 mhz) lo frequency mhz 250 carrier feedthrough dbm 500 800 v s = 5v, differential input = 1.2v p-p 50 350 650 950 300 400 450 550 600 700 750 850 900 1000 49 48 47 46 45 44 43 42 41 40 v s = 2.7v, differential input = 200mv p-p tpc 6. carrier feedthrough vs. f lo . (lo level = C2 dbm, t a = 25 c) rev. 0 ad8345 C6C temperature c 40 carrier feedthrough dbm 0 50 20 20 40 60 80 48 46 44 42 40 38 36 34 32 30 v s = 5v, differential input = 1.2v p-p v s = 2.7v, differential input = 200mv p-p tpc 7. carrier feedthrough vs. temperature. (f lo = 800 mhz, lo level = C2 dbm) carrier feedthrough dbm after nulling to 65dbm at +25 c 86 percentage 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 82 78 74 70 66 62 58 54 50 t = +85 t = 40 tpc 8. carrier feedthrough distribution at temperature extremes. after feedthrough nulled to rev. 0 ad8345 C8C circuit description overview the ad8345 can be divided into the following sections: local oscillator (lo) interface, mixer, differential voltage-to-cur- rent (v-to-i) converter, differential-to-single-ended (d-to-s) converter, and bias. a block diagram of the part is shown in figure 2. out loip loin ibbp ibbn qbbp qbbn phase splitter figure 2. ad8345 block diagram the lo interface generates two lo signals at 90 degrees of phase difference with each other, to drive two mixers in quadra- ture. baseband signals are converted into current form in the differential v-to-i converters, feeding into the two mixers. the outputs of the mixers are combined to feed the differential-to- single-ended converter, which provides a 50 ? output interface. bias currents to each section are controlled by the enable (enbl) signal. detailed description of each section follows. lo interface the lo interface consi sts of interleaved stages of p olyphase phase-splitters and buffer amplifiers. the polyphase phase-splitter contains resistors and capacitors connected in a circular manner to split the lo signal into i and q paths in precise quadra- ture with each other. the signal on each path goes through a buffer amplifier to make up for the loss and high frequency roll-off. the two signals then go through another polyphase network to enhance the quadrature accuracy. the broad oper- ating frequency range (250 mhz to 1000 mhz) is achieved by stagg ering the rc time constants of each stage of the phase- splitters. the outputs of the second phase-splitter are fed into the driver amplifiers for the mixers?lo inputs. differential v-to-i converter in this circuit, each baseband input pin is connected to an op amp driving a transistor connected as an emitter follower. a resistor between the two emitters maintains a varying current propor- tional to the differential input voltage through the transistor. t hese currents are fed to the two mixers in differential form. mixers there are two do uble-balanced mixers, one for the in-phase channel (i-channel) and one for the quadrature channel (q- channe l). each mixer uses the gilbert-cell design with four cross-connected transistors. the bases of the transistors are driven by the lo signal of the corresponding channel. the output currents from the two mixers are summed together in two load resistors. the signal developed across the load resistors is sent to the d-to-s stage. differential to single-ended converter the differential-to-single-ended converter consists of two emit- ter followers driving a totem-pole output stage whose output impedance is established by the emitter resistors in the output transistors. the output of this stage is connected to the output (vout) pin. bias a bandgap reference circuit based on the ? -vbe principle gen- erates the proportional-to-absolute-temperature (ptat) as well as temperature-stable currents used by the different sec- tions as references. when the bandgap reference is disabled by pulling down the voltage at the enbl pin, all other sections are shut off accordingly. lo level dbm noise floor dbm/hz 150 10 152 160 151 153 154 155 v s = 5v 156 157 158 159 9 8 7 6 5 4 3 2 1012 tpc 19. noise floor vs. lo input power. (t a = 25 c, f lo = 800 mhz, v s = 5 v, all i and q inputs are dc-biased to 0.7 v) noise measured at 20 mhz offset from carrier lo level dbm carrier feedthrough dbm 36 10 v s = 5.5v 40 50 38 42 44 46 48 9 8 7 6 5 4 3 2 1012 tpc 20. lo feedthrough vs. lo input power. (t a = 25 c, lo = 800 mhz, v s = 5.5 v) rev. 0 ad8345 C9C 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ad8345 qbbp qbbn com3 com3 vps2 vout com2 com3 ibbp ibbn com3 com1 loin loip vps1 enbl ip 1 t1 etc1-1-13 2 3 4 5 lo r1 50 c6 1000pf c7 1000pf in c3 1000pf c4 0.01 f +v s qp qn c1 1000pf c2 0.01 f +v s vout c5 1000pf figure 3. basic connections lo frequency mhz 40 sideband suppression dbc 60 60 80 100 120 140 160 180 200 220 240 260 280 300 55 50 45 40 35 30 25 20 15 10 5 v s = 5v, differential input = 1.2v figure 4. typical lower frequency sideband suppression performance baseband i and q channel drive the i and q channel baseband inputs should be driven differen- tially. this is convenient as most modern high-speed dacs have differential outputs. for optimal performance at v s = 5 v, the drive signal should be a 1.2 v p-p differential signal with a bias level of 0.7 v; that is, each input should swing from 0.4 v to 1 v. if the ad8345 is being run on a lower supply voltage, the peak-to-peak voltage on the i and q channel inputs must be reduced to avoid input clipping. for example, at a supply volt- age of 2.7 v, a 200 mv p-p differential drive is recommended. this will result in a corresponding reduction in output power (see tpc 1). the i and q inputs have a large input bandwidth of approximately 80 mhz. at lower baseband input levels, the input bandwidth increases (see tpc 2). if the baseband signal has a high peak-to-average ra tio (e.g., cdma or wcdma), the rms signal strength will have to be backed off from this peak level in order to prevent clipping of the signal peaks. clipping of signal peaks will tend to increase signal leakage into adjacent channels. backing off the i and q signal strength in the manner recommended will reduce the output power by a corresponding amount. this also applies to multicarrier applications where the per-carrier output power will be lower by 3 db for each doubling of the number of output carriers. basic connections the basic connections for operating the ad8345 are shown in figure 3. a single power supply of between 2.7 v and 5.5 v is applied to pins vps1 and vps2. a pair of esd protection diodes are connected internally between vps1 and vps2 so these must be tied to the same potential. both pins should be individually decoupled u sing 1000 pf and 0.01 f capa citors, located as close as possible to the device. for normal operation, the enable pin, enbl, must be pulled high. the turn-on threshold for enbl is v s /2. pins com1 to com3 should all be tied to the same low impedance ground plane. lo drive in figure 3, a 50 ? resistor to ground combines with the device s high input impedance to provide an overall input impedance of approximately 50 ? (see tpc 17 for a plot of lo port input impedance). for maximum lo suppression at the output, a differential lo drive is recommended. in figure 3, this is achieved using a balun (m/a-com part number etc1-1-13). the output of the balun is ac coupled to the lo inputs which have a bias level about 1.8 v dc. an lo drive level of ? dbm is recommended for lowest output noise. higher levels will degrade linearity while lower levels will tend to increase the noise floor slightly. for example, reducing the lo power from ? dbm to ?0 dbm will increase the noise floor by approximately 0.3 db (see tpc 19). the lo terminal can be driven single-ended at the expense of slightly higher lo leakage. loin is ac coupled to ground using a capacitor and loip is driven through a coupling capacitor from a (sing le-ended) 50 ? source (this scheme could also be reversed with the drive signal being applied to loin). lo frequency range the frequency range on the lo input is limited by the internal quad rature phase splitter. the phase splitter generates drive signals for the internal mixers which are 90 out of phase relative to one another. outside of the specified lo frequency range of 250 mhz to 1 ghz, this quadrature accuracy degrades, result- ing in decreased sideband suppression. see tpc 9 for a plot of sideband suppression vs. lo frequency from 250 mhz to 1 ghz. figure 4 shows the sideband suppression of a typical device from 50 mhz to 300 mhz. the level of sideband suppression degradation below 250 mhz will be subject to manufacturing process variations. rev. 0 ad8345 C10C the i and q inputs have high input impedances because they connect directly to the bases of pnp transistors. if a (dc-coupled) filter is being used between a dac and the modulator inputs, this filter will need to be terminated with the appropriate resis- tance. if the filter is differential, the termination resistor should be connected across the i and q differential inputs. reduction of lo leakage because the i and q signals are being effectively multiplied with the lo, any internal offset voltages on these inputs will result in leakage of the lo. the nominal lo leakage of ?2 dbm which results from these internal offset voltages, can be red uced further by appl ying offset compensation voltages on the i and q inputs. (note that lo feedthrough is reduced by varying the differential offset voltages on the i and q inputs, not by varying the nominal bias level of 0.7 v.) this is easily accomplished by programming (and then storing) the appropriate dac offset code to reduce the lo leakage. this does, however, require the path from the dac to the i and q inputs to be dc-coupled. (dc-coupling is also advantageous from the perspective of i and q input bias- ing if the dac is capable of delivering a bias level of 0.7 v). the procedure for reducing the lo feedthrough is simple. in order to isolate the lo in the output spectrum, a single side- band configuration is recommended (set i and q signals to sine and cosine waves at, say, 100 khz, set lo to f rf ?100 khz). an offset voltage is applied from the i dac until the lo leakage reaches a trough. with this offset level held, an offset voltage is applied to the q dac until a (lower) trough is reached. lo leakage compensation holds up well over temperature. tpc 8 shows the effect of temperature on lo leakage after compen- sation at ambient. compensated lo leakage will degrade somewhat as the frequency is moved away from the frequency at which the compensation was performed. this is due to the effects of lo to rf output leakage which are not a result of offsets on the i and q inputs. single-ended i and q drive where only single-ended i and q signals are available, a differ- ential amplifier such as the ad8132 or ad8138 can be used to generate the required differential drive signal for the ad8345. even though most dacs have differential outputs, using a single-ended low-pass filter between the dual dac and the i and q inputs, may be more desirable from the perspective of component count and cost. as a result, the output signal from the filter must be converted back to differential mode and possi- bly be rebiased to 0.7 v common mode. figure 5 shows a circuit which converts a ground-referenced, single-ended signal to a differential signal and adds the required 0.7 v bias voltage. two ad8132 differential op amps, config- ured for a gain of unity, are used. with a 50 ? input impedance, this circuit is configured to accept a signal from a 50 ? source (e.g., a low-pass filter). the input impedance can be easily changed by replacing the 49.9 ? shunt resistor (and the corresponding 24.9 ? resistor on the inverting input) with the appropriate value. the required dc-bias level is conveniently added to the signal by applying 0.7 v to the v ocm pins of the differential amplifiers. differential amplifiers such as the ad8132 and ad8138 can also be used to implement active filters. for more information on this topic, consult the data sheets of these devices. 0.1 f 10 f +5v 348 0.1 f 348 49.9 348 24.9 10k 1.5k 348 ad8132 phase splitter vout ibbp ibbn qbbp qbbn ad8345 loip loin vps1 vps2 0.01 f 1000pf 0.01 f 1000pf 0.1 f 10 f +5v 348 0.1 f 348 49.9 348 24.9 348 ad8132 q in i in 0.1 f 10 f 5v 0.1 f 10 f com1 com2 com3 5v figure 5. single-ended iq drive circuit rev. 0 ad8345 C11C note that this circuit assumes that the single-ended i and q signals are ground referenced. any differential dc-offsets will result in increased lo leakage at the output of the ad8345. it is possible to drive the baseband inputs with a single-ended signal biased to 0.7 v, with the unused inputs being biased to a dc level of 0.7 v. however, this mode of operation is not recom- mended b ecause any dc level difference between the bias level of the drive signal and the dc level on the unused input (including the effect of temperature drift) will result in increased lo leakage. in addition, the maximum output power will be re duced by 6 db. rf output the rf output is designed to drive a 50 ? load but should be ac coupled as shown in figure 3. if the i and q inputs are driven in quadrature by 1.2 v p-p signals, the resulting output power will be approximately ? dbm (see tpc 1). the rf output impedance is very close to 50 ? . as a result, no additional matching circuitry is required if the output is driving a 50 ? load. application with txdac figure 6 shows the ad8345 driven by the ad9761 txdac (any of the devices in adi? txdac family can also be used in this application). the signal from the dac is being filtered by a differential 51 mhz low-pass filter. the i and q dacs generate differential output currents of 0 ma to 20 ma and 20 ma to 0 ma, respectively. when loaded with 50 ? ground-referenced resistors, this would produce a 2 v p-p differential signal (i.e., 1 v p-p on each output) with a common- mode level of 0.5 v. in the configuration shown, each dac output sees a composite load of 48 ? (10 ? + 51 ? (100 ? + 51 ? )) in the passband. so, for example, when iouta is driven to its posi tive full scale, ibbp will be equal to 0.96 v. with ioutb at 0 ma, the voltage at ibbn will be equal to 0.456 v. this results in a full-scale differential signal of approximately 1 v p-p which will have a common-mode level of 0.7 v. soldering information the ad8345 is packaged in a 16-lead tssop package with exposed pad. for optimum thermal conductivity, the exposed pad can be soldered to the exposed metal of a ground plane. this results in a junction-to-air thermal impedance ( ja ) of 30 c/w. however, soldering is not necessary for safe operation. if exposed pad is not soldered down, the ja is equal to 95 c/w. evaluation board figure 7. shows the schematic of the ad8345 evaluation board. note that uninstalled components are marked as open. this is a 4-layer board, with the two center layers used as ground plane and top and bottom layers used as signal and power planes. the board is powered by a single supply (v s ) in the range, 2.7 v to 5.5 v. the power supply is decoupled by a 0.01 f and 1000 pf capacitors. the circuit closely follows the basic connection schematic with sw1 in b position. if sw1 is in position a, the enable pin will be pulled to ground by a 10 k ? resistor and the device will be in its power-down mode. all connectors are sma-type. the i and q inputs are dc-coupled to allow a direct connection to a dual dac with differen tial outpu ts. resistor pads are provided in case termina tion at the i and q inputs is required. the local oscillator input (lo) is terminated to approximately 50 ? with an external 50 ? resistor to ground. a 1:1 wide-band transformer (etc1-1-13) provides a differential drive to the ad8345? differential lo input. the device can also be driven single-ended by shorting out t1. 33pf 100 310nh 33pf 310nh 51 10 51 33pf 100 310nh 33pf 310nh 51 10 51 phase splitter vout ibbp ibbn qbbp qbbn ad8345 loip loin vps1 vps2 ioutb iouta i dac 2 latch i q dac 2 latch q qouta 0.1 f r set 2k refio fs adj sleep select write clock ad9761 mux control av d d dvdd dcom qoutb dac data inputs figure 6. ad8345/txdac interface rev. 0 ad8345 C12C - figure 10. layout of evaluation board, bottom layer 16 1 ibbp qbbp 15 2 ibbn qbbn 14 3 com3 com3 13 4 com1 com3 12 5 loin vps2 11 6 loip vout 10 7 vps1 com2 9 8 enbl com3 ad8345 ip in 1 t1 etc1-1-13 2 3 4 5 lo r6 50 c1 1000pf c2 1000pf c3 0.01 f c4 1000pf vpos qp qn c5 1000pf c6 0.01 f vpos vout c7 1000pf r2 (open) r1 (open) r7 0 sw1 a vpos b r8 10k enbl r12 0 r14 (open) r15 (open) r11 0 r10 (open) r9 (open) figure 7. evaluation board schematic enbl l0 in tp 4 ip qp qn r 6 c 4 r 8 r 2 r 1 r 9 r 10 r 14 r 15 tp 3 tp 1 r 12 tp 2 t 1 c 1 c 2 dut vout 08-007084 rev a ad8345 eval board component side c 5 c 7 sw 1 a b a figure 8. evaluation board silkscreen figure 9. layout of evaluation board, top layer rev. 0 ad8345 C13C ieee hp34970a d1 d2 d3 34901 34907 34907 d1 d2 d3 interface board i_in q_in output_1 output_2 arb function gen ieee tekafg2020 vps1 vn gnd vp +15v max com +25v max 25v max hp3631 ieee ad8345 characterization board p1 in ip qp qn enbl vout p1 in ip qp qn rfout ieee hp8648c lo ieee pc controller spectrum analyzer rf i/p sweep out ieee 28v hp8593e figure 11. characterization board ssb test setup characterization setups ssb setup essentially, two primary setups were used to characterize the ad8345. these setups are shown in figures 11 and 13. figure 11 shows the setup used to evaluate the product as a single sideband modulator. the interface board converts the single- ended i and q inputs from the arbitrary function generator to differential inputs with a dc bias of approximately 0.7 v. the interface board also provides connections for power supply routing. the hp34970a and its associated plug-in 34901 were used to monitor power supply currents and voltages being supplied to the ad8345 characterization board. two hp34907 plug-ins were used to provide additional miscellaneous dc and control signals to the interface board. the lo input was driven directly by an rf signal generator and the output was measured directly with a spectrum analyzer. with the i channel driven with a sine wave and the q channel driven with a cosine wave, the lower sideband is the single sideband output. the typical ssb output spectrum is shown in figure 12. 90 80 70 60 50 40 30 20 10 0 100 amplitude dbm center = 900mhz span = 1mhz figure 12. typical ssb output spectrum modulated waveform setup for evaluating the ad8345 with modulated waveforms, the setup shown in figure 13 was used. a rohde & schwarz amiq signal generator with differential outputs was used to generate the baseband signals. for all measurements the input level on each baseband input pin was 0.7 v 0.3 v peak. the output was measured with a rohde & schwarz fsiq spec- trum/vector analyzer. +15v max com +25v max 25v max hp3631 ieee ad8345 characterization board p1 in ip qp qn enbl vout lo rfout ieee hp8648c ieee pc controller spectrum analyzer rf i/p ieee fsiq pc control amiq in ip qp qn figure 13. test setup for evaluating ad8345 with modulated waveforms rev. 0 ad8345 C14C cdma is95 for measuring acpr, the i and q input signals used were generated with pilot (walsh code 00), sync (wc 32), paging (wc 01), and 6 traffic (wc 08, 09, 10, 11, 12, 13) channels active. figure 14 shows the typical output spectrum for this configuration. for performing evm, rho, phase, and amplitude balance mea- surements, the i and q input signals used were generated with only the pilot channel (walsh code 00) active. 90 80 70 60 50 40 30 20 10 100 110 amplitude dbm center = 880mhz span = 7.5mhz ch pwr = 12.41dbm acp up = 72.8db acp low = 72.8db figure 14. typical is95 output spectrum wcdma 3gpp for evaluating the ad8345 for wcdma, the 3gpp standard was used with a chip rate of 3.84 mhz. the plot in figure 15 is an acpr plot of the ad8345 using ?est model 1?from the 3gpp specification with 64 channels active. 90 80 70 60 50 40 30 20 10 100 110 amplitude dbm center = 380mhz span = 14.7mhz ch pwr = 10.95dbm acp up = 52.51db acp low = 52.41db figure 15. typical ad 8345 wcdma 3gpp output spectrum gsm for comparing the ad8345 output to the gsm transmit mask i and q signals were generated using msk modulation, gsm differential coding, a gaussian filter and a symbol rate of 270.833 khz. the transmit mask was manually generated on the fsiq using the gsm bts specification for reference. the plot in figure 16 shows that the ad8345 meets the gsm trans- mit mask requirements. 90 80 70 60 50 40 30 20 10 100 0 amplitude dbm center = 900mhz span = 1mhz figure 16. typical ad8345 gsm output spectrum rev. 0 ad8345 C15C 16-lead htssop with exposed pad (re-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) 0.118 (3.0) sq exposed pad seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm). C16C c00932C1.5C7/01(0) printed in u.s.a. |
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