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june 2003 1/166 this is preliminary information on a new product. details are subject to change without notice. rev. 2.3 st7265x low-power, full-speed usb 8-bit mcu with 32k flash, 5k ram, flash card i/f, timer, pwm, adc, i 2 c, spi datasheet n memories C up to 32k of rom or high density flash (hd- flash) program memory with read/write pro- tection C for hdflash devices, in-application pro- gramming (iap) via usb and in-circuit pro- gramming (icp) C up to 5 kbytes of ram with up to 256 bytes stack n clock, reset and supply management C pll for generating 48 mhz usb clock using a 12 mhz crystal C low voltage reset (except on e suffix devic- es) C dual supply management: analog voltage de- tector on the usb power line to enable smart power switching from usb power to battery (on e suffix devices). C programmable internal voltage regulator for memory cards (2.8v to 3.5v) supplying: flash card i/o lines (voltage shifting) up to 50 ma for flash card supply C clock-out capability n 47 programmable i/o lines C 15 high sink i/os (8ma @0.6v / 20ma@1.3v) C 5 true open drain outputs C 24 lines programmable as interrupt inputs n usb (universal serial bus) interface C with dma for full speed bulk applications com- pliant with usb 12 mbs specification (version 2.0 compliant) C on-chip 3.3v usb voltage regulator and transceivers with software power-down C 5 usb endpoints: 1 control endpoint 2 in endpoints supporting interrupt and bulk 2 out endpoints supporting interrupt and bulk C hardware conversion between usb bulk packets and 512-byte blocks n mass storage interface C dtc (data transfer coprocessor): universal serial/parallel communications interface, with software plug-ins for current and future proto- col standards: compact flash - multimedia card - secure digital card - smartmediacard - sony memory stick - nand flash - ata peripherals n 2 timers C configurable watchdog for system reliab ility C 16-bit timer with 2 output compare functions. n 2 communication interfaces C spi synchronous serial interface Ci 2 c single master interface up to 400 khz n d/a and a/d peripherals C pwm/brm generator (with 2 10-bit pwm/ brm outputs) C 8-bit a/d converter (adc) with 8 channels n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction C true bit manipulation n development tools C full hardware/software development package device summary tqfp64 10x10 tqfp48 so34 shrink features st72651 st72f651 st72652 program memory 32k rom 32k flash 16k rom user ram (stack) - bytes 5k (256) 512 (256) peripherals usb, dtc, timer, adc, spi, i 2 c, pwm, wdt usb, dtc, wdt operating supply dual 2.7v to 5.5v or 4.0v to 5.5v (for usb) dual 3.0v to 5.5v or 4.0v to 5.5v (for usb) single 4.0v to 5.5v package tqfp64 (10 x10) tqfp64 (10 x10) / tqfp48 (7x7) / so34 operating temperature 0c to +70c 1
table of contents 2/166 - 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 program memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4 power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2 data transfer coprocessor (dtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.3 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1
table of contents 3/166 11.5 pwm/brm generator (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.6 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.7 i2c single master bus interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.8 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.10timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.11communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 149 13.128-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 159 15.1 option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.2 device ordering information and transfer of customer code . . . . . 160 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 1
st7265x 4/166 1 introduction the st7265x mcu supports volume data ex- change with a host (computer or kiosk) via a full speed usb interface. the mcu is capable of han- dling various transfer protocols, with a particular emphasis on mass storage applications. st7265x is compliant with the usb mass storage class specifications, and supports related proto- cols such as bot (bulk only transfer) and cbi (control, bulk, interrupt). it is based on the st7 standard 8-bit core, with specific peripherals for managing usb full speed data transfer between the host and most types of flash media card: C a full speed usb interface with serial interface engine, and on-chip 3.3v regulator and trans- ceivers. C a dedicated 24 mhz data buffer manager state machine for handling 512-byte data blocks (this size corresponds to a sector both on computers and flash media cards). C a data transfer coprocessor (dtc), able to handle fast data transfer with external devices. this dtc also computes the crc or ecc re- quired to handle mass storage media. C an arbitration block gives the st7 core priority over the usb and dtc when accessing the data buffer. in usb mode, the usb interface is serv- iced before the dtc. C a flash supply block able to provide program- mable supply voltage and i/o electrical levels to the flash media. figure 1. usb data transfer block diagram 512-byte ram buffer 512-byte ram buffer data coprocessor data transfer buffer level shifters mass device usb sie st7 core storage transfer (dtc) arbitration usb data transfer buffer access 1
st7265x 5/166 introduction (contd) in addition to the peripherals for usb full speed data transfer, the st7265x includes all the neces- sary features for stand-alone applications with flash mass storage. C low voltage reset ensuring proper power-on or power-off of the device (not on all products) C digital watchdog C 16-bit timer with 2 output compare functions (not on all products - see device summary). C two 10-bit pwm outputs (not on all products - see device summary) C serial peripheral interface (not on all products - see device summary) C fast i 2 c single master interface (not on all prod- ucts - see device summary) C 8-bit analog-to-digital converter (adc) with 8 multiplexed analog inputs (not on all products - see device summary) the st72f65x are the flash versions of the st7265x in a tqfp64 package. the st7265x are the rom versions in a tqfp64 package. figure 2. digital audio player application example in play mode 512-byte ram buffer 512-byte ram buffer data coprocessor data transfer buffer level shifters mass device st7 core storage transfer (dtc) arbitration buffer access digital audio device i2c 1
st7265x 6/166 introduction (contd) figure 3. st7265x block diagram 8-bit core alu address and data bus oscin oscout reset data pd[7:0] (8 bits) 12mhz f cpu control ram (0.5/5 kbytes) program (16/32 kbytes) memory 16-bit timer* lvd* watchdog v dda v pp usbdp usbdm usbvcc * not on all products (refer to table 1: device summary) transfer coprocessor port c port e port d pe[7:0] (8 bits) pc[7:0] (8 bits) pb[7:0] (8 bits) pa[7:0] (8 bits) port f pf[6:0] (7 bits) 8-bit adc* i 2 c* flash supply v ddf v ssa power supply dual supply usbv ss manager * block 48mhz pll clock divider osc usb v ssf usbv dd v ss1, v ss2 v dd1, v dd2 pwm* port b port a data transfer buffer (1280 bytes) dtc s/w ram (256 bytes) regulator arbitration spi * 1
st7265x 7/166 2 pin description figure 4. 34-pin so package pinout 28 27 26 25 24 23 22 21 20 19 18 29 30 31 32 v dda v dd2 pc3 (hs) / dtc v dd1 v ss1 pd0 pd1 pd2 pd3 pd5 pd6 v pp /iccsel reset pf6 (hs) / iccdata pd4 pf5 (hs) / iccclk 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ssa v ss2 mco / (hs) pc0 dtc / pa3 dtc / pa2 dtc / pa1 dtc / pa0 v ssf v ddf usbvcc usbdm usbv ss oscout oscin usbv dd pc2 (hs) / dtc dtc / (hs) pc1 33 34 17 usbdp (hs) high sink capability ei x associated external interrupt vector i/o pin supplied by v ddf / v ssf ei1 ei0 ei2 ei2 1
st7265x 8/166 pin description (contd) figure 5. 48-pin tqfp package pinout 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 v dda v dd2 pf6 (hs) / iccdata pf5 (hs)/iccclk reset v pp/ iccsel pe4 oscout oscin v ss2 v ssa usbv dd v ddf v ssf dtc/pb0 dtc/pb1 dtc/pb3 usbv ss usbdm usbdp usbvcc dtc / pa0 dtc / pa1 dtc / pa2 dtc / pa3 dtc / pa4 dtc / pa5 dtc / pa6 dtc / pa7 dtc/pb5 dtc/pb6 dtc/pb7 pe2 (hs) / dtc pe1 (hs) / dtc pe0 (hs) / dtc pd7 v ss1 v dd1 pd0 pd1 pd2 pd3 pd5 pd6 pd4 pe3/dtc dtc/pb2 dtc/pb4 (hs) high sink capability ei x associated external interrupt vector i/o pin supplied by v ddf / v ssf ei1 ei0 1
st7265x 9/166 pin description (contd) figure 6. 64-pin tqfp package pinout dtc / pa2 dtc / pa3 dtc / pa4 dtc / pa5 dtc / pa6 dtc / pa7 ss / mco / (hs) pc0 miso / dtc / (hs) pc1 mosi / dtc / (hs) pc2 sck / dtc / (hs) pc3 v dd1 v ss1 dtc / pb6 dtc / pb7 dtc / pa0 dtc / pa1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei1 ei0 usbv dd v ddf v ssf dtc / pe5 (hs) dtc / pe6 (hs) dtc / pe7 (hs) dtc / pb0 dtc / pb1 dtc / pb2 dtc / pb3 dtc / pb4 dtc / pb5 usbv ss usbdm usbdp usbvcc pd7 / ain3 pd6 / ain2 pd5/ocmp2 pd4/ocmp1 pd3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 pe3 / pwm0 / ain7 / dtc pe2 (hs) / ain6 / dtc pe1 (hs) / ain5 / dtc pe0 (hs) / ain4 / dtc v dda v dd2 pf6 (hs)/iccdata pf5 (hs)/iccclk pf4 (hs) / usben pf3 / ain1 pf2 / ain0 pf1 (hs) / sda pf0 (hs) / scl reset v pp /iccsel pe4 / pwm1 oscout oscin v ss2 v ssa (hs) high sink capability ei x associated external interrupt vector i/o pin supplied by v ddf / v ssf ei2 ei2 1
st7265x 10/166 pin description (contd) legend / abbreviations: type: i = input, o = output, s = supply v ddf powered: i/o powered by the alternate sup- ply rail, supplied by v ddf and v ssf . in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = high sink (on n-buffer only) port and control configuration: C input:float = floating, wpu = weak pull-up, int = in- terrupt C output: od = open drain, t = true open drain, pp = push-pull, op = pull-up enabled by option byte. refer to i/o ports on page 49 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. table 1. device pin description pin pin name type v ddf powered level port / control main function (after reset) alternate function so34 tqfp48 tqfp64 input output input output float wpu int od pp 511usbv ss s usb digital ground 6 2 2 usbdm i/o usb bidirectional data (data -) 7 3 3 usbdp i/o usb bidirectional data (data +) 8 4 4 usbvcc o usb power supply, output by the on-chip usb 3.3v linear regulator. note: an external decoupling capacitor (typ. 100nf, min 47nf) must be connected be- tween this pin and usbv ss . 955usbv dd s usb power supply voltage (4v - 5.5v) note: external decoupling capacitors (typ. 4.7f+100nf, min 2.2f+100nfmust be con- nected between this pin and usbv ss . 10 6 6 v ddf sx power line for alternate supply rail. can be used as input (with external supply) or output (when using the on-chip voltage regulator). note: an external decoupling capacitor (min. 20nf) must be connected to this pin to stabi- lize the regulator. 11 7 7 v ssf sx ground line for alternate supply rail. can be used as input (with external supply) or output (when using the on-chip voltage regulator) - - 8 pe5/dtc i/o x c t hs x 2 x 2 x port e5 dtc i/o with serial capability (mmc_cmd) - - 9 pe6/dtc i/o x c t hs x x x port e6 dtc i/o with serial capability (mmc_dat) - - 10 pe7/dtc i/o x c t hs x x x port e7 dtc i/o with serial capability (mmc_clk) - 8 11 pb0/dtc i/o x c t x x port b0 dtc - 9 12 pb1/dtc i/o x c t x x port b1 dtc - 10 13 pb2/dtc i/o x c t x x port b2 dtc 1
st7265x 11/166 -1114pb3/ dtc i/o x c t x x port b3 dtc - 12 15 pb4/dtc i/o x c t x x port b4 dtc - 13 16 pb5/dtc i/o x c t x x port b5 dtc - 14 17 pb6/dtc i/o x c t x x port b6 dtc - 15 18 pb7/dtc i/o x c t x x port b7 dtc 12 16 19 pa0/dtc i/o x c t x ei 0 x x port a0 dtc 13 17 20 pa1/dtc i/o x c t x x x port a1 dtc 14 18 21 pa2/dtc i/o x c t x x x port a2 dtc 15 19 22 pa3/dtc i/o x c t x x x port a3 dtc - 20 23 pa4/dtc i/o x c t x x x port a4 dtc - 21 24 pa5/dtc i/o x c t x x x port a5 dtc - 22 25 pa6/dtc i/o x c t x x x port a6 dtc - 23 26 pa7/dtc i/o x c t x x x port a7 dtc 16 - 27 pc0/mco/ss i/o x c t hs x ei 2 x port c0 main clock output / spi slave select 1 17 - 28 pc1/dtc/mis0 i/o x c t hs x x port c1 dtc i/o with serial capability (datarq) / spi master in slave out 1 18 - 29 pc2/dtc/mosi i/o x c t hs x x port c2 dtc i/o with serial capability (sdat) / spi master out slave in 1 19 - 30 pc3/dtc/sck i/o x c t hs x x port c3 dtc i/o with serial capability (sclk) / spi serial clock 1 20 24 31 v dd1 s power supply voltage (2.7v - 5.5v) 21 25 32 v ss1 s digital ground - - 33 pc4/dtc i/o c t x ei 2 x port c4 dtc - - 34 pc5/dtc i/o c t x x port c5 dtc - - 35 pc6/dtc i/o c t x x port c6 dtc - - 36 pc7/dtc i/o c t x x port c7 dtc pin pin name type v ddf powered level port / control main function (after reset) alternate function so34 tqfp48 tqfp64 input output input output float wpu int od pp 1
st7265x 12/166 22 26 37 pd0 i/o c t x ei 1 x x port d0 23 27 38 pd1 i/o c t x x x port d1 24 28 39 pd2 i/o c t x x x port d2 25 29 40 pd3 i/o c t x x x port d3 26 30 41 pd4/ocmp1 i/o c t x x x port d4 timer output compare 1 1 27 31 42 pd5/ocmp2 i/o c t x x x port d5 timer output compare 2 1 28 32 43 pd6/ain2 i/o c t x x x port d6 analog input 2 1 - 33 44 pd7/ain3 i/o c t x x x port d7 analog input 3 1 - 34 45 pe0/dtc/ain4 i/o c t hs x x x port e0 analog input 4 1 / dtc - 35 46 pe1/dtc/ain5 i/o c t hs x x x port e1 analog input 5 1 / dtc - 36 47 pe2/dtc/ain6 i/o c t hs x x x port e2 analog input 6 1 / dtc -3748 pe3/ain7/dtc/ pwm0 i/o c t x x x port e3 analog input 7 1 / dtc / pwm output 0 1 - 38 49 pe4/pwm1 i/o c t x x x port e4 pwm output 1 1 29 39 50 v pp /iccsel s flash programming voltage. must be held low in normal operating mode. 30 40 51 reset i/o x x bidirectional. this active low signal forces the initialization of the mcu. this event is the top priority non maskable interrupt. this pin is switched low when the watchdog has trig- gered or v dd is low. it can be used to reset ex- ternal peripherals. - - 52 pf0 / scl i/o c t hs x t port f0 i 2 c serial clock 1 - - 53 pf1 / sda i/o c t hs x t port f1 i 2 c serial data 1 - - 54 pf2 / ain0 i/o c t x x port f2 analog input 0 1 - - 55 pf3 / ain1 i/o c t x x port f3 analog input 1 1 - - 56 pf4 / usben i/o c t hs x t port f4 usb power management usb enable (alternate function se- lected by option bit) 31 41 57 pf5 / iccclk i/o c t hs x t port f5 icc clock output 32 42 58 pf6 / iccdata i/o c t hs x t port f6 icc data input 33 43 59 v dd2 s main power supply voltage (2.7v - 5.5v on devices without lvd, otherwise 4v - 5.5v). 34 44 60 v dda s analog supply voltage pin pin name type v ddf powered level port / control main function (after reset) alternate function so34 tqfp48 tqfp64 input output input output float wpu int od pp 1
st7265x 13/166 1 if the peripheral is present on the device (see device summary on page 1) 2 a weak pull-up can be enabled on pe5 input and open drain output by configuring the peor register and depending on the pe5pu bit in the option byte. 14561v ssa s analog ground 24662v ss2 s digital ground 3 47 63 oscin i input/output oscillator pins. these pins con- nect a 12 mhz parallel-resonant crystal, or an external source to the on-chip oscillator. 4 48 64 oscout o pin pin name type v ddf powered level port / control main function (after reset) alternate function so34 tqfp48 tqfp64 input output input output float wpu int od pp 1
st7265x 14/166 figure 7. multimedia card or secure digital card writer application example (1) this line shows if the st72f65 pin is controlled by the st7 core or by the dtc. (2) as this is a single power supply application, the us- ben function in not needed. thus pf4/usben pin can be used as a normal i/o by configuring it as such by the op- tion byte. multimedia card pin cmd dat clk st72f65 pin pe5 pe6 pe7 st7 / dtc (1) dtc dtc dtc vcc usb dp dm usbv dd dtc usb port flash v ddf vpp gnd usb 4.7 m f v dd usbvdd power usb management 5v dp dm gnd 100nf 12v for led2 level translator flash prog. regulator i/o logic =4.0-5.5v up to 5 multimedia or sd cards clk dat cmd pe7 pe6 v dd pe5 (2) 100nf 100nf 1.5k w led1 (connect to gnd if not used) 1
st7265x 15/166 figure 8. smartmedia card writer or flash drive application example table 2. smartmedia interface pin assignment (1): this line shows if the st72f65 pin is controlled by the st7 core or the dtc. (2): these lines are not controlled by the dtc but by the user software running on the st7 core. the st72f65 pin choice is at customer discretion. the pins shown here are only shown as an example. (3): when a single card is to be handled, pa7 is free for other functions. when 2 smartmedia are to be handled, pins from both cards should be tied together (i.e. cle1 with cle2...) except for the ce pins. ce pin from card 1 should be connected to pa6 and ce pin from card 2 should be connect to pa7. selection of the operating card is done by st7 software. (4) as this is a single power supply application, the us- ben function in not needed. thus pf4/usben pin can be used as a normal i/o by configuring it as such by the op- tion byte. dtc flash v ddf vpp v dd power management 100nf 12v for level translator flash prog. regulator i/o logic up to 2 smartmedia cards pa pb v dd 8 6 i/o 0~7 ctrl (4) 2 pe vcc usb dp dm usbv dd usb port gnd usb 4.7 m f usbvdd usb 5v dp dm gnd =4.0-5.5v 100nf 100nf 1.5k w led2 led1 (connect to gnd if not used) 5 1 smartmedia pin i/o0~7 cle we ale re r/b wp (2) ce1 (2) ce2 (2)(3) st72f65 pin pb0-7 pa0 pa1 pa2 pa3 pa4 pa7 pe1 pe0 st7 / dtc (1) dtc dtc dtc dtc dtc dtc st7 st7 st7 1
st7265x 16/166 figure 9. compact flash card writer application example table 3. compact flash card writer pin assignment (1) this line shows if the st72f65 pin is controlled by the st7 core or by the dtc. (2) these lines are not controlled by the dtc but by the user software running on the st7 core. the choice of st72f65 pin is at the customers discretion. the pins shown here are given only as an example. (3) as this is a single power supply application, the us- ben function in not needed. thus pf4/usben pin can be used as a normal i/o by configuring it as such by the op- tion byte. compact flash card pin d0-7 d8-15 vs1 , vs2 , wait , cs1 , inpack , bvd1 , bvd2 iord , iowr , reg , ce2 , v cc csel , reset, gnd, a3-10 a0-2 ce1 r e we cd1 cd2, rdy/bsy, wp st72f65 pin pb0-7 nc nc v ddf v ssf pa0-2 pe2 +pull-up 4.7k w pa3 pa5 pa6 +pull-up 100k w nc st7 / dtc (1) dtc - - power power dtc st7 dtc dtc st7 - dtc flash v ddf vpp v dd power management 100nf level regulator i/o logic pa pb cf 8-bit memory mode 6 8 (3) pe [2] translator led1 vcc usb dp dm usbv dd usb port gnd usb 4.7 m f usbvdd usb 5v dp dm gnd =4.0-5.5v 100nf 100nf 1.5k w 4.7f led2 12v for flash prog. (connect to gnd if not used) 5 1 4.7k w 1
st7265x 17/166 figure 10. sony memory stick writer application example (1) this line shows if the st72f65 pin is controlled by the st7 core or by the dtc. (2) as this is a single power supply application, the us- ben function in not needed. thus pf4/usben pin can be used as a normal i/o by configuring it as such by the op- tion byte. multimedia card pin cmd dat clk st72f65 pin pe5 pe6 pe7 st7 / dtc (1) dtc dtc dtc vcc usb dp dm usbv dd dtc usb port flash v ddf vpp gnd usb 4.7 m f v dd usbvdd power usb management 5v dp dm gnd 100nf 12v for led2 level translator flash prog. regulator i/o logic =4.0-5.5v sony memory stick pc3 pc1 v dd pc2 (2) 100nf 100nf 1.5k w led1 (connect to gnd if not used) pc0 cd clk bs dat 4.7f 1
st7265x 18/166 3 register & memory map as shown in figure 11 , the mcu is capable of ad- dressing 64 kbytes of memories and i/o registers. the available memory locations consist of 80 bytes of register locations, up to 5 kbytes of ram and up to 32 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. important : memory locations noted re- served must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 11. memory map * program memory and ram sizes are product dependent (see table C ) ** the st7 core is not able to read or write in the usb data buffer if the st7265x is running at 6mz in stan- dalone mode. 0000h interrupt & reset vectors hw registers 0050h 004fh (see table 4 ) ffdfh ffe0h ffffh (see table 10 ) 8000h 7fffh program memory* 5 kbytes ram* 16 kbytes c000h reserved 1450h 144fh 32 kbytes 512 bytes ram* short addressing stack (256 bytes) 0100h 0200h 144fh 0050h 00ffh 01ffh 16-bit addressing ram ram (176 bytes) (4688 bytes) short addressing stack (256 bytes) 0100h 0200h 024fh 0050h 00ffh 01ffh 16-bit addressing ram ram (176 bytes) (80 bytes) 154fh 1a4fh 256 bytes 1280 bytes usb data buffer** dtc ram (write protected) 1
st7265x 19/166 table 4. hardware register memory map address block register label register name reset status remarks 0000h 0001h 0002h padr paddr paor port a data register port a data direction register port a option register 00h 00h 00h r/w r/w r/w 0003h 0004h pbdr pbddr port b data register port b data direction register 00h 00h r/w r/w 0005h reserved area (1 byte) 0006h 0007h 0008h pcdr pcddr pcor port c data register port c data direction register port c option register 00h 00h 00h r/w r/w r/w 0009h 000ah 000bh pddr pdddr pdor port d data register port d data direction register port d option register 00h 00h 00h r/w r/w r/w 000ch 000dh 000eh pedr peddr peor port e data register port e data direction register port e option register 00h 00h 00h r/w r/w r/w 000fh 0010h pfdr pfddr port f data register port f data direction register 00h 00h r/w r/w 0011h reserved area (1 byte) 0012h 0013h adc 1 adcdr adccsr adc data register adc control status register 00h 00h read only r/w 0014h wdg wdgcr watchdog control register 7fh r/w 0015h to 0017h reserved area (3 bytes) 0018h dsm pcr power control register 00h r/w 0019h 001ah 001bh spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 001ch 001dh 001eh 001fh dtc dtccr dtcsr reserved dtcpr dtc control register dtc status register dtc pointer register 00h 00h 00h r/w r/w r/w 1
st7265x 20/166 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah tim tcr1 tcr2 tsr chr clr achr aclr oc1hr oc1lr oc2hr oc2lr timer control register 1 timer control register 2 timer status register timer counter high register timer counter low register timer alternate counter high register timer alternate counter low register timer output compare 1 high register timer output compare 1 low register timer output compare 2 high register timer output compare 2 low register 00h 00h 00h ffh fch ffh fch 80h 00h 80h 00h r/w r/w read only read only read only read only read only r/w r/w r/w r/w 002bh flash flash control status register 00h r/w 002ch 002dh 002eh 002fh itc itspr0 itspr1 itspr2 itspr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh usb usbistr usbimr usbctlr daddr usbsr ep0r cnt0rxr cnt0txr ep1rxr cnt1rxr ep1txr cnt1txr ep2rxr cnt2rxr ep2txr cnt2txr usb interrupt status register usb interrupt mask register usb control register device address register usb status register endpoint 0 register ep 0 reception counter register ep 0 transmission counter register endpoint 1 register ep 1 reception counter register endpoint 1 register ep 1 transmission counter register endpoint 2 register ep 2 reception counter register endpoint 2 register ep 2 transmission counter register 00h 00h 06h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0040h 0041h 0042h 0043h 0044h 0045h 0046h i 2 c 1 i2ccr i2csr1 i2csr2 i2cccr not used not used i2cdr i 2 c control register i 2 c status register 1 i 2 c status register 2 i 2 c clock control register i 2 c data register 00h 00h 00h 00h 00h r/w read only read only r/w r/w 0047h usb bufcsr buffer control/status register 00h r/w 0048h reserved area (1 byte) 0049h miscr1 miscellaneous register 1 00h r/w 004ah miscr2 miscellaneous register 2 00h r/w 004bh reserved area (1 byte) address block register label register name reset status remarks 1
st7265x 21/166 note 1. if the peripheral is present on the device (see device summary on page 1) 004ch miscr3 miscellaneous register 3 00h r/w 004dh 004eh 004fh pwm 1 pwm0 brm10 pwm1 10-bit pwm/brm registers 80h 00h 80h r/w r/w r/w address block register label register name reset status remarks 1
st7265x 22/166 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a byte-by-byte ba- sis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features n three flash programming modes: C insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. C icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. C iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. n ict (in-circuit testing) for downloading and executing user application test patterns in ram n read-out protection against piracy n register access security system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 5 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 12 ). they are mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h- ffffh). table 5. sectors available in flash devices 4.4 program memory read-out protection the read-out protection is enabled through an op- tion bit. when this option is selected, the programs and data stored in the program memory (flash or rom) are protected against read-out piracy (in- cluding a re-write protection). in flash devices, when this protection is removed by reprogram- ming the option byte, the entire program memory is first automatically erased and the device can be reprogrammed. refer to the option byte description for more de- tails. figure 12. memory map and sector address flash memory size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k dv flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k 1
st7265x 23/166 flash program memory (contd) 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 13 ). for more details on the pin locations, refer to the device pinout de- scription. icp needs six pins to be connected to the pro- gramming tool. these pins are: C reset : device reset Cv ss : device power supply ground C iccclk: icc output serial clock pin C iccdata: icc input serial data pin C iccsel/v pp : programming voltage Cv dd : application board power supply cautions: 1. if reset , iccclk or iccdata pins are used for other purposes in the application, a serial resis- tor has to be implemented to avoid a conflict in case one of the other devices forces the signal lev- el. if these pins are used as outputs in the applica- tion, the serial resistors are not necessary. as soon as the external controller is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. 2. the use of pin 7 of the icc connector depends on the programming tool architecture. please re- fer to the documentation of the tool. this pin must be connected when using st programming tools (it is used to monitor the application power supply). note: to develop a custom programming tool, re- fer to the st7 flash programming and icc refer- ence manual which gives full details on the icc protocol hardware and software. figure 13. typical icp interface icc connector iccdata iccclk reset vdd he10 connector type >4.7k w application power supply optional (see caution 1) 1 2 4 6 8 10 975 3 programming tool icc connector application board icc cable optional (see caution 2) 10k w vss iccsel/vpp st7 1
st7265x 24/166 flash program memory (contd) 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase pro- tected to allow recovery in case errors occur dur- ing the programming operation. 4.7 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.8 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. table 6. flash register map and reset values 70 00000000 address (hex.) register label 76543210 002bh fcsr reset value 00000000 1
st7265x 25/166 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n low power halt and wait modes n priority maskable hardware interrupts n non-maskable software/hardware interrupts 5.3 cpu registers the 6 cpu registers shown in figure 14 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 14. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1
st7265x 26/166 central processing unit (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. its a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 1
st7265x 27/166 central processing unit (contd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 15 ). since the stack is 256 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 15 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 15. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h 1
st7265x 28/166 6 supply, reset and clock management 6.1 clock system 6.1.1 general description the mcu accepts either a 12 mhz crystal or an external clock signal to drive the internal oscillator. the internal clock (f cpu ) is derived from the inter- nal oscillator frequency (f osc ), which is 12 mhz in stand-alone mode and 48mhz in usb mode. the internal clock (f cpu ) is software selectable us- ing the cp[1:0] and cpen bits in the miscr1 reg- ister. in usbv dd power supply mode, the pll is active, generating a 48mhz clock to the usb. in this mode, f cpu can be configured to be up to 8 mhz. in v dd mode the pll and the usb clock are disa- bled, and the maximum frequency of f cpu is 6 mhz. the internal clock signal (f cpu ) is also routed to the on-chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz in the frequency range specified for f osc . the circuit shown in fig- ure 17 is recommended when using a crystal, and table 7 lists the recommended capacitance. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. table 7. recommended values for 12-mhz crystal resonator note: r smax is the equivalent serial resistor of the crystal (see crystal specification). 6.1.2 external clock an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 16 . the t oxov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see sec- tion 6.5 control timing). figure 16. external clock source connections figure 17. crystal resonator r smax 20 w 25 w 70 w c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf oscin oscout external clock nc oscin oscout c oscin c oscout 1
st7265x 29/166 6.2 reset sequence manager (rsm) 6.2.1 introduction the reset sequence manager includes three re- set sources as shown in figure 6.2.2 : n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset se quence consists of 3 phases as shown in figure 18 : n active phase depending on the reset source n min 512 cpu clock cycle delay (see figure 20 and figure 21 n reset vector fetch figure 18. reset sequences v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in t w(rstl)out run t h(rstl)in active watchdog underflow t w(rstl)out run run run reset reset source short ext. reset lvd reset long ext. reset watchdog reset internal reset (min 512 t cpu ) vector fetch t w(rstl)out phase active phase active phase delay 1
st7265x 30/166 reset sequence manager (contd) 6.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized. this detection is asynchro- nous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. if the external reset pulse is shorter than t w(rstl)out (see short ext. reset in figure 18 ), the signal on the reset pin will be stretched. other- wise the delay will not be applied (see long ext. reset in figure 18 ). starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . 6.2.3 internal low voltage detection reset two different reset s equences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop r eset the device reset pin acts as an output that is pulled low when v dd st7265x 31/166 reset sequence manager (contd) in stand-alone mode, the 512 cpu clock cycle de- lay allows the oscillator to stabilize and ensures that recovery has taken place from the reset state. in usb mode the delay is 256 clock cycles count- ed from when the pll lock signal goes high. the reset vector fetch phase duration is 2 clock cycles. figure 20. reset delay in stand-alone mode figure 21. reset delay in usb mode note: for a description of stand-alone mode and usb mode refer to section 6.4 . 512 x t cpu(stand-alone) reset fetch vector delay fetch vector 256 x t cpu(stand-alone) 256 x t cpu(usb) pll startup reset time (undefined) delay 400 s typ. 1
st7265x 32/166 6.3 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down, keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run- ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv it+ when v dd is rising Cv it- when v dd is falling the lvd function is illustrated in figure 22 . during a low voltage detector reset, the r eset pin is held low, thus permitting the mcu to reset other devices. figure 22. low voltage detector vs reset v dd v it+(lvd) reset v it-(lvd) v hyst 1
st7265x 33/166 6.4 power supply management 6.4.1 single power supply management in applications operating only when connected to the usb (flash writers, backup systems), the mi- crocontroller must operate from a single power supply (i.e. usb bus power supply or the local power source in the case of self-powered devic- es). devices with lvd (no e suffix) or without lvd (e suffix) can support this configuration. in order to enable the single power supply man- agement, the plgie bit in the pcr register should kept cleared by software (reset default value). in this case, pin v dd and usbv dd of the micro- controller must be connected together and sup- plied by a 4.0 to 5.5v voltage supply, either from the usb cable or from the local power source. see figure 23 . figure 23. single power supply mode . in this mode: C the pll is running at 48 mhz C the on-chip usb interface is enabled C the core can run at up to 8mhz internal frequen- cy C the microcontroller can be either usb bus pow- ered or supplied by the local power source (self powered) C the usben function is not used. the pf4 pin can be configured to work as a normal i/o by pro- gramming the option byte. 6.4.2 dual power supply management in case of a device that can be used both when powered by the usb or from a battery (digital au- dio player, digital camera, pda), the microcon- troller can operate in two power supply modes: stand-alone mode and usb mode. this configura- tion is only available on devices without lvd (e suffix). devices with lvd are kept under reset when the power supply drops below the lvd threshold voltage and thus stand-alone mode can not be entered. in order to enable dual power supply manage- ment: C the usben pin function must be selected by pro- gramming the option byte. C the user software must set the plgie bit in the pcr register in the initialization routine. stand-alone mode this mode is to be used when no usb communi- cation is needed. the microcontroller in this mode can run at very low voltage, making the design of low power / battery supplied systems easy. in this mode: C the usb cable is unplugged (no voltage input on usbv dd pin) C the pll is off C the on-chip usb interface is disabled C the core can run at up to 6 mhz internal frequen- cy C usben is kept floating by h/w. C the microcontroller is supplied through the v dd pin usb mode when connected to the usb, the microcontroller can run at full speed, still saving battery power by using usb power or self power source. to go into usb mode, a voltage from 4.0v to 5.5v must be provided to the usbv dd pin. in this mode: C the usb cable is plugged in C usbv dd pin is supplied by a 4.0 to 5.5v supply voltage, either from the usb cable or from the self powering source C the pll is running at 48 mhz C the on-chip usb interface is enabled C the core can run at up to 8 mhz internal frequen- cy C usben is set to output low level by hardware. this signal can be used to control an external transistor (usb switch) to change the power supply configuration (see figure 24 ). C the microcontroller can be usb bus powered v dd1 v dd2 v dda usbv dd st7 4.0 - 5.5 v note: ground lines not shown 1
st7265x 34/166 power supply management (contd) 6.4.2.1 switching from stand-alone mode to usb mode in stand-alone mode, when the user plugs in the usb cable, 4v min. is input to usbv dd . the on- chip power supply manager generates an internal interrupt when usbv dd reaches usbv it+ (if the plgie bit in the pcr register is set). the user pro- gram then can finish the current processing, and must generate a software reset afterwards. this puts the microcontroller into reset state and all i/o ports go into input high impedance mode. during and after this (software induced) reset phase, the usben pin is set to output low level by hardware. this causes the usb switch to be turned on. consequently, v dd pin is powered by usbv dd supply. see figure 24 . once in usb mode, no power is drawn from the step-up converter output. for more details, refer to figure 25 . figure 24. external power supply switch v dd1 usb switch v dd2 v dda usbv dd usben st7 (true od, h/w crtl) step-up converter 4v min. from usb note 1: ground lines not shown pcr register plg general purpose i/o (i/o port dr, ddr) option bit usben h/w control usbv it- usbv it+ usbv it- plg bit usbv dd alternate function (usben ) pmos vitpf usbv it+ vitmf bit vitpf bit plgie vitmf interrupt request reset logic s/w reset edge detector usb voltage detector with latch deten (note 2) note 2: suggested device: irlml6302 (international rectifier) or si230ds (siliconix) 1
st7265x 35/166 power supply management (contd) 6.4.2.2 switching from usb mode to stand- alone mode in usb mode, when the user unplugs the usb ca- ble, the voltage level drops on the usbv dd line. the on-chip power supply manager generates a plg interrupt when usbv dd reaches usbv it- . the user program then can finish the current processing, and must generate a software re- set . caution: care should be taken as during this peri- od the microcontroller clock is provided from the pll output. functionality in this mode is not guar- anteed for voltages below v pllmin . software must ensure that the software reset is generated before v dd . drops below v pllmin . fail- ing to do this will cause the clock circuitry to stop, freezing the microcontroller operations. once the user program has executed the software reset, the microcontroller goes into reset state and all i/o ports go into floating input mode. during and after this (software induced) reset phase, the usben pin is put in high impedance by hardware. it causes the usb switch to be turned off, so usbv dd is disconnected from v dd . the pll is automatically stopped and the in- ternal frequency is provided by a division of the crystal frequency. refer to figure 25 . the microcontroller is still powered by the residual usbv dd voltage (higher than step-up converter set output level). this v dd voltage decreases dur- ing the reset phase until it reaches the step-up converter set output voltage. at that time, step-up converter resumes operation, and powers the ap- plication. caution: in order to avoid applying excessive volt- age to the storage media, a minimum delay must be ensured during (and after if needed) the reset phase, prior to switching on the external stor- age switch. see figure 26 and figure 27 . 1
st7265x 36/166 power supply management (contd) figure 25. power supply management: dual power supply usb mode stand-alone stand-alone reset s/w stand-alone usbv dd v dd pin pll 48 mhz clock crystal (12mhz) pll crystal (12mhz) s/w reset plg interrupt on supply usbv it+ request usbv it- status processing 12 1. interrupt processing 2. finish current processing process. stand-alone 1 2 s/w reset processing stand-alone mode usben hi-z hi-z voltage supply voltages source pll off pll on pll off stable 48 mhz unde signal on/off fined 3 no clock 3. pll start-up time (automatically controlled by hardware following a software reset) usb mode no clock v pllmin48 reset reset reset v it+(lvd) v it-(lvd) rst 4 4. pll running with frequency in the range of 48 to 24 mhz (see section 13.3.3 on page 131 ) 1
st7265x 37/166 power supply management (contd) 6.4.3 storage media interface i/os the microcontroller is able to drive storage media through an interface operating at a different volt- age from the rest of the circuit. this is achieved by powering the storage media interface i/o circuitry through a specific supply rail connected to v ddf pin. the v ddf pin can be used either as an input or output. if the on-chip voltage regulator is off, power to the interface i/os should be provided externally to the v ddf pin. this should be the case when in stand- alone mode, or in usb mode when the current re- quired to power the storage media is above the current capacity of the on-chip regulator. if the on-chip voltage regulator is on, it powers the interface i/os, and v ddf pin can supply the stor- age media. this is recommended in usb mode, when the current required to power the storage media is within the capacity of the on-chip regula- tor. application example: stand-alone mode C the storage media interface supply is powered by v dd enabled by an external switch (see fig- ure 26 ) which connects v dd to v ddf . this switch can be driven by any true open drain i/o pin and controlled by user software. C the on-chip voltage regulator must be disabled to avoid any conflict and to decrease consump- tion (reset the regen bit in the pcr register). usb mode C in this case the core of the microcontroller is run- ning from the usb bus power or the self power supply. v dd and usbv dd pins are supplied with a voltage from 4.0 to 5.5v. C the storage media interface can be powered through the on-chip regulator (providing power to the i/o pins and output on pin v ddf ) if the current requirement is within the output capacity of the on chip regulator. C the regulator output voltage can be pro- grammed to 2.8v, 3.3v, 3.4v or 3.5 volts, de- pending on the storage media specifications. (see vset[1:0] bits in pcr register description) C should the current requirement for the storage media be higher than the current capacity of the on chip regulator, an external regulator should be used (see figure 27 ). thus the on-chip voltage regulator must be disabled to avoid any conflict (reset the regen bit in the pcr register). caution: the user should ensure that v dd does not exceed the maximum rating specified for the storage media v ddf max when switching stor- age switch on. 1
st7265x 38/166 power supply management (contd) figure 26. storage media interface supply switch (for low current media) figure 27. storage media interface supply switch (for high current media) v dd1 storage switch v dd2 v dda v ddf i/o pin st7 (true od) v dd note: ground lines not shown storage media i/os voltage regulator i/o logic 2.8v, 3.3v, 3.4v or 3.5v (2.7v - 5.5v) storage media this switch is turned on to the on-chip regulator i/f in usb mode power storage media i/f in stand-alone mode supplies the storage media pmos level translator v dd1 storage switch v dd2 v dda v ddf i/o pin st7 (true od) v dd note: ground lines not shown storage media i/os voltage regulator i/o logic 2.8v, 3.3v, 3.4v or 3.5v (2.7v - 5.5v) storage media this supply is not used regul this switch is turned on to power storage media i/f in stand-alone mode this regulator supplies the storage media i/f in usb mode and must be disabled pmos level translator 1
st7265x 39/166 power supply management (contd) 6.4.4 power management application example in the example shown in figure 28 , the v dd supply is provided by a step up. in this case the step up must be capable of tolerating voltages up to 5.5v on its vout pin. figure 28. dual power supply application example (low current storage media) mpeg dac decoder step up 1.2v i 2 s vcc usb dp dm keyboard usbv dd dtc i 2 c mp3 1.5mbit/s max usb port 2m - 128mbyte flash v ddf storage vpp gnd usb 10 m f cbus=40pf max 2 4 lcd display light audio amp tda7474 sta013 4.7 m f 50 m h v dd usbvdd power usb management 5v dp dm gnd 100nf vdd in stand-alone mode regulator output (2.8 - 3.5v) in usb mode 12v for storage switch usbv dd switch dec switch led level translator flash prog. regulator i/o logic i2c =4.0-5.5v media thresh usben 4.7f 1
st7265x 40/166 power supply management (contd) 6.4.5 register description power control register (pcr) reset value: 0000 0000 (00h) bit 7 = itpf voltage input threshold plus flag this bit is set by hardware when usbv dd rises over usbv it+ and cleared by hardware when us- bv dd drops below usbv it+ . 0: usbv dd < usbv it+ 1:usbv dd > usbv it+ bit 6 = itmf voltage input threshold minus flag this bit is set by hardware when usbv dd rises over usbv it- and cleared by hardware when us- bv dd drops below usbv it- . 0: usbv dd < usbv it- 1:usbv dd > usbv it- bit 5 = plg usb plug/unplug detection. this bit is set by hardware when it detects that the usb cable has been plugged in. it is cleared by hardware when the usb cable is unplugged. (de- tection happens when usbv dd rises over usb- v it+ or when usbv dd drops below usbv it- ). if the plgie bit is set, the rising edge of the plg bit also generates an interrupt request. 0: usb cable unplugged 1: usb cable plugged in bit 4 = plgie usb plug/unplug interrupt enable. this bit is set and cleared by software. 0: single supply mode: plg interrupt disabled. 1: dual supply mode: plg interrupt enabled (gen- erates an interrupt on the rising edge of plg). bit 3:2 = vset[1:0] voltage regulator output voltage. these bits are set and cleared by software to se- lect the output voltage of the on-chip voltage regu- lator (for the v ddf output). bit 1 = deten usb voltage detector enable. this bit is set and cleared by software. it is used to power-off the usb voltage detector in stand-alone mode. 0: the usb voltage detector is enabled. 1: the usb voltage detector disabled (itpf, itmf and plg bits are forced high) bit 0 = regen voltage regulator enable. this bit is set and cleared by software. 0: the regulator is completely shutdown and no current is drawn from the power supply by the voltage reference. 1: the on-chip voltage regulator is powered-on. 70 itpf itm f plg plg ie vse t1 vse t0 det en reg en vse t1 vse t0 voltage output of the regulator 00 3.5v 01 3.4v 1 0 3.3v 11 2.8v 1
st7265x 41/166 7 interrupts 7.1 introduction the cpu enhanced interrupt management pro- vides the following features: n hardware interrupts n software interrupt (trap) n nested or concurrent interrupt management with flexible interrupt priority and level management: C up to 4 software programmable nesting levels C up to 16 interrupt vectors fixed by hardware C 3 non maskable events: r eset, trap, tli this interrupt management is based on: C bit 5 and bit 3 of the cpu cc register (i1:0), C interrupt software priority registers (isprx), C fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with the standard (not nest- ed) cpu interrupt controller. 7.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see table 8 ). the process- ing flow is shown in figure 29 . when an interrupt request has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the previous level will resume. table 8. interrupt software priority levels figure 29. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 iret restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset tli pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt 1
st7265x 42/166 interrupts (contd) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: C the highest software priority interrupt is serviced, C if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 30 describes this decision process. figure 30. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and tli can be considered as having the highest software priority in the deci- sion process. different interrupt vector sources two interrupt source types are managed by the cpu interrupt controller: the non-maskable type (reset, trap, tli) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 29 ). after stacking the pc, x, a and cc registers (except for reset), the corres ponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. n tli (top level hardware interrupt) this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. caution : a trap instruction must not be used in a tli service routine. n trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 29 as a tli. caution: trap can be interrupted by a tli. n reset the reset source has the highest priority in the cpu. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. n external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the isx bits in the miscr1 and miscr3 registers. external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically nanded. n peripheral interrupts usually the peripheral interrupts cause the device to exit from halt mode except those mentioned in the interrupt mapping table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced 1
st7265x 43/166 interrupts (contd) 7.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column exit from halt in interrupt mapping table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision proc- ess shown in figure 30 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 7.4 concurrent & nested management the following figure 31 and figure 32 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 32 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 31. concurrent interrupt management figure 32. nested interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes 1
st7265x 44/166 interrupts (contd) 7.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see interrupt dedicated instruction set table). *note : tli, trap and r eset events can interrupt a level 3 program. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. C each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. C each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. C level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and tli vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits 1
st7265x 45/166 interrupts (contd) table 9. dedicated interrupt instruction set note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. in order not to lose the current software priority level, the rim, sim, halt, wfi and pop cc instructions should never be used in an interrupt routine. table 10. interrupt mapping instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 icp flash start programming nmi interrupt yes fffah-fffbh 1 plg power management usb plug/unplug pcr yes fff8h-fff9h 2 ei0 external interrupt port a n/a yes fff6h-fff7h 3 dtc dtc peripheral interrupt dtcsr no fff4h-fff5h 4 usb usb peripheral interrupt usbistr no fff2h-fff3h 5 esusp usb end suspend interrupt usbistr yes fff0h-fff1h 6 ei1 external interrupt port d n/a yes ffeeh-ffefh 7i 2 ci 2 c interrupt i2csrx no ffech-ffedh 8 tim timer interrupt tsr no ffeah-ffebh 9 ei2 external interrupt port c n/a yes ffe8h-ffe9h 10 spi spi interrupt spicsr yes ffe6h-ffe7h 1
st7265x 46/166 interrupts (contd) table 11. nested interrupts register map and reset values address (hex.) register label 76543210 002ch ispr0 reset value dtc ei0 plg isp i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 002dh ispr1 reset value i 2 c ei1 esusp usb i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 002eh ispr2 reset value not used spi ei2 tim i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 002fh ispr3 reset value 1 1 1 1 not used not used i1_13 1 i0_13 1 i1_12 1 i0_12 1 1
st7265x 47/166 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, two main pow- er saving modes are implemented in the st7. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. the user can also switch off any unused on-chip peripherals individually by programming the miscr2 register. 8.2 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i1:0] bits in the cc register are forced to 0, to enable all interrupts. all other registers and mem- ory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 33 . figure 33. wait mode flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i1:0] bits on on cleared off cpu clock oscillator periph. clock i1:0] bits on on set on fetch reset vector or service interrupt delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i1:0] bits are set during the interrupt routine and cleared when the cc register is popped. (refer to figure 20 and figure 21 ) 1
st7265x 48/166 power saving modes (contd) 8.3 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by ex- ecuting the halt instruction. the internal oscilla- tor is then turned off, causing all internal process- ing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i[1:0] bits in the condition code register are cleared. thus, any of the external interrupts (iti or usb end suspend mode), are allowed and if an interrupt occurs, the cpu clock becomes active. the mcu can exit halt mode on reception of ei- ther an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, an spi interrupt or a reset. the oscillator is then turned on and a stabilization time is provided be- fore releasing cpu operation. the stabilization time is 512 cpu clock cycles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 34. halt mode flow chart n n external interrupt* reset halt instruction fetch reset vector or service interrupt delay cpu clock oscillator periph. clock i1:0] bits on on set on cpu clock oscillator periph. clock i1:0] bits off off cleared off y y note: before servicing an interrupt, the cc register is pushed on the stack. the i1:0] bits are set during the interrupt routine and cleared when the cc register is popped. (refer to figure 20 and figure 21 ) 1
st7265x 49/166 9 i/o ports 9.1 introduction important note: please note that the i/o port configurations of this device differ from those of the other st7 devices. the i/o ports offer different functional modes: C transfer of data through digital inputs and outputs and for specific pins: C external interrupt generation C alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 functional description each port has 2 main registers: C data register (dr) C data direction register (ddr) and one optional register: C option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 35 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically nanded and inverted. for this rea- son if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see figure 36 ). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 9.2.2 output modes two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. reading the dr register returns the digital value present on the external i/o pin. consequently even in output mode a value written to an open drain port may differ from the value read from the port. for example, if software writes a 1 in the latch, this value will be applied to the pin, but the pin may stay at 0 depending on the state of the external circuitry. for this reason, bit manipulation even using instructions like bres and bset must not be used on open drain ports as they work by reading a byte, changing a bit and writing back a byte. a workaround for applications requiring bit manipulation on open drain i/os is given in section 9.2.4 . dr push-pull open-drain 0v ss vss 1v dd floating 1
st7265x 50/166 i/o ports (contd) 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 1
st7265x 51/166 i/o ports (contd) figure 35. i/o port general block diagram table 12. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the device against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up configuration p-buffer (see table below) n-buffer pull-up (see table below) analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access 1
st7265x 52/166 i/o ports (contd) table 13. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) configuration pad v dd r pu external interrupt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register configuration alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access w v dd alternate alternate enable output register not implemented in true open drain i/o ports r pad r pu data bus dr dr register access v dd alternate alternate enable output register not implemented in true open drain i/o ports r w 1
st7265x 53/166 i/o ports (contd) 9.2.4 bit manipulation on open drain outputs as mentioned in section 9.2.2 , software should avoid using bit manipulation instructions on the dr register in open drain output mode, but must al- ways access it using byte instructions. if bit manip- ulation is needed, the solution is to use a copy of the dr register in ram, change the bits (using bres or bclr instructions for example) and copy the whole byte into the dr register each time the value has to be output on a port. this way, no bit manipulation is performed on the dr register but each bit of the dr register can be controlled sepa- rately. 9.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 36 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 36. interrupt i/o port state transitions the i/o port register configurations are summa- rized as follows. port b (without option register) pb[7:0] table 14. port configuration (with option register) 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode ddr floating input 0 push-pull output 1 port pin name input output or = 0 or = 1 or = 0 or = 1 high-sink port a pa7:0 floating floating with interrupt open drain push-pull no port c pc7:4 floating floating with interrupt push-pull no pc3:0 floating floating with interrupt push-pull yes port d pd7:0 floating floating with interrupt open drain push-pull no port e pe7:6 floating open drain push-pull yes pe5 floating with pull-up, if se- lected by option byte see section 15.1 ) open drain (with pull-up, if select- ed by option byte see section 15.1 ) push-pull yes pe4:3 floating open drain push-pull no pe2:0 floating open drain push-pull yes port f pf6:4 floating true open drain yes pf3:2 floating push-pull no pf1:0 floating true open drain yes 1
st7265x 54/166 i/o ports (contd) 9.4 register description data register (dr) port x data register pxdr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bits 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register always returns the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bits 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, c, d, or e read/write reset value: 0000 0000 (00h) bits 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the interrupt capability or the basic config- uration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: floating input with interrupt (ports a, c and d). for port e configuration, refer to table 14 . output mode: 0: output open drain (with p-buffer deactivated) 1: output push-pull 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0 1
st7265x 55/166 i/o ports (contd) table 15. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h unused 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 1
st7265x 56/166 10 miscellaneous registers miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bits 7:6 = is1[1:0] ei0 interrupt sensitivity interrupt sensitivity, defined using the is1[1:0] bits, is applied to the ei0 interrupts (port a): these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 5 = mco main clock out selection this bit enables the mco alternate function on the i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu output on i/o port) bits 4:3 = is2[1:0] ei1 interrupt sensitivity interrupt sensitivity, defined using the is2[1:0] bits, is applied to the ei1 external interrupts (port d): these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bits 2:1 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the cpen bit. these two bits are set and cleared by software caution: C the st7 core is not able to read or write in the usb data buffer if the st7265x is configured at 6 mhz in standalone mode. C in usb mode, with f cpu 2 mhz, if the st7 core accesses the usb data buffer, this may prevent the usb interface from accessing the buffer, re- sulting in a usb buffer overrun error. this is be- cause an access to memory lasts one cycle and the usb has to send/receive at a fixed baud rate. bit 0 = cpen clock prescaler enable this bit is set and cleared by software. it is used with the cp[1:0] bits to configure the internal clock frequency. 0: default f cpu used (3 or 6 mhz) 1: f cpu determined by cp[1:0] bits 70 is11 is10 mco is21 is20 cp1 cp0 cpen is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge operating mode f cpu cp1 cp0 cpen stand-alone mode (f osc = 12 mhz) 3 mhz x x 0 6 mhz* 0 0 1 1.5 mhz 1 0 1 750 khz 0 1 1 375 khz 1 1 1 usb mode (48 mhz pll) 6 mhz x x 0 8 mhz 0 0 1 2 mhz 1 0 1 1 mhz 0 1 1 250 khz 1 1 1 1
st7265x 57/166 miscellaneous registers (contd) miscellaneous register 2 (miscr2) reset value: 0000 0000 (00h) bits 7:5 = reserved. bits 4:0 = p[4:0] power management bits these bits are set and cleared by software. they can be used to switch the on-chip peripherals of the microcontroller on or off. the registers are not changed by switching the peripheral off and then on (contents are frozen while off). 0: peripheral on (running) 1: peripheral off miscellaneous register 3 (miscr3) read/write reset value: 0000 0000 (00h) bit 7 = wdghalt watchdog and halt mode this bit is set and cleared by software. it deter- mines if a reset is generated when entering halt mode while the watchdog is active (wdga bit =1 in the wdgcr register). in either case, the watchdog will not reset the mcu if a halt instruction is executed while the usb is in suspend mode. 0: if the watchdog is active, it will reset the mcu if a halt instruction is executed (unless the usb is in suspend mode) 1: when a halt instruction is executed, the mcu will enter halt mode (without generating a reset) even if the watchdog is active. bits 6:4 = reserved, forced by hardware to 0. bits 3:2= is3[1:0] ei2 interrupt sensitivity interrupt sensitivity, defined using the is3[1:0] bits, is applied to the ei2 interrupts (port c): these 2 bits must be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 1 = pwm1 pwm1 output control 0: pwm1 output alternate function disabled (i/o pin free for general purpose i/o). 1: pwm1 output alternate function enabled bit 0 = pwm0 pwm0 output control 0: output alternate function disabled (i/o pin free for general purpose i/o). 1: pwm0 output alternate function enabled table 16. miscellaneous register map and reset values 70 0 0 0 p4p3p2p1p0 bit peripheral p0 pwm p1 timer p2 i2c p3 usb p4 dtc 70 wdg halt 0 0 0 is31 is30 pwm1 pwm0 is31 is30 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge address (hex.) register label 7 65 4 3210 49 miscr1 reset value is11 0 is10 0 mco 0 is21 0 is20 0 cp1 0 cp0 0 cpen 0 4a miscr2 reset value 0 0 0 0 0 0 p4 0 p3 0 p2 0 p1 0 p0 0 4c miscr3 reset value wdghalt 0 0 0 0 0 0 0 is31 0 is30 0 pwm1 0 pwm0 0 1
st7265x 58/166 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 11.1.2 main features n programmable free-running downcounter (64 increments of 65536 cpu cycles) n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero n hardware watchdog selectable by option byte 11.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 65,536 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. this downcounter is free- running: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 17 ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 17.watchdog timing (f cpu = 8 mhz) figure 37. watchdog block diagram cr register initial value wdg timeout period (ms) max ffh 524.288 min c0h 8.192 reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 65536 t1 t2 t3 t4 t5 1
st7265x 59/166 watchdog timer (contd) 11.1.4 software watchdog option if software watchdog is selected by option byte, the watchdog is disabled following a reset. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 11.1.5 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. 11.1.6 low power modes recommendations C make sure that an external event is available to wake up the microcontroller from halt mode. C before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. C when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as input before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. C the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. C as the halt instruction clears the i bits in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids en- tering other peripheral interrupt routines after ex- ecuting the external interrupt routine corresponding to the wake-up event (reset or ex- ternal interrupt). 11.1.7 interrupts none. mode description wait no effect on watchdog. halt if the wdghalt bit in the miscr3 register is set, halt mode can be used when the watchdog is enabled. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg restarts counting after 514 cpu clocks. in the case of the software watchdog option, if a reset is generated, the wdg is disabled (reset state). note: in usb mode, and in suspend mode, a reset is not generated by entering halt mode 1
st7265x 60/166 watchdog timer (contd) 11.1.8 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 18. watchdog timer register map and reset values 70 wdgat6t5t4t3t2t1t0 address (hex.) register label 765 4 3210 14 wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 1
st7265x 61/166 11.2 data transfer coprocessor (dtc) 11.2.1 introduction the data transfer coprocessor is a universal se- rial/parallel communications interface. by means of software plug-ins provided by stmicroelectron- ics, the user can configure the st7 to handle a wide range of protocols and physical interfaces such as: C 8 or 16-bit ide mode compact flash C multimedia card (mmc protocol) C smartmediacard C secure digital card support for different devices or future protocol standards does not require changing the micro- controller hardware, but only installing a different software plug-in. once the plug-in (up to 256 bytes) stored in the rom or flash memory of the st7 device is load- ed in the dtc ram, and that the dtc operation is started, the i/o ports mapped to the dtc assume specific alternate functions. main features n full-speed data transfer from usb to i/o ports without st7 core intervention n protocol-independency n support for serial and parallel devices n maskable interrupts 11.2.2 functional description the block diagram is shown in figure 38 . the main function of the dtc is to quickly transfer data between : n usb and st7 i/o ports n in between st7 i/o ports the protocol used to read or write from the i/o port is defined by the s/w plug-in in the dtc ram. figure 38. dtc block diagram i/o ports data transfer coprocessor load init stop 0 0 0 run dtccr err en en msb lsb dtcpr 0 0 0 0 0 0 error stop dtcsr interrupt request to usb data buffer dtc ram st7 data/address bus interface transfer 1
st7265x 62/166 data transfer coprocessor (contd) when the usb interface is used, data transfer is typically controlled by a host computer. the st7 core can also read from and write to the data buffer of the dtc. typically, the st7 controls the application when the usb not used (autono- mous mode). the buffer can potentially be ac- cessed by any one of three requestors, the st7, the dtc and the usb. mastership of the buffer is not time limited. while a master is accessing the buffer, other requests will not be acknowleged until the buffer is freed by the master. if several re- quests are pending, when the buffer is free it is granted to the source with the highest priority in the daisy-chain (fixed by hardware), first the st7, secondly the usb and finally the dtc. note: any access by the st7 to the buffer requires more cycles than either a dtc or usb access. for performance reasons, when the usb interface is exchanging data with the dtc, st7 accesses should be avoided if possible. 11.2.3 loading the protocol software the dtc must first be initialized by loading the protocol-specific software plug-in (provided by stmicroelectronics) into the dtc ram. to do this: 1. stop the dtc by clearing the run bit in the dtccr register 2. remove the write protection by setting the load bit in the dtccr register 3. load the (null-terminated) software plug-in in the dtc ram. 4. restore the write protection by clearing the load bit in the dtccr register the dtc is then ready for operation. 11.2.4 executing the protocol functions to execute any of the software plug-in functions follow the procedure below: 1. clear the run bit to stop the dtc 2. select the function by writing its address in the dtcpr register (refer to the separate docu- ment for address information). 3. set the init bit in the dtccr register to copy the dtcpr pointer to the dtc. 4. clear the init bit to return to idle state. 5. set the run bit to start the dtc. 11.2.5 changing the dtcpr pointer on the fly as shown in figure 39 , the pointer can be changed by writing init=1 while the dtc is running (run=1), however if the dtc is executing an in- ternal interrupt routine, there will be a delay until interrupt handling is completed. 11.2.6 low power modes figure 39. state diagram of dtc operations mode description wait no effect on dtc halt dtc halted. dtc idle pointer dtc running load dtc ram change pointer change on-the-fly init=0 init=1 load=1 load=0 run=1 run=0 init=1 init=0 run=0 init=1 load=0 run=0 init=0 load=1 run=1 init=1 load=0 run=1 init=0 load=0 run=0 init=0 load=0 1
st7265x 63/166 data transfer coprocessor (contd) 11.2.7 interrupts note : the dtc interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). 11.2.8 register description dtc control register (dtccr) read/write reset value: 0000 0000 (00h) bit 7:5 = reserved. must be left at reset value. bit 4 = erren error interrupt enable this bit is set and cleared by software. 0: error interrupt disabled 1: error interrupt enabled bit 3 = stopen stop interrupt enable this bit is set and cleared by software. 0: stop interrupt disabled 1: stop interrupt enabled bit 2 = load load enable this bit is set and cleared by software. it can only be set while run=0. 0: write access to dtc ram disabled 1: write access dtc ram enabled bit 1 = init initialization this bit is set and cleared by software. 0: do not copy dtcpr to dtc 1: copy the dtcpr pointer to dtc bit 0 = run start/stop control this bit is set and cleared by software. it can only be set while load=0. it is also cleared by hard- ware when stop=1 0: stop dtc 1: start dtc dtc status register (dtcsr) read/write reset value: 0000 0000 (00h) bit 7:2 = reserved. forced by hardware to 0. bit 1 = error error flag this bit is set by hardware and cleared by software reading this register. 0: no error event occurred 1: error event occurred (dtc is running) bit 0 = stop stop flag this bit is set by hardware and cleared by software reading this register. 0: no stop event occurred 1: stop event occurred (dtc terminated execution at the current intruction) dtc pointer register (dtcpr) write only reset value: 0000 0000 (00h) bit 7:0 = pc[7:0] pointer register. this register is written by software. it gives the ad- dress of an entry point in the protocol software that has previously been loaded in the dtc ram. note: to start executing the function, after writing this address, set the init bit. interrupt event event flag enable control bit exit from wait exit from halt error error erren yes no stop stop stopen yes no 70 000 err en stop en load init run 70 000000errorstop 70 msb lsb 1
st7265x 64/166 11.2.8.1 data transfer coprocessor (contd) table 19. dtc register map and reset values address (hex.) register label 76543210 1c dtccr 0 0 0 0 0 0 erren 0 stopen 0 load 0 init 0 run 0 1d dtcsr 0 0 0 0 0 0 0 0 0 0 0 0 error 0 stop 0 1f dtcpr msb 0000000 lsb 0 1
st7265x 65/166 11.3 usb interface (usb) 11.3.1 introduction the usb interface implements a full-speed func- tion interface between the usb and the st7 mi- crocontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and usb data buffer interface. no external com- ponents are needed apart from the external pull- up on usbdp for full speed recognition by the usb host. 11.3.2 main features n usb specification version 2.0 compliant n supports full-speed usb protocol n five endpoints (including default endpoint) n crc generation/checking, nrzi encoding/ decoding and bit-stuffing n usb suspend/resume operations n special data transfer mode with usb data buffer memory (2 x 512 bytes for upload or download) to dtc n on-chip 3.3v regulator n on-chip usb transceiver 11.3.3 functional description the block diagram in figure 40 , gives an overview of the usb interface hardware. for general information on the usb, refer to the universal serial bus specifications document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmis- sion/reception, and handshaking as required by the usb standard. it also performs frame format- ting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. data transfer to/from usb data buffer memory when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place to/from the usb data buffer. in normal con- figuration (mod[1:0] bits=00 in the ctlr register), at the end of the transaction, an interrupt is gener- ated. interrupts by reading the interrupt status register, applica- tion software can know which usb event has oc- curred. figure 40. usb block diagram cpu transceiver 3.3v voltage regulator sie endpoint buffer usb address, and interrupts usbdm usbdp usbvcc 48 mhz registers registers data busses usbgnd buffer usb data interface 1
st7265x 66/166 usb interface (contd) usb endpoint ram buffers there are five bidirectional endpoints including one control endpoint 0. endpoint 1 and endpoint 2 are counted as 4 bulk or interrupt endpoints (two in and two out). endpoint 0 and endpoint 1 are both 2 x 16 bytes in size. endpoint 2 is 2 x 64 bytes in size and can be configured to physically target different usb data buffer areas depending on the mod[1:0] bits in the ctlr register (see figure 41 , figure 42 and figure 43 ). the usb data buffer operates as a double buffer; while one 512-byte block is being read/written by the dtc, the usb interface reads/writes the other 512-byte block. the management of the data transfer is performed in upload and download mode (2 x 512 byte buff- ers for endpoint 2) by the usb data buffer manag- er. figure 41. endpoint 2 normal mode selected by (mod[1:0] bits = 00h) figure 42. endpoint 2 download mode selected by mod[1:0] bits = 10b endpoint 2 buffer out endpoint 1 buffer in endpoint 1 buffer out endpoint 0 buffer in endpoint 0 buffer out endpoint 2 buffer in 16 bytes 16 bytes 16 bytes 16 bytes 64 bytes 64 bytes 1550h 155fh 156fh 157fh 158fh 15cfh 160fh usb data usb data usb data usb data usb data 512-byte buffer as 64-byte slices 512-byte buffer as 64-byte slices 64-byte buffer 1650h 1a4fh 15cfh endpoint 2 buffer in endpoint 2 buffer out 158fh 1550h endpoint 1 buffer out endpoint 1 buffer in endpoint 0 buffer out endpoint 0 buffer in 1590h 1
st7265x 67/166 usb interface (contd) figure 43. endpoint 2 upload mode selected by mod[1:0] bits = 01b usb data usb data usb data usb data usb data 512-byte buffer as 64-byte slices 512-byte buffer as 64-byte slices 64-byte buffer 1650h 1a4fh 15cfh endpoint 2 buffer out endpoint 2 buffer in 158fh 1550h endpoint 1 buffer out endpoint 1 buffer in endpoint 0 buffer out endpoint 0 buffer in 1590h 1
st7265x 68/166 usb interface (contd) 11.3.4 usb data buffer manager the usb data buffer manager performs the data transfer between the usb interface and the two 512 bytes ram areas used for endpoint 2 in both upload and download modes. it also controls the status of endpoint 2, by setting the endpoint as nak when the current buffer is not yet available for either transmission (upload) or reception (down- load). it is based on a stand-alone hardware state-ma- chine that runs in parallel to the st7 processing flow. however, at any time, the st7 software can initialize the usb data buffer manager state-ma- chine in order to synchronize operations by writing a 1 to the clr bit in the bufcsr register. dedicated buffer status flags are defined to syn- chronize the usb data buffer manager with the data transfer coprocessor (dtc). these flags are used by the software plug-ins provided by stmicroelectronics) running on the dtc. 11.3.4.1 data transfer modes in usb normal mode (mod[1:0]=00b), the maxi- mum memory size of endpoint 2 is 64 bytes, and therefore reception of 512 bytes packets requires st7 software intervention every 64 bytes. this means that after a ctr interrupt the hardware puts the endpoint 2 status bits for the current di- rection (transmit or receive) in nak status. the st7 software must then write the status bits to valid when it is ready to transmit or receive new data. on the contrary, in upload or download mode, the physical address of endpoint 2 is automatically in- cremented every 64 bytes until a 512-byte buffer is full. toggling between the two buffers is automatically managed as soon as 512 bytes have been trans- mitted to usb (upload mode) or received from usb (download), if the next buffer is available: otherwise, the endpoint is set to invalid until a buffer has been released by the dtc. 11.3.4.2 switching back to normal mode the usb interface is reset by hardware in normal mode on reception of a packet with a length below the maximum packet size. in this case, the few bytes are received into one of the two 512-byte buffers and the st7 must process by software the data received. for this purpose, the information in- dicating which 512-byte buffer was last addressed is given to the st7 by the usb data buffer manag- er (bufnum bit in the bufcsr register), and the number of received bytes is obtained by reading the usb interface registers. with these two items of information, the st7 can determine what kind of data has been received, and what action has to be taken. 1
st7265x 69/166 usb interface (contd) figure 44. overview of usb, dtc and st7 interconnections 1650h 1850h 1a4fh 0 0 0 0 stat clr b0 stat b1 buf num 512-byte ram buffer 512-byte ram buffer data coprocessor data transfer buffer (1280 bytes) usb sie transfer (dtc) arbitration usb data buffer buffer access parameters usb ep0 usb ep1 usb ep2 bufcsr register (19h) 1550h manager dtc i/os (external devices) 1
st7265x 70/166 usb interface (contd) 11.3.5 low power modes 11.3.6 interrupts note : the usb end of suspend interrupt event is connected to a single interrupt vector (usb esusp) with the exit from halt capability (wake-up). all the other interrupt events are connected to another interrupt vector: usb interrupt (usb). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask bits (i0, i1) in cc register are reset (rim instruction). mode description wait no effect on usb. usb interrupt events cause the device to exit from wait mode. halt usb registers are frozen. in halt mode, the usb is inactive. usb operations resume when the mcu is woken up by an interrupt with exit from halt capability or by an event on the usb line in case of suspend. this event will generate an esusp interrupt which will wake-up from halt mode. interrupt event event flag enable con- trol bit exit from wait exit from halt correct transfer ctr ctrm yes no setup overrun sovr sovrm yes no error err errm yes no suspend mode request susp suspm yes no end of suspend mode. esusp esuspm yes yes usb reset reset resetm yes no start of frame sof sofm yes no 1
st7265x 71/166 usb interface (contd) 11.3.7 register description buffer control/status register (bufcsr) read only (except bit 0, read/write) reset value: 0000 0000 (00h) bits 7:4 = reserved, forced by hardware to 0. bit 3 = bufnum current usb buffer number this bit is set and cleared by hardware. when data are received by endpoint 2 in normal mode (refer to the description of the mod[1:0] bits in the ep2rxr register) it indicates which buffer con- tains the data. 0: current buffer is buffer 0 1: current buffer is buffer 1 bits 2:1 = statb[1:0] buffer status bits these bits are set and cleared by hardware. when data are transmitted or received by endpoint 2 in upload or download mode (refer to the description of the mod[1:0] bits in the ep2rxr register) the statb[1:0] bits indicate the status as follows: bit 0 = clr clear buffer status this bit is written by software to clear the buf- num and statb[1:0] bits (it also resets the pack- et counter of the buffer manager state machine). it can be used to re-initialize the upload/download flow (refer to the description of the mod[1:0] bits in the ep2rxr register). 0: no effect 1: clear bufnum and statb[1:0] bits interrupt status register (istr) read/write reset value: 0000 0000 (00h) these bits cannot be set by software. when an in- terrupt occurs these bits are set by hardware. soft- ware must read them to determine the interrupt type and clear them after servicing. note: the ctr bit (which is an or of all the end- point ctr flags) cannot be cleared directly, only by clearing the ctr flags in the endpoint regis- ters. bit 7 = ctr correct transfer . this bit is set by hardware when a correct transfer operation is performed. this bit is an or of all ctr flags (ctr0 in the ep0r register and ctr_rx and ctr_tx in the epnr registers). by looking in the usbsr register, the type of transfer can be determined from the pid[1:0] bits for end- point 0. for the other endpoints, the endpoint number on which the transfer was made is identi- fied by the ep[1:0] bits and the type of transfer by the in/out bit. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack handshakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. bit 6 = reserved, forced by hardware to 0. bit 5 = sovr setup overrun. this bit is set by hardware when a correct setup transfer operation is performed while the software is servicing an interrupt which occurred on the same endpoint (ctr0 bit in the ep0r register is still set when setup correct transfer occurs). 0: no setup overrun detected 1: setup overrun detected when this event occurs, the usbsr register is not updated because the only source of the sovr event is the setup token reception on the control endpoint (ep0). 70 000 0 buf- num stat b1 stat b0 clr meaning statbn value upload mode buffer n not full (usb waiting to read buffer n) 0 buffer n full (usb can upload this buffer) 1 download mode buffer n empty (can be written to by usb) 0 buffer n not empty (usb waiting to write to this buffer) 1 70 ctr 0 sovr error susp esusp reset sof 1
st7265x 72/166 usb interface (contd) bit 4 = err error . this bit is set by hardware whenever one of the er- rors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing, nonstandard framing or buffer overrun error detected note: refer to the err[2:0] bits in the usbsr register to determine the error type. bit 3 = susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb. the suspend request check is active immediately after each usb reset event and is disabled by hardware when suspend mode is forced (fsusp bit in the ctlr register) until the end of resume sequence. bit 2 = esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb in- terface up from suspend mode. this interrupt is serviced by a specific vector, in or- der to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected bit 1 = reset usb reset. this bit is set by hardware when the usb reset se- quence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0r, ep1rxr, ep1txr and ep2rxr, ep2txr registers are reset by a usb reset. bit 0 = sof start of frame. this bit is set by hardware when a sof token is re- ceived on the usb. 0: no sof received 1: sof received note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruc- tion where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read- modify-write instructions like and, xor.. interrupt mask register (imr) read/write reset value: 0000 0000 (00h) these bits are mask bits for all the interrupt condi- tion bits included in the istr register. whenever one of the imr bits is set, if the corresponding istr bit is set, and the i- bit in the cc register is cleared, an interrupt request is generated. for an explanation of each bit, please refer to the descrip- tion of the istr register. control register (ctlr) read/write reset value: 0000 0110 (06h) bit 7 = rsm resume detected this bit shows when a resume sequence has start- ed on the usb port, requesting the usb interface to wake-up from suspend state. it can be used to determine the cause of an esusp event. 0: no resume sequence detected on usb 1: resume sequence detected on usb bit 6 = usb_rst usb reset detected . this bit shows that a reset sequence has started on the usb. it can be used to determine the cause of an esusp event (reset sequence). 0: no reset sequence detected on usb 1: reset sequence detected on usb bits 5:4 reserved, forced by hardware to 0. bit 3 = resume resume . this bit is set by software to wake-up the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. 70 ctrm 0 sovr m errm susp m esusp m reset m sofm 70 rsm usb_ rst 00 resu me pdwn fsusp fres 1
st7265x 73/166 usb interface (contd) bit 2 = pdwn power down . this bit is set by software to turn off the 3.3v on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, soft- ware should allow at least 3 m s for stabilisation of the power supply before using the usb interface. bit 1 = fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be put in halt mode to reduce power consumption. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it resets this bit (it can also be reset by software). bit 0 = fres force reset. this bit is set by software to force a reset of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb interface is held in reset state until software clears this bit, at which point a usb-re- set interrupt will be generated if enabled. device address register (daddr) read/write reset value: 0000 0000 (00h) bit 7 reserved, forced by hardware to 0. bits 6:0 = add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received or forced through bit fres in the ctlr register. usb status register (usbsr) read only reset value: 0000 0000 (00h) bits 7:6 = pid[1:0] token pid bits 1 & 0 for end- point 0 control . usb token pids are encoded in four bits. pid[1:0] correspond to the most significant bits of the pid field of the last token pid received by endpoint 0. note: the least significant pid bits have a fixed value of 01. when a ctr interrupt occurs on endpoint 0 (see register istr) the software should read the pid[1:0] bits to retrieve the pid name of the token received. the usb specification defines pid bits as: bit 5 = in/out last transaction direction for end- point 1 or 2. this bit is set by hardware when a ctr interrupt occurs on endpoint 1 or endpoint 2. 0: out transaction 1: in transaction bits 4:3 = ep[1:0] endpoint number. these bits identify the endpoint which required at- tention. 00 = endpoint 0 01 = endpoint 1 10 = endpoint 2 70 0 add6add5add4add3add2add1add0 70 pid1 pid0 in/ out ep1 ep0 err2 err1 err0 pid1 pid0 pid name 0 0 out 10 in 1 1 setup 1
st7265x 74/166 usb interface (contd) bits 2:0 = err[2:0] error type . these bits identify the type of error which oc- curred: note: these bits are set by hardware when an er- ror interrupt occurs and are reset automatically when the error bit (istr bit 4) is cleared by soft- ware. endpoint 0 register (ep0r) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 0. bits 6:4 and bits 2:0 are also reset by a usb reset, ei- ther received from the usb or forced through the fres bit in ctlr. bit 7 = ctr0 correct transfer . this bit is set by hardware when a correct transfer operation is performed on endpoint 0. this bit must be cleared after the corresponding interrupt has been serviced. 0: no ctr on endpoint 0 1: correct transfer on endpoint 0 bit 6 = dtog_tx data toggle, for transmission transfers . it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware on recep- tion of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dtog_rx are normally updated by hardware, on receipt of a relevant pid. they can be also written by the user, both for testing purposes and to force a specific (data0 or data1) token. bits 5:4 = stat_tx [1:0] status bits, for transmis- sion transfers . these bits contain the information about the end- point status, as listed below: table 20. transmission status encoding these bits are written by software. hardware sets the stat_tx and stat_rx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint; this allows software to prepare the next set of data to be transmitted. bit 3 = reserved, forced by hardware to 0. bit 2 = dtog_rx data toggle, for reception transfers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by hardware in the first stage (setup stage) of a control transfer (setup trans- actions start always with data0 pid). the receiv- er toggles dtog_rx only if it receives a correct data packet and the packets data pid matches the receiver sequence bit. err2 err1 err0 meaning 0 0 0 no error 0 0 1 bitstuffing error 0 1 0 crc error 011 eop error (unexpected end of packet or se0 not followed by j-state) 100 pid error (pid encoding error, unexpected or unknown pid) 101 memory over / underrun (mem- ory controller has not an- swered in time to a memory data request) 111 other error (wrong packet, timeout error) 70 ctr0 dtog _tx stat_ tx1 stat_ tx0 0 dtog _rx stat_ rx1 stat_ rx0 stat_tx1 stat_tx0 meaning 00 disabled: no function can be executed on this endpoint and messages related to this end- point are ignored. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is enabled (if an address match occurs, the usb interface handles the transaction). 1
st7265x 75/166 usb interface (contd) bits 1:0 = stat_rx [1:0] status bits, for reception transfers . these bits contain the information about the end- point status, as listed below: table 21. reception status encoding these bits are written by software. hardware sets the stat_rx and stat_tx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint, so the software has the time to ex- amine the received data before acknowledging a new transaction. notes: if a setup is received while the status is other than disabled, it is acknowledged and the two directional status bits are set to nak by hardware. when a stall is answered by the usb device, the two directional status bits are set to stall by hardware. endpoint 1 reception register (ep1rxr) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 1 re- ception. bits 2:0 are also reset by a usb reset, ei- ther received from the usb or forced through the fres bit in the ctlr register. bits 7:4 reserved, forced by hardware to 0. bit 3 = ctr_rx correct reception transfer . this bit is set by hardware when a correct transfer operation is performed in reception. this bit must be cleared after the corresponding interrupt has been serviced. bit 2 = dtog_rx data toggle, for reception transfers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. the receiver toggles dtog_rx only if it receives a correct data packet and the packets data pid matches the receiver sequence bit. bits 1:0 = stat_rx [1:0] status bits, for reception transfers . these bits contain the information about the end- point status, as listed below: table 22. reception status encoding : these bits are written by software, but hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. stat_rx1 stat_rx0 meaning 00 disabled: no function can be executed on this endpoint and messages related to this end- point are ignored. 01 stall: the endpoint is stalled and all reception requests re- sult in a stall handshake. 10 nak : the endpoint is naked and all reception requests re- sult in a nak handshake. 11 valid : this endpoint is ena- bled (if an address match oc- curs, the usb interface handles the transaction). 70 0000 ctr_r x dtog _rx stat_ rx1 stat_ rx0 stat_rx1 stat_rx0 meaning 00 disabled: reception trans- fers cannot be executed. 01 stall: the endpoint is stalled and all reception requests re- sult in a stall handshake. 10 nak : the endpoint is naked and all reception requests re- sult in a nak handshake. 11 valid : this endpoint is ena- bled for reception. 1
st7265x 76/166 usb interface (contd) endpoint 1 transmission register (ep1txr) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 1 transmission. bits 2:0 are also reset by a usb re- set, either received from the usb or forced through the fres bit in the ctlr register. bit 3 = ctr_tx correct transmission transfer . this bit is set by hardware when a correct transfer operation is performed in transmission. this bit must be cleared after the corresponding interrupt has been serviced. 0: no ctr in transmission on endpoint 1 1: correct transfer in transmission on endpoint 1 bit 2 = dtog_tx data toggle, for transmission transfers . this bit contains the required value of the toggle bit (0=data0, 1=data1) for the next data packet. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and dtog_rx are normally updated by hardware, at the receipt of a relevant pid. they can be also written by the user, both for testing purposes and to force a specific (data0 or data1) token. bits 1:0 = stat_tx [1:0] status bits, for transmis- sion transfers . these bits contain the information about the end- point status, which is listed below table 23. transmission status encoding these bits are written by software, but hardware sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint. this allows software to prepare the next set of data to be transmitted. endpoint 2 reception register (ep2rxr) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 2 re- ception. bits 2:0 are also reset by a usb reset, ei- ther received from the usb or forced through the fres bit in the ctlr register. bits 7:6 = mod[1:0] endpoint 2 mode . these bits are set and cleared by software. they select the endpoint 2 mode (see figure 42 and figure 43 ). notes: 1. before selecting download mode, software must write the maximum packet size value (for in- stance 64) in the cnt2rxr register and write the stat_rx bits in the ep2rxr register to valid. 2. before selecting upload mode, software must write the maximum packet size value (for instance 64) in the cnt2txr register and write the stat_tx bits in the ep2txr register to nak. 70 0000 ctr_t x dtog _tx stat_ tx1 stat_ tx0 stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission. 70 mod1 mod0 0 0 ctr_r x dtog _rx stat_ rx1 stat_ rx0 mod1 mod0 mode 00 normal mode: endpoint 2 is managed by user software 01 upload mode to usb data buffer: bulk mode in under hardware control from dtc 1 10 download mode from usb data buffer: bulk mode out under hardware control to dtc 2 . 1
st7265x 77/166 usb interface (contd) download mode in transactions are managed the same way as in normal mode (by software with the help of ctr in- terrupt) but out transactions are managed by hardware. this means that no ctr interrupt is generated at the end of an out transaction and the stat_rx bits are set to valid by hardware when the buffer is ready to receive new data. this allows the 512-byte buffer to be written without software intervention. if the usb interface receives a packet which has a length lower than the maximum packet size (writ- ten in the cnt2rxr register, see note below), the usb interface switches back to normal mode and generates a ctr interrupt and the stat_rx bits of the ep2r register are set to nak by hardware as in normal mode. upload mode out transactions are managed in the same way as normal mode and in transactions are managed by hardware in the same way as out transactions in download mode. bits 5:4 reserved, forced by hardware to 0. bit 3 = ctr_rx reception correct transfer . this bit is set by hardware when a correct transfer operation is performed in reception. this bit must be cleared after that the corresponding interrupt has been serviced. bit 2 = dtog_rx data toggle, for reception transfers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. usb interface (contd) the receiver toggles dtog_rx only if it receives a correct data packet and the packets data pid matches the receiver sequence bit. bits 1:0 = stat_rx [1:0] status bits, for reception transfers . these bits contain the information about the end- point status, which is listed below: table 24. reception status encoding these bits are written by software, but hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. note : these bits are write protected in download mode (if mod[1:0] =10b in the ep2rxr register) endpoint 2 transmission register (ep2txr) read/write reset value: 0000 0000 (00h) this register is used for controlling endpoint 2 transmission. bits 2:0 are also reset by a usb re- set, either received from the usb or forced through the fres bit in the ctlr register. bit 3 = ctr_tx transmission transfer correct . this bit is set by hardware when a correct transfer operation is performed in transmission. this bit must be cleared after the corresponding interrupt has been serviced. 0: no ctr in transmission on endpoint 2 1: correct transfer in transmission on endpoint 2 stat_rx1 stat_rx0 meaning 00 disabled: reception trans- fers cannot be executed. 01 stall: the endpoint is stalled and all reception requests re- sult in a stall handshake. 10 nak : the endpoint is naked and all reception requests re- sult in a nak handshake. 11 valid : this endpoint is ena- bled for reception. 70 0000 ctr_t x dtog _tx stat_ tx1 stat_ tx0 1
st7265x 78/166 usb interface (contd) bit 2= dtog_tx data toggle, for transmission transfers . this bit contains the required value of the toggle bit (0=data0, 1=data1) for the next data packet. dtog_tx and dtog_rx are normally updated by hardware, on receipt of a relevant pid. they can be also written by the user, both for testing purposes and to force a specific (data0 or data1) token. bits 1:0 = stat_tx [1:0] status bits, for transmis- sion transfers . these bits contain the information about the end- point status, which is listed below table 25. transmission status encoding these bits are written by software, but hardware sets the stat_tx bits to nak when a correct transfer (ctr=1) addressed to this endpoint has occurred. this allows software to prepare the next set of data to be transmitted. note : these bits are write protected in upload mode (mod[1:0] =01b in the ep2rxr register) reception counter register (cnt0rxr, cnt1rxr) read/write reset value: 0000 0000 (00h) this register contains the allocated buffer size for endpoint 0 or 1 reception, setting the maximum number of bytes the related endpoint can receive with the next out (or setup for endpoint 0) transaction. at the end of a reception, the value of this register is the max size decremented by the number of bytes received (to determine the number of bytes received, the software must sub- tract the content of this register from the allocated buffer size). reception counter register (cnt2rxr) read/write reset value: 0000 0000 (00h) this register contains the allocated buffer size for endpoint 2 reception, setting the maximum number of bytes the related endpoint can receive with the next out transaction. at the end of a re- ception, the value of this register is the maximum size decremented by the number of bytes received (to determine the number of bytes received, the software must subtract the content of this register from the allocated buffer size). transmission counter register (cnt0txr, cnt1txr) read/write reset value 0000 0000 (00h) this register contains the number of bytes to be transmitted by endpoint 0 or 1 at the next in token addressed to it. transmission counter register (cnt2txr) read/write reset value 0000 0000 (00h) this register contains the number of bytes to be transmitted by endpoint 2 at the next in token ad- dressed to it. stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission. 70 0 0 0 cnt4 cnt3 cnt2 cnt1 cnt0 70 0 cnt6 cnt5 cnt4 cnt3 cnt2 cnt cnt0 70 0 0 0 cnt4 cnt3 cnt2 cnt1 cnt0 70 0 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 1
st7265x 79/166 table 26. usb register map and reset values address (hex.) register name 76543210 47 bufcsr reset value 0 0 0 0 0 0 0 0 bufnum 0 buf1st 0 buf0st 0 resetst 0 30 usbistr reset value ctr 0 0 0 sovr 0 err 0 susp 0 esusp 0 reset 0 sof 0 31 usbimr reset value ctrm 0 0 0 sovrm 0 errm 0 suspm 0 esuspm 0 resetm 0 sofm 0 32 usbctlr reset value rsm 0 usb_rst 0 00 resume 0 pdwn 1 fsusp 1 fres 0 33 daddr reset value 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 34 usbsr reset value pid1 0 pid0 0 in /out 0 ep1 0 ep0 0 err2 0 err1 0 err0 0 35 ep0r reset value ctr0 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 0 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 36 cnt0rxr reset value 0 0 0 0 0 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 37 cnt0txr reset value 0 0 0 0 0 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 38 ep1rxr reset value 00 0 0 ctr_rx 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 39 cnt1rxr reset value 0 0 0 0 0 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 3a ep1txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 3b cnt1txr reset value 0 0 0 0 0 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 3c ep2rxr reset value mod1 0 mod0 0 00 ctr_rx 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 3d cnt2rxr reset value 0 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 3e ep2txr reset value 00 0 0 ctr_tx 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 3f cnt2txr reset value 0 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 1
st7265x 80/166 11.4 16-bit timer 11.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. 11.4.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n output compare functions with C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n 2 alternate functions on i/o ports (ocmp1, ocmp2) the block diagram is shown in figure 45 . 11.4.3 functional description 11.4.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): C counter high register (chr) is the most sig- nificant byte (ms byte). C counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) C alternate counter high register (achr) is the most significant byte (ms byte). C alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 27 clock control bits . the value in the counter register re- peats every 131.072, 262.144 or 524.288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. 1
st7265x 81/166 16-bit timer (contd) figure 45. timer block diagram mcu-peripheral interface counter alternate output compare register output compare overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 f cpu timer interrupt 0 0 0 0 0 ocf2 ocf1 tof 0 oc1e 0 0 cc0 cc1 oc2e 0 folv2 0 olvl1 0 olvl2 folv1 ocie toie latch2 ocmp2 8 8 low 16 8 high 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 8 8 8 high low high low exedg timer internal bus circuit 1 output compare register 2 cc[1:0] counter pin pin register register 1
st7265x 82/166 16-bit timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set and C i bits of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte 1
st7265x 83/166 16-bit timer (contd) figure 46. counter timing diagram, internal clock divided by 2 figure 47. counter timing diagram, internal clock divided by 4 figure 48. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st7265x 84/166 16-bit timer (contd) 11.4.3.2 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the ocie bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. C select the timer clock (cc[1:0]) (see table 27 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). C a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bits are cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 27 clock control bits ) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * f cpu presc d oc i r = d t * f ext
st7265x 85/166 16-bit timer (contd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 50 on page 86 ). when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure on page 86 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new timeout period. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. figure 49. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1
st7265x 86/166 16-bit timer (contd) figure 50. output compare timing diagram, f timer =f cpu /2 figure 51. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i )
st7265x 87/166 16-bit timer (contd) 11.4.4 low power modes 11.4.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask bits in the cc register are reset (rim instruction). mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with exit from halt mode capability or from the counter reset value when the mcu is woken up by a reset. interrupt event event flag enable control bit exit from wait exit from halt output compare 1 event ocf1 ocie yes no output compare 2 event ocf2 yes no timer overflow event tof toie yes no
st7265x 88/166 16-bit timer (contd) 11.4.6 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (tcr1) read/write reset value: 0000 0000 (00h) bit 7 = reserved, forced by hardware to 0. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. bit 1 = reserved, forced by hardware to 0. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 0 ocie toie folv2 folv1 olvl2 0 olvl1
st7265x 89/166 16-bit timer (contd) control register 2 (tcr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode). whatever the value of the oc1e bit, the internal output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the internal output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bits 5:4 = reserved, forced by hardware to 0. bits 3:2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 27. clock control bits bits 1:0 = reserved, forced by hardware to 0. status register (tsr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = reserved, forced by hardware to 0. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = reserved, forced by hardware to 0. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bits 2:0 = reserved, forced by hardware to 0. 70 oc1e oc2e 0 0 cc1 cc0 0 0 timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 reserved 1 1 70 0 ocf1 tof 0 ocf2 0 0 0
st7265x 90/166 16-bit timer (contd) output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st7265x 91/166 16-bit timer (contd) table 28. 16-bit timer register map and reset values address (hex.) register name 76543210 20 tcr1 reset value 0 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 0 0 olvl1 0 21 tcr2 reset value oc1e 0 oc2e 0 0 0 0 0 cc1 0 cc0 0 0 0 0 0 22 tsr reset value 0 0 ocf1 0 tof 0 0 0 ocf2 0 0 0 0 0 0 0 23 chr reset value msb 1111111 lsb 1 24 clr reset value msb 1111110 lsb 0 25 achr reset value msb 1111111 lsb 1 26 aclr reset value msb 1111110 lsb 0 27 oc1hr reset value msb 1000000 lsb 0 28 oc1lr reset value msb 0000000 lsb 0 29 oc2hr reset value msb 1000000 lsb 0 2a oc2lr reset value msb 0000000 lsb 0
st7265x 92/166 11.5 pwm/brm generator (dac) 11.5.1 introduction this pwm/brm peripheral includes a 6-bit pulse width modulator (pwm) and a 4-bit binary rate multiplier (brm) generator. it allows the digital to analog conversion (dac) when used with external filtering. note: the number of pwm and brm channels available depends on the device. refer to the de- vice pin description and register map. 11.5.2 main features n fixed frequency: f cpu /64 n resolution: t cpu n steps of v dd /2 10 (5mv if v dd =5v) 11.5.3 functional description the 10 bits of the 10-bit pwm/brm are distributed as 6 pwm bits and 4 brm bits. the generator con- sists of a 10-bit counter (common for all channels), a comparator and the pwm/brm generation logic. pwm generation the counter increments continuously, clocked at internal cpu clock. whenever the 6 least signifi- cant bits of the counter (defined as the pwm coun- ter) overflow, the output level for all active chan- nels is set. the state of the pwm counter is continuously compared to the pwm binary weight for each channel, as defined in the relevant pwm register, and when a match occurs the output level for that channel is reset. this pulse width modulated signal must be fil- tered, using an external rc network placed as close as possible to the associated pin. this pro- vides an analog voltage proportional to the aver- age charge passed to the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc net- work should be selected for the filtering level re- quired for control of the system variable. each output may individually have its polarity in- verted by software, and can also be used as a log- ical output. figure 52. pwm generation counter 63 compare value overflow overflow overflow 000 t pwm output t t cpu x 64
st7265x 93/166 pwm/brm generator (contd) pwm/brm outputs the pwm/brm outputs are assigned to dedicated pins. the pwm/brm outputs can be connected to an rc filter (see figure 53 for an example). the rc filter time must be higher than t cpu x64. figure 53. typical pwm output filter table 29. 6-bit pwm ripple after filtering with rc filter (r=1k w ), f cpu = 8 mhz v dd = 5v pwm duty cycle 50% r=r ext note : after a reset these pins are tied low by de- fault and are not in a high impedance state. figure 54. pwm simplified voltage output after filtering c ext output voltage stage output r ext cext (f) v ripple (mv) 0.128 78 1.28 7.8 12.8 0.78 v dd 0v 0v dd v v ripple (mv) v outavg "charge" "discharge" "charge" "discharge" 0v v v 0v outavg v (mv) ripple v "charge" "discharge" "charge" "discharge" pwmout dd dd pwmout output voltage output voltage
st7265x 94/166 pwm/brm generator (contd) brm generation the brm bits allow the addition of a pulse to wid- en a standard pwm pulse for specific pwm cy- cles. this has the effect of fine-tuning the pwm duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. the incremental pulses (with duration of t cpu ) are added to the beginning of the original pwm pulse. the pwm intervals which are added to are speci- fied in the 4-bit brm register and are encoded as shown in the following table. the brm values shown may be combined together to provide a summation of the incremental pulse intervals specified. the pulse increment corresponds to the pwm res- olution. for example,if C data 18h is written to the pwm register C data 06h (00000110b) is written to the brm reg- ister C with a 8mhz internal clock (125ns resolution) then 3.0 m s-long pulse will be output at 8 m s inter- vals, except for cycles numbered 2,4,6,10,12,14, where the pulse is broadened to 3.125 m s. note. if 00h is written to both pwm and brm reg- isters, the generator output will remain at 0. con- versely, if both registers hold data 3fh and 0fh, respectively, the output will remain at 1 for all in- tervals 1 to 15, but it will return to zero at interval 0 for an amount of time corresponding to the pwm resolution (t cpu ). an output can be set to a continuous 1 level by clearing the pwm and brm values and setting pol = 1 (inverted polarity) in the pwm register. this allows a pwm/brm channel to be used as an additional i/o pin if the dac function is not re- quired. table 30. bit brm added pulse intervals (interval #0 not selected). figure 55. brm pulse addition (pwm > 0) brm 4 - bit data incremental pulse intervals 0000 none 0001 i = 8 0010 i = 4,12 0100 i = 2,6,10,14 1000 i = 1,3,5,7,9,11,13,15 t cpu x 64 t cpu x 64 t cpu x 64 t cpu x 64 increment m = 1 m = 0 m = 2 t cpu x 64 m = 15
st7265x 95/166 pwm/brm generator (contd) figure 56. simplified filtered voltage output schematic with brm added figure 57. graphical representation of 4-bit brm added pulse positions vdd pwmout 0v vdd output voltage 0v brm = 1 brm = 0 t cpu brm extended pulse = = 0100 bit2=1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwm pulse number (0-15) brm value 0001 bit0=1 0010 bit1=1 1000 bit3=1 examples 0110 1111
st7265x 96/166 pwm/brm generator (contd) figure 58. precision for pwm/brm tuning for vouteff (after filtering) 11.5.4 register description on a channel basis, the 10 bits are separated into two data registers: note: the number of pwm and brm channels available depends on the device. refer to the de- vice pin description and register map. pulse binary weight registers (pwmi) read / write reset value 1000 0000 (80h) bit 7 = reserved (forced by hardware to 1) bit 6 = pol polarity bit for channel i. 0: the channel i outputs a 1 level during the bina- ry pulse and a 0 level after. 1: the channel i outputs a 0 level during the bina- ry pulse and a 1 level after. bit 5:0 = p[5:0] pwm pulse binary weight for channel i. this register contains the binary value of the pulse. brm registers read / write reset value: 0000 0000 (00h) these registers define the intervals where an in- cremental pulse is added to the beginning of the original pwm pulse. two brm channel values share the same register. bit 7:4 = b[7:4] brm bits (channel i+1). bit 3:0 = b[3:0] brm bits (channel i) note: from the programmer's point of view, the pwm and brm registers can be regarded as be- ing combined to give one data value. for example : effective (with external rc filtering) dac value 70 1 pol p5 p4 p3 p2 p1 p0 70 b7 b6 b5 b4 b3 b2 b1 b0 1polpppppp+bbbb 1polppppppbbbb
st7265x 97/166 pulse width modulation ( contd) table 31. pwm register map and reset values address (hex.) register name 76543210 4d pwm0 reset value 1 1 pol 0 p5 0 p4 0 p3 0 p2 0 p1 0 p0 0 4e brm10 reset value b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 4f pwm1 reset value 1 1 pol 0 p5 0 p4 0 p3 0 p2 0 p1 0 p0 0
st7265x 98/166 11.6 serial peripheral interface (spi) 11.6.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves however the spi interface can not be a master in a multi-master system. 11.6.2 main features n full duplex synchronous transfers (on 3 lines) n simplex synchronous transfers (on 2 lines) n master or slave operation n six master mode frequencies (f cpu /2 max.) n f cpu /2 max. slave mode frequency n ss management by software or hardware n programmable clock polarity and phase n end of transfer interrupt flag n write collision, master mode fault and overrun flags 11.6.3 general description figure 59 shows the serial peripheral interface (spi) block diagram. there are 3 registers: C spi control register (spicr) C spi control/status register (spicsr) C spi data register (spidr) the spi is connected to external devices through 3 pins: C miso: master in / slave out data C mosi: master out / slave in data C sck: serial clock out by spi masters and in- put by spi slaves Css : slave select: this input signal acts as a chip select to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master mcu. figure 59. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0
st7265x 99/166 serial peripheral interface (contd) 11.6.3.1 functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 60 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this implies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 63 ) but master and slave must be programmed with the same timing mode. figure 60. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software
st7265x 100/166 serial peripheral interface (contd) 11.6.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 62 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: Css internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 61 ): if cpha=1 (data latched on 2nd clock edge): Css internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): Css internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 11.6.5.3 ). figure 61. generic ss timing diagram figure 62. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin
st7265x 101/166 serial peripheral interface (contd) 11.6.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following two steps in order (if the spicsr register is not written first, the spicr register setting may be not taken into account): 1. write to the spicsr register: C select the clock frequency by configuring the spr[2:0] bits. C select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 63 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. C either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 2. write to the spicr register: C set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 11.6.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 11.6.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: C select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 63 ). note: the slave must have the same cpol and cpha settings as the master. C manage the ss pin as described in section 11.6.3.2 and figure 61 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to e nable the spi i/o functions. 11.6.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 11.6.5.2 ).
st7265x 102/166 serial peripheral interface (contd) 11.6.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 63 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 63 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 63. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0)
st7265x 103/166 serial peripheral interface (contd) 11.6.5 error flags 11.6.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: C the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. C the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de- fault state. 11.6.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: C the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 11.6.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 11.6.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 64 ). figure 64. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result
st7265x 104/166 serial peripheral interface (contd) 11.6.5.4 single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 65 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. figure 65. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
st7265x 105/166 serial peripheral interface (contd) 11.6.6 low power modes 11.6.6.1 using the spi to wakeup the mcu from halt mode in slave configuration, the spi is able to wakeup the st7 device from halt mode through a spif interrupt. the data received is subsequently read from the spidr register when the software is run- ning (interrupt vector fetch). if multiple data trans- fers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the st7 from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the st7 enters halt mode. so if slave selec- tion is configured as external (see section 11.6.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 11.6.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the mcu is woken up by an interrupt with exit from halt mode ca- pability. the data received is subsequently read from the spidr register when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no
st7265x 106/166 serial peripheral interface (contd) 11.6.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1, modf=1 or ovr=1 in the spicsr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.6.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initially connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 32 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.6.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 32. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /2 1 0 0 f cpu /4 0 0 0 f cpu /8 0 0 1 f cpu /16 1 1 0 f cpu /32 0 1 0 f cpu /64 0 1 1
st7265x 107/166 serial peripheral interface (contd) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision status (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 64 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 11.6.5.2 ). an interrupt is generated if spie = 1 in spicsr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 11.6.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicsr register. this bit is cleared by a software sequence (an ac- cess to the spicsr register while modf=1 fol- lowed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 11.6.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a chip select by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will initiate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 59 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0
st7265x 108/166 serial peripheral interface (contd) table 33. spi register map and reset values address (hex.) register label 76543210 19 spidr reset value msb xxxxxxx lsb x 1a spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 1b spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0
st7265x 109/166 11.7 i2c single master bus interface (i2c) 11.7.1 introduction the i 2 c bus interface serves as an interface be- tween the microcontroller and the serial i 2 c bus. it provides single master functions, and controls all i 2 c bus-specific sequencing, protocol and timing. it supports fast i2c mode (400khz). 11.7.2 main features C parallel bus /i 2 c protocol converter C interrupt generation C standard i 2 c mode/fast i 2 c mode C 7-bit addressing n i 2 c single master mode C end of byte transmission flag C transmitter/receiver flag C clock generation 11.7.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i 2 c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i 2 c bus and a fast i 2 c bus. this selection is made by soft- ware. mode selection the interface can operate in the two following mo- des: C master transmitter/receiver by default, it is idle. the interface automatically switches from idle to master after it generates a start condition and from master to idle after it generates a stop con- dition. communication flow the interface initiates a data transfer and genera- tes the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are gene- rated by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condi- tion is the address byte. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to fig- ure 66 . figure 66. i 2 c bus protocol scl sda 12 8 9 msb ack stop start condition condition vr02119b
st7265x 110/166 i2c single master bus interface (contd) acknowledge may be enabled and disabled by software. the speed of the i 2 c interface may be selected between standard (0-100khz) and fast i 2 c (100- 400khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a pro- grammable clock divider which depends on the i 2 c bus mode. when the i2c cell is enabled, the sda and scl ports must be configured as floating open-drain output or floating input. in this case, the value of the external pull-up resistance used depends on the application. when the i2c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 67. i 2 c interface block diagram data register (dr) data shift register clock control register (ccr) status register 1 (sr1) control register (cr) sdai scli control logic status register 2 (sr2) interrupt clock control data control scl sda
st7265x 111/166 i2c single master bus interface (contd) 11.7.4 functional description (master mode) refer to the cr, sr1 and sr2 registers in section 11.7.7 . for the bit definitions. by default the i 2 c interface operates in idle mode (m/idl bit is cleared) except when it initiates a transmit or receive sequence. to switch from default idle mode to master mode a start condition generation is needed. start condition and transmit slave address setting the start bit causes the interface to switch to master mode (m/idl bit set) and genera- tes a start condition. once the start condition is sent: C the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the dr register with the slave address byte, holding the scl line low (see figure 68 transfer sequencing ev1). then the slave address byte is sent to the sda line via the internal shift register. after completion of this transfer (and acknowledge from the slave if the ack bit is set): C the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 regis- ter followed by a write in the cr register (for exam- ple set pe bit), holding the scl line low (see fi- gure 68 transfer sequencing ev2). next the master must enter receiver or transmit- ter mode. master receiver following the address transmission and after sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr regis- ter via the internal shift register. after each byte the interface generates in sequence: C acknowledge pulse if if the ack bit is set C evf and btf bits are set by hardware with an in- terrupt if the ite bit is set. then the interface waits for a read of the sr1 re- gister followed by a read of the dr register, hol- ding the scl line low (see figure 68 transfer se- quencing ev3). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to idle mode (m/idl bit clea- red). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the inter- nal shift register. the master waits for a read of the sr1 register fol- lowed by a write in the dr register, holding the scl line low (see figure 68 transfer sequencing ev4). when the acknowledge bit is received, the interface sets: C evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to gene- rate the stop condition. the interface goes auto- matically back to idle mode (m/idl bit cleared). error case C af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. note : the scl line is not held low.
st7265x 112/166 i2c single master bus interface (contd) figure 68. transfer sequencing legend: s=start, p=stop, a=acknowledge, na=non-acknowledge evx=event (with interrupt if ite=1) ev1: evf=1, sb=1, cleared by reading sr1 register followed by writing dr register. ev2: evf=1, cleared by reading sr1 register followed by writing cr register (for example pe=1). ev3: evf=1, btf=1, cleared by reading sr1 register followed by reading dr register. ev4: evf=1, btf=1, cleared by reading sr1 register followed by writing dr register. m aster rece i ver: master transmitter: s address a data1 a data2 a ..... datan na p ev1 ev2 ev3 ev3 ev3 s address a data1 a data2 a ..... datan a p ev1 ev2 ev4 ev4 ev4 ev4
st7265x 113/166 i2c single master bus interface (contd) 11.7.5 low power modes 11.7.6 interrupts figure 69. event flags and interrupt generation note : the i 2 c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bits in the cc register are reset (rim instruction). mode description wait no effect on i 2 c interface. i 2 c interrupts cause the device to exit from wait mode. halt i 2 c registers are frozen. in halt mode, the i 2 c interface is inactive and does not acknowledge data on the bus. the i 2 c interface resumes operation when the mcu is woken up by an interrupt with exit from halt mode capability. interrupt event event flag enable control bit exit from wait exit from halt end of byte transfer event btf ite yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no btf sb af evf interrupt ite * * evf can also be set by ev2 or an error from the sr2 register. *
st7265x 114/166 i2c single master bus interface (contd) 11.7.7 register description i 2 c control register (cr) read / write reset value: 0000 0000 (00h) bit 7:6 = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master capability notes: C when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0 C when pe=1, the corresponding i/o pins are se- lected by hardware as alternate functions. C to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = reserved. forced to 0 by hardware. bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). C in master mode: 0: no start generation 1: repeated start generation C in idle mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no acknowledge returned 1: acknowledge returned after a data byte is re- ceived bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disa- bled (pe=0) or when the stop condition is sent. C in master mode only: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 4 for the relationship between the events and the interrupt. scl is held low when the sb or btf flags or an ev2 event (see figure 68 ) is detected. 70 0 0 pe 0 start ack stop ite
st7265x 115/166 i2c single master bus interface (contd) i 2 c status register 1 (sr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event oc- curs. it is cleared by software reading sr2 register in case of error event or as described in figure 68 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: C btf=1 (byte received or transmitted) C sb=1 (start condition generated) C af=1 (no acknowledge received after byte transmission if ack=1) C address byte successfully transmitted. bit 6 = reserved. forced to 0 by hardware. bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware when the interface is disabled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = reserved. forced to 0 by hardware. bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr reg- ister. it is also cleared by hardware when the inter- face is disabled (pe=0). C following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev2 event (see figure 68 ). btf is cleared by reading sr1 register followed by writ- ing the next byte in dr register. C following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = reserved. forced to 0 by hardware. bit 1 = m/idl master/idle. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after generating a stop condition on the bus. it is also cleared when the interface is dis- abled (pe=0). 0: idle mode 1: master mode bit 0 = sb start bit generated. this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disa- bled (pe=0). 0: no start condition 1: start condition generated 70 evf 0 tra 0 btf 0 m/idl sb
st7265x 116/166 i2c single master bus interface (contd) i 2 c status register 2 (sr2) read only reset value: 0000 0000 (00h) bit 7:5 = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3:0 = reserved. forced to 0 by hardware. 70 000af0000
st7265x 117/166 i2c single master bus interface (contd) i 2 c clock control register (ccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i 2 c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i 2 c mode 1: fast i 2 c mode bit 6:0 = cc6-cc0 7-bit clock divider. these bits select the speed of the bus (f scl ) de- pending on the i 2 c mode. they are not cleared when the interface is disabled (pe=0). C standard mode (fm/sm=0): f scl <= 100khz f scl = f cpu /(2x([cc6..cc0]+2)) C fast mode (fm/sm=1): f scl > 100khz f scl = f cpu /(3x([cc6..cc0]+2)) note: the programmed f scl assumes no load on scl and sda lines. i 2 c data register ( dr) read / write reset value: 0000 0000 (00h) bit 7:0 = d7-d0 8-bit data register. these bits contains the byte to be received or transmitted on the bus. C transmitter mode: byte transmission start auto- matically when the software writes in the dr reg- ister. C receiver mode: the first data byte is received au- tomatically in the dr register using the least sig- nificant bit of the address. then, the next data bytes are received one by one after reading the dr register. table 34. i 2 c register map 70 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 70 d7 d6 d5 d4 d3 d2 d1 d0 address (hex.) register name 765 4 3210 40 cr reset value 0 0 pe 00 start 0 ack 0 stop 0 ite 0 41 sr1 reset value evf 00 tra 00 btf 00 m/idl 0 sb 0 42 sr2 reset value 0 0 0 af 00000 43 ccr reset value fm/sm 0 cc6 0 cc5 0 cc4 0 cc3 0 cc2 0 cc1 0 cc0 0 46 dr reset value dr7 0 dr6 0 dr5 0 dr4 0 dr3 0 dr2 0 dr1 0 dr0 0
st7265x 118/166 11.8 8-bit a/d converter (adc) 11.8.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 11.8.2 main features n 8-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 70 . 11.8.3 functional description 11.8.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. see electrical characteristics section for more de- tails. figure 70. adc block diagram ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 4 f adc f cpu hold control
st7265x 119/166 8-bit a/d converter (adc) (contd) 11.8.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.8.3.3 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 71 : n sample capacitor loading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. n a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximation cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 11.8.3.4 software procedure refer to the control/status register (csr) and data register (dr) in section 11.8.6 for the bit defini- tions and to figure 71 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =4/f cpu ). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: C select the ch[3:0] bits to assign the analog channel to be converted. adc conversion in the csr register: C set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete C the coco bit is set by hardware. C no interrupt is generated. C the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 71. adc conversion timings 11.8.4 low power modes note : the a/d converter may be disabled by reset- ting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.8.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a stabilisation time before ac- curate conversions can be performed. adccsr write adon coco bit set t load t conv operation hold control
st7265x 120/166 8-bit a/d converter (adc) (contd) 11.8.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved. must always be cleared. bits 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selec- tion varies according to the device. refer to the de- vice pinout. data register (dr) read only reset value: 0000 0000 (00h) bits 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the coco flag. 70 coco 0 adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d7 d6 d5 d4 d3 d2 d1 d0
st7265x 121/166 8-bit a/d converter (adc) (contd) table 35. adc register map and reset values address (hex.) register label 76543210 0012h adcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0013h adccsr reset value coco 00 adon 00 ch3 0 ch2 0 ch1 0 ch0 0
st7265x 122/166 12 instruction set 12.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 36. cpu addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st7265x 123/166 instruction set overview (contd) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st7265x 124/166 instruction set overview (contd) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 37. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative
st7265x 125/166 instruction set overview (contd) 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
st7265x 126/166 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
st7265x 127/166 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z
st7265x 128/166 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 s ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement is shown in figure 72 . figure 72. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 73 . figure 73. pin input voltage c l st7 pin v in st7 pin
st7265x 129/166 13.2 absolute maximum ratings stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics 13.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset , 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7265x 130/166 13.3 operating conditions 13.3.1 general operating conditions figure 74. f osc maximum operating frequency versus v dd supply voltage 1) notes: a/d operation not guaranteed below 1mhz. 1. operating conditions with t a =0 to +70c. 2. this mode is supported by all devices. 3. this mode is only supported by st72(f)651ar6t1e rom and flash devices (without lvd) 4. the 2.7v-3.0v voltage range is only supported by st72651ar6t1e rom devices (without lvd) symbol parameter conditions min max unit v dd supply voltage with usb peripheral ena- bled see figure 74 4.0 5.5 v supply voltage with usb peripheral disa- bled and lvd off (rom version) see figure 74 2.7 5.5 v supply voltage with usb peripheral disa- bled and lvd off (flash version) see figure 74 3.0 5.5 v f osc external clock frequency 12 12 mhz t a ambient temperature range 0 70 c f cpu [mhz] supply voltage [v] 8 4 2 0 2.0 2.5 3.0 3.5 4.0 4.55 5.0 functionality functionality functionality guaranteed in this area 2) not guaranteed in this area guaranteed in this area except usb cell 3) 5.5 2.7 3 see note 4
st7265x 131/166 operating conditions (contd) 13.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f osc , and t a . notes: 1. lvd typical data are based on t a =25c. they are given only as design guidelines and are not tested. 2. not tested, guaranteed by construction. 3. the v dd rise time condition is needed to insure a correct device power-on and lvd reset. not tested in production. 13.3.3 power supply manager characteristics subject to general operating conditions for v dd , f osc , and t a . not guaranteed on lvd devices (without e suffix). 1. not tested, guaranteed by construction. 13.3.4 storage device supply characteristics subject to general operating conditions for v dd , f osc , and t a . note: in stand-alone mode v ddf must be connected to v dd symbol parameter conditions min typ 1) max unit v it+ reset release threshold (v dd rise) 2.9 3.5 3.8 v v it- reset generation threshold (v dd fall) 2.6 3.1 3.5 v hys lvd voltage threshold hysteresis v it+ -v it- 150 300 mv f cutoff lvd filter cut-off frequency 2) not detected by the lvd 10 mhz. vt por v dd rise time 3) 0.3 10 ms symbol parameter conditions min typ max unit usbv it+ reset release threshold (v dd rise) 3.50 3.80 4.00 v usbv it- reset generation threshold (v dd fall) 3.30 3.65 3.80 usbv hys usb voltage threshold hysteresis usbv it+ -usbv it- 100 200 300 mv v pllmin48 minimum voltage required for stable 48mhz pll operation (pll locked) 3.7 1) v v pllmin40 minimum voltage required for 40mhz pll operation (pll un- locked) 3.4 1) v v pllmin24 minimum voltage required for 24mhz pll operation (pll un- locked) 3.0 1) v symbol parameter conditions min typ max unit v ddf voltage output for external storage device (i load max = 50ma) usb mode: vset[1:0]=11 2.5 2.8 3.2 v 10 2.9 3.3 3.6 01 3.0 3.4 3.8 00 3.1 3.5 3.9
st7265x 132/166 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 run mode figure 75. typical i dd in run vs. f cpu notes: 1. typical data are based on t a =25c, v dd =5v (4.0v v dd 5.5v range) and v dd =3.3v (2.7v v dd 4.0v range). 2. data based on characterization results, tested in production at v dd =5.5v. and f cpu = 8mhz 3. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in run mode 3) (see figure 75 ) 4.0v v dd 5.5v f cpu =8mhz 14 20 ma supply current in run mode 3) (see figure 75 ) 2.7v v dd 4.0v f cpu =3mhz 4 8 0 2 4 6 8 10 12 14 16 18 20 234567 vdd (v) idd (ma) 8 mhz 6 mhz 3 mhz
st7265x 133/166 supply current characteristics (contd) 13.4.2 wait mode figure 76. typical i dd in wait vs. f cpu notes: 1. typical data are based on t a =25c, v dd =5v (4v v dd 5.5v range) and v dd =3.3v (2.7v v dd 4.0v range). 2. data based on characterization results, tested in production at v dd = 5.5v and f cpu = 8mhz. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (osc1) driven by external square wave, lvd disabled. symbol parameter conditions typ 1) max 2) unit i wfi supply current in wait mode 3) (see figure 76 ) 4.0v v dd 5.5v f cpu =8mhz 8 11 ma supply current in wait mode 3) (see figure 76 ) 2.7v v dd 4.0v f cpu =3mhz 3 6 0 2 4 6 8 10 12 23 45 67 vdd (v) idd wfi (ma) 8 mhz 6 mhz 3 mhz
st7265x 134/166 supply current characteristics (contd) 13.4.3 halt mode notes: 1. typical data are based on t a =25c. 2. all i/o pins in input mode with a static value at v dd or v ss (no load). 13.4.4 suspend mode notes: 1. typical data are based on t a =25c. 2. external pull-up (1.5k w connected to usbv cc ) and pull-down (15k w connected to usbv ss ) current not included. 3. t a =25c symbol parameter conditions typ 1) max unit i halt supply current in halt mode 2) lvd off v dd =5.5v 3 tbd a v dd =3.0v 1 tbd lvd on v dd =5.5v 110 tbd v dd =3.0v 60 tbd symbol parameter conditions typ 1) max 3) unit i susp supply current in suspend mode 2) lvd off v dd =4-5.25v 150 230 a lvd on v dd =4-5.25v 230 300
st7265x 135/166 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 13.5.1 general timings 13.5.2 external clock source figure 77. typical application with an external clock source notes: 1. data based on typical application software. not tested in production. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2 4 12 t cpu f cpu =8mhz 250 500 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 i l oscx input leakage current v ss v in v dd 1 m a osc1 osc2 f osc external st72xxx clock source not connected internally v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10%
st7265x 136/166 13.6 memory characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. 13.6.1 ram and hardware registers 13.6.2 flash memory operating conditions: f cpu = 8 mhz. note 1: guaranteed by design. figure 78. two typical applications with v pp pin 1) note 1: when the icp mode is not required by the application, v pp pin must be tied to v ss . symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 2 v dual voltage flash memory symbol parameter conditions min typ max unit f cpu operating frequency read mode 8 mhz write / erase mode, t a =25c 8 v pp programming voltage 4.0v <= v dd <= 5.5v 11.4 12.6 v i pp v pp current write / erase 30 1) ma t prog byte programming time t a =25c 100 500 1) s t erase sector erasing time 2 10 1) sec device erasing time 5 10 1) t vpp internal v pp stabilization time 10 s t ret data retention t a 55c 20 years n rw write erase cycles t a =25c 100 cycles v pp st72xxx 10k w programming tool v pp st72xxx
st7265x 137/166 13.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). n esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb : burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 79. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested 10 m f and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter conditions neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 -1 >1.5 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dda pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 -2 2 v dd v ss 0.1 m f 10 m f v dd st72xxx v ssa v dda 0.1 m f power supply source st7 digital noise filtering external noise filtering
st7265x 138/166 emc characteristics (contd) 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/3 which specifies the board and the loading of each pin. note 1 . data based on characterization results, not tested in production. 13.7.3 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 13.7.3.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins of the device (3 parts*(n+1) supply pin). one model is simulated: human body model. this test conforms to the jesd22-a114a standard. see figure 80 and the following test se- quence. human body model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. absolute maximum ratings figure 80. typical equivalent esd circuit note 1: data based on characterization results, not tested in production. symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 3mhz 6mhz s emi peak level v dd = 5v, t a = +25c, tqfp64 package conforming to sae j 1752/3 0.1mhz to 30mhz 21 28 db m v 30mhz to 130mhz 16 30 130mhz to 1ghz 8 31 sae emi level 2 4 - symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 1500 v st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator human body model
st7265x 139/166 emc characteristics (contd) 13.7.3.2 static and dynamic latch-up n lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 81 . for more details, refer to the an1181 st7 application note. 13.7.3.3 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: C corrupted program counter C unexpected reset C critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). electrical sensitivities figure 81. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c t a = +125c a a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a r ch =50m w r d =330 w c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st7 v dd v ss
st7265x 140/166 emc characteristics (contd) 13.7.4 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 82 and figure 83 for standard pins and in figure 84 and figure 85 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: C a diode to v dd (3a) and a diode from v ss (3b) C a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: C a resistor in series with the pad (1) C a diode to v dd (2a) and a diode from v ss (2b) C a protection device between v dd and v ss (4) figure 82. positive stress on a standard pad vs. v ss figure 83. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path
st7265x 141/166 emc characteristics (contd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completely absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss , v ssa , ...) and power supply (v dd , v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 86 is implemented to protect the device against esd. figure 84. positive stress on a true open drain pad vs. v ss figure 85. negative stress on a true open drain pad vs. v dd figure 86. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v dda v ssa v dda v dd v ss back to back diode between grounds v ssa
st7265x 142/166 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. . notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure ). data based on design simulation and/or technology characteristics, not tested in production. 5. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 89 ). this data is based on characterization results, tested in production at v dd =5v. 6. data based on characterization results, not tested in production. 7. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. figure 87two typical applications with unused i/o pin symbol parameter conditions min typ 1) max unit v il input low level voltage v dd = 5.0v v ss 0.3xv dd v v ih input high level voltage v dd = 5.0v 0.7xv dd v dd v hys schmitt trigger voltage hysteresis 3) 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 4) floating input mode 200 r pu weak pull-up equivalent resistor 5) v in = v ss v dd =5v 70 100 130 k w v dd =3v 130 200 260 c io i/o pin capacitance 6) 5pf t f(io)out output high to low level fall time 6) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 6) 25 t w(it)in external interrupt pulse time 7) 1t cpu 10k w unused i/o port st72xxx 10k w unused i/o port st72xxx v dd
st7265x 143/166 . i/o port pin characteristics (contd) figure 88. v il and v ih vs. v dd with v in =v ss figure 89. typical i pu vs. v dd with v in =v ss figure 90. typical r pu vs. v dd with v in =v ss 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 5.5 6 vdd (v) vil and vih(v) vih vil -90 -80 -70 -60 -50 -40 -30 -20 -10 0 234567 vdd (v) ipu (a) 0 50 100 150 200 250 300 234567 vdd (v) rpu (kohms)
st7265x 144/166 i/o port pin characteristics (contd) 13.8.2 output driving current subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 91. typical v ol at v dd =5v (standard) figure 92typical v dd -v oh at v dd =5v figure 93. typical v ol at v dd =5v (high-sink) notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 91 and figure 94 ) v dd =5v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 93 and figure 95 ) i io =+20ma 1.3 i io =+8ma 0.6 v oh 2) output high level voltage for an i/o pin when 8 pins are sourced at same time (see figure 92 and figure 96 ) i io =-5ma v dd -1.4 i io =-2ma v dd -0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 01234567 iol (ma) vol (v) 0 0.2 0.4 0.6 0.8 1 1.2 01234567 -ioh (ma) vdd-voh (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5 10 15 20 25 30 iol (ma) vol (v)
st7265x 145/166 i/o port pin characteristics (contd) figure 94.typical v ol vs. v dd (standard i/os) figure 95. typical v ol vs. v dd (high-sink i/os) figure 96. typical v oh vs. v dd 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 234567 vdd (v) vol (v) at lio=2ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 234567 vdd (v) vol (v) at lio=5ma 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 234567 vdd (v) vol (v) at lio=20ma 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 234567 vdd (v) vol (v) at lio=8ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 234567 vdd (v) vdd-voh (v) at lio=2ma 0 0.5 1 1.5 2 2.5 3 234567 vdd (v) vdd-voh (v) at lio=5ma
st7265x 146/166 13.9 control pin characteristics 13.9.1 asynchronous reset pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 97. typical application with reset pin 8) notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the i io current sunk must always respect the absolute maximum rating specified in section 13.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . not tested in production. 5. the r on pull-up equivalent resistor is based on a resistive transistor (corresponding i on current characteristics de- scribed in figure 97 ). this data is based on characterization results, not tested in production. 6. all short pulse applied on reset pin with a duration below t h(rstl)in can be ignored. 7. the reset network protects the device against parasitic resets, especially in a noisy environment. 8. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). symbol parameter conditions min typ 1) max unit v il input low level voltage 2) v dd =5v v ss 0.3xv dd v v ih input high level voltage 2) v dd =5v 0.7xv dd v dd v hys schmitt trigger voltage hysteresis 3) 400 mv v ol output low level voltage 4) v dd =5v i io =+5ma 0.68 0.95 v i io =+2ma 0.28 0.45 r on weak pull-up equivalent resistor 5) v in = v ss v dd =5v 70 100 130 k w v dd =3.3v 130 200 260 t w(rstl)out generated reset pulse duration external pin or internal reset sources 4 1/f sfosc t h(rstl)in external reset pulse hold time 6) 20 m s t g(rstl)in filtered glitch duration 7) 100 ns reset v dd watchdog reset st72xxx lvd reset internal r on 0.1 m f v dd 0.1 m f v dd 4.7k w external reset circuit 8) reset control optional
st7265x 147/166 control pin characteristics (contd) 13.9.2 v pp pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 98. two typical applications with v pp pin 2) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. when the icp mode is not required by the application, v pp pin must be tied to v ss . symbol parameter conditions min max unit v il input low level voltage 1) v ss 0.2 v v ih input high level voltage 1) v dd -0.1 12.6 i l input leakage current v in =v ss 1 m a v pp st72xxx 10k w programming tool v pp st72xxx
st7265x 148/166 13.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 13.10.1 watchdog timer 13.10.2 pwm generator symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 65,536 4,194,304 t cpu f cpu =8mhz 8.192 524.288 ms symbol parameter conditions min typ max unit t repetition rate t cpu =125ns - 125 - khz res resolution t cpu =125ns - 125 - ns s output step v dd =5v - 5 - mv
st7265x 149/166 13.11 communication interface characteristics 13.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 99. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in
st7265x 150/166 communication interface characteristics (contd) figure 100. spi slave timing diagram with cpha=1 1) figure 101. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck)
st7265x 151/166 communication interface characteristics (contd) 13.11.2 i 2 c - inter ic control interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. figure 102. typical application with i 2 c bus and timing diagram 4) notes: 1. data based on standard i 2 c protocol requirement, not tested in production. 2. the device must internally provide a hold time of at least 300ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 4. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter standard mode i 2 c fast mode i 2 c unit min 1) max 1) min 1) max 1) t w(scll) scl clock low time 4.7 1.3 m s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3) 0 2) 900 3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 0.6 m s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 ns t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 ms c b capacitive load for each bus line 400 400 pf repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k w sdai st72xxx scli v dd 100 w 100 w v dd 4.7k w i 2 cbus
st7265x 152/166 communication interface characteristics (contd) 13.11.3 i 2 c - inter ic control interface 1) the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl 2) the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal cb = total capacitance of one bus line in pf i 2 c-bus timings parameter standard i 2 c fast i 2 c symbol unit min max min max bus free time between a stop and start con- dition 4.7 1.3 t buf ms hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 t hd:sta m s low period of the scl clock 4.7 1.3 t low m s high period of the scl clock 4.0 0.6 t high m s set-up time for a repeated start condition 4.7 0.6 t su:sta m s data hold time 0 (1) 0 (1) 0.9(2) t hd:dat ns data set-up time 250 100 t su:dat ns rise time of both sda and scl signals 1000 20+0.1cb 300 t r ns fall time of both sda and scl signals 300 20+0.1cb 300 tf ns set-up time for stop condition 4.0 0.6 t su : sto ns capacitive load for each bus line 400 400 cb pf
st7265x 153/166 communication interface characteristics (contd) 13.11.4 usb - universal bus interface note 1: rl is the load connected on the usb drivers. note 2: all the voltages are measured from the local ground potential. note 3: an external decoupling capacitor (typical 100nf, min 47nf) must be connected between this pin and usbv ss . figure 103. usb: data signal rise and fall time note1: measured from 10% to 90% of the data signal. for more detailed informations, please refer to chapter 7 (electrical) of the usb specification (version 1.1). usb dc electrical characteristics parameter symbol conditions min. 2) max. 2) unit input levels: differential input sensitivity vdi i(d+, d-) 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 v single ended receiver threshold vse 1.3 2.0 v output levels static output low vol rl of 1.5k ohms to 3.6v 1) 0.3 v static output high voh rl of 15k ohm to v ss 1) 2.8 3.6 v usbv cc : voltage level 3) usbv v dd =4.0v - 5.5v i load max = 3ma 3.00 3.60 v usb: full speed electrical characteristics parameter symbol conditions min max unit driver characteristics: rise time tr note 1,cl=50 pf 4 20 ns fall time tf note 1, cl=50 pf 4 20 ns rise/ fall time matching trfm tr/tf 90 110 % output signal crossover voltage vcrs 1.3 2.0 v differential data lines v ss tf tr crossover points vcrs
st7265x 154/166 13.12 8-bit adc characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 104. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refer to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion range voltage 2) v ssa v dda v r ain external input resistor 10 3) k w c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =2mhz 0 4) m s t adc conversion time (sample+hold) 6 - sample capacitor loading time - hold conversion time 4 8 1/f adc ainx st72xxx c io ~2pf v dd i l 1 m a v t 0.6v v t 0.6v v ain r ain v dda v ssa 0.1 m f v dd adc
st7265x 155/166 8-bit adc characteristics (contd) adc accuracy figure 105. adc accuracy characteristics notes: 1. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input - at 5v v dd supply, and worst case temperature. 2. data based on characterization results with t a =25c. 3. data based on characterization results over the whole temperature range, monitored in production. symbol parameter conditions ? ? v dd =5.5v, 2) f cpu =1mhz v dd =5.0v, 3) f cpu =8mhz 1) v dd =3.3v, 3) f cpu =8mhz 1) min max min max min max e t total unadjusted error 1) 2.5 2.5 2.5 e 0 offset error -0.5 1.5 -1.0 1.5 -1.0 1.5 e g gain error 1) -2.0 0 -2.0 0 -2.0 0 |e d | differential linearity error 1) 1.5 1.5 1.5 |e l | integral linearity error 1) 2.5 2.5 3.0 e o e g 1lsb ideal 1lsb ideal v dda v ssa C 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa
st7265x 156/166 14 package characteristics 14.1 package mechanical data figure 106. 48-pin thin quad flat package figure 107. 34-pin plastic small outline package, shrink 300-mil width dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 e 9.00 0.354 e1 7.00 0.276 e 0.50 0.020 q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 48 e e1 d d1 l1 l h c e b a1 a2 a dim. mm inches min typ max min typ max a 2.464 2.642 0.097 0.104 a1 0.127 0.292 0.005 0.012 b 0.356 0.483 0.014 0.019 c 0.231 0.318 0.009 0.013 d 17.72 9 18.05 9 0.698 0.711 e 7.417 7.595 0.292 0.299 e 1.016 0.040 h 10.16 0 10.41 4 0.400 0.410 h 0.635 0.737 0.025 0.029 a 0 8 0 8 l 0.610 1.016 0.024 0.040 number of pins n 34 h x 45 c l a a a1 e b d h e
st7265x 157/166 package mechanical data (contd) figure 108. 64-pin 10 x 10 thin quad flat package dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.50 0.020 k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 nd 16 ne 16 l1 l k 0.10mm .004 seating plane
st7265x 158/166 package mechanical data (contd) figure 109. recommended reflow oven profile (mid jedec) 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [c] ramp up 2c/sec for 50sec 90 sec at 125c 150 sec above 183c ramp down natural 2c/sec max tmax=220+/-5c for 25 sec
st7265x 159/166 15 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom). flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer us- ing the option bytes while the rom devices are factory-configured. 15.1 option byte the option byte allows the hardware configuration of the microcontroller to be selected. the option byte has no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program- ming tool). the default content of the flash is fixed to ffh. this means that all the options have 1 as their default value. in masked rom devices, the option byte is fixed in hardware by the rom code (see option list) opt7 = reserved. must be kept at 1. opt6 = pe5pu i/o port pe5 pull-up option this option bit determines if a pull-up is connected on port e5. 0: pull up present on pe5 1: no pull-up on pe5 when pe5pu=00: C for input, software can enable or disable the pull-up by programming peor.5 and ped- dr.5=0. C for output, the pull-up is enabled when open drain is selected by programming peor.5= and peddr.5=1. refer to the following table. opt5:4 = psmod[1:0] power supply mode these option bits configure the power supply mode. opt3 = reserved. must be kept at 1. opt2= wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt1 = usben 0: usben alternate function disabled. port f4 is free for general purpose i/o 1: usben alternate function e nabled on port f4 (function controlled by hardware) opt0= fmp_r flash memory read-out protection this option indicates if the user flash memory is protected against read-out piracy. this protection is based on read and a write protection of the memory in test modes and iap. erasing the option bytes when the fmp_r option is selected will cause the whole user memory to be erased first, and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.4 on page 22 for more details. 0: read-out protection enabled 1: read-out protection disabled 70 - pe5 pu ps mod 1 ps mod 0 - wdg sw usb en fmp_ r configuration pe5pu option peor.5 peddr.5 input floating 0 00 output open drain with pull-up 01 input with pull-up 1 0 output push pull 1 1 input floating 1 00 output open drain 0 1 input floating 1 0 output push pull 1 1 mode opt5 opt4 stand-alone mode forced 0 0 dual supply (normal) mode x 1 usb mode forced 1 0
st7265x 160/166 15.2 device ordering information and transfer of customer code customer code is made up of the rom contents. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all unused bytes must be set to ffh. the customer code should be communicated to stmicroelectronics with the correctly completed option list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 110. sales type coding rules 2) table 38. ordering information note 1. /xxx stands for the rom code name assigned by stmicroelectronics note 2. devices with e suffix have no embedded lvd st 7265 1 ar 6 t 1 e / xxx family (rom, flash, fastrom) product line (1,2,3 ...) number of pins rom size package temperature range no lvd option rom code (three letters) e= without lvd (external reset needed) 0= 25c t=thin quad flat pack 6=32k ar = 64 pins (tqfp64 (10x10)) no letter = with lvd 1= standard (0 to +70c) m=small outline package 4=16k c=48 pins l=34 pins sales type 1) 2) program memory (bytes) user ram (bytes) package operating voltage st72f651ar6t1 32k flash 5k tqfp 64 (10x10) 4.0v-5.5v st72651ar6t1/xxx 32k rom 5k st72652ar4t1/xxx 16k rom 512 st72652c4t1/xxx 16k rom 512 tqfp48 st72652l4m1/xxx 16k rom 512 so34 st72f651ar6t1e 32k flash 5k tqfp 64 (10x10) 3.0v-5.5v st72651ar6t1e/xxx 32k rom 5k 2.7v-5.5v
st7265x 161/166 st7265x microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. stmicroelectronics references: device type/memory size/package (check only one option): conditioning (check only one option): lvd option: [ ] yes [ ] no marking: [ ] standard marking [ ] special marking: tqfp64 (10 char. max): _ _ _ _ _ _ _ _ _ _ authorized characters are letters, digits, '.', '-', '/' and spaces only. please consult your local stmicroelectronics sales office for other marking details if required. pull-up on pe5: [ ] disabled [ ] enabled power supply mode: [ ] stand-alone mode [ ] dual supply mode [ ] usb mode watchdog selection: [ ] software activation [ ] hardware activation usben alternate function: [ ] disabled [ ] enabled readout protection: [ ] disabled [ ] enabled software development: [ ] stmicroelectronics [ ] customer [ ] external laboratory comments: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --------------------------------- rom device: --------------------------------- | | ---------------------------------------------------- 16k (without low voltage feature) ---------------------------------------------------- | | ------------------------------------------ 32k ------------------------------------------ tqfp64: | [ ] st72652ar4t1 | [ ] st72651ar6t1 tqfp48: | [ ] st72652c4t1 | so34: | [ ] st72652l4m1 | [ ] tray [ ] tape & reel
st7265x 162/166 15.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st, all of them connect to a pc via a parallel (lpt) or usb port: see table 39 for more details. table 39. stmicroelectronics tool features note : 1. in-application programming (iap) and in-circuit programming for flash devices. 2. these products come with a cd rom which contains the following software: C st7 assembly toolchain C stvd7 and wgdb7 powerful source level debugger for win 3.1, win 95 and nt C c compiler demo versions C st realizer for win 3.1 and win 95 C windows programming tools for win 3.1, win 95 and nt 3. tqfp64 package only. in-circuit emulation programming capability 1) sales type remarks st7 flash hds2 emulator 3) yes, powerful emulation features including trace/ logic analyzer no st7mdtu5-emu2b st7 programming board 3) no yes st7mdtu5-epb/eu st7mdtu5-epb/us 220v 110v gang programmer see 3rd party tqfp64 package c hiware compiler st7-hicross for pc hiware debugger st7-hiwave for pc
st7265x 163/166 15.4 st7 application notes identification description example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripheral registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 application to st72f264 product optimization
st7265x 164/166 an 982 using st7 with ceramic renator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1477 emulated data eeprom with xflash memory an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscil- lator programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus identification description
st7265x 165/166 16 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 2.3 added tqfp48 and so34 packages changed device summary changed section 4.4 on page 22 : and the device can be reprogrammed added added section 4.7 related documentation on page 24 changed section 7 on page 41 : removed reference to eicr register (isx bits are in the miscr1 and miscr3 registers and not in the eicr register). changed section 9.1 on page 49 : added an important note changed section 9.2.4 on page 53 : removed references to a second solution when using bit manipulation changed section 9.4 on page 54 : modified description of d[7:0] bits added text specifying that the watchdog counter is a free-running downcounter: section 11.1.2 and section 11.1.3 on page 58 added the following tables: flash register map and reset values on page 24, miscel- laneous register map and reset values on page 57 and 16-bit timer register map and reset values on page 91 added section 11.3.5 and section 11.3.6 on page 70 removed reference to pwm mode and one pulse mode in the description of olvl2 and ocie bits in section 11.4.6 on page 88 updated section 11.6.5.4 on page 104 (removed reference to multimaster system) removed reference to busy flag in section 11.7.2 on page 109 removed reference to busy bit and berr bit in table 34, i2c register map, on page 117 added section 11.7.5 and section 11.7.6 on page 113 changed section 13.3.1 on page 130 and figure 74 changed section 13.7.1 on page 137 and added section 13.7.2 on page 138 changed section 14 on page 156 updated description of option byte 0 ( section 15.1 on page 159 ) changed section 15.2 on page 160 and section 15.3 on page 162 please read carefully section 9 i/o ports june 03
st7265x 166/166 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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