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isplsi 2032ve 3.3v in-system programmable high density superfast pld 2032ve_08 1 copyright ?2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. january 2002 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com features superfast high density in-system programmable logic 1000 pld gates 32 i/o pins, two dedicated inputs 32 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic 100% functional, jedec and pinout compatible with isplsi 2032v devices 3.3v low voltage 2032 architecture interfaces with standard 5v ttl devices high performance e 2 cmos technology f max = 300 mhz maximum operating frequency t pd = 3.0 ns propagation delay electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power in-system programmable 3.3v in-system programmability using boundary scan test access port (tap) open-drain output option for flexible bus interface capability, allowing easy implementation of wired-or or bus arbitration logic increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping 100% ieee 1149.1 boundary scan testable the ease of use and fast system speed of plds with the density and flexibility of fpgas enhanced pin locking capability three dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control flexible pin placement optimized global routing pool provides global interconnectivity functional block diagram global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) a7 a6 a5 a4 input bus output routing pool (orp) a2 glb logic array dq dq dq dq 0139bisp/2000 description the isplsi 2032ve is a high density programmable logic device that can be used in both 3.3v and 5v systems. the device contains 32 registers, 32 universal i/o pins, two dedicated input pins, three dedicated clock input pins, one dedicated global oe input pin and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2032ve features in-system programmability through the boundary scan test access port (tap) and is 100% ieee 1149.1 boundary scan testable. the isplsi 2032ve offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. the basic unit of logic on the isplsi 2032ve device is the generic logic block (glb). the glbs are labeled a0, a1 .. a7 (see figure 1). there are a total of eight glbs in the isplsi 2032ve device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device.
specifications isplsi 2032ve 2 functional block diagram figure 1. isplsi 2032ve functional block diagram the device also has 32 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi- directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. device pins can be safely driven to 5 volt signal levels to support mixed-voltage systems. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by the orps. each isplsi 2032ve device contains one megablock. the grp has as its inputs the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2032ve device are selected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2032ve are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. the default configuration when the device is in bulk erased state is the totem-pole configu- ration. the open-drain/totem-pole option is selectable through the lattice design tools. global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) a7 a6 a5 a4 input bus output routing pool (orp) a2 clk 0 clk 1 clk 2 goe 0 note: *y1 and reset are multiplexed on the same pin i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 tdi/in 0 tdo/in 1 i/o 4 i/o 5 y0 y1* tck/y2 bscan tsnc be bb
specifications isplsi 2032ve 3 absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature .............................. -65 to +150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). c symbol table 2-0006/2032ve c parameter i/o capacitance 6 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 3.3v, v = 0.0v v = 3.3v, v = 0.0v cc cc i/o in c clock capacitance 10 3 pf v = 3.3v, v = 0.0v cc y t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/2032ve v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 3.0 3.0 2.0 v ?0.5 3.6 3.6 5.25 0.8 v v v v ss commercial industrial erase reprogram specifications table 2-0008a/2032ve parameter minimum maximum units erase/reprogram cycles 10,000 cycles capacitance (t a =25 c, f=1.0 mhz) dc recommended operating condition
specifications isplsi 2032ve 4 switching test conditions input pulse levels table 2-0003/2032ve input rise and fall time 10% to 90% input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. 1.5 ns output load conditions (see figure 2) dc electrical characteristics over recommended operating conditions figure 2. test load + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a/2032ve test condition r1 r2 cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 348 ? 35pf active high active low c 316 ? 348 ? 5pf 348 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004a/2032ve v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using two 16-bit counters. 3. typical values are at v = 3.3v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . 5. unused inputs at v = 0v. table 2-0007/2032ve 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4, 5 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current bscan input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma v v 5.25v 0v v v (max.) 0v v v 0v v v v = 3.3v, v = 0.5v v = 0.0v, v = 3.0v f = 1mhz ol oh in il in il in il cc out clock il ih condition min. typ. max. units 3 2.4 80 -300/-225 0.4 10 -10 10 -150 -150 -100 v v a a a a a ma ma cc il a out others ma 65 cc in cc cc (v - 0.2)v v v cc in cc
specifications isplsi 2032ve 5 use 2032ve-300 for new designs external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of 4, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. 4. -225 speed grade supersedes earlier -200. all parameters other than fmax (internal) are the same. table 2-0030a/2032ve v.0.1 1 4 3 2 1 tsu2 + tco1 ( ) description # parameter a1 data propagation delay, 4pt bypass, orp bypass ns t pd2 a2 data propagation delay ns f max a3 clock frequency with internal feedback mhz f max (ext.) ? clock frequency with external feedback mhz f max (tog.) ? clock frequency, max. toggle mhz t su1 ? glb reg. setup time before clock, 4 pt bypass ns t co1 a7 glb reg. clock to output delay, orp bypass ns t h1 ? glb reg. hold time after clock, 4 pt bypass ns t su2 ? glb reg. setup time before clock ns t co2 a1 0 glb reg. clock to output delay ns t h2 ? 1 glb reg. hold time after clock ns t r1 a1 2 ext. reset pin to output delay, orp bypass ns t rw1 ? 3 ext. reset pulse duration ns t ptoeen b1 4 input to output enable ns t ptoedis c1 5 input to output disable ns t goeen b1 6g lobal oe output enable ns t goedis c1 7g lobal oe output disable ns t wh ? 8 external synchronous clock pulse duration, high ns t wl ? 9 external synchronous clock pulse duration, low ns -225 min. max. 4.0 225 0.0 3.5 0.0 3.5 2.0 2.0 154 250 2.5 3.0 4.0 5.0 7.0 7.0 3.5 3.5 6.0 -300 min. max. 3.0 300 0.0 2.8 0.0 3.0 1.5 1.5 208 333 2.0 2.0 2.5 4.5 5.0 5.0 3.0 3.0 4.5
specifications isplsi 2032ve 6 external timing parameters over recommended operating conditions t pd1 units -135 min. test cond. 1. unless noted otherwise, all parameters use a grp load of 4, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030b/2032ve v.0.1 1 3 2 1 tsu2 + tco1 ( ) -110 min. max. max. description # parameter a1 data propagation delay, 4pt bypass, orp bypass 7.5 10.0 ns t pd2 a2 data propagation delay ns f max a3 clock frequency with internal feedback 135 111 mhz f max (ext.) ? clock frequency with external feedback mhz f max (tog.) ? clock frequency, max. toggle mhz t su1 ? glb reg. setup time before clock, 4 pt bypass ns t co1 a7 glb reg. clock to output delay, orp bypass ns t h1 ? glb reg. hold time after clock, 4 pt bypass 0.0 ns t su2 ? glb reg. setup time before clock 5.5 ns t co2 a1 0 glb reg. clock to output delay ns t h2 ? 1 glb reg. hold time after clock 0.0 ns t r1 a1 2 ext. reset pin to output delay, orp bypass ns t rw1 ? 3 ext. reset pulse duration 5.0 ns t ptoeen b1 4 input to output enable ns t ptoedis c1 5 input to output disable ns t goeen b1 6g lobal oe output enable ns t goedis c1 7g lobal oe output disable ns t wh ? 8 external synchronous clock pulse duration, high 3.0 ns t wl ? 9 external synchronous clock pulse duration, low 3.0 ns 100 167 4.0 4.5 5.5 9.0 12.0 12.0 6.0 6.0 10.0 77.0 125 5.5 0.0 7.5 0.0 6.5 4.0 4.0 13.0 5.0 6.5 12.5 14.5 14.5 7.0 7.0 -180 min. max. 5.0 180 118 200 3.0 0.0 4.0 0.0 4.0 2.5 2.5 7.5 4.0 5.0 6.0 10.0 10.0 5.0 5.0
specifications isplsi 2032ve 7 use 2032ve-300 for new designs internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/2032ve v.0.1 inputs units description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb ns global reset -225 min. max. 0.6 1.3 0.7 2.2 2.2 2.2 0.0 1.2 1.2 0.8 1.7 0.7 1.3 3.2 4.2 0.5 2.8 1.3 0.3 1.2 2.0 1.5 1.5 2.0 0.8 1.0 0.8 1.0 2.2 -300 min. max. 0.4 1.0 0.6 1.9 1.9 1.9 0.0 0.9 1.1 0.5 1.5 0.3 1.3 2.5 3.0 0.4 2.3 0.6 0.1 1.0 2.0 1.0 1.0 2.0 0.6 0.8 0.6 0.8 2.1
specifications isplsi 2032ve 8 internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/2032ve v.0.1 inputs units -135 min. -110 min. max. max. description # 2 parameter 20 input buffer delay 1.3 ns t din 21 dedicated input delay 2.5 ns t grp 22 grp delay 1.2 ns glb t 1ptxor 25 1 product term/xor path delay 5.4 ns t 20ptxor 26 20 product term/xor path delay 5.4 ns t xoradj 27 xor adjacent path delay 5.4 ns t gbp 28 glb register bypass delay 1.4 ns t gsu 29 glb register setup time before clock 1.4 ns t gh 30 glb register hold time after clock 4.1 ns t gco 31 glb register clock to output delay 1.0 ns 3 t gro 32 glb register reset to output delay 2.7 ns t ptre 33 glb product term reset to register delay 7.1 ns t ptoe 34 glb product term output enable to i/o cell delay 8.6 ns t ptck 35 glb product term clock delay 2.5 4.4 ns orp t ob 38 output buffer delay 1.8 ns t sl 39 output slew limited delay adder 2.0 ns 0.8 1.7 grp 0.9 t 4ptbpc 23 4 product term bypass path delay (combinatorial) 4.8 ns t 4ptbpr 24 4 product term bypass path delay (registered) 3.4 ns 4.4 4.4 4.4 1.0 3.9 2.9 1.1 2.9 0.9 1.8 6.1 6.9 1.7 4.1 t orp 36 orp delay 1.9 ns t orpbp 37 orp bypass delay 0.9 ns 1.5 0.5 outputs 1.4 2.0 t oen 40 i/o cell oe to output enabled 3.4 ns t odis 41 i/o cell oe to output disabled 3.4 ns 3.4 3.4 t goe 42 global output enable 3.6 ns 2.6 t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 1.7 1.8 1.8 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 1.9 2.0 2.0 ns clocks 1.7 1.9 t gr 45 global reset to glb 7.1 ns global reset 5.3 -180 min. max. 0.8 1.5 0.7 3.1 3.1 3.1 0.2 0.9 2.1 0.8 1.3 4.0 5.7 1.4 3.6 1.3 2.0 1.8 2.1 1.4 0.4 2.8 2.8 2.2 1.5 1.5 1.7 1.7 3.0
specifications isplsi 2032ve 9 isplsi 2032ve timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0 #42 #40, 41 0491/2000 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock = = = = t su 2.0ns 1.9ns 5.2ns logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.4 + 0.6 + 1.9) + (0.5) - (0.4 + 0.6 + 0.4) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.4 + 0.6 + 2.3) + (1.5) - (0.4 + 0.6 + 1.9) = = = = t co clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.4 + 0.6 + 2.3) + (0.3) + (0.6 + 1.0) table 2-0042/2032ve note: calculations are based on timing specifications for the isplsi 2032ve-300l.
specifications isplsi 2032ve 10 power consumption power consumption in the isplsi 2032ve device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127a/2032ve i cc can be estimated for the isplsi 2032ve using the following equation: for isplsi 2032ve-300 and -225: i cc (ma) = 4.5 + (# of pts * 1.29) + (# of nets * fmax * 0.0068) for isplsi 2032ve-180 and slower: i cc (ma) = 4.5 + (# of pts * 1.05) + (# of nets * fmax * 0.0068) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. notes: configuration of two 16-bit counters typical current at 3.3v, 25 c isplsi 2032ve-300 and -225 isplsi 2032ve-180 and slower 75 125 025 50 75 100 125 150 175 200 225 250 275 300 f max (mhz) i cc (ma) 150 100 25 50
specifications isplsi 2032ve 11 signal descriptions goe 0 global output enable input pin y0 dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs in the device. reset /y1 this pin performs two functions: (1) active low (0) reset pin which resets all of the registers in the device. (2) dedicated clock input. bscan input ?dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. tdi/in 0 input ?this pin performs two functions. (1) when bscan is logic low, it functions as a serial data input pin to load programming data into the device. (2) when bscan is high, it functions as a dedicated input pin. tms/nc 1 input ?this pin performs two functions. (1) when bscan is logic low, it functions as a mode control pin for the boundary scan state machine. (2) when bscan is high, this pin is not to be connected to any active signals, vcc or gnd. tdo/in 1 output/input ?this pin performs two functions. (1) when bscan is logic low, it functions as an output pin to read serial shift register data. (2) when bscan is high, it functions as a dedicated input pin. tck/y2 input ?this pin performs two functions. (1) when bscan is logic low, it functions as a clock pin for the boundary scan state machine. (2) when bscan is high, it functions as a dedicated clock input. gnd ground (gnd) vcc vcc nc 1 no connect i/o input/output pins ?these are the general purpose i/o pins used by the logic array. signal name description goe 0 40 2 43 a4 y0 5 11 5 c1 reset /y1 29 35 31 d7 bscan 7137d1 tdi/in 0 8 14 8 e2 tms/nc 1 30 36 32 c6 tdo/in 1 18 24 19 g4 tck/y2 27 33 29 e7 gnd 17, 39 1, 23 18, 42 c4, e4 vcc 6, 28 12, 34 6, 30 d3, d5 nc 1 12, 24, 36, 48 a1, a7, d4, g1, g7 signal 44-pin tqfp 44-pin plcc 48-pin tqfp 49-ball cabga 1. nc pins are not to be connected to any active signals, vcc or gnd. signal locations i/o locations signal 44-pin tqfp 44-pin plcc 48-pin tqfp 49-ball cabga i/o 0 - i/o 6 9, 10, 11, 12, 13, 14, 15 15, 16, 17, 18, 19, 20, 21 9, 10, 11, 13, 14, 15, 16 e1, f2, f1, e3, f3, g2, f4 i/o 7 - i/o 13 16, 19, 20, 21, 22, 23, 24 22, 25, 26, 27, 28, 29, 30 17, 20, 21, 22, 23, 25, 26 g3, f5, g5, f6, g6, e5, e6 i/o 14 - i/o 20 25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40, 41 27, 28, 33, 34, 35, 37, 38 f7, d6, c7, b6, b7, c5, b5 i/o 21 - i/o 27 36, 37, 38, 41, 42, 43, 44 42, 43, 44, 3, 4, 5, 6 39, 40, 41, 44, 45, 46, 47 a6, b4, a5, b3, a3, b2, a2 i/o 28 - i/o 31 1, 2, 3, 4 7, 8, 9, 10 1, 2, 3, 4 c3, c2, b1, d2
specifications isplsi 2032ve 12 pin configuration isplsi 2032ve 44-pin plcc pinout diagram (0.5in lead pitch/0.65 x 0.65in body size) pin configuration isplsi 2032ve 44-pin tqfp pinout diagram (0.8mm lead pitch/10.0 x 10.0mm body size) i/o 18 i/o 17 i/o 16 tms/nc 1 reset/y1 vcc tck/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 18 5 19 4 20 3 21 2 22 1 23 44 24 43 25 42 26 41 27 40 28 1. nc pins are not to be connected to any active signals, vcc or gnd. isplsi 2032ve top view 0123/2032ve i/o 18 i/o 17 i/o 16 tms/nc 1 reset/y1 vcc tck/y2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc bscan tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2032ve top view 1 2 3 4 6 5 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 0851/2032ve 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 2032ve 13 signal configuration isplsi 2032ve 49-ball cabga signal diagram (0.8mm lead pitch/7.0 x 7.0mm body size) 7654321 a b c d e f g a b c d e f g 7654321 i/o 21 i/o 23 i/o 25 i/o 27 nc 1 nc 1 i/o 16 i/o 18 tms/ nc 1 tck/ y2 i/o 19 i/o 29 i/o 28 y0 gnd i/o 11 i/o 9 tdo/ in1 i/o 5 i/o 7 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. i/o 14 i/o 10 i/o 8 i/o 6 i/o 4 i/o 1 i/o 2 49-bga/2032ve reset / y1 vcc vcc i/o 15 i/o 31 nc 1 i/o 13 i/o 12 i/o 3 i/o 0 tdi/ in0 goe 0 bscan i/o 22 i/o 20 i/o 17 i/o 24 i/o 26 i/o 30 nc 1 nc 1 gnd bottom view isplsi 2032ve pin configuration isplsi 2032ve 48-pin tqfp pinout diagram (0.5mm lead pitch/7.0 x 7.0mm body size) i/o 18 i/o 17 i/o 16 tms/nc 2 reset/y1 1 vcc tck/y2 1 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc bscan 1 tdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd 1 tdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2032ve top view 1 2 3 4 6 5 7 8 9 10 11 35 34 33 32 31 30 29 28 27 26 25 47 13 46 14 45 15 44 16 43 17 42 18 41 19 40 20 39 21 38 22 37 23 48tqfp/2032ve 2 nc 12 2 nc 24 nc 2 36 nc 2 48 1. pins have dual function capability. 2. nc pins are not to be connected to any active signals, v cc or gnd.
specifications isplsi 2032ve 14 part number description isplsi 2032ve ordering information device number 2032ve isplsi 2032ve ?xxx x xxx grade blank = commercial i = industrial x speed 300 = 300 mhz f max 225 = 225 mhz f max* 180 = 180 mhz f max 135 = 135 mhz f max 110 = 110 mhz f max power l = low package t44 = 44-pin tqfp t48 = 48-pin tqfp j44 = 44-pin plcc b49 = 49-ball cabga device family 0212a/2032ve 135 44-pin tqfp 7.5 isplsi 2032ve-135lt44 135 48-pin tqfp 7.5 isplsi 2032ve-135lt48 135 44-pin plcc 7.5 isplsi 2032ve-135lj44 135 49-ball cabga 7.5 isplsi 2032ve-135lb49 110 10 44-pin plcc isplsi 2032ve-110lj44 110 10 49-ball cabga isplsi 2032ve-110lb49 110 10 44-pin tqfp isplsi 2032ve-110lt44 110 10 48-pin tqfp isplsi 2032ve-110lt48 table 2-0041a/2032ve 180 5.0 44-pin plcc isplsi 2032ve-180lj44 180 5.0 49-ball cabga isplsi 2032ve-180lb49 isplsi 180 44-pin tqfp 5.0 isplsi 2032ve-180lt44 180 48-pin tqfp 5.0 isplsi 2032ve-180lt48 family f max (mhz) ordering number package t pd (ns) 225 44-pin plcc 4.0 isplsi 2032ve-225lj44 225 49-ball cabga 4.0 isplsi 2032ve-225lb49* 225 44-pin tqfp 4.0 isplsi 2032ve-225lt44* 225 48-pin tqfp 4.0 isplsi 2032ve-225lt48* 300 49-ball cabga 3.0 isplsi 2032ve-300lb49 300 44-pin tqfp 3.0 isplsi 2032ve-300lt44 300 48-pin tqfp 3.0 isplsi 2032ve-300lt48 commercial *2032ve-300 recommended for new designs table 2-0041b/2032ve family f max (mhz) ordering number package t pd (ns) isplsi 180 44-pin tqfp 5.0 isplsi 2032ve-180lt44i industrial

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