View CY7C265-50LMB_2954329.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8k x 8 registered prom cy7c265 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-04012 rev. ** revised march 14, 2002 65 features ? cmos for optimum speed/power high speed (commercial and military) ? 15 ns address set-up ? 12 ns clock to output low power ? 660 mw (commercial) ? 770 mw (military) on-chip edge-triggered registers ? ideal for pipelined microprogrammed systems eprom technology ? 100% programmable ? reprogrammable (7c265w) 5v 10% v cc , commercial and military capable of withstanding >2001v static discharge slim 28-pin, 300-mil plastic or hermetic dip functional description the cy7c265 is a 8192 x 8 registered prom. it is organized as 8,192 words by 8 bits wide, and has a pipeline output reg- ister. in addition, the device features a programmable initialize byte that may be loaded into the pipeline register with the ini- tialize signal. the programmable initialize byte is the 8,193rd byte in the prom and its value is programmed at the time of use. packaged in 28 pins, the prom has 13 address signals (a 0 through a 12 ), 8 data out signals (o 0 through o 7 ), e /i (enable or initialize), and clock. clock functions as a pipeline clock, loading the contents of the addressed memory location into the pipeline register on each rising edge. the data will appear on the outputs if they are enabled. one pin on the cy7c265 is programmed to per- form either the enable or the initialize function. if the asynchronous enable (e ) is being used, the outputs may be disabled at any time by switching the enable to a logic high, and may be returned to the active state by switching the enable to a logic low. if the synchronous enable (e s) is being used, the outputs will go to the off or high-impedance state upon the next positive clock edge after the synchronous enable input is switched to a high level. if the synchronous enable pin is switched to a logic low, the subsequent positive clock edge will return the output to the active state. following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next low-to-high transition of the clock. this unique feature allows the cy7c265 decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs. if the e /i pin is used for init (asynchronous), then the outputs are permanently enabled. the initialize function is useful dur- ing power-up and time-out sequences, and can facilitate im- plementation of other sophisticated functions such as a built-in ? jump start ? address. when activated, the initialize control in- put causes the contents of a user programmed 8193rd 8-bit word to be loaded into the on-chip register. each bit is pro- grammable and the initialize function can be used to load any desired combination of 1 ? s and 0 ? s into the register. in the un- programmed state, activating init will generate a register clear (all outputs low). if all the bits of the initialize word are programmed to be a 1, activating init performs a register pre- set (all outputs high). applying a low to the init input causes an immediate load of the programmed initialize word into the pipeline register and onto the outputs. the init low disables clock and must return high to enable clock independent of all other inputs, including the clock.
cy7c265 document #: 38-04012 rev. ** page 2 of 13 f maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage............................................ ? 3.0v to +7.0v dc program voltage .....................................................13.0v uv exposure.................................................7258 wsec/cm 2 static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma logic block diagram pin configurations top view lcc/plcc (opaque only) 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 25 28 27 26 top view dip/flatpack 15 7c265 a 7 a 6 a 5 a 4 a 3 a 2 gnd clk a 1 a 0 o 0 o 1 o 2 gnd v cc a 8 a 9 a 10 a 11 a 12 e/e s ,i gnd gnd o 7 o 6 o 4 o 5 o 3 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 column multiplexer a 4 a 3 a 2 a 1 programmable multiplexer address decoder programmable array 8-bit edge- triggered register clk init/e/e s clk programmable initialize word d c o 28 4 5 6 7 8 9 10 321 27 13 14 15 16 17 26 25 24 23 22 21 20 11 12 19 o 0 18 a 0 a 1 a 3 a 2 a 10 gnd a 11 a 12 gnd o 7 gnd clk e/e s ,i a 4 a 5 a 6 a 7 v cc a 8 a 9 o 1 o 2 gnd o 3 o 4 o 5 o 6 a 5 a 0 row address column address selection guides 7c265 ? 15 7c265 ? 25 7c265 ? 40 7c265 ? 50 minimum address set-up time (ns) 15 25 40 50 maximum clock to output (ns) 12 15 20 25 maximum operating current (ma) com ? l 120 120 100 80 mil 140 140 120 operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [1] ? 40 c to +85 c 5v 10% military [2] ? 55 c to +125 c 5v 10% notes: 1. contact a cypress representative for industrial temperature range spec- ifications. 2. t a is the ? instant on ? case temperature.
cy7c265 document #: 38-04012 rev. ** page 3 of 13 electrical characteristics over the operating range [3] 7c265-15, 25 7c265-40 7c265-50 parameter description test conditions min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 2.0 ma 2.4 v v cc = min., i oh = ? 4.0 ma 2.4 2.4 v ol output low voltage v cc = min., i ol = 8.0 ma com ? l 0.4 v v cc = min., i ol = 12.0 ma 0.4 0.4 v cc = min., i ol = 6.0 ma mil 0.4 v cc = min., i ol = 8.0 ma 0.4 v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i ix input load current gnd < v in < v cc ? 10 +10 ? 10 +10 ? 10 +10 a i oz output leakage current gnd < v out < v cc , output disabled ? 40 +40 ? 40 +40 ? 40 +40 a i os [4] output short circuit current v cc = max., v out = gnd 90 90 90 ma i cc v cc operating supply current v cc = max., i out = 0 ma com ? l 120 100 80 ma mil 140 120 v pp programming supply voltage 12 13 12 13 12 13 v i pp programming supply current 50 50 50 ma v ihp input high programming voltage 3.0 3.0 3.0 v v ilp input low programming voltage 0.4 0.4 0.4 v capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf notes: 3. see the last page of this specification for group a subgroup testing information. 4. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 sec onds. 5. see introduction to cmos proms in this data book for general information on testing.
cy7c265 document #: 38-04012 rev. ** page 4 of 13 ac test loads and waveforms r2 333 ? (403 ? mil) 3.0v 5v output r1 500 (658 ? mil) 30 pf including jig and scope gnd 90% 10% 90% 10% 5ns 5 ns 5v output 5pf including jig and scope (a) normal load (b) high z load output r th 200 ? 5v output 5v output r1 250 ? 30 pf including jig and scope 5pf including jig and scope (c) normal load (d) high z load output 2.0v r th 100 ? r1 250 ? r1 500 ? (658 ? mil) r2 333 ? (403 ? mil) r2 167 ? r2 167 ? 250 ? mil equivalent to: th venin equivalent equivalent to: th venin equivalent test load for -15 through -25 speeds test load for -40 through -50 speeds switching characteristics over the operating range [3, 5] 7c265-15 7c265-25 7c265-40 7c265-50 parameter description min. max. min. max. min. max. min. max. unit t as address set-up to clock 15 25 40 50 ns t ha address hold from clock 0 0 0 0 ns t co clock to output valid 12 15 20 25 ns t pwc clock pulse width 12 15 15 20 ns t ses e s set-up to clock (sync. enable only) 12 15 15 15 ns t hes e s hold from clock 5 5 5 5 ns t di init to output valid 15 18 25 35 ns t ri init recovery to clock 12 15 20 25 ns t pwi init pulse width 12 15 25 35 ns t cos output valid from clock (sync. mode) 12 15 20 25 ns t hzc output inactive from clock (sync. mode) 12 15 20 25 ns t doe output valid from e low (async. mode) 12 15 20 25 ns t hze output inactive from e high (async. mode) 12 15 20 25 ns
cy7c265 document #: 38-04012 rev. ** page 5 of 13 erasure characteristics wavelengths of light less than 4000 angstroms begin to erase the 7c265 in the windowed package. for this reason, an opaque label should be placed over the window if the prom is exposed to sunlight or fluorescent lighting for extended pe- riods of time. the recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (uv inten- sity exposure time) of 25 wsec/cm 2 . for an ultraviolet lamp with a 12 mw/cm 2 power rating the exposure time would be approximately 45 minutes. the 7c265 needs to be within one inch of the lamp during erasure. permanent damage may re- sult if the prom is exposed to high-intensity uv light for an extended period of time. 7258 wsec/cm 2 is the recommended maximum dosage. control byte 00 asynchronous output enable (default condition) 01 synchronous output enable 02 asynchronous initialize programming modes the 7c265 offers a limited selection of programmed architec- tures. programming these features should be done with a sin- gle 10-ms-wide pulse in place of the intelligent algorithm, mainly because these features are verified operationally, not with the vfy pin. architecture programming is implemented by applying the supervoltage to two additional pins during pro- gramming. in programming the 7c265 architecture, vpp is ap- plied to pins 3, 9, and 22. the choice of a particular mode depends on the states of the other pins during programming, so it is important that the condition of the other pins be met as set forth in the mode table. the considerations that apply with respect to power-up and power-down during intelligent pro- gramming also apply during architecture programming. once the supervoltages have been established and the correct logic states exist on the other device pins, programming may begin. programming is accomplished by pulling pgm from high to low and then back to high with a pulse width equal to 10 ms. switching waveform t hzc t pwc t hes valid data t cos t co t pwi t di address clock synchronous enable (programmable) asynchronous init (programmable) output asynchronous enable t hze t ses t ah t as t doe t ri bit map data programmer address (hex.) ram data decimal hex contents 0 . . 8191 8192 8193 0 . . 1fff 2000 2001 data . . data init byte control byte
cy7c265 document #: 38-04012 rev. ** page 6 of 13 programming information programming support is available from cypress as well as from a number of third-party software vendors. for detailed programming information, including a listing of software pack- ages, please see the prom programming information located at the end of this section. programming algorithms can be ob- tained from any cypress representative. table 1. mode selection pin function read or output disable a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 mode other a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 asynchronous enable read a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 synchronous enable read a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 asynchronous initialization read a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 program memory a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 program verify a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 program inhibit a 12 a 11 a 10 ? a 7 a 6 a 5 a 4 ? a 3 a 2 program synchronous enable v ihp v ihp a 10 ? a 7 v ihp v pp a 4 ? a 3 v ihp program initialize v ilp v ihp a 10 ? a 7 v ihp v pp a 4 ? a 3 v ilp program initial byte a 12 v ilp a 10 ? a 7 v ihp v pp a 4 ? a 3 v ilp pin function read or output disable a 1 a 0 gnd clk gnd e , i o 7 ? o 0 mode other a 1 a 0 pgm clk vfy v pp d 7 ? d 0 asynchronous enable read a 1 a 0 gnd v il gnd v il o 7 ? o 0 synchronous enable read a 1 a 0 gnd v il /v ih gnd v il o 7 ? o 0 asynchronous initialization read a 1 a 0 gnd v il gnd v il o 7 ? o 0 program memory a 1 a 0 v ilp v ilp v ihp v pp d 7 ? d 0 program verify a 1 a 0 v ihp v ilp v ilp v pp o 7 ? o 0 program inhibit a 1 a 0 v ihp v ilp v ihp v pp high z program synchronous enable v pp v ilp v ilp v ilp v ihp v pp d 7 ? d 0 program initialize v pp v ilp v ilp v ilp v ihp v pp d 7 ? d 0 program initial byte v pp v ihp v ilp v ilp v ihp v pp d 7 ? d 0 figure 1. programming pinout 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 25 28 27 26 a 7 a 6 a 5 a 4 a 3 a 2 pgm clk a 1 a 0 d 0 d 1 d 2 gnd v cc a 8 a 9 a 10 a 11 a 12 v pp na vfy d 7 d 6 d 4 d 5 d 3 15 28 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 11 12 19 a 5 v cc gnd a 6 a 7 d 3 d 1 d 0 18 d 4 d 5 a 0 a 1 a 3 a 2 a 8 d 7 pgm clk d 2 a 10 v pp vfy a 12 na d 6 a 11 a 9 a 4 lcc/plcc (opaque only) dip/flatpack
cy7c265 document #: 38-04012 rev. ** page 7 of 13 typical dc and ac characteristics 1.4 1.6 1.0 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 ? 55 25 125 1.2 1.1 normalized acces s time 60 40 30 20 10 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature normalized supply current vs. ambient temperature ambient temperature ( c) output voltage (v) output source current vs. output voltage 0.6 1.2 150 175 125 75 50 25 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 100 output sink current vs. output voltage 1.0 0.9 0.8 normalized i cc normalized i cc i cc i cc v cc =5.0v t a =25 c 0.6 0 30 25 20 15 10 5 0 200 400 600 800 delta t (ns) co capacitance (pf) typical access time change vs. output loading 0 1000 v cc =4.5v t a =25 c ambient temperature ( c) output voltage (v) t a =25 c f=max. 50 35 1.00 1.05 0.95 0.85 0.80 0.75 025 5075 100 0.70 0.90 normalized supply current vs. clock period clock period (ns) normalized i cc v cc =5.5v t a =25 c
cy7c265 document #: 38-04012 rev. ** page 8 of 13 military specifications group a subgroup testing ordering information [6] speed (ns) i cc (ma) ordering code package name package type operating range 15 120 cy7c265 ? 15jc j64 28-lead plastic leaded chip carrier commercial cy7c265 ? 15pc p21 28-lead (300-mil) molded dip cy7c265 ? 15wc w22 28-lead (300-mil) windowed cerdip 140 cy7c265 ? 15dmb d22 28-lead (300-mil) cerdip military cy7c265 ? 15lmb l64 28-square leadless chip carrier cy7c265 ? 15qmb q64 28-pin windowed leadless chip carrier cy7c265 ? 15wmb w22 28-lead (300-mil) windowed cerdip 25 120 cy7c265 ? 25jc j64 28-lead plastic leaded chip carrier commercial cy7c265 ? 25pc p21 28-lead (300-mil) molded dip cy7c265 ? 25wc w22 28-lead (300-mil) windowed cerdip 140 cy7c265 ? 25dmb d22 28-lead (300-mil) cerdip military cy7c265 ? 25lmb l64 28-square leadless chip carrier cy7c265 ? 25qmb q64 28-pin windowed leadless chip carrier cy7c265 ? 25wmb w22 28-lead (300-mil) windowed cerdip 40 100 cy7c265 ? 40jc j64 28-lead plastic leaded chip carrier commercial cy7c265 ? 40pc p21 28-lead (300-mil) molded dip cy7c265 ? 40wc w22 28-lead (300-mil) windowed cerdip 50 80 cy7c265 ? 50jc j64 28-lead plastic leaded chip carrier commercial cy7c265 ? 50pc p21 28-lead (300-mil) molded dip cy7c265 ? 50wc w22 28-lead (300-mil) windowed cerdip 120 cy7c265 ? 50dmb d22 28-lead (300-mil) cerdip military cy7c265 ? 50lmb l64 28-square leadless chip carrier cy7c265 ? 50qmb q64 28-pin windowed leadless chip carrier cy7c265 ? 50wmb w22 28-lead (300-mil) windowed cerdip note: 6. most of these products are available in industrial temperature range. contact a cypress representative for specifications and product availability. dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t as 7, 8, 9, 10, 11 t ha 7, 8, 9, 10, 11 t co 7, 8, 9, 10, 11 t pw 7, 8, 9, 10, 11 t ses 7, 8, 9, 10, 11 t hes 7, 8, 9, 10, 11 t cos 7, 8, 9, 10, 11
cy7c265 document #: 38-04012 rev. ** page 9 of 13 package diagrams 28-lead (300-mil) cerdip d22 mil-std-1835 d-15 config. a 51-80032 28-lead plastic leaded chip carrier j64 51-85001-a
cy7c265 document #: 38-04012 rev. ** page 10 of 13 package diagrams (continued) 28-square leadless chip carrier l64 mil-std-1835 c-4 51-80051 51-85014-b 28-lead (300-mil) molded dip p21
cy7c265 document #: 38-04012 rev. ** page 11 of 13 package diagrams (continued) 28-pin windowed leadless chip carrier q64 mil ? std ? 1835 c ? 4 51-80102
cy7c265 document #: 38-04012 rev. ** page 12 of 13 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-lead (300-mil) windowed cerdip w22 mil-std-1835 d-15 config. a 51-80087
cy7c265 document #: 38-04012 rev. ** page 13 of 13 document title: cy7c265 8k x 8 registered prom document number: 38-04012 rev. ecn no. issue date orig. of change description of change ** 114139 3/18/02 dsg change from spec number: 38-00084 to 38-04012

▲Up To Search▲

Price & Availability of CY7C265-50LMB

	To Download CY7C265-50LMB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .