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1/18 ? semiconductor MSM82C84A-2rs/gs/js general description the MSM82C84A-2rs/gs is a clock generator designed to generate msm80c86a-10 and msm80c88a-10 system clocks of 8mhz. due to the use of silicon gate cmos technology, standby current is only 40 m a (max.), and the power consumption is very low with 16 ma (max.) when a 8 mhz clock is generated. features ? operating frequency of 6 to 24 mhz (clk output 2 to 8 mhz) ?3 m silicon gate cmos technology for low power consumption ? built-in crystal oscillator circuit ? 3 v to 6 v single power supply ? built-in synchronized circuit for msm80c86a-10 and msm80c88a-10 ready and reset ? ttl compatible ? built-in schmitt trigger circuit (res input) ? 18-pin plastic dip (dip18-p-300-2.54): (product name: MSM82C84A-2rs) ? 20-pin plastic qfj (qfj20-p-s350-1.27): (product name: MSM82C84A-2js) ? 24-pin plastic sop (sop24-p-430-1.27-k): (product name: MSM82C84A-2gs-k) functional block diagram ? semiconductor MSM82C84A-2rs/gs/js clock generator and driver reset osc pclk clk ready d c q 1 2 1 3 s y n c s y n c d c q (f2) d c - q (f1) res x 1 x 2 f/ c efi csync rdy 1 aen 1 aen 2 async rdy 2 crystal oscillator e2o0012-27-x2 this version: jan. 1998 previous version: aug. 1996
2/18 ? semiconductor MSM82C84A-2rs/gs/js pin configuration (top view) 18 pin plastic dip 24 pin plastic sop 20 pin plastic qfj 18 17 16 15 14 rdy 2 aen 2 rdy 1 ready nc 9 10 11 12 13 clk gnd reset res osc 3 2 1 20 19 aen 1 pclk csync x 1 4 5 6 7 8 v cc async efi f/ c nc x 2 x 2 nc async efi nc f/ c osc nc x 1 res reset nc aen 1 rdy 1 ready nc rdy2 aen 2 nc csync pclk clk gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v cc 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 async efi f/ c osc x 2 x 1 res reset aen 1 rdy 1 ready rdy 2 aen 2 csync pclk clk gnd v cc (nc not connected)
3/18 ? semiconductor MSM82C84A-2rs/gs/js absolute maximum ratings C55 to +150 MSM82C84A-2rs/js supply voltage v cc C0.5 to +7 v input voltage v in C0.5 to v cc +0.5 v output voltage v out C0.5 to v cc +0.5 v storage temperature t stg c power dissipation p d w parameter unit symbol respect to gnd ta = 25c condition rating MSM82C84A-2gs 0.7 0.8 operating ranges range supply voltage v cc 3 to 6 v operating temperature t op C40 to +85 c parameter unit symbol recommended operating conditions dc characteristics max. "l" level output voltage (clk) v ol 0.4 v "h" output voltage (clk) v ol 0.4 v parameter unit symbol min. v cc C0.4 i ol = 4 ma i ol = 2.5 ma i oh = C4 ma condition "h" output voltage (others) v oh v v cc C0.4 i oh = C1 ma res input hysteresis v ihr -v ilr v 0.2*v cc input leak current (except async ) i li +1 m a C1 0 v in v cc input current ( async ) i lia +10 m a C100 0 v in v cc standby supply current i ccs 40 m a note 1 input capacitance c in 7 pf f =1 mhz "l" level output voltage (others) operating supply current v oh v i cc 16 ma f = 24 mhz, c l = o p f (v cc = 5 v 10%, ta = C40 to 85c) note: 1. x1 3 v cc C 0.2 v, x2 0.2 v f/c 3 v cc C 0.2 v, async = v cc or open vih 3 v cc C 0.2 v, vil 0.2 v typ. supply voltage v cc 5v t op +25 "l" level input voltage v il v ih "h" level input voltage (except res ) min. 4.5 C40 C0.5 2.2 max. 5.5 +85 +0.8 v cc +0.5 parameter unit symbol c v v 0.6*v cc operating temperature "h" level input voltage ( res )
4/18 ? semiconductor MSM82C84A-2rs/gs/js ac characteristics (1) parameter symbol min. max. unit efi "h" pulse width efi "l" pulse width crystal oscillator frequency set up time of rdy 1 or rdy 2 to clk falling edge (active) efi cycle time conditions set up time of rdy 1 or rdy 2 to clk rising edge (active) set up time of rdy 1 or rdy 2 to clk falling edge (inactive) hold time of rdy 1 or rdy 2 to clk falling edge set up time of async to clk falling edge hold time of async to clk falling edge set up time of aen 1 (aen 2 ) to rdy 1 (rdy 2 ) rising edge hold time of aen 1 (aen 2 ) to clk falling edge set up time of csync to efi rising edge hold time of csync to efi rising edge csync pulse width set up time of res to clk falling edge hold time of res to clk falling edge input rising edge time input falling edge time t ehel t eleh t elel t r1vcl t r1vch t r1vcl t clr1x t ayvcl t clayx t a1r1v t cla1x t yheh t yhyl t i1hcl t cli1h t ilih t ihil t ehyl 13 17 36 6 35 35 35 0 50 0 15 0 20 10 2 t elel 65 20 24 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns mhz ns ns ns ns ns 90% to 90% 10% to 10% async = high async = low output load capacitance clk output c l = 100 pf others 30 pf (v cc = 5 v 10%, ta = C40 to 85c) note: parameters where timing has not been indicated in the above table are measured at v l = 1.5 v and v h = 1.5 v for both inputs and outputs.
5/18 ? semiconductor MSM82C84A-2rs/gs/js ac characteristics (2) parameter symbol min. max. unit clk cycle time clk "h" pulse width clk rising and falling edge times clk "l" pulse width conditions pclk "h" pulse width time from ready falling edge to clk falling edge time from ready rising edge to clk rising edge delay from clk falling edge to reset falling edge delay from clk falling edge to pclk rising edge delay from clk falling edge to pclk falling edge delay from osc falling edge to clk falling edge output rising edge time (except clk) output falling edge time (except clk) t clcl t chcl t clch t ch1ch2 t phpl t rylcl t ryhch t clil t clph t clpl t olcl t oloh t ohol 125 t clcl C20 -8 2 10 40 22 22 35 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns output load capacitance clk output c l = 100 pf others 30 pf (v cc = 5 v 10%, ta = -40 to 85c) pclk "l" pulse width t cl2cl1 t plph delay from osc falling edge to clk rising edge t olch 1 3 t clcl + 2 2 3 t clcl C15 t clcl C20 2 3 t clcl C15 C5 22 ns 1.0 v to 3.5 v 0.8 v to 2.2 v 2.2 v to 0.8 v note: parameters where timing has not been indicated in the above table are measured at v l = 1.5 v and v h = 1.5 v for both inputs and outputs.
6/18 ? semiconductor MSM82C84A-2rs/gs/js pin description csync name clock synchronization single input pin symbol input/output function aen 1 aen 2 address enable signals input rdy 1 rdy 2 bus ready signals input ready ready output output clk clock output output res reset in input synchronizing signal for output of in-phase clk signals when more than one MSM82C84A-2 is used. the internal counter is reset when this signal is at high level, and a high level clk output is generated. the internal counter is subsequently activated and a 33% duty clk output is generated when this signal is switched to low level. when this signal is used, external synchronization of efi is necessary. when the internal oscillator is used, it is necessary for this pin to be kept to be low level. pclk output this peripheral circuit clock signal is output in a 50% duty cycle at a frequency half that of the clock signal. the aen 1 signal enables rdy 1 , and the aen 2 signal rdy 2 . the respective rdy inputs are activated when the level applied to these pins is low. although two separate inputs are used in multi-master systems, only the aen which enables the rdy input to be used is to be switched to low level in the case of not using multi-master systems. completion of data bus reading and writing by the device connected to the system data bus is indicated when one of these signals is switched to high level. the relevant rdy input is enables only when the corresponding aen is at low level. this signal is obtained by synchronizing the bus ready signal with clk. this signal is output after guaranteeing the hold time for the cpu in phase with the rdy input. this signal is the clock used by the cpu and peripheral devices connected to the cpu system data bus. the output waveform is generated in a 33% duty cycle at a frequency 1/3 the oscillating frequency of the crystal oscillator connected to the x 1 and x 2 pins, or at a frequency 1/3 the efi input frequency. this low-level active input is used to generate a cpu reset signal. since a schmitt trigger is included in the input circuit for this signal, "power on resetting" can be achieved by connection of a simple rc circuit. reset reset output output this signal is obtained by clk synchronization of the input signal applied to res and is output in opposite phase to the res input. this signal is applied to the cpu as the system reset signal. this signal selects the fundamental signal for generation of the clk signal. the clk is generated from the crystal oscillator output when this signal is at low level, and from the efi input signal when at high level. the signal applied to this input pin generaters the clk signal when f/ c is at high level. the frequency of the input signal needs to be three times greater than the desired clk frequency. f/c clock select signal input osc crystal resonator output output efi external clock signal input peripheral clock output crystal oscillator connections. the crystal oscillator frequency needs to be three times greater than the desired clk frequency. x 1 , x 2 crystal oscillator connecting pins input crystal oscillator output. this output frequency is the same as the oscillating frequency of the oscillator connected to the x 1 and x 2 pins. as long as a xtal oscillator is connected to the x 1 and x 2 pins, this output signal can be obtained independently even if f/ c is set to high level to enable the efi input to be used clk generation purpose.
7/18 ? semiconductor MSM82C84A-2rs/gs/js async name ready synchronization select signal input pin symbol input/output function signal for selection of the synchronization mode of the ready signal generator circuit. when this signal is at low level, the ready signal is generated by double synchronization. and when at high level, the ready signal is generated by single synchronization. this pin is equipped with internal pull-up resistor. v cc +5 v power supply gnd gnd timing diagram clk ? pclk ? osc waveforms efi t elel t ehel t eleh t ehyl t olch t yheh t yhyl t clcl t olcl t chcl t ch1ch2 t cl2cl1 t clpl t clch t phpl t clph t plph osc csync clk pclk clk res reset t cli1h t i1hcl t clil reset waveform
8/18 ? semiconductor MSM82C84A-2rs/gs/js ready waveform ( async = l) clk t r1vch t clr1x t r1vcl t clr1x t a1r1v t ayvcl t cla1x t clayx t rylcl t ryhch rdy 1 - 2 aen 1 - 2 async ready t clr1x t r1vcl t clr1x t r1vcl t cla1x t clayx t rylcl t ryhch t ayvcl t a1r1v clk rdy 1 - 2 aen 1 - 2 async ready ready waveform ( async = h)
9/18 ? semiconductor MSM82C84A-2rs/gs/js operational description (1) oscillator circuit the MSM82C84A-2 internal oscillator circuit can be driven by connecting a crystal oscillator to the x 1 and x 2 pins. the frequency of the crystal oscillator in this case needs to be three times greater than the desired clk frequency. since the oscillator circuit output (the same output as for the crystal resonator frequency) appears at the osc pin, independent use of this output is also possible. oscillator circuit example c 1 c 2 x 1 x 2 msm 82c84a-2 osc crystal oscillator when input frequency is 6 to 15 mhz c 1 = c 2 = 33 pf when input frequency is 15 to 24 mhz c 1 = c 2 = 10 pf note: because oscillator circuit and values depend on crystal oscillator characteristics, oki recommends to make contact with crystal oscillator vendor to determine the best circuit and values for customers' a pp lication. (2) clock generator circuit this circuit generates two clock outputs-clk obtained by dividing the input external clock or crystal oscillator circuit output by three, and pclk obtained by halving clk. clk and pclk are generated from the external clock applied to the efi pin when f/ c is at high level, and are generated from the crystal oscillator circuit when at low level. (3) reset circuit since a schmitt trigger circuit is used in the res input, the MSM82C84A-2 can be reset by power on by connection to a simple rc circuit. if the msm80c86a-10 or msm80c88a-10 is used as the cpu in this case, it is necessary to keep the res input at low level for at least 50 ms after vcc reaches the 4.5v level.
10/18 ? semiconductor MSM82C84A-2rs/gs/js (4) ready circuit the ready signal generator circuit can be set to synchronization mode by async . (i) when async is at low level the rdy input is output as the ready signal by double synchronization. the high-level rdy input is synchronized once by the rising edge of the clk of the first stage flip-flop (f1 in the circuit diagram), and then synchronized again by the falling edge of the clk of the next stage flip-flop (f2 in the circuit diagram), resulting in output of a high-level ready output signal (see diagram below). the low-level rdy input is synchronized directly by the falling-edge of the clk of the next stage flip-flop, resulting in output of a low-level ready output signal (see diagram below). (ii) when async is at high level the rdy input is output as the ready signal by single synchronization. both low-level and high-level rdy inputs are synchronized by the falling edge of the clk of the next stage flip-flop, resulting output of respective low-level and high-level ready output signals (see diagram below). clk rdy ready clk rdy ready
11/18 ? semiconductor MSM82C84A-2rs/gs/js example of use (csync) the MSM82C84A-2 1/3 frequency divider counter is unsettled when the power is switched on. therefore, the csync pin has been included to synchronize clk with another signal. when csync is at high level, both clk and pclk are high-level outputs. if csync is then switched to low level, clk is output from the next input clock rising edge, and is divided by 3. if csync has not been synchronized with the input clock, use the following circuit to achieve the required synchronization external sychronizing signal d ck - q d ck q efi clk clk csync msm 82c84a-2 external clock signal (efi) when an external clock efi is used as the clock source external sychronizing signal d ck - q d ck q osc clk f/ c csync msm 82c84a-2 when the crystal oscillator is used as the clock source clk x 1 x 2 notes on use the MSM82C84A-2 cannot be used if the msm80c86a-10 or msm80c88a-10 is used within the range of 8 mhz < operating frequency 10 mhz.
12/18 ? semiconductor MSM82C84A-2rs/gs/js notice on replacing low-speed devices with high-speed devices the conventional low speed devices are replaced by high-speed devices as shown below. when you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. high-speed device (new) low-speed device (old) remarks m80c85ah m80c85a/m80c85a-2 8bit mpu m80c86a-10 m80c86a/m80c86a-2 16bit mpu m80c88a-10 m80c88a/m80c88a-2 8bit mpu m82c84a-2 m82c84a/m82c84a-5 clock generator m81c55-5 m81c55 ram.i/o, timer m82c37b-5 m82c37a/m82c37a-5 dma controller m82c51a-2 m82c51a usart m82c53-2 m82c53-5 timer m82c55a-2 m82c55a-5 ppi
13/18 ? semiconductor MSM82C84A-2rs/gs/js differences between msm82c84a and msm82c84a-5/MSM82C84A-2 1) manufacturing process all these devices use a 3 m si-gate cmos process technology. the chip size of these devices is same. the chip of the msm82c84a-5 is entirely identical to that of the MSM82C84A-2. 2) functions 3) electrical characteristics 3-1) dc characteristics as shown above, the msm82c84a-5/MSM82C84A-2 satisfies the characteristics (except for v ol and input current ( async ) of the msm82c84a. item msm82c84a msm82c84a-5/-2 internal processing of async pin normal cmos input pin input pin with built-in pull up resistor notes on use the pin should have a pullup or pulldown resistor if it is unused. the value of pulldown resistor (when used) is limited. (see page 3.) parameter symbol msm82c84a msm82c84a-5/-2 ''l''level output voltage (clk) 0.45 v maximum (+5 ma) 0.40 v maximum (+4 ma) ''l''level output voltage (other than clk) 0.45 v maximum (+5 ma) 0.40 v maximum (+2.5 ma) v ol v ol v oh v oh v ihr- v ilr i lia i li i ccs ''h''level output voltage (clk) 3.7 v minimum (-1 ma) v cc -0.1 v minimum (-4 ma) ''h''level output voltage (other than clk) 3.7 v minimum (-1 ma) v cc- 0.1 v minimum (-1 ma) res input hysteresis width 0.25 v minimum 0.2 v cc min input current ( async ) -10 m a to +10 m a -100 m a~+10 m a input leak current -10 m a to +10 m a -1 m a~+1 m a supply current (standby) 100 m a maximum 40 m a maximum
14/18 ? semiconductor MSM82C84A-2rs/gs/js 3-2) ac charasteristics 1) msm82c84a and MSM82C84A-2 as shown above, the MSM82C84A-2 satisfies the characteristics (except for input rise/fall time) of the msm82c84a. 1) msm82c84a-5 and MSM82C84A-2 as shown above, the MSM82C84A-2 satisfies the characteristics of the msm82c84a-5. parameter symbol msm82c84a-5 MSM82C84A-2 efi high time 20 ns minimum 13 ns minimum efi low time 20 ns minimum 17 ns minimum t ehel t eleh t chcl crystal frequency 15 mhz maximum 24 mhz maximum clk period 200 ns minimum 125 ns minimum efi period t elel 66 ns minimum 36 ns minimum parameter symbol msm82c84a MSM82C84A-2 input rise time 20 ns maximum 15 ns maximum input fall time 20 ns maximum 15 ns maximum t ilih t ilih t clch t ch1ch2 t phpl t ryhch clk low time 119 ns minimum 2/3 t clcl -15 ns minimum clk rise/fall time 15 ns maximum 10 ns maximum pclk high time 180 ns minimum t clcl -20 ns minimum ready falling to clk rising 114 ns minimum 2/3 t clcl -15 ns minimum t plph pclk low time 180 ns minimum t clcl -20 ns minimum clk high time t chcl t cl1cl2 65 ns minimum 1/3 t clcl +2 ns minimum
15/18 ? semiconductor MSM82C84A-2rs/gs/js 4) notices on use note the following when replacing devices as the async pin is differently treated between the msm82c84a and the msm82c84a-5/MSM82C84A-2: case 1: when only a pullup resistor is externally connected to. the msm82c84a can be replaced by the MSM82C84A-2. case 2: when only pulldown resistor is externally connected to. when the pulldown resistor is 8 kiloohms or less, the msm82c84a can be replaced by the MSM82C84A-2. when the pulldown resistor is greater than 8 kiloohms, use a pulldown resistor of 8 kiloohms or less. case 3: when an output of the other ic device is connected to the device. the msm82c84a can be replaced by the MSM82C84A-2 when the i ol pin of the device to drive the async pin of the MSM82C84A-2 has an allowance of 100 m a or more.
16/18 ? semiconductor MSM82C84A-2rs/gs/js (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip18-p-300-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.30 typ.
17/18 ? semiconductor MSM82C84A-2rs/gs/js (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj20-p-s350-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 0.59 typ. spherical surface
18/18 ? semiconductor MSM82C84A-2rs/gs/js (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sop24-p-430-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.58 typ. mirror finish

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