1 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hi-reliability product edi88512va-rp 512kx8 plastic monolithic 3.3v sram cmos features n 512kx8 bit cmos static n random access memory ? access times of 15, 17, 20, 25ns ? extended temperature testing n 36 lead jedec approved revolutionary pinout ? plastic soj (package 319) n single +3.3v ( 10%) supply operation top view june 1999 rev. 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a0 a1 a2 a3 a4 cs i/o0 i/o1 vcc vss i/o2 i/o3 we a5 a6 a7 a8 a9 nc a18 a17 a16 a15 oe i/o7 i/o6 vss vcc i/o5 i/o4 a14 a13 a12 a11 a10 nc 36 pin revolutionary wedc's ruggedized plastic 512kx8 sram that allows the user to capitalize on the cost advantage of using a plastic component while not sacrificing all of the reliability available in a full military device. extended temperature testing is performed with the test patterns developed for use on wedcs fully compliant 512kx8 srams. wedc fully characterizes devices to determine the proper test patterns for testing at temperature extremes. this is critical because the operating characteristics of a device change when it is operated beyond the commercial temperature range. using commercial methods will not guarantee a devicee that operates reliabily in the field at temperature extremes. users of wedcs ruggedized plastic benefit from wedcs extensive experience in characterizing srams for use in military systems. wedcs ruggedized plastic soj is footprint compatible with wedcs full military ceramic 36 pin soj. pin description i/o 0-7 data inputs/outputs a 0-18 address inputs we write enable cs chip select oe output enable v cc power (+3.3v ) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a -18 i/o -7 we cs oe fig. 1 pin configuration
2 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi88512va-rp absolute maximum ratings parameter unit voltage on any pin relative to vss -0.5 to 7.0 v operating temperature t a (ambient) commercial 0 to +70 c industrial -40 to +85 c military -55 to +125 c storage temperature, plastic -65 to +125 c power dissipation 0.55 w output current 20 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v supply voltage v ss 000v input high voltage v ih 2.2 vcc +0.3 v input low voltage v il -0.3 +0.8 v parameter symbol condition max unit address lines c i v in = vcc or vss, f = 1.0mhz 7pf data lines c o v in = vcc or vss, f = 1.0mhz 8pf these parameters are sampled, not 100% tested. capacitance (t a = +25 c) truth table oe cs we mode output power x h x standby high z icc 2 , icc3 h l h output deselect high z icc 1 l l h read data out icc 1 x l l write data in icc 1 note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional op- eration of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 w vcc q figure 1 figure 2 255 w 5pf 480 w vcc q 255 w ac test conditions parameter symbol conditions units min max input leakage current i li v in = 0v to v cc -2 2 m a output leakage current i lo v i/o = 0v to v cc -2 2 m a operating power supply current i cc1 we, cs = v il , i i/o = 0ma, min cycle (15ns) 170 ma (20-55ns) 160 ma standby (ttl) power supply current i cc2 cs 3 v ih , v in v il , v in 3 v ih 50ma full standby power supply current i cc3 cs 3 v cc -0.2v 10ma v in 3 vcc -0.2v or v in 0.2v output low voltage v ol i ol = 8.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v note: dc test conditions: v il = 0.3v, v ih = vcc -0.3v dc characteristics (v cc = 5v, t a = -55 c to +125 c)
3 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi88512va-rp ac characteristics C read cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 15ns 17ns 20ns 25ns parameter jedec alt. min max min max min max min max units read cycle time t avav t rc 15 17 20 25 ns address access time t avqv t aa 15 17 20 25 ns chip enable access time t elqv t acs 15 17 20 25 ns chip enable to output in low z (1) t elqx t clz 33 33 ns chip disable to output in high z (1) t ehqz t chz 070708010ns output hold from address change t avqx t oh 00 00 ns output enable to output valid t glqv t oe 7 8 10 12 ns output enable to output in low z (1) t glqx t olz 00 00 ns output disable to output in high z(1) t ghqz t ohz 070708010ns 1. this parameter is guaranteed by design but not tested. ac characteristics C write cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 15ns 17ns 20ns 25ns parameter jedec alt. min max min max min max min max units write cycle time t avav t wc 15 17 20 25 ns chip enable to end of write t elwh t cw 13 14 15 17 ns t eleh t cw 13 14 15 17 ns address setup time t avwl t as 0000 ns t avel t as 0000 ns address valid to end of write t avwh t aw 12 14 15 17 ns t aveh t aw 12 14 15 17 ns write pulse width t wlwh t wp 12 14 15 17 ns t wleh t wp 12 14 15 17 ns write recovery time t whax t wr 0000 ns t ehax t wr 0000 ns data hold time t whdx t dh 0000 ns t ehdx t dh 0000 ns write to output in high z (1) t wlqz t whz 0 7 08 08010 ns data to write time t dvwh t dw 8 8 10 12 ns t dveh t dw 8 8 10 12 ns output active from end of write (1) t whqx t wlz 0000 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi88512va-rp address data i/o read cycle 1 (we high; oe, cs low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data i/o read cycle 2 (we high) t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz oe cs ws32k32-xhx fig. 2 timing waveform - read cycle fig. 4 write cycle - cs controlled fig. 3 write cycle - we controlled address data in write cycle 2, cs controlled t aveh t eleh t ehax t wleh t dveh t ehdx t avav data valid high z we cs data out t avel address data in write cycle 1, we controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we cs data out
5 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi88512va-rp fig. 5 normalized operating graphs -55 125 25 icc1 (20ns) vs temp temp. (c) 14 13 12 11 10 9 8 7 6 -55 125 25 write pulse width vs. temp. write pulse width (ns) temp. (c) -55 125 25 icc3 vs. temp temp. (c) 22 20 18 190 16 14 12 -55 125 25 tavqv vs. temp tavqv ( ns ) temp. (c) 10 1 0.1 0.01 0.001 -55 125 25 iccdr vs. temp iccdr (ma) normalized curves are offered as a service to our customers. they are not to be construed as a guarantee of operating characterics. characteristics of actual devices will vary. 10 1 0.1 0.01 icc3 (ma) 220 210 200 190 180 170 160 icc1 (ma) idr, 2v idr, 3v temp. (c)
6 white electronic designs corporation ? phoenix, az ? (602) 437-1520 edi88512va-rp ordering information package 319: 36 lead, plastic small outline j-lead (soj) pin 1 indicator 0.920 0.930 0.395 0.405 0.026 0.032 0.375 typ. 0.050 typ. 0.015 0.021 0.148 max. 0.360 0.380 0.435 0.445 0.027 min. all dimensions are in inches white electronic designs sram organization, 512kx8 technology: va = 3.3v cmos standard power access time (ns) package type: m = 36 lead plastic soj device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 8 512 va x x x
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