philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet general description quick reference data n-channel enhancement mode symbol parameter max. unit logic level field-effect power transistor in a plastic envelope v ds drain-source voltage 55 v suitable for surface mounting. i d drain current (dc) t sp = 25 ?c 5.5 a the device features very low drain current (dc) t amb = 25 ?c 2.5 a on-state resistance and has p tot total power dissipation 8.3 w integral zener diodes giving t j junction temperature 150 ?c esd protection. it is intended for r ds(on) drain-source on-state 150 m w use in dc-dc converters and resistance v gs = 5 v general purpose switching applications. pinning - sot223 pin configuration symbol pin description 1 gate 2 drain 3 source 4 drain (tab) limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ds drain-source voltage - - 55 v v dgr drain-gate voltage r gs = 20 k w -55v v gs gate-source voltage - - 13 v i d drain current (dc) t sp = 25 ?c - 5.5 a t amb = 25 ?c - 2.5 a i d drain current (dc) t sp = 100 ?c - 3.8 a t amb = 100 ?c - 1.75 a i dm drain current (pulse peak value) t sp = 25 ?c - 22 a t amb = 25 ?c - 10 a p tot total power dissipation t sp = 25 ?c - 8.3 w t amb = 25 ?c - 1.8 w t stg , t j storage & operating temperature - - 55 150 ?c esd limiting value symbol parameter conditions min. max. unit v c electrostatic discharge capacitor human body model - 2 kv voltage (100 pf, 1.5 k w ) d g s 4 1 23 january 1998 1 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet thermal resistances symbol parameter conditions typ. max. unit r th j-sp from junction to solder point mounted on any pcb 12 15 k/w r th j-amb from junction to ambient mounted on pcb of fig.17 - 70 k/w static characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma 55 - - v voltage t j = -55?c 50 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1.0 1.5 2.0 v t j = 150?c 0.6 - - v t j = -55?c - - 2.3 v i dss zero gate voltage drain current v ds = 55 v; v gs = 0 v; - 0.05 10 m a t j = 150?c - - 100 m a i gss gate source leakage current v gs = 5 v - 0.02 1 m a t j = 150?c - - 5 m a v (br)gss gate source breakdown voltage v gs = 1 ma 10 - - v r ds(on) drain-source on-state v gs = 5 v; i d = 5 a - 120 150 m w resistance t j = 150?c - - 277 m w dynamic characteristics t mb = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit g fs forward transconductance v ds = 25 v; i d = 5 a; t j = 25?c 3 5 - s q g(tot) total gate charge i d = 5 a; v dd = 44 v; v gs = 5 v - 4.5 - nc q gs gate-source charge - 1 - nc q gd gate-drain (miller) charge - 2.5 - nc c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 250 330 pf c oss output capacitance - 65 80 pf c rss feedback capacitance - 35 50 pf t d on turn-on delay time v dd = 30 v; i d = 5 a; - 11 17 ns t r turn-on rise time v gs = 5 v; r g = 10 w ; - 38 60 ns t d off turn-off delay time - 25 38 ns t f turn-off fall time t j = 25?c - 20 38 ns reverse diode limiting values and characteristics t j = -55 to 175?c unless otherwise specified symbol parameter conditions min. typ. max. unit i dr continuous reverse drain t sp = 25?c - - 5.5 a current i drm pulsed reverse drain current t sp = 25?c - - 30 a v sd diode forward voltage i f = 2 a; v gs = 0 v - 0.85 1.1 v t rr reverse recovery time i f = 2 a; -di f /dt = 100 a/ m s; - 43 - ns q rr reverse recovery charge v gs = -10 v; v r = 30 v - 0.16 - m c january 1998 2 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet avalanche limiting value symbol parameter conditions min. typ. max. unit w dss drain-source non-repetitive i d = 1.9 a; v dd 25 v; - - 15 mj unclamped inductive turn-off v gs = 5 v; r gs = 50 w ; t sp = 25 ?c energy january 1998 3 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t sp ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t sp ); conditions: v gs 3 5 v fig.3. safe operating area. t sp = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-sp = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ); parameter v gs fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ); parameter v gs 0 20 40 60 80 100 120 140 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 1e-07 1e-05 1e-03 1e-01 1e+01 t / s zth / (k/w) 1e+02 3e+01 1e+01 3e+00 1e+00 3e-01 1e-01 3e-02 1e-02 0 0.5 0.2 0.1 0.05 0.02 d = t p t p t t p t d bukx8150-55 0 20 40 60 80 100 120 140 tmb / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0246810 0 2 4 6 8 10 2.2 2.4 2.6 2.8 3.0 3.2 3.4 vgs = 3.6 v 3.8 4 5 10 drain current, id (a) drain-source voltage, vds (v) vds/v id/a 1 us 10 us 100 us 1 ms 10 ms 100 ms tp = 0.1 1 10 100 11055 rds(on) = vds/id dc bukx8150-55 1234567891011 50 100 150 200 250 300 350 400 rds(on)mohm id/a 5 4 3.6 3.4 3.2 3 january 1998 4 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet fig.7. typical transfer characteristics. i d = f(v gs ) ; conditions: v ds = 25 v; parameter t j fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ); conditions: v ds = 25 v fig.9. normalised drain-source on-state resistance. a = r ds(on) /r ds(on)25 ?c = f(t j ); i d = 5 a; v gs = 5 v fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz 012345 0 2 4 6 8 10 id/a vgs/v tj/c = 150 25 buk98xx-55 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 tj / c vgs(to) / v max. typ. min. 2 3 4 5 6 7 12345678910 transconductance, gfs (s) drain current, id (a) 0 0.5 1 1.5 2 2.5 3 1e-05 1e-05 1e-04 1e-03 1e-02 1e-01 sub-threshold conduction 2% typ 98% buk98xx-55 -100 -50 0 50 100 150 200 0.5 1 1.5 2 2.5 tmb / degc rds(on) normalised to 25degc a 0.01 0.1 1 10 100 0 100 200 300 400 500 600 ciss coss crss vds/v pf january 1998 5 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ); conditions: i d = 5 a; parameter v ds fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. normalised avalanche energy rating. w dss % = f(t sp ); conditions: i d = 1.9 a fig.16. avalanche energy test circuit. 012345 0 1 2 3 4 5 6 vgs/v qg/nc vds = 14v vds = 44v 20 40 60 80 100 120 140 tmb / c 120 110 100 90 80 70 60 50 40 30 20 10 0 wdss% 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 2 4 6 8 10 if/a vsds/v tj/c = 150 25 l t.u.t. vdd rgs r 01 vds -id/100 + - shunt vgs 0 w dss = 0.5 li d 2 bv dss /( bv dss - v dd ) january 1998 6 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet printed circuit board dimensions in mm. fig.17. pcb for thermal resistance and power rating for sot223. pcb: fr4 epoxy glass (1.6 mm thick), copper laminate (35 m m thick). 36 60 9 10 4.6 18 4.5 7 15 50 january 1998 7 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet mechanical data dimensions in mm net mass: 0.11 g fig.18. sot223 surface mounting package. notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. refer to surface mounting instructions for sot223 envelope. 3. epoxy meets ul94 v0 at 1/8". 6.7 6.3 3.1 2.9 4 1 23 2.3 1.05 0.85 0.80 0.60 4.6 3.7 3.3 7.3 6.7 b a 0.10 0.02 13 16 max 1.8 max 10 max 0.32 0.24 (4x) b m 0.1 a m 0.2 january 1998 8 rev 1.100
philips semiconductors product specification trenchmos ? transistor pht6n06lt logic level fet definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1998 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. january 1998 9 rev 1.100
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