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dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in general description the dm 562a p integrated modem i s a two-chi p set desi gn that provide s a compl e te solution fo r state-of-the -a rt, voice-b a n d plain old telepho ne switchi ng (p ots) co mm unication. the mode m provid es fo r data (up to 56,000 bp s), fax (up to 33,600 bp s), fast co nne ctio n, voice and full dupl ex spea ker-p h o ne function s to comply with variou s intern ational stand ards. the d e si gn of the dm 562ap is o p timize d for desktop pe rsonal co mpute r appli c ation s , embedde d microp ro ce ssor ap plicatio ns , set-top-box (stb), point-of-sal e (pos), an d mu lti-fu nctio n perip heral (mfp) fax appli c ation. i t provide s a low cost, highly relia b l e, maximum integratio n, with the minimum a m ount of sup p o r ts re quired. th e dm5 62ap modem ca n ope rate ov er a dial-up netwo rk (pst n) o r 2 wi re l eased line s . the mod e m integrate s auto dial a nd an swer capabilities, synchron ous/asynchronous data tran smissio n s, serial a nd p a rall el interfa c e s , variou s tone detecti on scheme s and data test modes. the dm5 6 2 ap modem referen c e design is pre - ap proved for fcc part 68 a n d provid es minimum de sign cycl e time, with minimum co st to insu re the ma ximum amou nt of succe s s. the simplifie d modem system, sho w n in figure below, illust rates the basi c interconnection bet ween the mcu, ds p, afe and ot her ba sic co mpon ents of a mod e m. th e individ ual el ement s of the dm5 62ap are: ? dm6 580 anal og fro n t end (afe). 48-pi n lqfp packa ge. ? dm6 588a itu-t v.90 in tegrate d pro c e s sors with 32k bytes sram built in 128-pi n qfp packa ge block diagram led tx ds p ring det e ct or dm 6580 analog front end scl k di t dot tf s di r do r rf s r xsc lk cl k i n txdc lk rx dc l k da a rxin txa 1 txa 2 line speaker dr iv er pc i bu s rx dsp v.2 4 in t e rf a c e ua r t v.24 in t e rfa c e pnp spkr m i croph one driver 29 . 4912 m h z 30 . 2 4 m hz optiona l dm6588a txs c lk *2 isa bu s co ntroller mic r o unit 32 kb sra m 2m fl a s h final 1 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 2 final table of contents gene ral de scription 1 b l o c k d i a g r a m 1 features 3 chi p se t chi p 1: dm6 588 a mode m control l e r uni t w i th pnp dm6 588a de scriptio n 4 dm6 588a bl ock dia g ram 4 dm6 588a fe ature s 4 dm6 588a external pin co nfiguration 5 dm6 588a isa pin configu r ation 6 dm6 588a pci pin configuration 7 dm6 588a pi n de scriptio n 8 dm6 588a pi n de scriptio n - isa interface only 11 dm6 588a pi n de scriptio n - pci interfa c e only 12 dm6 588a fu nction al de scription 14 1. operating mode sele cti o n 14 2. micro - controller program memory 14 3. micro - controller po we r down m ode 14 4. enhan ced internal dire ct memory 14 5. re-fla sh program memo ry 14 6. micro - controller i/o de scription 14 7. hdl c descri ption 16 8. micro - controller control regi ste r for intern al m o d e 1 7 9. host control regi ste r for virtual 15 50 a uart 17 10. micro-co n t roller cont rol regi ster for pci i n t e r f a c e 2 2 11. pci confi guration r egi ster definition 23 dm6 588a external ele c tri c al cha r a c teri stics 35 dm6 58a extern al absol u te maximum rating s 35 dm6 58a extern al dc ch a r a c teri stics 35 dm6 588a isa electrical characte risti c s 36 dm6 588a isa absolute m a ximum ratin g s 36 dm6 588a isa dc characteristi c s 36 dm6 588a isa ac cha r a c teri stics & timing diag ram s 3 7 dm6 588a pci electrical characte risti c s 38 dm6 588a pci absolute ma ximum rating s 38 dm6 588a pci dc ch aract e ri stics 38 dm6 588a pci ac charact e ri stics & timing diag ram s 3 9 chip 2: dm6 580 analog front end dm6 580 de scri ption 40 dm6 580 blo c k dia g ram 40 dm6 580 fe ature s 41 dm6 580 pin config uration 41 dm6 580 pin de scriptio n 42 dm6 580 fu n c tional de scri ption 43 dm6 580 regi ster de scripti o n 43 dm6 580 ab solute maximu m rating s 44 dm6 580 dc cha r a c teri stics 44 dm6 580 ac cha r a c teri stics & timing di agrams 45 dm6 580 pe rforma nce 45 packag e information 47 ord e rin g information 48 com pany ov ervie w 48 c o n t a c t s 4 8 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/ voice/ speaker phone modem device single chip with memory built in final 3 version: dm562 ap-ds-f0 3 features z d a t a - itu-t v.90 (5 6000 to 28 00 0 bps) - itu-t v.34 (3 3600 to 24 00 bps) - itu-t v.32b is (1 440 0, 1200 0, 960 0, 7200, 48 00b p s ) - itu-t v.32 (9 600, 480 0bp s) - itu-t v.22bi s (2 400, 12 00 bps) - itu-t v.22 (1 200b ps) - itu-t v.23 (1 200/75 bp s) - itu-t v.21 (3 00bp s) - bell 212a (1 2 00bp s) - bell 103 (3 00 bps) - v.22 fast con nect z fax - itu-t v.34 (3 3600 to 24 00 bps) - itu-t v.17 (1 4400, 12 000, 9600,7 200 bp s) - itu-t v.29 (96 00, 720 0b ps) - itu-t v.27te r (480 0, 2400 bps) - itu-t v.21 chann el 2 (3 00 bps) - group iii, c l as s 1,2 - automatic rate adaptatio n in v.34 half-d uplex m ode - suppo rt ecm mode - support rx polling function z data er ror c o rr ectio n - m n p c l ass 4 - itu-t v.42 lapm z d a ta compres s i on - m n p c l ass 5 - itu-t v.42bi s z voice comp re ssi on - 4 bit adpcm (itu -t) - 2, 3 an 4 bit adpcm (dav icom pro p rieta r y) - 8 bit pcm z synchrono us mode - lega cy syn c h r on ou s dce mode z d t e interface - asynchro nou s dte spee d up to 1152 00b ps - serial v.24 (eia-232-d) z integrate d uart 165 50 z enhan ce d ?a t? co mman d set and s re g i sters - tia/eia 602 itu v.25ter a t comm and set - tia/eia 578 fax cla ss 1,2 comma nd se t - tia/eia is-101 voice com m and set z parallel (isa/pci) and se ri al (ua r t) int e rfa c e s - 6, 7 and 8 bit cha r a c ter sup port - even, odd, mark and n one parity detectio n and gene ration - 1 and 2 sto p bit supp ort - auto dte dat a spe ed dete c tion z suppo rt calle r identificatio n (caller id) z spea kerpho n e z selecta b le world wide call pro g re ss tone detectio n z enhan ce d 80 32 co mpatibl e micro-co ntroller z powe r do wn mode z access up to 256k bytes e x ternal prog ram memo ry z access up to 64k bytes extern al data me mory z nvram to st ore two user config urable, sele ctabl e profiles with th ree programm able telepho ne nu mbers z 32k bytes sram built in parallel bus for embed d e d microproc essor com patible t o isa bus pci internal modem only z pci plug and play (pnp) suppo rt z com p liant wit h pci spe c ification 2.1 z com p liant wi th pci bu s powe r ma n agem ent interface spe c ificatio n revi sion 1.0 applica t ions : z mfp/fax machine, efax box z set-top - box (stb), reply chann el z electronic poi n t-of-sal e (e pos) z indust r ial/me dical m onitori ng devices z voice broadcasting de vices, utility meters z secu rit y sy st ems z fw t,cdma/ g sm/gprs w i reless fax nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in chip 1: integrated processor unit w i th pnp dm6 588 a de scription the dm 658 8 a modem co ntrol unit is d e sig ned for use in high spe ed intern al and external mode m appli c ation s . the dm65 88 a inco rpo r ate s a 80 c3 2 micro-co ntroll er, a virtual 1655 0a uart with fifo mode, an d plug & play co ntrol logi c. the dm6 5 8 8 a mcu p e rforms gen eral mod e m cont rol fun c ti ons, a nd i s also de sign e d to provide plug and play capability for pci bus systems. dm6588a block diagram dm6588a features ? cont rol interf ace sup p o r t ? suppo rts pa rallel and se ri al interfa c e s ? includ es a 8 0 c 32 mi cro-co ntrolle r ? 256k bytes m a ximum exte rnal program memo ry ? 32k bytes dat a memo ry bui lt in ? provide s auto m atic plug an d play or softwa r e configuration capabilities ? virtual 165 50 a uart com patible pa rall el interface ? fully prog ram m able seri al interfa c e: - 6, 7 or 8-bit cha r a c ters - even, odd, mark and n o n e parity bit gene ratio n an d detectio n - 1 and 2 stop bit generatio n - baud rate g ene ration - inclu d e s i/o control logi c for mode m co ntrol interface final 4 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 5 dm6588a external pin configur ation ud 0 ud 1 ud 2 ud 3 gn d rxdc l k ud 5 rd _ s p2 txd c l k gn d d s ptxd ou t p 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 11 8 11 9 12 0 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 vd d d m 6588 a ex t e r n a l 43 42 41 40 39 ou t p 2 ou t p 1 23 24 25 26 28 27 29 vd d gn d 31 32 33 34 36 38 35 37 52 51 50 48 49 47 46 45 44 58 57 56 55 54 53 64 63 62 61 60 59 11 5 11 6 11 7 osc o os c i 102 101 100 99 98 97 96 94 95 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 10 9 11 0 11 1 11 2 11 3 11 4 fr_ s p 1 /po r vo i c e s e l1 vo ice se l2 co de c _ c l k vd d 10 3 10 4 10 5 10 6 10 7 10 8 d3 d2 d1 d0 fr _s p2 gn d ud 4 vc c ud 7 ud 6 gn d d4 d5 ca1 vdd ca4 ca7 gn d ca6 ca5 ca3 ca2 ca0 d7 d6 ca9 ca1 0 ca1 1 ca1 2 ca1 3 ca1 4 ca1 5 ca8 rd _ s p1 ou t p 0 in p 2 in p 3 in p 0 in p 1 dsp r xd te st 1 r eset t est2 tes t 3 30 txsc l k gn d /r i ee pr om 3 ee pr om 2 ee pr om 1 /vo i c e /d t r /oh xt a l 2 xt a l 1 ca 17 /pw r vd d t1 t0 gn d ca 16 td _s p1 /r d /w r / p sen txd rx d vd d /l c s r xsc l k vc c gn d sc l k td_ s p 2 e x t /inb gn d ps1 in t # te st4 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 6 final version: dm562 ap-ds-f0 3 nov. 09, 2007 dm6588a isa pin configuration ud0 ud1 ud2 ud3 gnd ud5 gnd ua2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 11 8 11 9 12 0 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 v d d d m 6588 a is a 43 42 41 40 39 ua 1 ua 0 23 24 25 26 28 27 29 vd d gnd 31 32 33 34 36 38 35 37 52 51 50 48 49 47 46 45 44 58 57 56 55 54 53 64 63 62 61 60 59 11 5 11 6 11 7 osco os c i 102 101 100 99 98 97 96 94 95 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 10 9 11 0 11 1 11 2 11 3 11 4 fr_ s p 1 /p or voic e s e l 1 voic e s e l 2 co de c_ c l k vd d 103 104 105 106 107 108 d3 d2 d1 d0 fr _ s p 2 gn d ud4 vc c ud7 ud6 gnd d4 d5 ca 1 vd d ca 4 ca 7 gnd ca 6 ca 5 ca 3 ca 2 ca 0 d7 d6 ca 9 ca 1 0 ca 1 1 ca 1 2 ca 1 3 ca 1 4 ca 1 5 ca 8 io r b io w b cs n ir q te st 1 rs t # test2 test 3 30 ri n gnd tx sc l k ee pr o m 3 ee pr o m 2 eep ro m 1 /v o i c e /d tr /o h xtal 2 xtal 1 ca 1 7 /pw r vdd gn d ca 1 6 td_sp 1 /r d /w r /psen r d _sp1 rd_ s p 2 vd d sc l k r xsc l k vc c gn d td _s p2 e x t/in b gn d ps 1 tes t4
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 7 version: dm562 ap-ds-f0 3 nov. 09, 2007 dm6588a pci pin configuration ad 27 ad 26 ad 25 ad 24 gnd ids e l c/ b e 3 # ad 22 ad 16 c/ be 2# fr ame# gnd ir dy# trdy # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 11 8 11 9 12 0 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 ad 28 vd d dm6588 a pci ad 3 1 ad 30 ad 29 43 42 41 40 39 d evse l # sto p # 23 24 25 26 28 27 29 vd d gn d 31 32 33 34 36 38 35 37 52 51 50 48 49 47 46 45 44 58 57 56 55 54 53 64 63 62 61 60 59 11 5 11 6 11 7 os c o os ci 10 2 10 1 100 99 98 97 96 94 95 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 10 9 11 0 11 1 11 2 11 3 11 4 fr_ s p1 /po r vo ic e s e l 1 vo i c e s e l 2 co de c_c l k vd d 10 3 10 4 10 5 10 6 10 7 10 8 d3 d2 d1 d0 fr _ s p2 gn d ad 2 3 ad 17 ad 1 8 ad 19 vc c ad 20 ad 21 gn d ad 1 d4 d5 ca 1 vdd ca 4 ca 7 gn d ca 6 ca 5 ca 3 ca 2 ca 0 d7 d6 ca 9 ca10 ca11 ca12 ca13 ca14 ca15 ca 8 c/ b e 1 # par s e rr# p e rr# ad 1 4 ad15 ad12 ad 13 ad 11 po w e r o ff te s t 1 rst # tes t 2 test 3 30 rin gnd txs c lk ee p r om3 ee p r om2 ee p r o m 1 /v o i c e /d tr /o h xta l 2 xta l 1 ad1 0 ad8 ad9 ca 17 /p w r vd d c/ b e 0 # ad 6 ad 7 gn d ca 16 td _sp 1 ad 4 ad 5 ad 2 ad 3 /rd /w r /psen rd _s p 1 rd _s p 2 vd d sclk ad 0 r xsclk vc c pm e # gnd pc lk td _sp 2 e x t/i nb gn d ps1 in t # tes t4
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 8 final version: dm562ap-ds-f03 nov. 09, 2007 dm6588a pin description pin no. external pin no. internal pci pin no. internal isa pin name i/o description 1 1 1 test4 i test pin 4, normal ground. external: n/c (low). pci: n/c (low). isa: connect to 3.3v. 2,3,4,5, 9,10,11, 12 ud0 - ud7 o modem control output , for external modem: memory address mapping of the controller is e800h. 8 rxdclk i receive data rate clock:(external) this pin is used as reference clock of dsprxd pin. 18 68 68 rd_sp2 i data input pin of the serial port 2: the serial data is sampled at the falling edge of the sclk. the msb is coming immediately after the falling of fr_sp2 signal. 19 txdclk i transmit data rate clock:(external) this pin is used as reference clock of dsptxd pin. 21 dsptxd i modem transmit data (external) shifted into tx /rx dsp from eia port through this pin at the rising edge of txdclk. 28 69 69 rd_sp1 i data input pin of the serial port 1: the serial data is sampled at the falling edge of the sclk. the msb is coming immediately after the falling of fr_sp1 signal. 6,20,37 50,77,80, 89,107, 118,123 6,20,37 50,80,89 107,118, 123 6,20,37 50,77,80, 89,107, 118,123 gnd p ground 22, 23, 24, 25 outp3, outp2, outp1, outp0 o modem control output for external modem, these pins are bit7~4 of the modem control output. memory address mapping of the controller is c800h. 29, 30, 31, 32 inp3, inp2, inp1, inp0 i modem control input:(external) these pins are bit3~0 of the modem control input. memory address mapping of the controller is c800h. 33,45 67,94, 113,128 33,45, 67,94, 113,128 33,45, 67,94, 113,128 vdd p +3.3v power supply 13,74 13,74 13,74 vcc p +2.5v power supply 34 34 34 test2 i test pin 2,normal ground 35 35 35 test3 i test pin 3,normal ground 36 reset i reset: an active high signal used to reset the dm6588a. 42 42 42 xtal1 i crystal oscillator input
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 9 version: dm562ap-ds-f03 nov. 09, 2007 43 43 43 xtal2 o crystal oscillator output 46 46 46 /pwr o controller program write enable: this pin is used to enable flash rom programming. 48 48 48 td_sp1 o data output pin of serial port 1 the serial data is clocked out through this pin according to the rising edge of sclk. the msb is sent immediately after the falling edge of the fr_sp1 signal. 49 47 49 47 49 47 ca16 ca17 o bank switch control: these signals are used to sw itch external program memory between banks. ca16 ca17 bank 0 0 0 bank 1 1 0 bank 2 0 1 bank 3 1 1 51 t0 i controller counter 0 input 52 t1 i controller counter 1 input 57 76 76 /ri i ring signal input 76 57 57 txsclk*2 i txdsp interrupt 1 input 58 58 58 /dtr i dtr input pin (p1.1) 59 59 59 /oh o hook relay control (p1.2) 60 60 60 /voice o voice relay control. modem control output (memory map is bit 3 of daa at memory address d000h) 61-63 61-63 61-63 eeprom 1-3 i/o eeprom control pins (p1.4-p1.6) 66 /lcs i loop current detection. modem input control: this pin is mapped to bit0 of address d000h. 79 66 66 sclk i reference clock for serial port 1 and serial port 2 68 rxd i controller serial port data input 69 txd o controller serial port data output 70 70 70 rxsclk i rx dsp interrupt 3 input 71 71 71 /psen o controller program store enable: this output goes low during a fetch from external program memory. 72 72 72 /wr o controller external data memory write control 73 73 73 /rd o controller external data memory read control 78 dsprxd o modem received data : (external) shifted out to the eia port through this pin according to the rising edge of rxdclk. 117 117 117 test1 test pin 1, normal ground 81,82, 83,84, 85,86, 87,88 81,82, 83,84, 85,86, 87,88 81,82, 83,84, 85,86, 87,88 ca15,ca14, ca13,ca12, ca11,ca10, ca9,ca8 o controller address bus
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 10 final version: dm562ap-ds-f03 nov. 09, 2007 90,91, 92,93, 95,96, 97,98 90,91, 92,93, 95,96, 97,98 90,91, 92,93, 95,96, 97,98 ca7 - ca0 o controller address bus 99,100, 101,102, 103,104, 105,106 99,100, 101,102, 103,104, 105,106 99,100, 101,102, 103,104, 105,106 d7,d6, d5,d4, d3,d2, d1,d0 i/o controller data bus 108 108 108 fr_sp2 i/o frame signal of serial port 2 109 109 109 fr_sp1 i/o frame signal of serial port 1 110 110 110 /por o dsp reset output 111 112 111 112 111 112 voice se1 1 voice se1 2 o modem control output memory map is bit 1-2 of daa at memory address d000h 114 114 114 codec_clk o 20.16mhz clock output for dm6580 chip 115 115 115 osco o optional codec x?tal clock output 116 116 116 osci i optional codec x?tal clock input 117 117 117 test1 i test pin 1,normal ground 119 119 119 td_sp2 o data output pin of serial port 2 the serial data is clocked out through this pin according to the rising edge of sclk. the msb is sent immediately after the falling edge of the fr_sp2 signal. 120 120 120 ps1 o modem control port select output: memory address mapping of the controller is d800h. 122 122 122 ext/intb i select pin: used to select internal or external operation. 0: internal modem, pci or isa. 1: external modem 7,14,15, 16,17,26, 27,38,39, 40,41,44, 53,54,55, 56,64,65, 75,121, 124,125, 126,127 7,8, 14,15,16, 17,21,25, 26,27,28, 32,38,39, 40,41,44, 51,52,53, 554,55,56, 64,65,75, 79,121, 124,125, 126,127 nc n nc
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 11 dm6588a pin description- isa interface only pin n o . pin n a me i/o d e scription 2-5, 9-1 2 ud0-ud3, ud4-ud7 i/o da ta bu s si gnal : the s e si gnal s are co nne ct ed to the dat a bus of the pc (o r ho st) i/o. they are u s e d to transfe r data between the pc and the dm 658 8a. 2 2 - 2 4 u a 0 - u a 2 i sy stem address : the s e si gnal s are co nne ct ed to the bu s of pc (or ho st) i/o. they are u s e d to sele ct the dm 6588a offset uart i/o ad dre s s. 2 9 / i o w b i i/o w r ite: an active low input sign al use d to write data to the dm658 8a. 3 0 / i o r b i i/o r ead : an active low input sign al use d to rea d data from the dm65 88a. 3 1 / c sn i addr ess ena b le: this i s an a c tive low sig nal to enable the system a ddre ss fo r dm6 5 8 8 a. 3 6 / r s t i res e t : an active low signal u s e d to re set the dm658 8a. 7 8 i r q o interrup t r e ques t: the active pi n will go high when an inte rrupt request is generat ed from the dm6 588a. version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6588a pin description-pci interface only pin n o . pin n a me i/o d e scription 7 8 p o w e r o f f o po w e r off w h en high 1 2 1 i n t # o pc i interrupt r e quest this sign al wi ll be asse rted low wh en an interrupt co nd ition as defin ed in cr5 is set an d the co rre sp ondin g ma sk bit in cr7 i s not set. 7 9 p c l k i pci sy stem clock this sign al is the pci bus clock that prov ides timin g for all bu s pha ses. the freq uen cy is 33mhz. 7 5 p m e # o po w e r man a gement ev ent the si gnal in dicate s that a powe r man a geme n t event. 124 -12 7 ,2-5 9-1 2 ,14-17 29-32,38 -41 51-56,64,6 5 ad 3 1 - a d 0 i / o pci addre s s & da ta bu s the s e are the multiplexed address an d data sig nal s. dm6 588a will deco de ea ch address on t he bu s and re spo nd if it is the targ et being a d d r e s sed. 7 idsel i initializ ation d e v i ce select for the a c cesse s to the co nfigurati on ad dre s s sp ace, the device sel e ct de codi ng is d one externall y and is sig n a l ed via this pi n. this si gnal is asse rted high du rin g configu r ation read an d write access. 8 18 28 44 c/be3# c/be2# c/be1# c/be0# i pc i b u s command/b y te enable du ring the a d d re ss pha se, these sign als define the bu s co mman d o r the type of the bus tran saction that wil l take pla c e. du ring the d a t a phase, these pin s indi ca te which byte lane s co ntain valid data. c/be0# appli e s to bit7~0 a nd c/be3# a pplie s to bit 31~2 4 . 1 9 f r a m e # i pci c y cle frame this sign al is driven lo w by the maste r to indicate the b eginni ng an d duration of a bus tra n saction. it is de-a s serte d when the tra n saction i s in its final phase. 2 1 i r d y # i pc i initiator r e ad y this sign al is driven lo w wh en the ma ster is rea d y to complete the current data pha se of the tran sa ction. a data pha se i s c o mpleted on any c l oc k both ir d y # and t rdy# a r e sample d a s serte d . 2 2 t r d y # i / o pc i target read y this sign al is driven lo w wh en the targ et is re ady to co mplete the cu rre nt data pha se of the tran sa ction. durin g a rea d , it indicate s that the valid data is asse rte d du ring write, it indicate s that t he target pre pares to a c cept data. 2 3 d e v s e l # i / o pci dev i ce select dm6 588a a s se rts the si gn al low when it recogni ze s its targ et address after frame# is asserted. 2 4 s t o p # i / o pci stop this sign al is asse rted lo w by the target device to req uest the ma st er devi c e to stop the curre n t transactio n . 2 5 p e r r # i / o pci parit y er ror dm6 588a will assert this si gnal lo w to indicate a p a rit y erro r on an y incomin g data. 2 6 s e r r # o pci sy stem error this sign al is asse rted lo w whe n an ad dr ess pa rity is detected with pcics bit31 enabl ed. the system e r ror asse rts two cl ock cycl es aft e r the ad dre s s if an add re ss p a rit y erro r is dete c ted. 12 final version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 13 2 7 p a r i / o pci parit y this sign al in dicate s even parity across ad0~ ad31 and c/be0#~c/be3# inclu d ing the par pin. it is stable a nd va lid one cl ock after the add ress pha se. 3 6 r s t # i res e t : an active low signal u s e d to re set the dm658 8a. 7 6 r i n i ring signal input for auxiliar y po w e r 7 7 g n d _ a u x p auxiliar y gr ound version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 14 final dm6588a functional description 1. opera t ing mode selec t ion the dm 658 8 a can be u s e d in intern al o r external modem a ppli c ation s . wh e n ope rating a s an inte rnal modem, the ext/intb input (pin 12 2) must be attache d to ground, an d vice versa (vdd) wh en ope rating a s an extern al modem. external mode is operated w i th hos t by u a r t . internal mo de can supp ort parallel (isa) and pci interfa c e to h o st. the test4 input ( pin 1) is for isa or pci sel e cti on. 2. micro-con t roller progr am memory the dm 658 8 a supp orts two ban k switch control pin s to switch external p r og ram memo ry amo ng four ban ks. th e dm658 8a can acce ss a total of 256k of external p r og ram mem o ry. addre s s map p ing: bank0: 00000 h - 0 ffffh bank1: 10000 h - 1 ffffh bank2: 20000 h - 2 ffffh bank3: 30000 h - 3 ffffh for ba nk swit chin g, three i n structio ns m u st be inclu ded in so ftware. sw itc h to bank 1: c l r p 1 . 3 s e t b p 1 . 7 jmp b a nk 1 address sw itc h to bank 2: c l r p 1 . 7 s e t b p 1 . 3 jmp b a nk 2 address sw itc h to bank 3: c l r p 1 . 7 c l r p 1 . 3 jmp b a nk 3 address r e turn to bank 0: s e t b p 1 . 7 s e t b p 1 . 3 jmp bank 0 address * for detail e d information a bout the micro-controlle r, refer to the program m e r's guide to 80 3 2 . 3. micro-con t roller po w e r do w n mod e an inst ru ct io n t hat set s t h e regi ster pd (pco n.1) wil l cau s e the 80 c32 to enter power do wn mode. there are three ways to wa ke up the 80c32 (1) po sitive p u lse sign al o c curring at th e re set pin of the 80c32 (2) ne gative pulse occu rri ng at /ri (p1.0) of the 80c32 (3) program ming the pnp wake up controll e r regi ste r . 4. enhanced internal dire ct memory there a r e two 1 28 byt e ban ks of intern al direct memo ry in the 80 c3 2. the sy stem u s e s the lo we r 128 bytes u n der no rmal condi tion s. switching to the uppe r ba nk i s achieved by loading registe r 8f h.1 (sfr of the 80c32 ) with 1. switchi ng to the lo we r ban k ca n be achieve d by loading the sam e regi ste r w i th 0. 5. re-flash p r ogram mem o ry by setting 8f h.2 the sy ste m can switch prog ram and data me mory . if the syste m uses fla s h mem o ry as pro g ra m me mory this fu nction i s u s ed to re -flash pro g ra m co d e by downl o ading the p r ogram to data memo ry then swit chin g the m . example: s e t b 8 f h . 2 ljmp 0000h 6. micro-controller i/o d e scription modem e x p a nsion por t: addr ess c80 0 h (external only ) bit7 bit6 bit5 b i t 4 b i t 3 b i t 2 b i t 1 bit0 out p3 out p2 out p1 out p0 in p 3 i n p2 in p1 in p0 bit0 to bit3: read only bit4 to bit7: w r ite onl y modem outp ut port 1 re gister : add r ess d000 h write only bit7 bit6 bit5 bit4 bi t 3 b i t 2 bit1 bit0 / v o i c e voice -sel2 voice -sel1 /por version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 15 version: dm562 ap-ds-f0 3 the s e 4 bits cont rol the dm658 8a outp u t ports. modem outp ut port 2 re gister : add r ess d800 h write only b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 bit2 bit1 bit0 /mu t e /pu l se /c id the s e 3 bits cont rol the dm658 8a outp u t ports. memor y mapping of micro-controller 80c32 : addr ess des c ri pti o n extern a l i n t e r n a l c 8 00h g p i o ou tp3-ou tp0(bit7 ~ 4 );inp3~ i n p 0 ( b i t 3 ~ 0 ) y n d 0 0 0 h d a a p o r t y y d40 0 h uart clo ck regi st e r n y d80 0 h ps1 port (mo dem hybri d ci rcuit control p o rt) y y d c 0 x h h d l c regi ste r s y y e000 h modem uart status regi ster n y e400h /rucs port(rx dsp du al port regi sters) y y e800 h modem le d output port ud7 ~ ud0 y n ec00 h uart ba ud gene rato r di visor l a tch registe r n y f000h /tucs port (tx dsp dual port regi ster) y y f80xh pci vende r & device id po rt regi ster n y nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 16 final version: dm562 ap-ds-f0 3 7. hdl c d e s c ri pti on hd lc rx dat a bi t s regi s t er: a ddre ss dc 00 h write only once the r x d a tabit s e t to 1, the data in the r x buffer will be transferred to rxfi fo. the transfer bit numb e r is the same a s the pro g ra mming value of r x d a tabit s regis t er. hd lc rx buf f er : addr ess dc0 1h write only receive data will be written to the rxbuffer and will be input to the rxhdl c ci rcuit. the rxb u ffer is 16 bytes w i de. hd lc rxfi f o : add r es s dc 01 h rea d only after the data has be en pa ssed from the rxbuffer to the rxhdlc circuit, the rx hdlc circuit will remove the 7eh p a ttern s and tra n sf er the re sult s to the rxfifo. there rxfifo is 21 bytes wi de . hd lc tx da t a bi t s regi s t er: a ddre ss dc 02 h write only data written to txdatabits will be presented to the txfifo. the data in txfi fo will be transferred to txhdlc circuit. the transf e r bit numb e r is the sam e as the value of txdatabits regi ster. if th e txfifo is empty , a 7e pattern will be loaded to the txfifo. if txfifo is not empty and the data frame has the pattern of five con s e c utive ?1? , then the txhdlc circuit will insert ?0? automatically. hdlc tx fifo regis t er : addr ess dc03h write only the ori g inal hdlc frame data will be loaded to the txfifo, presented to the input of the txhdlc circuit. the txfifo is 21 bytes wi de. hd lc tx bu f f er : addr ess dc0 3h rea d only accordi ng to txdatabits, the txhdlc circuit will tran sfer the same num be r data bits to the txbuffer. the txbuffer is 16 bytes wi de. hdlc cnt l/stat us re gister : add r ess dc0 4 h bit0:txready 0 0: indicate s the data in the txfifo has decea sed to zero and th e hdlc circu i t has tran sferred the 1 st 7eh pattern. 1:indicates th at the txfifo data is g r e a ter than or eq ual to the thre shol d value. bit1:rxdata 0: all the data in the rxbuffer ha s be en read. 1:prog rame d by softwa r e to indicate tha t all data in the rxdata bits regi ster h a s be en written to the r x buffer. bit2:txfifo thres h old 0: txfifo thresh old no. = 11 1: txfifo thresh old no. =16 bit3:txfifo status 0:data no. in txfifo >= th re shol d 1:data no. in txfifo <= th re shol d bit4:txdata 0:a write acti on to txdatabites regi ster will clear this bit. 1:bit n o . in txbuffer = txdatabits regis t er. bit5: r x fifo empty 0:data bytes no. in rxfif o <>0 1:data bytes no. in rxfif o = 0 bit6: r e s e t 0:no rmal stat e 1:res e t hd lc c i rc uit zero deletion in _ buffer register: ad dress dc 08 h write only cont rolle r wri t e the origin al data to this temp buffer. zero deletion out _ buffe r registe r : addres s dc 08 h rea d only c ont roller read the res u lt data from this buffer zero deletio n statu s /rs t register: ad dress dc09 h bit0: data rea d y flag (rea d only) 1:data ha s be en load to out _ buffer. (c lear automati c ally by a read f r om out _ buffer) 0: data has n o t been loa d to out _ buffer. nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 17 bit1: frame end flag (read only) 1:indic a te end of h d l c frame (c lear by a res e t action ) bit2: fram ready flag (read only) 1: cr c c h e c k ok. 0: cr c c h e c k f a il. bit3: in _ buffer empty flag 1:in _ buffer empty (c lear automatically by a w r ite to in _ buffer) 0:in _ buffer not empty bit7: res e t bit (write only) 1:s o ftw are res e t crcl re gister: addre ss dc0ah (r ea d only ) crch regis t er: addre ss dc0bh (r ea d only ) 8. micro-co ntroller con t rol register for intern al mode uart clock (inter nal mode only ) the internal clock of the virt ual uart lo gic is fixed at 1.8432 mhz. the cl ock is d e rived fro m a n external 30m hz crystal. the uart 1.8432mhz cl ock will be obtaine d by division. wh en the operating freque ncy of the dm65 8 8 a controlle r cha nge s, the divider sho u ld be ch ange d acco rd ingly. this div i der i s spe c ified by the co nfigu r at ion re giste r whi c h can be written by the dm65 88a co ntrolle r. the add re ss mappi ng of the regi ster i s d40 0 h: (dm6 588a cont rolle r me mory map p in g) bit 0: always 0. bit 6-1: define the clo ck di vider ra nge from 2 to 64 (ev en n u mbe r). bit 7: n o t us ed. ua rt cl ock regi s t e r: ( intern al mode only ) addre s s d4 0 0 h reset state: 06h write only b i t 7 b i t 6 b i t 5 bit4 b i t 3 b i t 2 bit1 bit0 x d a t 6 d a t 5 d a t 4 d a t 3 d a t 2 dat1 0 uart baud gener a to r di v i sor latch regis t er : addr ess ec00h ( intern a l mode only ) rea d only bit7 bit6 bit5 bit4 bi t 3 b i t 2 bit1 bit0 dat7 dat6 dat5 dat4 d a t 3 d a t 2 dat1 dat0 by reading thi s re giste r , the micro - control l er can monitor the v a lue of the lo w byte diviso r latch of the virtual ua rt baud gen erat or (se e dll i n next se ctio n) and dete r min e the baud ra te clock itself. modem sta t us con t rol registe r (mscr): addr ess e00 0 h ( internal mode only ) write only bit7 bit6 bit5 bit4 bit3 b i t 2 b i t 1 bit0 0 0 0 0 / c t s / d s r / d c d /ri this regi ster contai ns info rmation ab out the line status of the modem. th e available sign als a r e ri ng dete ct (/ri), ca rrie r dete ct (/dcd), dat a set ready (/dsr) an d clear to se nd (/cts). 9. host con t rol register for virtual 16 550 a uart (inter nal mode only ) r e ceiv er b u ffer (r ead), transmitter holding r e gist er (w rit e ): addr ess : 0 (dlab=0) re set state 00h bit7 bit6 bit5 bit4 bi t 3 b i t 2 bit1 bit0 dat7 dat6 dat5 dat4 d a t 3 d a t 2 dat1 d at0 whe n this re giste r add re ss is read, it contain s the parallel re cei v ed data. dat a to be tran smitted is w r itten to this regis t er. interrup t en able regis t e r (ier): addr ess 1 re set state 00h, write o n l y bit7 bit 6 bit 5 bit4 b i t 3 b i t 2 b i t 1 bit0 0 0 0 0 e n a b l e modem status intr enab le line status intr enab le tx hold ing register intr enab le rx data intr this 8 - bit re gi ster e nabl es t he four type s of interru pts as de scri bed belo w . each i n terrupt so urce can activate the int outp u t sig nal if enable d by this regi ster. resetting bits 0 through 3 will disable all u a r t interrupts . bit 0: this bit en abl es the received data avail able and timeo u t interrupts in th e fifo mode when s e t to logic 1. version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 18 final version: dm562 ap-ds-f0 3 bit 1: this bit en abl es the tran smitter holdi n g regi ste r emp t y interrupt when set to logic 1. bit 2: this bit en abl es t he receiver lin e status interrupt w h en s e t to logic 1. bit 3: this bit en abl es the mo de m status interru pt w h en s e t to logic 1. bit 4-7: not used interrup t ide n tifica tion registe r (iir): addr ess 2 re set state 01h, rea d onl y b i t 7 b i t 6 b i t 5 b i t 4 bit3 b i t 2 b i t 1 bit0 fifo enab le 0 0 0 d 3 : int d 2 d2: int d 1 d1: int d 0 d0: int pend ing in ord e r to provid e mi nimum software overhea d duri ng data tran sfers, the virtual ua rt pri o riti ze s interrupts i n to four level s as follo ws: re ceive r lin e status (p rio r ity 1), re ceive r data avail a ble (p rio r ity 2), cha r a c ter ti meout indi ca tion (p rio r ity 2, fifo mod e only), tran smitter ho ldin g re giste r e m pty (pri ority 3), and mo dem status (p riorit y 4). the iir regi st er give s prio ri tized info rmat ion reg a rdi ng the status of inte rru pt con d itio ns. wh en acce ssed, the iir indicate s the high est prio rity interrupt that is pen ding. bit 0: this bit ca n be used in either a pri o ritized interrupt o r polled env ironm ent to indicate wheth e r a n interru pt is pen ding. wh en this bit i s logic 0, an interrupt is pendin g , and the iir conte n ts m a y be u s ed as a poi nter to the app rop r iate i n terrupt servi c e routin e. whe n bit 0 is logic 1, no interrupt is pendi ng, and polling (if use d ) conti nue s. bit 1-2: these two bits of the iir are u s ed to ide n tify the highe st priority int e rrupt pe ndi ng, as indicated in the table bel o w . bit 3: in cha r a c ter mode, this bit is 0. in fifo mode, this bit is set, along with bit 2, when a tim eout interrupt is pe nding. bit 4-6: not used bit 7: fifo always e nabl ed . interrup t ide n tifica tion registe r (iir): addr ess 2 (c ontinued ) d3 d2 d1 d0 priorit y le v e l interrup t t y pe condition res e t 0 0 0 1 - - - - 0 1 1 0 high e s t re ceive r line status ov err un er ror , parity error, frami ng erro r or bre a k interrupt rea d s the li ne status regi ste r 0 1 0 0 seco n d re ceiv e r dat a available re ceive r dat a available or t r ig ge r le ve l r e ac he d r e ads the r e c e iver buffer regi ste r or th e fifo has dropp ed belo w the thre shol d value 1 1 0 0 seco n d c h ar ac te r timeout indi cation no cha r a c ters have be en read from or w r itten to the rx fifo duri ng programming time interval, and the rx fi fo is not empty rea d s t he r e ceiv e r buf f e r regi ste r 0 0 1 0 t h i r d trans m itter holdi ng regi ster empty rea d y to accept new d a ta f o r t r an smi ssi on rea d s the iir regi ster o r (if s o urce of interrupt) write s to th e tran smitter holdi ng regi ster 0 0 0 0 f o u r t h modem statu s c l ear to send, d a ta set rea d y, ring indicator o r d a ta carrier d e tec t ed rea d s the m odem status regi ste r nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 19 fifo con t rol register (f cr): addr es s 2 re set state 00h , write onl y bit7 b i t 6 bit5 bit4 bit3 bit2 bit1 bit0 rcvr tr i g (msb) rcvr tr i g (lsb) 0 0 dma mode tx f i f o reset rx fifo reset fifo enab le this is a writ e only registe r at the same location a s the iir, which is a read o n l y registe r . this regi ste r is use d to e nab le the fifo s, clea r the fifos, set the rxfifo trig g e r level, a n d sele ct the t y pe of dma sign al. bit 0: fifo enable, this bit is al ways hi gh bit 1: writin g a 1 to fcr1 cl ea rs all bytes in the rxfifo and reset s the co u n ter logi c to 0 . bit 2: writin g a 1 to fcr2 cl ea rs all bytes in the txfifo and reset s the co u n ter logi c to 0 . bit 3: setting fcr3 to 1 will cause the rx rdy and txrdy pi ns to chan ge fro m mode 0 to mode 1 if fcr0 = 1 . bit 4-5: reserved bit 6-7: fcr6, fcr7 are u s ed t o set the tri gge r level for the r x fifo interrupt. fcr7 fcr6 rxfifo trig ger lev e l 0 0 0 1 0 1 0 4 1 0 0 8 line con t rol register (l cr): addr es s 3 re set state 00h, write o n l y b i t 7 b i t 6 b i t 5 bit4 b i t 3 b i t 2 bit1 bit0 d l a b s b r k s t p e p s p e n s t b w l s1 w l s0 this regi ster is availabl e to maintain compatibility with the stan dard 1655 0 r egiste r set, and provid es informatio n t o the inte rnal hardware th at is u s e d to determi ne the numbe r of bits pe r ch ara c t e r. w l s 1 w l s 0 w o r d le n g t h 0 0 5 b i t s 0 1 6 b i t s 1 0 7 b i t s 1 1 8 b i t s bit 0-1: wls0-1 spe c ifies the numbe r o f bits in each tran smitted a nd re ceive d serial cha r a c te r. bit 2: stb sp ecifie s the nu mber of sto p bits in ea ch tran smitted characte r. if bit 2 is logic 0, one stop bit is ge nerated in the transmitted d a ta. if bit 2 is logi c 1 wh en a 5 - bit wo rd l e n g th is sele cted via bits 0 and 1, o ne and a half stop s are g ene rate d. if bit 2 is a logic 1 when either a 6-, 7- or 8-bit word len g t h is sele cted , two stop bits a r e gene rate d. the re ceive r che c ks the first stop-bit only, regardle s s of the numb e r of stop bits sele cted. bit 3: logi c 1 in dicates that the pc ha s en able d parity gen erat ion and che c king. bit 4: logi c 1 indicates that the pc is reque st ing an even numb e r of logic 1s (even parity gene ratio n ) to be transm i tted or che c ked. logi c 0 indicates that the pc is requesting odd pa rity ge neration an d che c king. bit 5: whe n bits 3, 4 and 5 are l ogic 1, the pa rity bit is transmitted and che c ked by the receiv er as logic 0. if bits 3 and 5 are 1 and bit 4 is logic 0, then the p a rit y is tran smitted an d che c ked a s logic 1. bit 6: this i s a bre a k control bi t. when it is set to logic 1, a b r e a k conditio n is indi cated. bit 7: the divi sor latch a c cess bit must be set to logic 1 to a c ce ss th e divi so r lat che s of the baud ge nerator duri n g a read or write ope ration. it must be set to logic 0 to a c cess the re ceive r buffer, the tran smitter holdi ng regi ste r , or the interrupt enable regi ste r . version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 20 final version: dm562 ap-ds-f0 3 modem con t rol register (mcr): addr ess 4 re set state 00h b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 bit1 bit0 0 0 0 0 0 0 rts d t r bit 0: this bit a s se rts a da ta termi nal rea d y con d ition that is reada ble via port p1.1 of th e micro-co ntroll er 80 c3 2. when bit 0 i s set to logic 1, the p1.1 is forced to logi c 0. whe n bi t 0 is reset to logic 0, the p 1 .1 is forced t o logic 1. bit 1: this bi t asserts a reque st to s end con d ition that is read a b le via port p3 .4 of the micro-co ntroll er 80c32. wh en bit 1 is set to logic 1, the p3.4 is forced to logic 0. when bit 1 is reset to logic 0, the p3.4 is forced to logi c 1. line statu s regis t er (lsr): add r es s 5 re set state 60h, rea d onl y b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 bit0 r c v e t e m t t h r e b i f e p e oe dr this re giste r provid es stat us inform atio n to the host pc co ncerni ng characte r transfe r. bit 1-4 in dicate s error conditi o n s that pro d u c e a receive r line status interrupt wh eneve r any of the correspon ding con d ition s are detecte d. t he line statu s re giste r is valid for read operations only. bit 0: set to logic 1 when a re ceived cha r a c ter is available i n the rxfifo. this bit is re set to logi c 0 whe n the rx fifo is empt y. bit 1: an overrun error will occur only after the rxfifo is full and the next chara c ter h a s overwritte n the un rea d fi fo data. t h i s bit i s reset upon re adin g the line status regi ster. bit 2: a logic 1 in dicate s that a re ceive d characte r doe s not ha ve the corre c t even or odd p a rity a s sele cted by the parity se lect bit. this error is set whe n the corre s po ndin g characte r is at the top of th e rxfifo. it w ill remain set until the cpu reads the lsr. bit 3: this bit is the frami ng er r o r (fe) in dic a tor. bit 3 indicates that the received characte r did not have a valid stop bit. bit 3 is set to logic 1 whe n e ver the sto p bit followin g the la st data bit or p a rity b i t is dete c ted as a ze ro bi t (spa cing le vel). the fe bit is reset whe neve r the cpu read s t he conten ts of the line status regi st er. the fe erro r con d ition is asso ciate d with the pa rticula r charact e r in the fif o to whi c h it applie s. thi s erro r is reve aled to the cpu whe n its asso ciated ch ara c ter i s at the top of the fifo. bit 4: this bit is a brea k interru pt (bi) indicator. bit 4 is set to logi c 1 wh eneve r the re ceive d data inp u t is held in the spaci ng (lo g ic 0) state for longe r than a full w o rd trans m is s i on time (that is , the total time of start bit + d a ta bits + p a rity + stop bits). th e bi indicator i s re set when e v er the cp u read s the conte n ts of the lin e status regi ster. the bi error con d ition i s a s soci ated wit h the p a rticul ar cha r a c ter i n the fifo to whi c h it applies. this erro r is revealed to the cp u wh e n its a s soci ated cha r a c ter is at the top of the fifo. bit 5: this bit is a t r an smitter ho lding regi ster empty indicator. bit 5 indicat e s th at uart is re ady to acce pt a new cha r a c ter for tran sm issi on. in add ition, this bit cau s e s the uart to issue an inte rru pt to the cpu whe n the tra n smit hol d in g regi ster empty interrup t enable i s set high. the t hre bit is re set to logic 0 whe n the host cpu lo ads a ch ara c ter into the tran smit hol d ing re giste r . in the fifo mode, this bit is set when the txfifo is em pty, and is cl eare d whe n at least 1 byte is written to the txfifo. bit 6: this bit is the tran smitter empty indicat o r. bit 6 is set to logic 1 when eve r the transm i tter holding regi ste r (t hr) i s empty, and is re set to logic 0 whe neve r the thr cont ains a ch ara c ter. in fif o mode, this bit is set to 1 wheneve r the tran smit fifo is empty. bit 7: in chara c te r mode, this bit is 0. in fif o mode, this bit is set whe n there is at lea s t on e parity erro r, framing e rro r, or brea k indi cation in the fifo. if there are no sub s eque nt erro rs in the fifo, lsr7 is clea re d wh en the cpu re a d s the ls r. nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in final 21 modem sta t us regis t er (msr): add r e ss 6 re set state bit 0-3 : low , bit 4-7: input signal b i t 7 b i t 6 b i t 5 bit4 b i t 3 b i t 2 bit1 bit0 dc d r i d s r c t s dd c d teri dds r d c t s this 8 - bit re giste r provid es the curre n t state of the cont rol line s from the mod e m to the cpu. in addition, four bits of the modem status registe r provi d e cha nge info rmation. the s e bits are set to logic 1 whe neve r a cont rol input from the modem ch ang e s state. they a r e re set to lo gic 0 when e v er the cpu rea d s the mo dem status registe r . bit 0: this bit is t he delta cl ear to sen d (dcts) indicator. bit 0 indicate s that the cts (msr bit 4) has cha nge d state sin c e the last time i t was read b y t he cpu. bit 1: this bit is th e de lta data set ready (ddsr) indicator. bit 1 indicate s that the dsr (msr bit 5) has cha nge d state sin c e the last time i t was read b y t he cpu. bit 2: this bit is the trailing ed g e of ring indi cato r. bit 2 indi cate s th at the ri (ms r bit 6) h a s chang ed from a low to a hig h state. bit 3: this bit is the delt a d a ta car r i er d e t e c t (d dcd ) indicator. bit 3 indicate s that the dcd (msr bit 7) has cha nge d state. not e : whe neve r bit 0, 1, 2 or 3 is set to logic 1, a modem statu s interrupt is gene rate d. bit 4: this bit reflec ts the value of msr bit 4 (c ts). bit 5: this bit reflec ts the value of msr bit 5 (d sr ). bit 6: this bit reflec ts the value of msr bit 6 (r i). bit 7: this bit reflec ts the value of msr bit 7 (d cd ). scratch re gister (scr): addr ess 7 re set state 00h this 8-bit re ad/write reg i ster doe s n o t control the uart i n any way. it is in tended as a scrat c h pa d regi ste r to b e used by t he programm e r to hol d d a ta temporarily. div i sor latc h (dll ): add r ess 0 (dl a b = 1 ) re set state 00h bit7 bit6 bit5 bit4 b i t 3 b i t 2 bit1 bit0 dat7 dat6 dat5 d a t 4 d a t 3 d a t 2 dat1 dat0 this re giste r contai ns ba u d rate inform ation from the host pc. th e pc set s the divisor l a tch regi ste r values. div i sor latc h (dlm ): ad dress 1 (dl ab = 1) re set state 00h bit7 bit6 bit5 bit4 b i t 3 b i t 2 bit1 bit0 dat7 dat6 dat5 d a t 4 d a t 3 d a t 2 dat1 dat0 this re giste r contai ns ba u d rate inform ation from the hos t pc . not e : two 8 - bit latches (dll-dl m) sto r e the diviso r in 16-digit bina ry format. the desired bau d rate can b e obtaine d by dividing th e 115 200 hz clo ck by the diviso r. desir e d baud ra te di v i sor value 5 0 2 3 0 4 7 5 1 5 3 6 1 1 0 1 0 4 7 1 5 0 7 6 8 3 0 0 3 8 4 6 0 0 1 9 2 1 2 0 0 9 6 2 4 0 0 4 8 4 8 0 0 2 4 9 6 0 0 1 2 1920 0 6 3840 0 3 5760 0 2 1152 0 0 1 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 22 final version: dm562 ap-ds-f0 3 10. micro-c ontroller control regi ster for p c i interface pci vender id lo w by te data port: addr es s f800 h (p ci only ) write only this p o rt con f igure s pci v ende r id lo w byte. (offset 00 of pci con f iguratio n regi ster spa c e ) pci vender id high b y te data p o rt: add r es s f801 h (p ci only ) write only this p o rt configu r e s pci vende r id high byte . (offset 01 of pci config ura t ion regi ster space) pci dev i ce id lo w by te da ta port: addres s f802 h write only this port c o nfigures pc i devic e id low byte. (offs et 02 of pci con f iguratio n regi ster spa c e ) pci dev i ce i d hi gh b y te data p o rt: ad dres s f803 h write only this port c o nfigures pc i d e vice id low byte.( offs et 00 of pci con f iguratio n regi ster spa c e ) pci subs y s t e m vender id lo w b y te data port: addr ess f8 0 4 h (p ci only ) write only this po rt co nfigures pci subsystem vende r id low byte. (offs et 2c of pc i c o nf iguration re giste r sp ace) pci subs y s tem vender i d high b y te data port: addr ess f8 0 5 h (p ci only ) write only this p o rt con f igure s pci subsy s tem vende r id hi g h byte. (offs et 2d of pc i c o nf iguration re giste r sp ace) pci subsy s tem dev i ce id lo w by te data por t : addr ess f8 0 6 h write only this po rt co nfigures pci subs ys tem d e vice id low byte. (offset 2e of pci c onfigu r ation registe r spa c e ) pci subs y s tem dev i ce id high b y te da ta por t : addr ess f8 0 7 h write only this port c o nfigures pc i s ubs y s tem devic e id low byte. (offs et 2f of pc i c onfiguration re gi st e r sp ac e) pc i po w e r management n e w capabilit y : a ddress f808 h, bit 4 (pci only ) write only this bit confi gures if supp ort pci powe r manag eme n t. (offset 06 bit 4 of pci conf i guration re gister sp ace) pci po w e r managem e nt po w e r state: addr ess f8 0 9 h, bit[1..0] (pci only ) write / re ad the s e bit s co nfigure pci p o we r ma nag ement po we r state. (offset 54 bit [1..0] of pci configu r atio n regi ster spa c e) pci po w e r managem e nt pme_status: addr ess f8 0 ah, bi t 1 write only this bit co nfigures p c i powe r status. (offset 55 b i t 7 of pci confi guration re gister sp ace) pci po w e r managem e nt pme_en: addr ess f8 0 ah, bi t 0 write only this bit con f igure s pci if enable p m e wa ke u p (offset 55 bit 0 of pci confi guration re gister sp ace) pci pme_d3 _suppor t: addr ess f8 0 bh, bi t 0 write only this po rt co n f igure s pci if supp ort pme wake u p a t d3 state. (o ffset 53 bit [8..7] of pci config uration regi ster spa c e) nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 11. pci configuration re gister definition the d e finitio n s of p c i configu r ation regi ste r s are based on th e pci spe c ification revisi on 2.1 and provid e the initializatio n and configu r ation informatio n to ope rate the pci interface in the dm6 588a. all registe r s ca n be acce sse d with byte, wo rd, or d o uble word m ode. as d e fined in p c i specification 2.1, read acce sses to re serve or unimpl e ment ed regi sters will return a value of ?0.? the s e regi ste r s are to be d e scri bed in the following se ct ion s . pci configuration registers ma pping: des c ri pti o n identifier addr ess off s e t value of r eset identification p c i i d 0 0 h 6588a 128 2 h comm and & status pcics 04h 0410 000 1h revisi o n p c i r v 0 8 h 0700 021 0 h miscella neo u s p c i l t 0 c h 0000 000 0 h i/o base address pciio 10h xxxxxxxx0 01 re se rv e d - - -- -- - - 1 4 h - 28 h subsy s tem identificati o n p c i s i d 2 c h undefin e d capability pointer cap_ptr 34h 00000050h re se rv e d - - -- -- - - 3 8 h interru pt & latency pciint 3ch 2814 01xxh powe r man a geme n t regi ster pmr 50h 0011 000 1h powe r man a geme n t control & status p m c s r 5 4 h 0000 000 0 h final 23 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 24 final version: dm562 ap-ds-f0 3 vendor id device id status (with bit 4 set to 1) command revisio latency timer cach line size class code = 070002 header type bist bass address register cbio reserved 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch reserved subsystem vendor id subsystem id reserved cap_ptr max_lat min_gnt interrupt pin = 1 interrupt line configuration register structure 40h 44h 48h 4ch 50h 54h power management control and status next item pointer capability id power management capability reserved reserved reserved reserved reserved key to defa ul t in the regi ster descri p ti on that follows, the default c o lumn takes the form < r es et value> whe r e j : 1 bit set to logic one 0 bit s e t to logic z e ro x no defa u lt value : ro = rea d o n ly rw = re ad/ write r/ c: mea n s rea d / writ e & writ e "1" f o r cle a r. _wr = controller write _rd = contro ller read nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in identifica tio n id (xxx xxx 00 - pciid) 31 16 15 0 dev_id vend_id device id vendor id b i t d e f a u l t ty p e des c ription 3 1 : 1 6 6 5 8 8 a h r o _wr the field ide n t ifies the parti cula r dev i c e. uniq ue an d fixed numb e r for the dm6 588a is 6588a h. it is the produ ct nu mber a s sign e d by davico m. 1 5 : 0 1 2 8 2 h r o _wr this field id e n tifies the ma nufactu re r of the device. unique a nd fixed numb e r for davicom i s 128 2h. it is a regi stered num be r from sig. command & status (xx x xxx0 4 - pcics) 31 16 15 0 status command status command statu s regis t er definition: 31 30 29 28 27 26 25 24 23 22 21 20 16 0 0 1 1 0 0 19 1 detected parity error signal for system error master abort detected target abort detected devsel timing data parity error detected slave mode fast back to back new capability 66mhz capability user definable send target abort final 25 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 26 final version: dm562 ap-ds-f0 3 b i t d e f a u l t ty p e des c ri pti o n 3 1 0 r / c detected par i t y error the dm6 588 a sample s the ad[0:31], c/be[0:3]#, and the par sign al to che ck p a rity and to set pa rity errors. 3 0 0 r / c signaled sy stem error this bit is set when the serr# sig nal is driven by the dm6 588a. t his sy stem e r ror o c cu rs wh en an a ddress pa rity is detecte d und er the conditi on that bit 8 and bit 6 in c o mman d regi ster b e lo w are set. 2 9 0 r / c master ab or t de tec t ed the dm 6588a will never support the function 2 8 0 r / c targe t abo r t detected the dm 6588a will never support the function 2 7 0 r o send targe t abor t (0 fo r no implem en tation) the dm 6588a will never support the function. 2 6 : 2 5 1 0 r o devsel timing (10 sele ct slow timing ) slow timing of devsel# means the dm6588a wi ll assert devsel# si gnal two cl ocks after frame# is sampl e ?a sserted. ? 2 4 0 r / c data parit y error detected the dm 6588a will never support the function 2 3 0 r o sla v e mode fast back -to-ba ck capable (1 for goo d capability) the dm 6588a will never support the function 2 2 0 r o use r -de f ina b le-fe a tur e supported (0 fo r no su ppo rt) 2 1 0 r o 66 mhz cap a ble (0 for no capability) 2 0 1 ro _wr n e w capabilities this bit in dicates wheth e r this functio n impleme n ts a list of extended capabilities such as pci power managem ent. when set this bit in dicates the presen ce of new capabilities. a value of 0 mean s that this functio n do es not implem ent ne w capabilities. 1 9 : 1 6 0 0 0 0 r o re se r v e d nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in command registe r de fin i tion: 1 5 1 0 987 654 3 21 0 reserved r/w 0 r/w 0 0 r/w r/w r/w 0 0 parity error response enable/disable i/o space access enable/disable memory space access enable/disable master device capability enable/disable serr# driver enable/disable mast mode fast back-to-back address/data steeping vga palette snoop special cycle memory write and invalid b i t d e f a u l t ty p e des c ription 1 5 : 1 0 0 0 0 0 0 0 r o re se r v e d 9 0 r o master fas t bac k -to-bac k mode (0 f o r no sup p o r t) the dm6588a does not suppo rt master mode fast back-to-back capability and will not generate fast back-to-back cycles. 8 0 r w ser r # d r iv e r enable/d isable this bit controls the asse rtion of serr# signal outp u t. the serr# outpu t will be assert ed on detection of an address pari ty error and if both this bit and bit 6 are set. 7 0 r o addr ess/ data stepping (0 for no stepping ) 6 0 r w parit y error res pons e enable/disa b le setting this bi t will enabl e the dm 6588a to assert pe rr# on the detection of a data parity error an d to assert serr# for re portin g addre s s pa rity error. 5 0 r o vga palette snooping (0 for no supp ort) 4 0 r o memor y w r ite and inv a l i d (0 for no su ppo rt) 3 0 r o special c y cles (0 fo r no implementati on) 2 0 r w master dev i ce c a pability enable/d isable the dm 6588a will never support the function. 1 0 r w memory spa ce ac ces s enable/disa b le the dm 6588a will never support the function. 0 1 r w i/o space ac cess ena b le/disable this bit controls the abilit y of i/o space access. final 27 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 28 final version: dm562 ap-ds-f0 3 rev i sion id (xxxx xx0 8 - pcirv) 31 0 7 8 revision id class code class code revision major number revision minor number b i t d e f a u l t ty p e des c ription 3 1 : 8 0 7 0 0 0 2 h r o class code (0700 02h ) this i s the stand ard co d e for simple comm uni ca tions controll er.16 550 com patible serial controlle r . 7 : 4 0 0 0 1 r o rev i si on major num b er this is the silicon-major revisi on number that will increase for the sub s e que nt version s of the dm65 88a 3 : 0 0 0 0 0 r o rev i sion minor numbe r this is the silicon-mi n or revisi on number that will increase for the sub s e que nt version s of the dm65 88a. miscellaneo u s func tion (xxxx xx0 c - pcilt) 31 16 15 0 87 23 24 bist header type latency timer cache line size built-in self test header type latency timer for the bus master cache line size for memory read b i t d e f a u l t ty p e des c ription 3 1 : 2 4 0 0 h r o b u ilt-in self test (=00h m ean s no impl ementatio n) 2 3 : 1 6 0 0 h r o hea d er ty pe (= 00 h mean s sin g le fun c tion with pre d e f ined he ade r type ) 1 5 : 8 0 0 h r o late nc y timer for the bus mas t er . the dm 6588a will never support the function. 7 : 0 0 0 h r o cac h e line size for me mory read mode selec t ion (00h m e ans no implementati on for use) nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in i/o base ad dress (xxxx xx10 - pciio) 31 0 1 2 3 1 00 i/o base address i/o base address pci i/o range indication i/o or memory space indicator b i t d e f a u l t ty p e des c ription 3 1 : 3 u n d e f i n e d r w pc i i/o b ase a ddress this is the base address value for i/o access cycl es. it will be compared to ad[31:3] in the add re ss p hase of bus comm and cycle for the i/o resou r ce ac ce ss. 2 : 1 0 0 r o pc i i/o r a nge indication it indic a tes that the minimum i/o res o urce s i ze is 08h. 0 1 r o i/o space or memory spa ce ba se indicato r dete rmine s that the regi st er map s into the i/o s p ac e. (=1 indicates i/o base) subs y s tem identific a tion (xxxxx x2c - pcisid) 0 31 subsystem id subsystem vendor id subsystem id subsystem vendor id b i t d e f a u l t ty p e des c ription 3 1 : 1 6 x x x x h ro _wr subs y s tem id nod e num ber loaded from cont rolle r an d different fro m each ca rd. 1 5 : 0 x x x x h ro _wr subs y s tem vendor id uniq ue nu mb er given by pci sig and lo aded from co ntrolle r. final 29 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 30 final version: dm562 ap-ds-f0 3 capabilities pointer (xxxxxx34 - cap _ptr) 0 0 0000 11 cap_ptr offset 34h 0 7 b i t d e f a u l t ty p e des c ription 3 1 : 8 0 0 0 0 0 0 h r o re se rved 7 : 0 0 1 0 1 000 0 r o c a pabilit y p o inter the cap_ptr provide s an offset (def a u lt is 50h ) in to the functi on?s p c i configuration space for t he location of the first term in the capabilities linked li st. the ca p_ptr o ffset is do uble word ali gned so the two lea s t signifi cant bit s sig n ifica n t bits are al way s ?0?s interrup t & l a ten c y configuration (xx xxxx 3c - pci i nt) 31 16 15 0 87 23 24 max_lat min_gnt int_pin int_line maximum latency timer minimum grant interrupt pin interrupt line b i t d e f a u l t ty p e des c ription 3 1 : 2 4 2 8 h r o maximum la tency timer that can be sustain ed (re ad only and rea d as 28h ) 2 3 : 1 6 1 4 h r o minimum gran t minimum l e n g th of a burst period (re a d only and read as 1 4h) 1 5 : 8 0 1 h r o interrup t pin read a s 01 h to indicate inta# 7 : 0 x x h r w in t e r r u pt l i ne that is rout ed to the interru pt cont roll er nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in po w e r man a gement regi ster (xxxx xx 50h ~pmr) 31 16 15 0 87 power management capabilities next item pointer capability identifier pmc next item pointer capability id b i t d e f a u l t ty p e des c ription 3 1 : 2 7 0 0 0 0 0 ro _wr pme_suppo rt this five-bit field indicate s the pow e r states in which the function may asse rt pme#. a value of 0 for any bi t indicate s th at the functio n is not cap able of a s se rting the pme# sign al while in that po we r state. bit27 ? pm e# s u pp or t d 0 bit28 ? pm e# s u pp or t d 1 bit29 ? pm e# s u pp or t d 2 bit30 ? pm e# s u pp or t d 3 (h o t ) bit31 ? pm e# s u pp or t d 3 (c o l d) dm6 588a? s b i t31~2 7 =110 0 0 indicates p m e# can b e asse rted from d3(hot) & d(cold). 2 6 : 2 2 0 0 0 0 0 ro re se rved (dm658 8a not sup p o r ts d1, d2 ) 2 1 0 ro a ?1? indi cate s that the function requi re s a device spe c ific initiali zati on seq uen ce foll owin g tran siti on to the d0 un-i n itialized state. 2 0 1 ro auxiliary power source this bit is o n l y meaningful if bit31 is a ?1 ?. this bit is ?1? in dm6 588a i ndicates that sup p o r t for pme# in d3 (cold) requires auxil iary power. 1 9 0 ro pme# clock ?0? in dicates t hat no pci cl ock is requi re d for the funct i on to gene rat e pme#. 1 8 : 1 6 0 0 1 ro versi on a value of 001 indicates th at this functi o n com p lie s wi th the revisio n 1.0 of the pci powe r mana gem e n t interface s pecifi c ation. 1 5 : 8 0 0 h ro n e xt item pointer the offset int o the function ?s pci co nfig uratio n space pointing to the location of next item in the function? s capability list is ?00h? 7 : 0 0 1 h ro capability identifier whe n ?0 1h? i ndicates the li nke d list item as bei ng the pci powe r mana geme n t regi ste r s. final 31 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 32 final version: dm562 ap-ds-f0 3 power managem e nt con t rol/status(xxxxxx54h~pmcsr) 0 r/w r/w r/w 0 0 0 0 0 0 0 000 0 0 1 2 15 8 7 9 14 pmcsr offset=54h b i t d e f a u l t ty p e des c ription 3 1 : 1 6 0 0 0 0 h ro re se rved 1 5 0 r/ c _wr pme_status this bit is set when the function w ould norm a lly assert the pme# signal indep end ent of the state o f the pme_en bit. writing a ?1 ? to this bit will c l ear it. this bit d e fa ults to ?0 ? if the fun c tion d oes not su pp ort pme# ge neration from d 3 (c old). if the functio n sup port s pme# from d3 (cold ) then this bit is sticky and must be ex plicitly clea re d by t he operating sy stem ea ch time th e ope rating system is initially loaded. 1 4 : 9 0 0 0 0 0 0 ro re se rved. it means that the dm6 588a does n o t sup port re po rting powe r con s u m ption. 8 0 rw _wr pme_en write ?1? to e nable s the fu nction to a s sert pme#, wri t e ?0? to disab l e pme# asserti on. this bit defa u l ts to ?0? if the function do e s not su ppo rt pme# gene ra tion from d 3 (c old). if the function supp ort s pme# from d3 (cold) the n this bit is sticky and must be expli c itly clea red b y t he operatin g system e a ch time the ope rating system is initially loaded. 7 : 2 0 0 0 0 0 0 ro re se rved 1 : 0 0 0 rw _wr _rd po w e r state . this two bits field is both u s ed to determi ne the cu rren t powe r state of a function a nd to set the function into a ne w po we r stat e. the definiti ons given belo w . 00 : d0 11 : d3(hot) pci func tion po w e r mana gement s t a t e the dm65 88 a sup port s p c i functio n p o we r states d0, d3 (hot), d3 (cold ) . additio nal pci sign a l pme# to pin a19 of the standa rd pci conne cto r . pme context pme (power mana geme n t event) cont ext is define d as the functio nal state in fo rmation a nd logic requi re d to generate powe r manage ment e v ents (pmes), rep o rt pme status, and e n a b le pmes. for mo dem, pme context consi s t s of pme_en bit, pme_status bit , ri ng de tec t ,and ring to pme cir c uit . pci modem po w e r man a gement ope r ation during a true power-on si tuation (no auxiliary and norm a l po we r), pme_en = 0 to avoid to asse rt pme#. whe n asse rt rst#, the pci configu r ation space is set to default v a lue exce pt pme context whi c h mu st p r es er ve . nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 33 version: dm562 ap-ds-f0 3 nov. 09, 2007 dm6 588a ca n not assert pme# from d0. but can assert pme# from d3(h ot) and d3 (col d). hen c e th e ring to pme# circuit must check the p o we r state. if ring come s at d0 power st ate, it can not assert pme#. when host detect pme# as serted, it will power up pci bus a nd asse rt rst# to initialize p c i modem. at the s a me time, it w r ite 1 into pme_en bit or pme_status bit to stop pme#. before ente r d3 (hot) state, host mu st : software will enable its u s e by setting the pme_en bit in the pmcsr. 5. write 1 into p m e_status bi t to clear previous pme status it must continue to asse rt pme# until software either clea rs the pme_en bit or cl ears the pme_status bit. 6. write 1 into p m e_en bit to enabl e pme function. before ente r d3 (col d) stat e, host mu st : 7. write 3 into p o we r_ state 1. write 1 into pme_status bit to clear p r eviou s pme status w h en r i ng come, r i ng to pme# c i rcuit check if pme_en=1 and power_stau s < > 0. i f y e s, asse rt pme# and se t pme_status=1. 2. write 1 i n to pme_en bit to enable pme function. when host detect pme# asse rted, it will re-initiali z e pci m odem a nd set power_state=0 to return d0 stat e. at the s a me time, it w r ites 1 into pme_en bit or pme_status bit to stop pme#. 3. write 3 into p o we r_ state 4. pow e r off pc i bus . whe n ring com e s, rin g t o pme# circ uit che ck i f pme_en=1 and po we r_ stau s <>0. if yes, assert pme# and se t pme_status=1. pci modem boar d po w e r managem e nt tx dsp ring de tecto r d m 65 80 an al og fron t end sc l k di t do t tfs di r do r rfs r xsc l k cl k i n tx d c lk rx d c l k da a rxi n tx a1 tx a2 li ne speaker driv e r rx d s p spkr mi cro pho ne drive r 30 . 2 4 m h z pc i bu s vc c _ a u x pci t o is a ri t o pm e # vdd : pci +3. 3 v power vs b : auxil ily +3. 3 v power vdd p o w er o n / o ff v cc_au x vsb p o w er swi t c h vcc = v dd if powe r o n vc c = f l oating if powe r of f vd d mi cro cont rol unit dm65 88a t xsc l k * 2 final
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 34 final ring hold ckt vdda pme# ring to pme# circuit ring in rst# power on/off power state = 11 =other pci to isa reserve pme context other set to default (power state = 00) reset ri\, at command power on inverse rst# 1.&@&/ 1.&@4ubuvt configuration register 8031 kernel vdda dm6588a pci pow e r configuration version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6588a external electrical c h aracteristics dm6 588 a ex tern al absol u te ma ximum ratings * (25 c) sy m b o l p a r a m e t e r m i n . m a x . u n i t condition s d vcc ,a vcc s u p p l y v o l t a g e - 0 . 3 3 . 6 v v in dc inp u t voltage (vin) -0.5 5.5 v v ou t dc o u tput voltage (vout ) -0.3 3.6 v t a ambient tem perature 0 +70 c tstg storage t e m perature ran g (tstg ) -65 +15 0 c l t lead t e mp. (tl, solderi n g , 10 sec. ) - 245 c pb -fre e *c omments stresse s abo ve those liste d unde r ?ab s olute maximum ra tings 6? may cause pe rman ent dama ge to the device. these are stre ss rating s o n ly. fun c tional o p e ratio n of this device at the s e o r any other con d itio ns ab ove tho s e indi cate d in the ope ration al section of this spe c ification i s not implie d or inten ded. exposu r e to absolute max i mum ratin g con d ition s for extended pe riods m a y affect device reliability . dm6 588 a ex tern al dc electric a l char acteristic s (vdd = 3.3v, gnd = 0v) sy m b o l p a r a m e t e r m i n . t y p . m a x . u n i t condition s v dd ope r ating vol t age 3.15 3.3 3.45 v i dd o p e r ating cu rre n t 9 0 m a v ih input high vo ltage 2.0 v v il input low vol t age 0.8 v i il input lea kag e cu rre nt -1.0 1.0 ? a v in = 0, 3.45v v oh output hig h voltage 2.4 v i oh = -0.5ma v ol output lo w voltage 0.4 v i ol = 1.5ma c in i n p u t cap a cit a n c e 1 0 . 0 p f v ilreset r e s e t sc hmit t v il 0 . 8 v v ihreset r e s e t sc hmit t v ih 2 . 8 v final 35 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 36 final dm6588a isa electrical characteristics dm6 588 a i s a ab sol u te maxi m u m r a ti ngs* (25 q c) sy m b o l p a r a m e t e r m i n . m a x . u n i t condition s d vcc ,a vcc s u p p l y v o l t a g e - 0 . 3 3 . 6 v v in dc inp u t voltage (vin) -0.5 5.5 v v ou t dc o u tput voltage (vout ) -0.3 3.6 v t a ambient tem perature 0 +70 q c tstg storage t e m perature ran g (tstg ) -65 +15 0 q c l t lead t e mp. (tl, solderi n g , 10 sec. ) - 245 q c pb -fre e *c omments stresse s abo ve those liste d unde r ?ab s olute maximum ra tings 6? may cause pe rman ent dama ge to the device. these are stre ss rating s o n ly. fun c tional o p e ratio n of this device at the s e o r any other con d itio ns ab ove tho s e indi cate d in the ope ration al section of this spe c ification i s not implie d or inten ded. exposu r e to absolute max i mum ratin g con d ition s for extended pe riods m a y affect device reliability . dm6 588 a isa dc electri cal char ac te ristics (v dd = 3.3v, gnd = 0v) sy m b o l p a r a m e t e r m i n . t y p . m a x . u n i t condition s v dd ope r ating vol t age 3.15 3.3 3.45 v i dd o p e r ating cu rre n t 9 0 m a v ih input high vo ltage 2.0 v v il input low vol t age 0.8 v i il input lea kag e cu rre nt -1.0 1.0 ? a v in = 0, 3.45v v oh output hig h voltage 2.4 v i oh = -0.5ma v ol output lo w voltage 0.4 v i ol = 1.5ma c in i n p u t cap a cit a n c e 1 0 . 0 p f v ilreset r e s e t sc hmit t v il 0 . 8 v v ihreset r e s e t sc hmit t v ih 2 . 8 v version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6588a isa ac electrical charact eristics & timing w aveforms dm6 588 a isa ac electri cal char ac te ristics (v dd = 3.3v, g nd = 0v ) sy m b o l p a r a m e t e r m i n . t y p . m a x . u n i t condition s t aw iow del a y from address 18 ns t wc w r i t e c y c l e 1 0 6 n s t dow i o w strobe w i d t h 2 2 n s t ds data setup ti me 22 ns t dh d a ta hold time 5 ns t ar ior del a y fro m addre s s 5 ns t rc r e a d cycl e 1 0 2 n s t diw i o r strobe w i d t h 2 2 n s t ddd delay from i o r to data v a lid - 20 ns 100p f loadi n g t hz ior to floati ng data dela y - 30 ns 100p f loadi n g dm6 588 a isa signals ti ming diagra ms write c y cle a2 - a 0 valid t aw t wc t do w valid t ds t dh /iow /ior dat a ud7- ud0 rea d c y cle final 37 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 38 final version: dm562ap-ds-f03 nov. 09, 2007 dm6588a pci electrical characteristics dm6588a pci absolute maximum ratings* (25 q c) symbol parameter min. max. unit conditions d vcc ,a vcc supply voltage -0.3 3.6 v v in dc input voltage (vin) -0.5 5.5 v v out dc output voltage(vout) -0.3 3.6 v t a ambient temperature 0 +70 q c tstg storage temperature rang (tstg) -65 +150 q c l t lead temp. (tl, soldering, 10 sec.) - 245 q c pb -free *comments stresses above those listed under ?absolute maximum ratings 6? may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational section of this specification is not implied or intended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dm6588a pci dc electrical charac teristics (vdd = 3.3v, gnd = 0v) symbol parameter min. typ. max. unit conditions v dd operating voltage 3.15 3.3 3.45 v i dd operating current 120 ma v ih input high voltage 2.0 v v il input low voltage 0.8 v i il input leakage current -1.0 1.0 ? a v in = 0, 3.45v v oh output high voltage 2.4 v i oh = -0.5ma v ol output low voltage 0.4 v i ol = 1.5ma c in input capacitance 10.0 pf v ilreset reset schmitt v il 0.8 v v ihreset reset schmitt v ih 2.8 v
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6588a pci ac electrical character istics & timing waveforms (v dd = 3.3v, g nd = 0v; t a = 25
) pci clock s p ecifica tions timing t high 2.0v 0.8v t r t f t low t cycle sy m b o l p a r a m e t e r m i n . t y p . m a x . u n i t condition s t r pci_c l k risi ng time 4 - - ns - t f pci_clk falling time 4 - - ns - t cy c l e c y c l e t i m e 3 0 - - n s - t high pci_c l k hig h time 12 - - ns - t low pci_clk lo w time 12 - - ns - othe r pci signals timing diagram t off t h t su input t on output c lk 2.5v t val (max) t val (min) sy m b o l p a r a m e t e r min. t y p . m a x . u n i t condition s t val clk-to-si g n a l valid del a y 2 - 15 ns c load = 50 pf t on float-t o-a c tive delay fro m clk 2 - - ns - t of f activ e -to - flo a t delay fro m clk - - 28 ns - t su input signal valid setup t i me before clk 7 - - ns - t h input signal hold tim e from clk 5 - - ns - final 39 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 40 final chip 2: dm6580 an alog front end dm6580 description the dm65 80 is a singl e chi p analo g fro n t end (afe) desi gne d to be implem ent ed in voice g r ad e modem s for data rate s u p to 5 6 0 00bp s. th e dm6 580 i s a n essential pa rt the complete modem de vice set. the afe converts the analog signal into digi tal form and tran sfers the digital data to the dsp through the seri al port. all the clo ck i n form a t ion nee ded in a mod e m device i s al so gen erate d i n the dm 658 0. differential analo g output s are p r ovide d to achieve the maximum output si gn al level. an audi o monitor wit h pro g ra mmabl e volume lev e ls is built in to monitor th e on-li ne si gnal . inside the d e vice, a 16 -bi t adc and a 16-bit dac with over-sa m pling an d noise-sh apin g techni que s is impleme n ted to maximize perfo rma n ce. the dm 658 0 offers wid e -band tra n smi t and receive filters so that the voice ba nd sig nal is t r an smitted o r re ceived wit hout amplit ude disto r ti on and wit h minimum gro up delay. in o r de r to suppo rt multi-mode modem stan dards, su ch as v.90, v . 34+, v.32bi s, v.32, v.22bis, v.22, v.23, v.21, bell 21 2a, bell 103, v.17, v.29, v.27ter, pro g ram m abl e baud and dat a rate clo c k ge nerators are provid ed. for asymmetri c cha nnel u s a ge, the tra n smit an d receive clo c k gene rato rs a r e ind epe nd ent. in orde r to enha nce ech o -ca n cell ation, the re ce iv e clo c k is sy nc hro n iz e d with the transmit clock a nd the best re ceive timing sam p le is reconst r u c ted by a recon s tru c tion filter. the tran smit di gital phase lock lo o p (dp ll) i s self-tu n ing to provide a ma ste r , slave or free-run n in g mode for the data termin al interface. a re ceive dpl l that is step prog ramm a b le by the host dsp is impleme n ted to get the best sam p le s for the releva nt sign al processing. dm6580 block diagram rxsclk rxdclk rfs dor dir tfs dot dit digital reconstruction filter sclk digital interface rx clock system tx clock system divider control registers tx filter & dac rx filter & adc lpf & attenuator voltage reference 0/-6 db audio amplifier power-on detector spkr rxin v refn v refp txa2 txa1 clkin txsclk*2 txdclk extclk v cm version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6580 f eatures ? 16-bit 2 - ? a/d and d/a conve r ters ? dynami c ra n ge : 86db ? total harmoni c disto r tion : -86db ? separate tran smit and rece ive clocks ? symbol rate : 75, 300, 6 00, 1200, 16 00, 2400, 2743, 28 00, 3 000, 320 0, 34 29, 8000 hz ? data rate v.34 : 75, 300, 600, 1200, 2 4 00, 4800, 7200, 960 0, 12000, 14400, 1680 0, 19200, 2160 0, 2400 0 , 26400, 288 0 0 , 31200, 33 6 00 bp s ? data rate v.90 : up to 5600 0 bps ? dual syn c hro nou s serial i n terfa c e to h o st di gital signal pro c e s sor (dsp) ? separate tra n smit digital phase lock loop and re ceive digital phase lock lo op ? full echo cancellation capability ? differe ntial a nalog o u tput ? single-end ed analog in put ? single po we r sup p ly voltage : +5v ? low p o wer consumptio n dm6580 pin configuration final 41 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 42 final dm6580 pin description pin no. 48pin lqfp pin n a me i/o d e scription 2 rxin i re ceive anal og input 3 a v d d r i analog v dd for the re cei v er analog ci rcuitry (+5v dc ) 4 s p k r o s p e a k e r driv e r 7 rxdclk o re ceive data clock 8 v dd p d i g i t a l p o w e r 9 rxsclk o re ceive sam p le clo c k 10 rfs i re ceive fra m e synch r oni zation 15 do r o data outp ut for receiver 16 dir i data input fo r re ceive r 1 7 d g n d p digit a l g r ou n d 1 8 s c l k o serial cl ock synchr oniz e d w i th all serial d a ta 19 d o t o d a ta output for trans m itter 20 dit i data input fo r tra n smitte r 22 tfs i tran smit fra m e synch r oni zation 26 txsclk*2 o tran smit sa mple cl ock * 2 27 txdclk o tran smit data clo ck 28 clkin i maste r clo c k input (20.1 6 m hz = 40.3 2 m hz / 2 ) 2 9 / r e s e t i codec r e s e t i n p u t 30 extc l k i external trans mit d a ta c l oc k 33 vr o internal reference voltage. conn ect 0.1 u f to dg nd 3 5 a v d d t i analog v dd for the t r an smitter analog circuitry (+5 v dc ) 39 txa2 o tran smit neg a tive analog output 40 txa1 o tran smit posi tive analog o u tput 41 agndr p analog re cei v er circuit r y signal return path 4 3 v refn o neg a tive ref e re nce voltage, v cm - 1v 4 4 v cm o comm on mo de voltage o u tput, 2.5v 4 5 v refp o positive refe ren c e voltag e, v cm + 1v 46 agndt p analog t r an smitter circuitry signal retu rn path 1,5,6, 11,12,13, 14,21,23, 24,25,31, 32,34,36, 37,38,42, 47,48 n c n n c version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6580 f unctional description in this chip, we co uld rou ghly divide it into two majo r part s : digital portion a n d analo g p o rtion. the function al bl ocks a r e d e s crib ed sepa rately in this se ction. the analo g ci rcui ts in clud e a sigm a-delt a modul ator/de m odul ator, decimat ion/interpolati o n filters, a spe a ke r drive r , low-pa ss filter and certai n logic circuit s . the digital circuit s are com p o s ed of tx/rx clock gene rato r/pl l, se ri al po rt, seri al/paralle l conve r sion s and contro l r egiste r s. all the clock informatio n the an alog circuit s nee d sh ould b e provid ed by t he digital cl o ck sy st e m si nce t h e b e st sam p ling in st ant of a/d and d/a de pend s on th e re ceived sign al and tran sm it signal s. th e data form at of a/d and d/ a is 2's compl e ment. the m a ste r clock (f q) i s obtaine d fro m an exte rna l sign al conn e c ted to clkin. the diffe rent tran smit and re ceive clocks are obtai ne d by master clo c k frequ en cy division in several prog ram m able counte r s. the tx and rx clocks can be syn c h r oni ze d on external si gn als by perfo rming the pha se shifts in th e frequ en cy division p r o c e s s. two indep e ndent digital pha se lo cke d loop s are implemente d usin g this prin cipl e, one for transmi t clock syste m , the other, re ceive clo c k. the tracki n g of the transmit clo c k i s automati c ally done by the tran smit dpl l circuit. th e re ceive dp l l circuit i s controlled by the host pro c e s sor a nd it is act ually an adj ustabl e pha se s h ifter. dm6580 register description r e g i s t e r d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 pr ogr a m me func tio n s txcr0 r 1 x 3 x 2 x 1 x 0 n 3 n 2 n 1 n 0 r 0 s t t x data rate clock txcr1 q 1 d m 1 m 0 q 0 f y u 2 u 1 u 0 t x baud sample c l ock txcr2 v o l 1 v o l 2 f 1 f 0 w att l t x l c sst emx v f miscell ane ou s control tx te s t r e s e r v e d rxcr 0 r 1 h 2 h 1 h 0 n 3 n 2 n 1 n 0 r 0 s t rx data rate clock rxcr 1 q 1 rst d m 1 m 0 q 0 p y u 2 u 1 u 0 rx ba ud sampleclock rxcr 2 - 6 d b l l ps4 ps3 ps2 ps1 ps0 ap2 a p 1 a p 0 rx ph ase shift control rxt est r e s e r v e d final 43 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 44 final dm6580 absolute maximum ratings* absolu te ma ximum ratin g s* (2 5 q c) sy m b o l p a r a m e t e r m i n . m a x . u n i t condition s d vcc ,a vcc s u p p l y v o l t a g e - 0 . 3 3 . 6 v v in dc inp u t voltage (vin) -0.5 5.5 v v ou t dc o u tput voltage (vout ) -0.3 3.6 v t a ambient tem perature 0 +70 q c tstg storage t e m perature ran g (tstg ) -65 +15 0 q c l t lead t e mp. (tl, solderi n g , 10 sec. ) - 260 q c pb -fre e *c omments stresse s abo ve those liste d unde r ?ab s olute maximum ra tings 6? may cause pe rman ent dama ge to the device. these are stre ss rating s o n ly. fun c tional o p e ratio n of this device at the s e o r any other con d itio ns ab ove tho s e indi cate d in the ope ration al section of this spe c ification i s not implie d or inten ded. exposu r e to absolute max i mum ratin g con d ition s for extended pe riods m a y affect device reliability. dm6 580 dc electrical ch arac teris t ic s & timing wav e forms (vdd = 5v) sy m b o l p a r a m e t e r m i n . t y p . max. u n i t condition s v dd o p e r ating vol t a g e 4 . 7 5 5 5.25 v v cm output co m m on mod e voltage 2.5 v i dd s u p p l y cu rre n t 2 5 m a v il input low vol t age 0.8 v v ih input high vo ltage 2.0 v v ol output lo w voltage 0.4 v v oh output hig h voltage 2.4 v i il input leakage current -2.0 r 1.0 2.0 p a v i =0v,5.25v c in i n p u t cap a cit a n c e 5 . 0 p f v ref differe ntial refere nce voltage output 1 . 9 2 . 0 2 . 1 v v cmd_ out output co m m on mod e offset -20 0 200 mv =(txa1 +txa 2)/2-v cm v dif_ ou t differe ntial o u tput voltage 3 *v ref v txa1-txa2 d 3*v ref v of f_ out d i fferential output d c offset voltage -10 0 1 0 0 m v v dc (t x a1)-v dc (t x a2) r in input re sista n ce rxin 1 0 0 k : r out output re si stance txa1, txa2, spkr 1 2 k : r l load re sista n ce txa1, txa2, spkr 2 0 k : c l load cap a cit ance txa1, txa2, spkr 5 0 p f version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in dm6580 ac charact eristics & timing waveforms (vdd = 5v) serial port timing sym b o l p a r a m e t e r m i n . typ. m a x . u n i t conditi o n s 1 s c l k perio d 4 9 n s 2 sclk lo w width 24 ns 3 sclk hig h width 24 ns 4 sclk ri se ti me 5 ns 5 sclk fall ti me 5 ns 6 fs to sclk setup 17 ns 7 fs to sclk hold 17 ns 8 di to sclk setup 5 ns 9 di to sclk hold 5 ns 10 sclk hig h t o do valid 8 ns 11 sclk to do hiz 8 ns 1 23 4 5 6 7 89 fi rs t bus fi rs t bu s last bus last bus hiz 11 10 sclk fs di do dm6580 performance (v dd = 5v, fq= 20.1 6 m h z, mea s urem ent band = 2 20hz to 3.6k hz, rx dpll free runni n g ) symbol p arameter m in. t yp. m ax. u nit c onditions gab s absol u te gai n at 1khz -0.5 0.5 db r x sig nal: v in = 2.5 v pp, f = 1khz thd total ha rmo n i c di stortio n -84 db tx signal: v out (d if f ) = 5 v pp , f = 1 k h z dr dynami c ran ge 86 db f = 1khz psrr powe r suppl y rejectio n rat i o 50 db f = 1khz, v ac = 200m v pp ctxrx crosstal k 95 db tran smit cha nnel to re ceiv e cha nnel final 45 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 46 final package information qfp 128l o u tline dimen s ions unit: i n ch es/m m l l1 detail f t seating plane see detail f d y 0.10 see detail a a a2 a 1 y b e 13 8 128 103 65 102 d d1 e1 e 64 39 with plating base metal detail a c b s y m b ol dimen s io n in i n ch dimen s io n in m m a 0.134 ma x. 3.40 max. a1 0.010 min. 0.25 min. a 2 0 . 1 1 2 r 0.005 2.85 r 0.12 b 0 . 0 0 9 r 0.002 0.22 r 0.05 c 0 . 0 0 6 r 0.002 0.145 r 0.055 d 0 . 9 1 3 r 0.007 23.20 r 0.20 d 1 0 . 7 8 7 r 0.004 20.00 r 0.10 e 0 . 6 7 7 r 0.008 17.20 r 0.20 e 1 0 . 5 5 1 r 0.004 14.00 r 0.10 e 0.020 bsc 0.5 bsc l 0 . 0 3 5 r 0.006 0.88 r 0.15 l1 0.063 bsc 1.60 bsc y 0.004 ma x. 0.10 max. t 0 q ~12 q 0 q ~12 q not e : 1. dime nsi on d1 and e1 do not inclu de re sin fins. 2. all dimensi o n s are ba sed o n metric syst em. 3. gene ral a ppe ara n ce sp ec. sho u ld ba se i t self on final visual in sp ecti on sp ec. version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in lqfp 48l (f.p. 2mm) outline d i mensions unit: inch es/mm z % % sy m b ol di m e nsions in in c h es di m e nsions in mm m i n . no m . max. min. no m . max. a - - 0. 0 6 3 - - 1. 60 a 1 0 . 0 0 2 - 0. 0 0 6 0. 0 5 - 0. 15 a 2 0 . 0 5 3 0. 0 5 5 0. 0 5 7 1. 3 5 1. 4 0 1. 45 b 0 . 0 0 7 0. 0 0 9 0. 0 1 1 0. 1 7 0. 2 2 0. 27 b 1 0 . 0 0 7 0. 0 0 8 0. 0 0 9 0. 1 7 0. 2 0 0. 23 c 0 . 0 0 4 - 0. 0 0 8 0. 0 9 - 0. 20 c 1 0 . 0 0 4 - 0. 0 0 6 0. 0 9 - 0 . 16 d 0 . 3 5 4 b s c 9. 0 0 b s c d 1 0 . 2 7 6 b s c 7. 0 0 b s c e 0 . 3 5 4 b s c 9. 0 0 b s c e 1 0 . 2 7 6 b s c 7. 0 0 b s c e 0. 0 2 0 b s c 0 . 5 0 b s c l 0 . 0 1 8 0. 0 2 4 0. 0 3 0 0. 4 5 0. 6 0 0. 75 l 1 0 . 039re f 1. 00re f y 0 . 0 0 3 m a x 0. 0 8 m a x 0- 12 0 - 12 1rw h v 7rehghwh u p l qhgdwvh d wlq j sodqh 'lph qvl r q v ' dqg ( gr qrw l qfoxgh pro g surwuxvl rq ' dqg ( d uh p d[lp xp s odvwl f erg \ vl]hglphqvl rqvlqfoxgl qj progplvpdw f k 'lph qvl r q v e grh v q r w lqfo xgh g d p e d u surwuxvl rq 7rwdo lq h [fhvv ri w kh e glphq v lr q dw p d[lp xp pdwhuldo f rq glwlrq ' dp edu f dqq rw eh orfdwh g r q wkhorzh uud gl xvriwkhirrw ([d f wvkd sh rihdfk fr uqh u lvrswlr qdo 7kh v h glph q v lrq v d s s o\ w r wkh iodw v hfwlrq ri w kh ohdg ehw zhh q pp dqg pp iur p w kh ohdg wls $ l v ghilqh g d v wkh glvwdqfh iurp w kh vhdwlq j sodqhwrwkho r zh vwsrlqwr iwkhsdfndjh erg\ &rqw uroolqjgl phqvlrqplool phwhu 5 h ihuhqf hgrf xphqwv - ( ' (& 06%%& final 47 version: dm562 ap-ds-f0 3 nov. 09, 2007
dm562ap v.90 integrated data/ fax/voice/speakerphone modem device single chip with memory built in 48 final ordering information part nu mb er pin co un t pack ag e dm658 0 e 4 8 lq f p dm658 0 e p 4 8 lq f p ( p b -free) dm658 8af 1 2 8 q f p dm658 8af p 1 2 8 q f p ( p b -free) disclaimer the info rma t ion app eari ng in thi s publi c ation i s believed to b e accu rate. i n tegrated circuits sol d by davicom semico ndu ct or are covere d by th e wa rra nty and patent indem nificatio n provisio n s stipulate d in the terms of sale only. davicom makes no wa rranty , expres s, statutory, im plied o r by description reg a rdi ng t he info rmat ion in thi s publi c ation or rega rdi n g the inform ation in thi s publi c ation or reg a rdi ng th e free dom of the de scrib e d chip (s) fro m patent infringeme n t. further, davicom makes no warra nty of mercha nt ability or fitness for a n y purpose. davicom reserv e s the right to ha lt pro d u c tion or alter the sp ecification s a nd pri c e s at any time without notice. ac cordi ngly, the rea der i s cautio ned to verify that the data she e ts and othe r informatio n i n this pu bli c ation a r e current befo r e placi ng ord e rs. produ cts describe d herein are intende d for use i n n o rm a l comm ercial appli c ation s . application s involving unu sual env ironm ental or reliability requirem ents, e.g. military equipment or medi cal life sup p o r t equi pment, are specifi c ally no t re comm end e d without addition al p r o c e ssi ng b y davicom fo r su ch appli c ation s . plea se n o te that appli c ation ci rcuits illustrat ed in thi s document are for referen c e pu rposes o n ly. davicom? s terms an d condition s pri n ted on the ord e r ackn owle dgm ent govern all sale s by davicom. davicom will not be bound by any terms inco nsi s tent with thes e unle ss davicom a g re es otherwi se in writing. a c ceptan ce of the buyer? s ord e rs sh all b e based on th ese te rms. compan y overview d avic o m se m i c o n d u c t o r , in c . de ve lo ps a nd manufa c tures integrated circuits for integration into data comm u n icatio n pro duct s . our mission is to desi gn and produ ce ic prod uct s that are the indu stry?s b e s t value for data, audi o, video, an d internet/intranet appli c ati ons . to achi eve this goal, we have built an org ani zat i on that is ab le to develop chip set s in re spo n se to the evolvin g technol og y requirement s of our custom ers whil e still delivering pro d u c ts that meet their co st req u ire m en ts. products we offe r only pro d u c ts tha t satisfy hig h perfo rma n ce req u ire m ent s and whi c h are co mpatib le with majo r hardware a n d softwa r e stand ards. our curre n tly available an d so on to be re leased pro d u c ts are ba se d on ou r p r op ri etary de sig n s an d delive r high q uality, high p e rfo r m ance chip set s that compl y with mod e m comm uni cati on stand ard s and ethern e t networkin g stand ards. contacts for ad ditional inform ation about davico m prod uct s , contact the sal e s de pa rtm ent at: hea dquar t er s h s in-chu of fice: n o .6, li-hs i n. r d . vi, sc ie nc e- b a s e d pa r k , hsi n - c h u cit y , taiwan, r. o . c. tel: 886-3-5 7987 97 fax: 886-3 - 6 6698 31 dav i com usa santa clara, california 4633 ol d iron side s dr., ste 318 santa cla r a, ca 950 54, usa. tel: 1-40 8-9 8091 08 fax: 1-408 -9 8092 36 email: s a les@ davic o m8.com email: sales @dav ic om.com. t w w arn in g conditions be y o nd those listed for the absol ute m a ximum ma y des tro y o r damag e t he pr oducts. in addition, conditio n s for sustai ned periods at near t he limits of the operating ran ges w ill stress and ma y tempo r aril y (a nd permane ntl y ) affect and dama ge structur e, performa n ce and /or function. version: dm562 ap-ds-f0 3 nov. 09, 2007

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