View ISL97682_3116067.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 compact 2-3-4-ch led drivers with phase shift control ISL97682, isl97683, isl97684 the ISL97682, isl97683, isl97684 are intersil?s highly integrated 2-3-4-channels led drivers that are suitable for medium size tft-lcd backlights. these parts can drive multiple channels of leds from inputs as low as 4v to outputs of up to 45v. they can also operate from inputs as low as 3v to outputs of up to 26.5v in bootstrap configuration (see figure 26 for 3v operation). the ISL97682, isl97683, isl97684 feature optional channels phase shift control. this feature is used to minimize the input, output ripple characteristics an d load transient, which help eliminate or reduce the video and audio noise interference from the backlight driver operation. the ISL97682, isl97683, isl97684 offer 8-bit pwm dimming for systems that need frequency tuni ng flexibility. with the unique adaptive boost switching archit ecture, the ISL97682, isl97683, isl97684 also offer direct pwm dimming with output, which follows input and achieves linearity as low as 0.009% at 200hz or 1.35% at 30khz. the drivers incorporate dynamic he adroom control that monitors the highest led forward voltage stri ng and uses its feedback signal for the minimum output regula tion. the ISL97682, isl97683, isl97684 incorporates extensive fault protection functions including string open and short circuit detect ions, ovp, and otp. the switching frequency can be selected at eith er 600khz or 1.0mhz in pfm or pwm mode. these parts are available in the thin and compact 16 ld 3mmx3mm tqfn package and operate in ambient temperature from -40c to +85c. features ? ISL97682 - 2 x 100ma channels ? isl97683 - 3 x 50ma channels ? isl97684 - 4 x 50ma channels ? input voltage 4.0v~26.5v with max v out of 45v ? input voltage 3.0v (see figure 26)~24v with max v out of 26.5v ? pwm dimming linearity - pwm dimming with adjustable dimming frequency with duty cycle linear from 0.4% to 100% <30khz - direct pwm dimming with duty cycle linear from 0.009% to 100% at 200hz ? current matching of 0.7% typical from 1%~100% dimming ? selectable 600khz or 1mhz switching frequency in pwm/pfm mode ? dynamic headroom control ?fault protection -string open/short circui t protections, ovp, otp ? thin and compact tqfn-16 3mmx3mm package applications ? tablet to notebook pc displays led backlighting ? pmp led backlighting figure 1a. direct pwm dimming figure 1b. pwm dimming with dimming frequency adjustment using r fpwm figure 1. isl97684 typical application diagrams v in = 4~26.5v vdc vin ovp 45v, 4 x 50ma* ch1 ch4 ch2 ch3 11 16 15 14 13 12 7 lx 9 isl97684 l1 10h d1 co 4.7f ci 10f 1f 10 pgnd 0.1f agnd 1 rset pwmi comp 5 3 8 2 6 fsw 4 fpwm/directpwm en *v in > = 9v and with good leds matching v in = 4~26.5v vdc vin ovp 45v, 4 x 50ma* ch1 ch4 ch2 ch3 11 16 15 14 13 12 7 lx 9 isl97684 l1 10h d1 co 4.7f ci 10f 1f 10 pgnd 0.1f agnd 1 rset pwmi comp 5 3 8 2 6 fsw 4 fpwm/directpwm en *v in >=9v and with good leds matching march 11, 2011 fn7689.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL97682, isl97683, isl97684 2 fn7689.0 march 11, 2011 block diagram ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ISL97682irtz 7682 -40 to +85 16 ld 3x3 tqfn l16.3x3d isl97683irtz 7683 -40 to +85 16 ld 3x3 tqfn l16.3x3d isl97684irtz 7684 -40 to +85 16 ld 3x3 tqfn l16.3x3d ISL97682irtz-evalz evaluation board isl97683irtz-eval evaluation board isl97684irtz-evalz evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL97682, isl97683, isl97684 . for more information on msl please see techbrief tb363 . figure 2. isl97684 block diagram output = 45v, 4 x 50ma* ref gen gm amp comp + - ch1 ch4 v in = 4~26.5v logic fet driver ovp lx isl97684 osc & ramp comp ? = 0 imax ilimit vdc temp sensor pwmi pgnd rset + - agnd vin reg o/p short ref ovp ref vsc internal bias + - 10h/1.5a 4.7f/50v pe open ckt, short ckt detects 8-bit digitizer 1 ovp 4 vset phase select phase shift & pwm controlle r fsw highest vf string detect dynamic headroom control 8-bit dac en fpwm/ directpwm optional fuse directpwm detect fsw detect phase select *v in >= 9v and with good leds matching =
ISL97682, isl97683, isl97684 3 fn7689.0 march 11, 2011 pin configurations ISL97682 (16 ld tqfn) top view isl97683 (16 ld tqfn) top view isl97684 (16 ld tqfn) top view 1 3 4 15 agnd comp rset fsw nc ch2 nc ch1 16 14 13 2 12 10 9 11 6 578 ovp vdc pgnd lx pwmi en vin fpwm_directpwm 1 3 4 15 agnd comp rset fsw nc ch3 ch2 ch1 16 14 13 2 12 10 9 11 6 578 ovp vdc pgnd lx pwmi en vin fpwm_directpwm 1 3 4 15 agnd comp rset fsw ch4 ch3 ch2 ch1 16 14 13 2 12 10 9 11 6 578 ovp vdc pgnd lx pwmi en vin fpwm_directpwm
ISL97682, isl97683, isl97684 4 fn7689.0 march 11, 2011 pin descriptions pin ISL97682 isl97683 isl97684 description 1 agnd agnd agnd analog ground for precision circuits 2 comp comp comp external compensation pin 3 rset rset rset resistor connection for setting led cu rrent, (see equation 2 for calculating the iledpeak) 4 fsw fsw fsw fsw = 0 ~ 0.25 * vdc, boost switching frequency = 600k hz with phase shift an d pfm mode enabled. fsw = 0.25 * vdc ~ 0.5 * vdc, boost switching frequency = 600khz with phase shift and pwm mode enabled. fsw = 0.5 * vdc ~ 0.75 * vdc, boost switching freq uency = 1mhz with phase shift and pwm mode enabled. fsw = 0.75 * vdc ~ vdc, boost switching frequency = 1mhz with phase shift and pfm mode enabled. 5 pwmi pwmi pwmi pwm brightness control pin. 6 en en en enable, can be tied directly to vin if the system lacks of i/o 7 vin vin vin led and driver supply voltage. led supply and driv er supply can be separated if high voltage application is needed and dual supplies are available 8fpwm/ directpwm fpwm/ directpwm fpwm/ directpwm external pwm dimming with frequency modulati on or direct pwm dimming without frequency modulation. with a resistor connected to ground, the dimming frequency will be set by the setting resistor. when this pin is floating, the part enters direct pwm mode such that the di mming follows the input pwm signal without frequency modulation. 9lx lx lxinput to boost switch 10 pgnd pgnd pgnd power ground (lx, c in , and c out power return) 11 vdc vdc vdc de-couple capacitor for internally generated 5v supply 12 ovp ovp ovp overvoltage protection input 13 ch1 ch1 ch1 input 1 to current source, ch, and monitoring 14 nc ch2 ch2 input 2 to current source, ch, and monitoring (isl 97682 is no connect) 15 ch2 ch3 ch3 input 3 to current source, ch, and monitoring 16 nc nc ch4 input 4 to current source, ch, and monitoring (ISL97682, is l97683 are no connect)
ISL97682, isl97683, isl97684 5 fn7689.0 march 11, 2011 5. absolute maximum rating s thermal information vin, en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v vdc, pwmi, fpwm/directpwm, fsw, rs et, comp, ovp . . . -0.3v to 5.5v ch1 to ch4, lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 45v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to agnd pin operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 16 ld tqfn (notes 4, 5) . . . . . . . . . . . . . . . 51 4.6 thermal characterization (typical) psi jt (c/w) 16 ld tqfn (note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.11 maximum continuous junction temperature . . . . . . . . . . . . . . . . .+125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. psi jt is the psi junction-to-top thermal characterization parameter. if the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the jc and jc thermal resistance ratings. electrical specifications all specifications below are characterized at t a = -40c to +85c; v in = 12v, en = 5v, r set = 20k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. parameter description condition min (note 7) typ max (note 7) unit general v in backlight supply voltage, (note 8) t a = +25c 4.0 26.5 v i vin vin active current en = 3.3v 5 ma ivin_stby vin shutdown current en = 0v, t a = 25c 5 a v out output voltage 4.0v < v in 26.5v 45 v v uvlo undervoltage lockout threshold 2.2 2.5 v v uvlo_hys undervoltage lockout hysteresis 100 mv linear regulator v dc ldo output voltage v in > 6v 4.6 4.8 5 v v ldo vdc ldo dropout voltage v in = 5v, i vdc = 20ma 30 200 mv en low guaranteed range for en input low voltage 0.5 v en hi guaranteed range for en input high voltage 1.5 v t en(low) en low time before shut-down 29.5 ms boost switching regulator ss soft-start 100% led duty cycle 7 ms sw ilimit boost fet current limit 1.4 1.8 2.3 a r ds(on) internal boost switch on-resistance 500 m eff_peak peak efficiency v in = 24v, 48 leds, 30ma each, l = 10h with dcr 100m , t a = +25c 90.1 % v in = 12v, 48 leds, 30ma each, l = 10h with dcr 100m , t a = +25c 87 % d max boost maximum duty cycle v fsw < 2.4v (f sw =600khz) 92 % v fsw > 2.4v (f sw =1.0mhz) 85 %
ISL97682, isl97683, isl97684 6 fn7689.0 march 11, 2011 d min boost minimum duty cycle v fsw < 2.4v (f sw =600khz) 8 % v fsw > 2.4v (f sw = 1.0mhz) 15 % f sw boost switching frequency f sw < 2.4v 500 600 650 khz f sw > 2.4v 0.9 1.0 1.1 mhz ilx_leakage lx leakage current lx = 45v, en = 0 10 a reference i match channel-to-channel dc current matching r set = 20k (i led = 20ma for isl97683/4 and 40ma for ISL97682) -2 +2 % r set = 40k (i led = 10ma for isl97683/4 and 20ma for ISL97682) -2.5 +2.5 % i acc current accuracy i led = 20ma (isl97683/4) i led = 40ma (ISL97682) -2 +2 % fault detection v sc channel short circuit threshold 3.8 4.4 4.9 v v temp over-temperature threshold 150 c v temp_acc over-temperature threshold accuracy 5 c v ovplo overvoltage limit on ovp pin 1.18 1.22 1.24 v ovp fault ovp short detection fault level 70 mv current sources v headroom dominant channel current source headroom at ch pin i led = 20ma 500 mv v rset voltage at rset pin 1.2 1.22 1.24 v i led(max) maximum led current per channel ISL97682 100 ma isl97683 50 ma isl97684 50 ma pwm generator v il guaranteed range for pwm input low voltage 0.8 v v ih guaranteed range for pwm input high voltage 1.5 v f pwmi pwmi input frequency range 100 30,000 hz dpwm acc direct pwm dimming output maximum resolution 85 ns t dpwm_on_min direct pwm dimming minimum on-time direct pwm mode 250 450 ns pwm acc pwm dimming with adjustable dimming frequency output resolution 8bit pwm hyst pwmi input allowable jitter hysteresis -0.46 +0.46 lsb f pwm generated pwm dimming frequency range 100 30,000 hz v fpwm voltage at fpwm pin r fpwm = 3.3k 1.20 1.22 1.24 v notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. at maximum v in of 26v, minimum v out is 28v. minimum v out can be lower at lower v in . electrical specifications all specifications below are characterized at t a = -40c to +85c; v in = 12v, en = 5v, r set = 20k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 7) typ max (note 7) unit
ISL97682, isl97683, isl97684 7 fn7689.0 march 11, 2011 typical performance curves figure 3. isl97683 typical efficiency for 3v to 4.2v in a 3p7s, iled = 20ma/ch single supply configuration at f sw = 600khz in pwm mode figure 4. isl97683 typical efficiency for 3v to 4.2v in a 3p7s, iled = 20ma/ch configuration at f sw = 600khz in pwm mode with v in supply = 5v figure 5. isl97683 typical efficiency for 5v in in a 3p7s, iled = 20ma/ch configuration at f sw = 600khz in pwm mode figure 6. isl97684 efficiency for 4p10s at 20ma/ch at 600khz in pwm mode figure 7. isl97864 pwm vs pfm efficiency vs dc at v in = 15v in4p8s configuration figure 8. pfm vs pfm mode for 4p8s vs v in at 1mhz 0 10 20 30 40 50 60 70 80 90 0 20406080100 dc (%) efficiency (%) 3.7v in 4.2v in 3v in 50 55 60 65 70 75 80 85 0 20406080100 efficiency (%) dc (%) 3v in 3.7v in 4.2v in 50 60 70 80 90 050100 efficiency ( %) dc (%) 5v 70 75 80 85 90 95 0 5 10 15 20 25 30 efficiency (%) dc (%) 600k pwm 58 63 68 73 78 83 88 93 0 102030405060708090100 dc (%) efficiency (%) 1000k pwm v in = 15v 1000k pfm v in = 15v 83 84 85 86 87 0102030 1000k pwm 50% 1000k pfm 50%
ISL97682, isl97683, isl97684 8 fn7689.0 march 11, 2011 figure 9. current linearity vs low level pwm dimming duty cycle at 12v in for 4p10s at 20ma/ch figure 10. current linearity vs pwm dimming duty cycle at 12v in for 4p10s at 20ma/ch figure 11. quiescent current vs v in with en = high, no leds connected figure 12. channel voltage vs v in for v in = 12v at 4p10s at 20ma/ch figure 13. line regulation with v in change from 6v to 26v for 4p10s at 20ma/c figure 14. line regulation with v in change from 26v to 6v for 4p10s at 20ma/ch typical performance curves (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.8 1.6 2.4 3.2 4.0 4.8 dc (%) current (ma) measured calculated 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 20 40 60 80 100 ch4 ch2 ch3 ch1 dimming duty cycle (%) channel current (ma) 0 1 2 3 4 5 0 5 10 15 20 25 30 i in (ma) v in (v) 0 0.2 0.4 0.6 0.8 1.0 0102030 v headroom (v) v in (v) ch4 ch2 ch3 ch1 v in (5v/div) i in (0.5a/div) iled (20ma/div) v in (5v/div) i in (0.5a/div) iled (20ma/div)
ISL97682, isl97683, isl97684 9 fn7689.0 march 11, 2011 figure 15. load regulation with iled change fdrom 100% to 0% pwm dimming, v in = 12v at 20ma/ch figure 16. v out ripple voltage, v in = 12v, 4p10s at 20ma/ch figure 17. in-rush and led current at v in = 5v for 4p10s at 20ma/ch figure 18. in-rush and led current at v in = 12v for 4p10s at 20ma/ch typical performance curves (continued) v o (1v/div) iled (20ma/div) vout(50mv/div) lx=20v/div v out (50mv/div) lx = 20v/div) vout iin(0.5a/div) iled(20ma/div) en v out i in (0.5a/div) iled (20ma/div) en vout iin(0.5a/div) iled(20ma/div) en v out i in (0.5a/div) iled (20ma/div) en
ISL97682, isl97683, isl97684 10 fn7689.0 march 11, 2011 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the ISL97682, isl97683, isl97684 employs current mode control boost architecture that has a fast curr ent sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly change to an ac/dc adapter without rendering a noticeable visual nuisance. the number of leds that can be driven by the ISL97682, isl97683, isl97684 de pend on the type of led chosen in the application. th e ISL97682, isl97683, isl97684 are capable of boosting up to 45v and typically driving 13 leds in series for each of the 4 channels, enabling a total of 52 pieces of the 3.2v/20ma type of leds. ovp the overvoltage protection (ovp) pi n has a function of setting the overvoltage trip level as well as limiting the v out regulation range. the ISL97682, isl97683, isl97684 ovp threshold is set by r upper and r lower shown by equation 1: v out can only regulate between 42% and 100% of the v out_ovp such that: allowable v out = 42% to 100% of v out_ovp for example, if 10 leds are used with the worst case being v out of 35v. if r 1 and r 2 are chosen such that the ovp level is set at 40v, then the v out is allowed to operate between 16.8v and 40v. if the requirement is changed to 4 leds of 14v v out application, then the ovp level must be reduced and users should follow the v out = (42% ~100%) ovp level requirement. otherwise, the headroom control will be disturbe d such that the channel voltage can be much higher than expected and sometimes can prevent the driver from operating properly. the ratio of the ovp capacitor should be the inverse of the ovp resistor. for example: if r upper /r lower = 33/1, then c upper /c lower = 1/33 with c upper = 100pf and c upper =3.3nf. enable an en signal is required to enable the internal regulator for normal operation. if there is no signal fo r longer than 28ms, the device will enter shutdown. power sequence there is no specific power sequence requirement for the ISL97682, isl97683, isl97684. the en signal can be tied to v in but not the vdc that will prevent the device from powering up. current matching and current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 19. the led peak current is set by translating the r set current to the output with a scaling factor of 401.8/r set . the source terminals of the current source mosfets ar e designed to run at 500mv to optimize power loss versus accu racy requirements. the sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. these parameters are optimized for current matching and absolute current accuracy. however, the absolute accuracy is additionally determined by the external r set . a 1% tolerance resistor is recommended. dynamic headroom control the ISL97682, isl97683, isl97684 feature a proprietary dynamic headroom control circuit that detects the highest forward voltage string or the lowe st voltage from any of the ch pins digitally. when the lowest ch voltage is lower than the short circuit threshold (v sc ), such voltage will be used as the feedback signal for the boost regulator. the boost makes the output to the correct level such that the lowest ch is at the target headroom voltage. since all led stacks ar e connected to the same output voltage, the other ch pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same current. the output voltage will regulate cycle-by-cycle and it is always referenced to the highest forward voltage string in the architecture. dimming controls the ISL97682, isl97683, isl97684 allow two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment 2. pwm chopping of the led current defined in step 1. there are various ways to achieve dc or pwm current control, which will be described in the following. (eq. 1) v out_ovp = 1.22v * (r upper + r lower )/r lower figure 19. simplified cu rrent source circuit ref + - pwm dimming rset + -
ISL97682, isl97683, isl97684 11 fn7689.0 march 11, 2011 maximum dc current setting the initial brightness should be set by choosing an appropriate value for r set . this should be chosen to fix the maximum possible led current as shown in equation 2 for ISL97682 and equation 3 for isl97683 and isl97684: dc current adjustment once r set is fixed, the led dc current can be adjusted. for example, in the 4-channel is l97684, if the maximum required led current (i led(max) ) is 20ma, rearranging equation 3 yields equation 4: pwm control the ISL97682, isl97683, isl97684 have high speed 8-bit digitizers that decode the incoming pwm signal and convert it into 2- 3- or 4- channels of 8-bi t pwm current with a phase shift function that will be described later. during the pwm on period, the led peak current is defined by the r set resistor value. the average led current of each channel is controlled by i ledmax and the pwm duty cycle in percent shown by equation 5: when the pwm input = 0, all channels are disconnected and the i led is guaranteed to be <5a in this state. the pwm dimming frequency is adjusted by a resistor at the rfpwm pin, described in ?pwm dimming frequency adjustment? on page 12. i ledmax 804 () r set -------------- - = (eq. 2) i ledmax 402 () r set -------------- - = (eq. 3) r set 402 () 0.02 ? 20.1k == (eq. 4) i led ave () i ledmax pwm = (eq. 5) figure 20. conventional 4-ch led driver with 10% pwm dimming channel current (upper) and total current (lower) iled1-20ma iled_total_80ma time (ms) iled2-20ma iled3-20ma iled4-20ma 51015 figure 21. phase shift 4-ch led driver with 10% pwm dimming channel current (upper) and total current (lower) iled1-20ma iled_total_20ma time (ms) iled2-20ma iled3-20ma iled4-20ma 5 10 figure 22. conventional led driver pwm dimming channel and total current at 50% duty cycle iled4-20ma iled_total_80ma time (ms) iled3-20ma iled2-20ma iled1-20ma 5 10 figure 23. equal phase shift led driver pwm dimming channel at 50% duty cycle iled4-20ma iled_total_40ma time (ms) iled3-20ma iled2-20ma iled1-20ma 5 10
ISL97682, isl97683, isl97684 12 fn7689.0 march 11, 2011 phase shift control the ISL97682, isl97683, isl97684 are capable of delaying the phase of each current source. conventional led drivers exhibit the worst load transients to the boost circuit by turning on all channels simultaneously as sh own in figures 20 and 21. in contrast, the ISL97682, isl97683, isl97684 phase shifts each channel by turning them on on ce during each pwm dimming period as shown in figures 23 and 24. at each dimming duty cycle except at 100%, the sum of the phase shifted total current will be less than a conventional led drivers? total current. for ISL97682, the two channels are separated by 180. for isl97683, the three channels are separated by 90 and not 120. for isl97684, the four channels are separated by 90. if the channels are combined for higher current application, the phase shift function must be di sabled by running the part in direct pwm mode by floati ng the rfpwm/directpwm and selecting switching frequency by biasing the fsw pin as explained in table 2. pwm dimming frequency adjustment the dimming frequency is set by an external resistor at the rfpwm/directpwm pin to gnd calculated by equation 6: where fpwm is the desirable pwm dimming frequency and r fpwm is the setting resistor. do not bias rfpwm/directpwm if direct pwm dimming is used; see table 1 for clarification. the pwm dimming frequency can be set or applied up to 30khz with duty cycle from 0.4% to 100% . the lower limit of 0.4% is the result of 8-bit digitizer resolution. direct pwm dimming the ISL97682, isl97683, isl97684 can also operate in direct pwm dimming mode such that th e output follows the input pwm signal without phase shifting. the fsw pin can still be used to select between 600khz and 1m hz in pwm or pfm mode as explained in ?pin descriptions? on page 4. to use direct pwm mode, users should float the rf pwm/directpwm pin. the input pwm frequency should be limited to 30khz and the minimum duty cycle be calculated by equation 7: for example, for a 200hz input pwm frequency, the minimum duty cycle is: table 1 shows the pwm dimming with phase shift and direct pwm dimming configurations. switching frequency and pwm/pfm mode when the fsw pin is biased from vdc with a resistor divider r upper and r lower , the switching frequency and pfm/pwm mode will change according to th e following fsw levels shown in table 2 with the recommended r upper and r lower . the ISL97682, isl97683, isl97684 goes into pfm mode at f sw = 600khz/1mhz when the fsw pin is biased at 0/vdc volts. the part will only go into pfm mode depending on the led output voltage and loading conditions an d can be more efficient than running the part in pwm mode as shown in figures 5 and 6. the dimming frequency can be set or applied up to 30khz with duty cycle from 0.4% to 100%. the lower limit of 0.4% is the result of an 8-bit digitizer resolution. soft-start the in-rush current will flow towards c out when v in is applied and it is determined by the ramp rate of v in and the values of c out and l. once the part is enabled, the boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. the ISL97682, isl97683, isl97684 include a soft-start feature where this current limit starts at a low value (225ma). this is stepped up to the final 1.8a current limit in 7 further steps of 225ma. these steps will happen over approximately 8ms and will be extended at a low led pwm frequency if the led duty cycle is low. this allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. figure 24. isl97684 4 channels phase shift illustration iled1 iled2 iled3 iled4 iled1 t on pwmi 60% 40% 60% 40% t pwmin t fpwm (t pwmout ) t off (eq. 6) f pwm 12.4 () 10 7 rfpwm -------------------------------- - = ?? ?? (eq. 7) min duty cycle 450ns input pwm frequency = table 1. rfwm/ directpwm function phase shift dimming resolution connects with resistor pwm dimming with frequency adjust yes 8-bit floating directpwm without frequency adjust no n/a table 2. fsw f sw phase shift mode r upper r lower (0 ~ 0.25)*vdc 600khz yes pfm open 0 (0.25~0.5)*vdc 600khz yes pwm 156k 100k (0.5~0.75)*vdc 1.0mhz yes pwm 100k 122k (0.75~1) vdc 1.0mhz yes pfm 0 open (eq. 8) min dc 450ns 200hz 0.009% ==
ISL97682, isl97683, isl97684 13 fn7689.0 march 11, 2011 fault protection and monitoring the ISL97682, isl97683, isl97684 feature extensive protection functions to cover all the perceivable failure conditions. the failure mode of a led can be either open circuit or as a short. the behavior of an open circuited led can also take the form of either infinite resistance (or fo r some leds, a zener diode), which is integrated into the device in parallel with the now opened led. for basic leds (which do not have built-in zener diodes), an open circuit failure of an led will only result in the loss of one channel of leds without affecting other channels. similarly, a short circuit condition on a channel that result s in that channel being turned off does not affect other channels unless a similar fault is occurring. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the ISL97682, isl97683, isl97684 use feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 3 for more details. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit th reshold. when an led becomes shorted, the action taken is descri bed in table 3. the short circuit threshold is 4.4v. open circuit protection (ocp) when one of the leds becomes op en circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the ISL97682, isl9 7683, isl97684 monitors the current in each channel such that any string which reaches the intended output current, is considered ?good?. should the current subsequently fall below the target, the channel will be considered an ?open circuit?. furthermore, should the boost output of the ISL97682, isl97683, isl97684 reach the ovp limit, all channels which are no t ?good? will immediately be considered as ?open circuit?. de tection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. some users employ some special types of leds that have zener diode structure in parallel with the led for esd enhancement, thus enabling open circuit operation. wh en this type of led goes open circuit, the effect is as if the led forward voltage has increased, but no light is emitted. any affected string will not be disabled, unless the failure results in th e boost ovp limit being reached, allowing all other leds in the st ring to remain functional. care should be taken in this case that the boost ovp limit and scp limit are set properly, in order to assu re that multiple failures on one string do not cause all other good channels to be faulted out. this is due to the increased forward voltage of the faulty channel making all other channels look as if they have led shorts. see table 3 for details for responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit monitors the output voltage and keeps the voltage at a safe level. the ov p threshold is set as equation 9: these resistors should be large to minimize the power loss. for example, a 1mk r upper and 30k r lower sets ovp to 41.2v. large ovp resistors also allow c out discharges slowly during the pwm off time. parallel capacitors should also be placed across the ovp resistors such that r upper /r lower = c lower /c upper . using a c upper value of at least 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which is important when using high value resistors. undervoltage lockout if the input voltage falls below the uvlo level of 2.5v, the device will stop switching and be reset. operation will restart only if the device is re-powered and re-enabled once the input voltage is back in the normal operating range. over-temperature protection (otp) the ISL97682, isl97683, isl97684 over-temperature protection threshold is set to +150c. each time this is reached, the boost will stop switching and the output current sources will be switched off. for the extensive fault protection conditions, please refer to figure 25 and table 3 for details. ovp 1.22v r upper r lower + () r lower ? = (eq. 9)
ISL97682, isl97683, isl97684 14 fn7689.0 march 11, 2011 figure 25. simplified fault protections vin imax i limit vin vset/2 reg logic o/p fet vsc thrm shdn otp phase shift and logic control vset pwm1/oc1/sc1 ovp lx + ref t2 t1 temp sensor q1 vset pwm4/oc4/sc4 q4 ch4 vout short driver - + - table 3. protections table case failure mode detection mode failed channel action good channels action v out regulated by 1 ch1 short circuit over-temperature protection limit (otp) not triggered and ch1 < 4.4v ch1 on and burns power ch2 through ch4 normal highest vf of ch2 through ch4 2 ch1 short circuit otp triggered but vch1 < 4.4v all channels switched off until power-cycled. highest vf of ch2 through ch4 3 ch1 short circuit otp not triggered but ch1 > 4.4v ch1 faults out after 6 pwm cycle (7-18 in direct pwm) time-out ch2 through ch4 normal highest vf of ch2 through ch4 4ch1 open circuit with infinite resistance otp not triggered and ch1 < 4.4v v out will ramp to ovp. ch1 will time-out after 6 pwm cycles (7-18 in direct pwm) and switch off. v out will drop to normal level. ch2 through ch4 normal highest vf of ch2 through ch4 5ch1 led open circuit but has paralleled zener otp not triggered and ch1 < 4.4v ch1 remains on and has highest vf, thus v out increases ch2 through ch4 on, q2 through q4 burn power vf of ch1 6ch1 led open circuit but has paralleled zener otp triggered but ch1 < 4.4v ch1 goes off same as ch1 vf of ch1 7ch1 led open circuit but has paralleled zener otp not triggered but chx > 4.4v ch1 remains on and has highest vf, thus v out increases. v out increases then ch-x switches off after 6 pwm cycles. this is an unwanted shut off and can be prevented by setting ovp at an appropriate level. vf of ch1 8 channel-to-channel vf too high otp triggered but chx < 4.4v all channels switched off until chip cooled highest vf of ch1 through ch4 9 output led stack voltage too high v out > v ovp driven with normal current. any chan nel that has insufficient headroom will fault out after 6 pwm cycle (7-18 in direct pwm) time-out. highest vf of ch1 through ch4
ISL97682, isl97683, isl97684 15 fn7689.0 march 11, 2011 components selections according to the inductor voltage-second balance principle, the change of inductor current during the switching regulator on-time is equal to the change of inductor current during the switching regulator off-time. since the voltage across an inductor is as shown in equation 10: and i l @ on = i l @ off, therefore: where d is the switching duty cycle defined by the turn-on time over the switching periods. v d is a schottky diode forward voltage that can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle as equations 12 and 13: input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interaction between the regulator and input supply, thereby improving system stability. the high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. a capacitor with low internal seri es resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. inductor the selection of the inductor should be based on its maximum and saturation current (i sat ) characteristics, power dissipation (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. the inductor?s maximum current capability must be adequate enough to handle the peak curren t at the worst case condition. additionally if an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi susceptible applications, such as led backlighting. the peak current can be derived from the voltage across the inductor during the off-period, expressed in equation 14: the choice of 85% is just an average term for the efficiency approximation. the first term is the average current, which is inversely proportional to the inpu t voltage. the second term is the inductor current change, which is inversely proportional to l and f sw as a result, for a given switching. applications low voltage operations the ISL97682, isl97683, isl97684 vin pin can be separately biased from the leds power input to allow low voltage operation. for systems that have only single supply, vout can be tied to the driver vin pin to allow initial start-up; see figure 26. the circuit works as follows; when the input voltage is available and the device is not enabled, the v out follows v in with a schottky diode voltage drop. the v out bootstrapped to vin pin allows an initial start-up once the part is enabled. once the driver starts up with v out regulating to the target, the vin pin voltage also increases. as long as the v out does not exceed 26.5v and the extra power loss on vin is acceptable, this co nfiguration can be used for input voltage as low as 3.0v. for syst ems where a single input supply of 4v to 5.5v is available, the vin pin can be shorted to vdc, allowing a slight gain in efficiency due to bypassing the internal ldo. for systems that have dual supplies, the vin pin can be biased from 5v to 12v. the input voltage can be as low as 2.7v without the limitations previously mentioned; see figure 27. v l l i l t ? = (eq. 10) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 11) v o v i 11d ? () ? = ? (eq. 12) dv o ( v i ) v o ? ? = (eq. 13) il peak v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f sw ) ? ? [] ? + ? = (eq. 14)
ISL97682, isl97683, isl97684 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7689.0 march 11, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL97682, isl97683, isl97684 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php figure 26. single supply 3v operation v in = 3v ~ 24v vin vdc en pwmi fsw rset comp lx ovp pgnd ch1 ch2 ch3 ch4 agnd isl97684 v out < 26.5v 20ma figure 27. dual supplies 2.7v operation 2.7 to 24 v in vin vdc en pwmi fsw rset comp lx ovp pgnd ch1 ch2 ch3 ch4 agnd isl97684 v out < 26.5v 20ma 5v to 12v bias revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/11/11 fn7689.0 initial release.
ISL97682, isl97683, isl97684 17 fn7689.0 march 11, 2011 package outline drawing l16.3x3d 16 lead thin quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 m a c 4 6 6 0.05 1 12 4 9 13 16 8 5 1.60 sq 16x 0.23 16x 0.400.10 4x 1.50 12x 0.50 (16x 0.60) ( 1.60) (2.80 typ) (16x 0.23) (12x 0.50) c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 0.75 0.05 0.08 0.10 c c c index area see detail ?x? jedec reference draw ing: mo-220 weed. 7.

▲Up To Search▲

Price & Availability of ISL97682

	To Download ISL97682 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .