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| general description the max1718t step-down controller is intended for core cpu dc-to-dc converters in notebook computers. it fea- tures a dynamically adjustable output, ultra-fast transient response, high-dc accuracy, and high efficiency need- ed for leading-edge cpu core power supplies. maxim? proprietary quick-pwm quick-response, constant-on- time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on response to load transients while maintaining a relatively constant switching frequency. the output voltage can be dynamically adjusted through the 5-bit digital-to-analog converter (dac) over a 0.6v to 1.75v range. the max1718t has an internal multiplexer that accepts three unique 5-bit vid dac codes corresponding to performance, battery, and sus- pend modes. precision slew-rate control provides ?ust- in-time?arrival at the new dac setting, minimizing surge currents to and from the battery. a pair of complementary offset control inputs allows easy compensation for ir drops in pcb traces or cre- ation of a voltage-positioned power supply. voltage positioning modifies the load-transient response to reduce output capacitor requirements and total system power dissipation. single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down the 5v system supply instead of the battery) at a higher switching frequency allows the mini- mum possible physical size. the max1718t is available in a 28-pin qsop package. applications 2-cell to 4-cell li+ battery to cpu core supply converters 5v to cpu core supply converters features quick-pwm architecture ?% v out accuracy over line and load 5-bit on-board dac with input muxes precision-adjustable v out slew control 0.6v to 1.75v output adjust range precision offset control supports voltage-positioned applications 2v to 28v battery input range requires a separate 5v bias supply 200khz/300khz/550khz/1000khz switching frequency overvoltage/undervoltage protection drives large synchronous-rectifier fets 700? (typ) i cc supply current 2? (typ) shutdown supply current 2v ?% reference output vgate blanking during transition small 28-pin qsop package max1718t notebook cpu step-down controller ________________________________________________________________ maxim integrated products 1 19-2682; rev 1; 10/08 ordering information quick-pwm is a trademark of maxim integrated products, inc. dual mode is a trademark of maxim integrated products, inc. v cc vcc 5v input batt 2v to 28v power-good output skp/sdn ilim output 0.6v to 1.75v d0 d1 d2 shutdown dl lx v+ dh bst gnd fb neg pos vgate ovp v dd d3 d4 s1 s0 sus mux control suspend input decoder zmode time cc ref ton dual mode vid mux inputs max1718t minimal operating circuit for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. part temp range pin-package 28 qsop -40? to +85? MAX1718TEEI
max1718t notebook cpu step-down controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v v+ = 15v, v cc = v dd = v skp/ sdn = 5v, v out = 1.25v, t a = 0? to +85? , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +30v v cc , v dd to gnd .....................................................-0.3v to +6v d0?4, zmode , vgate, ovp , sus to gnd ..........-0.3v to +6v skp/ sdn to gnd ...................................................-0.3v to +16v ilim, cc, ref, pos, neg, s1, s0, ton, time to gnd .....................................-0.3v to (v cc + 0.3v) dl to gnd ..................................................-0.3v to (v dd + 0.3v) bst to gnd ............................................................-0.3v to +36v dh to lx .....................................................-0.3v to (bst + 0.3v) lx to bst..................................................................-6v to +0.3v ref short circuit to gnd ...........................................continuous continuous power dissipation 28-pin qsop (derate 10.8mw/? above +70?).........860mw operating temperature range ..........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units pwm controller battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v dac codes from 0.9v to 1.75v -1 +1 dc output voltage accuracy v v+ = 4.5v to 28v, includes load regulation error dac codes from 0.6v to 0.875v -1.5 +1.5 % line regulation error v cc = 4.5v to 5.5v, v batt = 4.5v to 28v 5 mv input bias current fb, pos, neg -0.2 +0.2 a pos, neg common-mode range 0.4 2.5 v pos, neg differential range pos - neg -80 +80 mv pos, neg offset gain vfb / (pos - neg); pos - neg = 50mv 0.81 0.86 0.91 v/v 150khz nominal, r time = 120k -8 +8 380khz nominal, r time = 47k -12 +12 time frequency accuracy 38khz nominal, r time = 470k -12 +12 % v v+ = 5v, fb = 1.2v, ton = gnd (1000khz) 230 260 290 ton = ref (550khz) 165 190 215 ton = open (300khz) 320 355 390 on-time (note 1) v v+ = 12v, fb = 1.2v ton = v cc (200khz) 465 515 565 ns ton = v cc , open, or ref (200khz, 300khz, or 550khz) 400 500 minimum off-time (note 1) ton = gnd (1000khz) 300 375 ns bias and reference quiescent supply current (v cc ) measured at v cc , fb forced above the regulation point 700 1200 ? quiescent supply current (v dd ) measured at v dd , fb forced above the regulation point <1 5 a quiescent battery supply current (v+) 25 40 ? shutdown supply current (v cc ) skp/ sdn = gnd 2 5 ? shutdown supply current (v dd ) skp/ sdn = gnd <1 5 a shutdown battery supply current (v+) skp/ sdn = gnd, v cc = v dd = 0v or 5v <1 5 a max1718t notebook cpu step-down controller _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v v+ = 15v, v cc = v dd = v skp/ sdn = 5v, v out = 1.25v, t a = 0? to +85? , unless otherwise noted.) parameter conditions min typ max units reference voltage v cc = 4.5v to 5.5v, no ref load 1.98 2 2.02 v reference load regulation i ref = 0 to 50? 0.01 v ref sink current ref in regulation 10 a fault protection overvoltage trip threshold measured at fb 1.95 2.00 2.05 v overvoltage fault propagation delay fb forced 2% above trip threshold 10 s output undervoltage fault protection threshold with respect to unloaded output voltage 65 70 75 % output undervoltage fault propagation delay fb forced 2% below trip threshold 10 s output undervoltage fault blanking time from skp/ sdn signal going high, clock speed set by r time 256 clks t a = +25? to +85? 90 100 110 current-limit threshold voltage (positive, default) gnd - lx, ilim = v cc t a = 0? to +85? 85 115 mv v ilim = 0.5v 35 50 65 current-limit threshold voltage (positive, adjustable) gnd - lx ilim = ref (2v) 165 200 230 mv current-limit threshold voltage (negative) lx - gnd, ilim = v cc -140 -117 -95 mv current-limit threshold voltage (zero crossing) gnd - lx 4 mv current-limit default switchover threshold 3v cc - 1 v cc - 0.4 v thermal shutdown threshold hysteresis = +10? 150 ? v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v vgate lower trip threshold measured at fb with respect to unloaded output voltage -12 -10 -8 % vgate upper trip threshold measured at fb with respect to unloaded output voltage +8 +10 +12 % vgate propagation delay fb forced 2% outside vgate trip threshold 10 s vgate output low voltage i sink = 1ma 0.4 v vgate leakage current high state, forced to 5.5v 1 a gate drivers dh gate-driver on-resistance bst - lx forced to 5v 1.0 3.5 dl, high state (pullup) 1.0 3.5 dl gate-driver on-resistance dl, low state (pulldown) 0.4 1.0 dh gate-driver source/sink current dh forced to 2.5v, bst - lx forced to 5v 1.6 a dl gate-driver sink current dl forced to 2.5v 4 a dl gate-driver source current dl forced to 2.5v 1.6 a max1718t notebook cpu step-down controller 4 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1, v v+ = 15v, v cc = v dd = v skp/ sdn = 5v, v out = 1.25v, t a = -40? to +85? , unless otherwise noted.) (note 2) electrical characteristics (continued) (circuit of figure 1, v v+ = 15v, v cc = v dd = v skp/ sdn = 5v, v out = 1.25v, t a = 0? to +85? , unless otherwise noted.) parameter conditions min typ max units dl rising 35 dead time dh rising 26 ns logic and i/o logic input high voltage d0?4, zmode, sus, ovp 2.4 v logic input low voltage d0?4, zmode, sus, ovp 0.8 v dac b-mode programming resistor, low d0?4, 0 to 0.4v or 2.6v to 5.5v applied through resistor, zmode = v cc 1.05 k dac b-mode programming resistor, high d0?4, 0 to 0.4v or 2.6v to 5.5v applied through resistor, zmode = v cc 95 k pullup 40 d0?4 pullup/pulldown entering impedance mode pulldown 8 k d0?4, zmode = gnd -1 +1 logic input current zmode, sus, ovp -1 +1 ? for high v cc - 0.4 for open 3.15 3.85 for ref 1.65 2.35 four level input logic levels (ton, s0, s1) for low 0.5 v skp/ sdn , s0, s1, and ton input current skp/ sdn , s0, s1, ton forced to gnd or v cc -3 +3 ? skp/ sdn = logic high (skip mode) 2.8 6.0 skp/ sdn = open (pwm mode) 1.4 2.2 skp/ sdn = logic low (shutdown mode) 0.5 skp/ sdn input levels to enable no-fault mode 12 15 v skp/ sdn float level i skp / sdn = 0? 1.8 2.2 v parameter conditions min typ max units pwm controller dac codes from 0.9v to 1.75v -1.5 +1.5 dc output voltage accuracy v v+ = 4.5v to 28v, includes load regulation error dac codes from 0.6v to 0.875v -2.0 +2.0 % 150khz nominal, r time = 120k -8 +8 380khz nominal, r time = 47k -12 +12 time frequency accuracy 38khz nominal, r time = 470k -12 +12 % v v+ = 5v, v fb = 1.2v, ton = gnd (1000khz) 230 290 ton = ref (550khz) 165 215 ton = open (300khz) 320 390 on-time (note 1) v v+ = 12v, v fb = 1.2v ton = v cc (200khz) 465 565 ns max1718t notebook cpu step-down controller _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v v+ = 15v, v cc = v dd = v skp/ sdn = 5v, v out = 1.25v, t a = -40? to +85? , unless otherwise noted.) (note 2)) parameter conditions min typ max units ton = v cc , open, or ref (200khz, 300khz, or 550khz) 500 minimum off-time (note 1) ton = gnd (1000khz) 375 ns bias and reference quiescent supply current (v cc ) measured at v cc , fb forced above the regulation point 1300 ? quiescent supply current (v dd ) measured at v dd , fb forced above the regulation point 5 a quiescent battery supply current (v+) 40 ? shutdown supply current (v cc )v skp/ sdn = 0 5 ? shutdown supply current (v dd )v skp/ sdn = 0 5 ? shutdown battery supply current (v+) v skp/ sdn = 0, v cc = v dd = 0 or 5v 5 a reference voltage v cc = 4.5v to 5.5v, no ref load 1.98 2.02 v fault protection overvoltage trip threshold measured at fb 1.95 2.05 v output undervoltage protection threshold with respect to unloaded output voltage 65 75 % current-limit threshold voltage (positive, default) gnd - lx, ilim = v cc 80 115 mv ilim = 0.5v 33 65 current-limit threshold voltage (positive, adjustable) gnd - lx ilim = ref (2v) 160 240 mv current-limit threshold voltage (negative) lx - gnd, ilim = v cc -145 -90 mv v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v vgate lower trip threshold measured at fb with respect to unloaded output voltage -12.5 -7.5 % vgate upper trip threshold measured at fb with respect to unloaded output voltage +7.5 +12.5 % gate drivers dh gate-driver on-resistance bst - lx forced to 5v 3.5 dl, high state (pullup) 3.5 dl gate-driver on-resistance dl, low state (pulldown) 1.0 logic and i/o logic input high voltage d0?4, zmode, sus, ovp 2.4 v logic input low voltage d0?4, zmode, sus, ovp 0.8 v max1718t notebook cpu step-down controller 6 _______________________________________________________________________________________ typical operating characteristics (circuit of figure 1, v v+ = 12v, v dd = v cc = v skp/ sdn = 5v, v out = 1.25v, t a = +25?, unless otherwise noted.) 95 50 0.01 0.1 1 10 100 efficiency vs. load current 300khz voltage positioned max1718t toc01 load current (a) efficiency (%) 65 75 85 80 70 60 55 90 skip mode v+ = 7v skip mode v+ = 20v pwm mode v+ = 12v pwm mode v+ = 20v skip mode v+ = 12v pwm mode v+ = 7v 400 300 200 100 0 010 51520 frequency vs. load current max1718t toc02 load current (a) frequency (khz) pwm mode skip mode 250 280 270 260 290 300 310 320 330 340 350 7.0 13.8 10.4 17.2 20.6 24.0 frequency vs. input voltage max1718t toc03 input voltage (v) frequency (khz) i out = 18a i out = 3a 323.0 324.0 323.5 325.0 324.5 325.5 326.0 -40 10 -15 35 60 85 frequency vs. temperature max1718t toc04 temperature ( c) frequency (khz) i out = 19a 20 30 25 40 35 45 50 -40 10 -15 35 60 85 output current at current limit vs. temperature max1718t toc05 temperature ( c) current (a) 0 300 200 100 400 500 600 700 800 900 1000 5 10152025 no-load supply current vs. input voltage max1718t toc06 input voltage (v) supply current ( a) i cc + i dd i+ note 1: on-time specifications are measured from 50% to 50% at the dh pin, with lx forced to 0v, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times can be different due to mos- fet switching speeds. note 2: specifications to t a = -40? are guaranteed by design and not production tested. electrical characteristics (continued) (circuit of figure 1, v v+ = 15v, v cc = v dd = v skp/ sdn = 5v, v out = 1.25v, t a = -40? to +85? , unless otherwise noted.) (note 2)) parameter conditions min typ max units dac b-mode programming resistor, low d0?4, 0 to 0.4v or 2.6v to 5.5v applied through resistor, zmode = v cc 1.05 k dac b-mode programming resistor, high d0?4, 0 to 0.4v or 2.6v to 5.5v applied through resistor, zmode = v cc 95 k max1718t 40 s/div dynamic output voltage transition (pwm mode) a max1718t toc11 b0a a = v out , 100mv/div, ac-coupled b = inductor current, 10a/div c = vgate, 5v/div d = zmode, 5v/div c d v out = 1.15v to 1.25v i out = 3a, r time = 62k notebook cpu step-down controller _______________________________________________________________________________________ 7 0 5 10 15 20 25 30 35 40 5 10152025 no-load supply current vs. input voltage max1718t toc07 input voltage (v) supply current (ma) i cc + i dd i+ 40 s/div load-transient response (pwm mode) a max1718t toc08b b0a a = v out , 50mv/div, ac-coupled b = inductor current, 10a/div 40 s/div load-transient response (skip mode) a b max1718t toc08a 0a a = v out , 50mv/div, ac-coupled b = inductor current, 10a/div 100 s/div startup waveform (pwm mode, no load) a max1718t toc09 b0a a = v out , 1v/div b = inductor current, 10a/div c = skp/sdn, 5v/div c 100 s/div startup waveform (pwm mode, i out = 12a) a max1718t toc10 b0a a = v out , 1v/div b = inductor current, 10a/div c = skp/sdn, 5v/div c typical operating characteristics (continued) (circuit of figure 1, v v+ = 12v, v dd = v cc = v skp/ sdn = 5v, v out = 1.25v, t a = +25?, unless otherwise noted.) max1718t notebook cpu step-down controller 8 _______________________________________________________________________________________ 100 s/div shutdown waveform (pwm mode, no load) a max1718t toc13 b0a a = v out , 1v/div b = inductor current, 10a/div c = skp/sdn, 5v/div c 100 s/div shutdown waveform (pwm mode, i out = 12a) a max1718t toc14 b0a a = v out , 1v/div b = inductor current, 10a/div c = skp/sdn, 5v/div c typical operating characteristics (continued) (circuit of figure 1, v v+ = 12v, v dd = v cc = v skp/ sdn = 5v, v out = 1.25v, t a = +25?, unless otherwise noted.) 40 s/div dynamic output voltage transition (pwm mode) a max1718t toc12 b0a a = v out , 500mv/div, ac-coupled b = inductor current, 10a/div c = vgate, 5v/div d = sus, 5v/div c d v out = 0.7v to 1.25v i out = 3a, r time = 62k offset function scale factor vs. dac setting max1718t toc15 dac setting (v) pos-neg scale factor measured theoretical 1.00 1.10 1.05 1.25 1.20 1.15 1.40 1.35 1.30 1.45 -300 -100 -200 0 100 200 output voltage vs. pos-neg differential max1718t toc16 pos-neg (v) output voltage (v) max1718t notebook cpu step-down controller _______________________________________________________________________________________ 9 typical operating characteristics (continued) (circuit of figure 1, v v+ = 12v, v dd = v cc = v skp/ sdn = 5v, v out = 1.25v, t a = +25?, unless otherwise noted.) 0 5 15 10 20 25 -0.48 output voltage distribution max1718t toc17 output voltage error (%) sample percentage (%) -0.24 0.48 0.24 0 v out = 1.25v 0 5 15 10 20 25 1.995 reference voltage distribution max1718t toc18 reference voltage (v) sample percentage (%) 1.998 2.005 2.002 2.000 pin description pin name function 1v+ battery voltage sense connection. connect v+ to input power source. v+ is used only for pwm one-shot timing. dh on-time is inversely proportional to input voltage over a range of 2v to 28v. 2 skp/ sdn combined shutdown and skip-mode control. drive skp/ sdn to gnd for shutdown. leave skp/ sdn open for low-noise forced-pwm mode, or drive to v cc for pulse-skipping operation. low-noise forced-pwm mode causes inductor current recirculation at light loads and suppresses pulse-skipping operation. forcing skp/ sdn to 12v to 15v disables both the overvoltage protection and undervoltage protection circuits and clears the fault latch, with otherwise normal pulse-skipping operation. do not connect skp/ sdn to > 15v. 3time slew-rate adjustment pin. connect a resistor from time to gnd to set the internal slew-rate clock. a 470k to 47k resistor sets the clock from 38khz to 380khz, f slew = 150khz 5 120k / r time . 4 fb feedback input. connect fb to the junction of the external inductor and the positioning resistor (figure 1). 5 neg feedback offset adjust negative input. the output shifts by an amount equal to the difference between pos and neg multiplied by a scale factor that depends on the dac codes (see the integrator amplifiers/output voltage offsets section). connect both pos and neg to ref if the offset function is not used. 6cc integrator capacitor connection. connect a 47pf to 1000pf (47pf typ) capacitor from cc to gnd to set the integration time constant (see the integrator amplifiers/output voltage offsets section). 7, 8 s0, s1 suspend-mode voltage select input. s0 and s1 are four-level digital inputs that select the suspend-mode vid code for the suspend-mode multiplexer inputs. if sus is high, the suspend-mode vid code is delivered to the dac (see the internal multiplexers (zmode/sus) section). 9v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage (4.5v to 5.5v) with a series 20 resistor. bypass to gnd with a 0.22? (min) capacitor. max1718t notebook cpu step-down controller 10 ______________________________________________________________________________________ pin description (continued) pin name function 10 ton on-time selection control input. this is a four-level input that sets the k factor (table 2) to determine dh on-time. connect ton to the following pins for the indicated operation: gnd = 1000khz ref = 550khz open = 300khz v cc = 200khz 11 ref 2v reference output. bypass to gnd with 0.22? (min) capacitor. can source 50? for external loads. loading ref degrades fb accuracy according to the ref load-regulation error. 12 ilim current-limit adjustment. the gnd - lx current-limit threshold defaults to 100mv if ilim is connected to v cc . in adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ilim over a 0.5v to 3v range. the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. connect ilim to ref for a fixed 200mv threshold. 13 pos feedback offset adjust negative input. the output shifts by an amount equal to the difference between pos and neg multiplied by a scale factor that depends on the dac codes (see the integrator amplifiers/output voltage offsets section). connect both pos and neg to ref if the offset function is not used. 14 vgate open-drain power-good output. vgate is normally high when the output is in regulation. if v fb is not within a ?0% window of the dac setting, vgate is asserted low. during dac code transitions, vgate is forced high until 1 clock period after the slew-rate controller finishes the transition. vgate is low during shutdown. 15 gnd analog and power ground. also connects to the current-limit comparator. 16 dl low-side gate-driver output. dl swings gnd to v dd . 17 v dd supply voltage input for the dl gate driver, 4.5v to 5.5v. bypass to gnd with a 1? capacitor. 18 sus suspend-mode control input. when sus is high, the suspend-mode vid code, as programmed by s0 and s1, is delivered to the dac. connect sus to gnd if the suspend-mode multiplexer is not used (see the internal multiplexers (zmode/sus) section). 19 zmode performance-mode mux control input. if sus is low, zmode selects between two different vid dac codes. if zmode is low, the vid dac code is set by the logic-level voltages on d0?4. on the rising edge of zmode, during power-up with zmode high, or on the falling edge of sus when zmode is high, the vid dac code is determined by the impedance at d0?4 (see the internal multiplexers (zmode/sus) section). 20 ovp overvoltage protection control input. connect ovp low to enable overvoltage protection. connect ovp high to disable overvoltage protection. the overvoltage trip threshold is approximately 2v. the state of ovp does not affect output undervoltage fault protection or thermal shutdown. 21?5 d4?0 vid dac code inputs. d0 is the lsb, and d4 is the msb of the internal 5-bit vid dac (table 3). if zmode is low, d0?4 are high-impedance digital inputs, and the vid dac code is set by the logic-level voltages on d0?4. on the rising edge of zmode, during power-up with zmode high, or on the falling edge of sus when zmode is high, the vid dac code is determined by the impedance at d0?4 as follows: logic low = source impedance is 1k + 5%. logic high = source impedance is 100k - 5%. 26 bst boost flying capacitor connection. connect bst to the external boost diode and capacitor as shown in figure 1. an optional resistor in series with bst allows the dh pullup current to be adjusted (figure 8). 27 lx inductor connection. lx is the internal lower supply rail for the dh high-side gate driver. it also connects to the current-limit comparator and the skip-mode zero-crossing comparator. 28 dh high-side gate-driver output. dh swings lx to bst. max1718t notebook cpu step-down controller ______________________________________________________________________________________ 11 v cc v cc 5v input batt 7v to 24v power-good output l1 0.68 h skp/sdn ton 1 10 c7 1 f 2 3 25 24 23 22 26 28 27 16 15 4 5 13 14 20 9 17 output 0.6v to 1.75v d1 cmpsh-3 d2 central semiconductor cmsh5-40 c1 1 f c3 0.1 f c5 0.22 f c6 47pf irf7811a q1 fds7764a q2 r5 100k 2x 2x c2, 25v, x5r 5 x 10 f c4 6 x 270 f, 2v panasonic sp eefue0d271r r1 20 d0 d1 d2 shutdown dl lx v+ dh bst gnd fb neg pos vgate ovp v dd max1718t 6 11 12 5v d3 21 d4 8 s1 7 s0 18 sus 19 mux control suspend input decoder zmode time cc ref ilim r4 62k r3 100k r2 100k r7 4.75k r6 511k r8 0.004 ref r19 27.4k r18 24.9k sumida cep125#4712-to11 figure 1. standard application circuit max1718t notebook cpu step-down controller 12 ______________________________________________________________________________________ detailed description 5v bias supply (v cc and v dd ) the max1718t requires an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebook? 95%-efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an external linear regulator. the 5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f (q g1 + q g2 ) = 10ma to 40ma (typ) where i cc is 800? (typ), f is the switching frequency, and q g1 and q g2 are the mosfet data sheet total gate-charge specification limits at v gs = 5v. v+ and v dd can be tied together if the input power source is a fixed 4.5v to 5.5v supply. if the 5v bias supply is powered up prior to the battery supply, the enable signal (skp/ sdn going from low to high or open) must be delayed until the battery voltage is pre- sent to ensure startup. free-running, constant-on-time pwm controller with input feed forward the quick-pwm control architecture is a pseudofixed- frequency, constant-on-time current-mode type with voltage feed forward (figure 2). this architecture relies on the output filter capacitor? esr to act as the cur- rent-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined sole- ly by a one-shot whose period is inversely proportional to input voltage and directly proportional to output volt- age. another one-shot sets a minimum off-time (400ns typ). the on-time one-shot is triggered if the error com- parator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v+ input, and proportional to the output voltage. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefits of a con- stant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-cur- rent operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple: on-time = k (v out + 0.075v) / v in where k is set by the ton pin-strap connection and 0.075v is an approximation to accommodate the expect- ed drop across the low-side mosfet switch (table 2). the on-time one-shot has good accuracy at the operating points specified in the electrical characteristics table (?0% at 200khz and 300khz, ?2% at 550khz and 1000khz). on-times at operating points far removed from the conditions specified in the electrical characteristics table can vary over a wider range. for example, the 1000khz setting typically runs about 10% slower with inputs much greater than +5v due to the very short on- times required. on-times translate only roughly to switching frequencies. the on-times guaranteed in the electrical character- istics table are influenced by switching delays in the manufacturer phone fax central semiconductor 516-435-1110 516-435-1824 dale- vishay 402-564-3131 402-563-6418 fairchild 408-721-2181 408-721-1635 international rectifier 310-322-3331 310-322-3332 kemet 408-986-0424 408-986-1442 motorola 602-303-5454 602-994-6430 nihon 847-843-7500 847-843-2798 panasonic 714-373-7939 714-373-7183 sanyo 619-661-6835 619-661-1055 sgs-thomson 617-259-0300 617-259-9442 sumida 708-956-0666 708-956-0702 taiyo yuden 408-573-4150 408-573-4159 tdk 847-390-4373 847-390-4428 toko 800-745-8656 408-943-9790 zetex 516-543-7100 516-864-7630 table 1. component suppliers max1718t notebook cpu step-down controller ______________________________________________________________________________________ 13 ref -10% from d/a ref ref fb ovp zmode time 10k error amp toff ton ref +10% neg r-2r d/a converter chip supply g m g m cc pos vgate d0 d1 d2 d3 s1 sus s0 d4 on-time compute ton 1-shot 1-shot trig v batt 2v to 28v trig q q s r 2v ref ref fb gnd 5v output dl v cc v dd lx zero crossing current limit dh bst i lim ref 5v 5v q ovp/uvp detect skp/sdn ton v+ 70k max1718t s r q muxes and slew control 9 1 figure 2. functional diagram max1718t external high-side mosfet. resistive losses, including the inductor, both mosfets, output capacitor esr, and pcb copper losses in the output and ground tend to raise the switching frequency at higher output cur- rents. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in pwm mode (skp/ sdn = open) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor? emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pcb resistances; v drop2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pcb resistances; and t on is the on-time calculated by the max1718t. integrator amplifiers/output voltage offsets two transconductance integrator amplifiers provide a fine adjustment to the output regulation point. one amplifier forces the dc average of the feedback volt- age to equal the vid dac setting. the second amplifier is used to create small positive or negative offsets from the vid dac setting, using the pos and neg pins. the integrator block has the ability to lower the output voltage by 8% and raise it by 8%. for each amplifier, the differential input voltage range is at least ?0mv total, including dc offset and ac ripple. the two amplifiers outputs are directly summed inside the chip, so the inte- gration time constant can be set easily with one capacitor at the cc pin. use a capacitor value of 47pf to 1000pf (47pf typ). the g m of each amplifier is 160? (typ). the pos/neg amplifier is used to add small offsets to the vid dac setting or to correct for voltage drops. to create an output offset, bias pos and neg to a voltage (typically v out or ref) within their common-mode range, and offset them from one another with a resistive divider (figures 3 and 4). if v pos is higher than v neg , then the output is shifted in the positive direction. if v neg is higher than v pos , then the output is shifted in the negative direction. the amount of output offset is less than the difference from pos to neg by a scale factor that varies with the vid dac setting as shown in table 3. the common-mode range of pos and neg is 0.4v to 2.5v. for applications that require multiple offsets, an exter- nal multiplexer can be used to select various resistor values (figure 5). both the integrator amplifiers can be disabled by con- necting neg to v cc . forced-pwm mode (skp/ sdn open) the low-noise forced-pwm mode (skp/ sdn open) dis- ables the zero-crossing comparator, allowing the inductor current to reverse at light loads. this causes the low-side gate-drive waveform to become the com- plement of the high-side gate-drive waveform. the ben- efit of forced-pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be 10ma to 40ma, depend- ing on the external mosfets and switching frequency. forced-pwm mode is required during downward output voltage transitions. the max1718t uses pwm mode during all transitions, but only while the slew-rate con- troller is active. due to voltage positioning, when a tran- sition uses high negative inductor current, the output voltage does not settle to its final intended value until well after the slew-rate controller terminates. consequently it is possible, at very high negative slew currents, for the output to end up high enough to cause vgate to go low. f vv tvv v out drop on in drop drop = + + () () 1 12 - notebook cpu step-down controller 14 ______________________________________________________________________________________ table 2. approximate k-factor errors min recommended v batt at ton setting ton frequency (khz) k-factor (?) approximate k-factor error (%) v out = 1.25v (v) v out = 1.75v (v) v cc 200 5 10 1.7 2.3 open 300 3.3 10 1.8 2.5 ref 550 1.8 12.5 2.6 3.5 gnd 1000 1.0 12.5 3.6 4.9 thus, it is necessary to use forced-pwm mode during all negative transitions. most applications should use pwm mode exclusively, although there is some benefit to using skip mode while in the low-power suspend state (see the using skip mode during suspend (skp/ sdn = v cc ) section.) automatic pulse-skipping switchover in skip mode (skp/ sdn high), an inherent automatic switchover to pfm takes place at light loads (figure 6). this switchover is effected by a comparator that trun- cates the low-side switch on-time at the inductor current? zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between con- tinuous and discontinuous inductor-current operation. the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 6). for a battery range of 7v to 24v, this thresh- old is relatively constant, with only a minor dependence on battery voltage: where k is the on-time scale factor (table 2). for exam- ple, in the standard application circuit this becomes: the crossover point occurs at a lower value if a swing- ing (soft-saturation) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. current-limit circuit the current-limit circuit employs a unique ?alley?current- sensing algorithm that uses the on-resistance of the low-side mosfet as a current-sensing element. if the current-sense signal is above the current-limit thresh- old, the pwm is not allowed to initiate a new cycle (figure 7). the actual peak current is greater than the 33 125 2068 12 1 25 12 27 . . . . . ? = sv h vv v a - i kv l vv v load skip out batt out batt () 2 - max1718t notebook cpu step-down controller ______________________________________________________________________________________ 15 ref max1718t pos neg figure 3. resistive divider from ref dl dh max1718t pos neg figure 4. resistive divider from output dl dh b a max1718t sel mux pos neg max4524 figure 5. programmable offset voltage max1718t current-limit threshold by an amount equal to the induc- tor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a func- tion of the mosfet on-resistance, inductor value, and battery voltage. the reward for this uncertainty is robust, lossless overcurrent sensing. when combined with the undervoltage protection circuit, this current- limit method is effective in almost every circumstance. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with an external resistor-divider at ilim. the current-limit threshold volt- age adjustment range is from 50mv to 300mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ilim. the threshold defaults to 100mv when ilim is connected to v cc . the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. the adjustable current limit accommodates mosfets with a wide range of on-resistance characteristics (see the design procedure section). for a high-accuracy current-limit application, see figure 16. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current- sense signals seen by lx and gnd. place the ic close to the low-side mosfet with short, direct traces, mak- ing a kelvin-sense connection to the source and drain terminals. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving mod- erate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v batt - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate for the adaptive dead-time cir- cuit to work properly. otherwise, the sense circuitry in t0he max1718t interprets the mosfet gate as ?ff?while there is actually still charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the max1718t). the dead time at the other edge (dh turning off) is determined by a fixed 35ns (typ) internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.4 (typ) on-resistance. this helps pre- vent dl from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous- rectifi- er mosfet. however, for high-current applications, you might still encounter some combinations of high- and low-side fets that causes excessive gate-drain cou- pling, which can lead to efficiency-killing, emi- producing shoot-through currents. this is often remedied by adding a resistor in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 8). por power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and preparing the pwm for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switching, forces vgate low, notebook cpu step-down controller 16 ______________________________________________________________________________________ inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out i t = figure 6. pulse-skipping/discontinuous crossover point inductor current i limit i load 0 time i peak figure 7. ?alley?current-limit threshold point and forces the dl gate d river high (to enforce output overvoltage protection). when v cc rises above 4.2v, the dac inputs are sampled and the output voltage begins to slew to the dac setting. for automatic startup, the battery voltage should be present before v cc . if the max1718t attempts to bring the output into regulation without the battery voltage present, the fault latch trips. the skp/ sdn pin can be toggled to reset the fault latch. shutdown when skp/ sdn goes low, the max1718t enters low- power shutdown mode. vgate goes low immediately. the output voltage ramps down to 0v in 25mv steps at the clock rate set by r time . when the dac reaches the 0v setting, dl goes high, dh goes low, the reference is turned off, and the supply current drops to about 2?. when skp/ sdn goes high or floats, the reference pow- ers up, and after the reference uvlo is passed, the dac target is evaluated and switching begins. the slew- rate controller ramps up from 0v in 25mv steps to the currently selected code value (based on zmode and sus). there is no traditional soft-start (variable current limit) circuitry, so full output current is available immedi- ately. vgate goes high after the slew-rate controller has terminated and the output voltage is in regulation. uvlo if v cc drops low enough to trip the uvlo comparator, it is assumed that there is not enough supply voltage to make valid decisions. to protect the output from over- voltage faults, dl is forced high in this mode. this forces the output to gnd, but it does not use the slew- rate controller. this results in large negative inductor current and possibly small negative output voltages. if v cc is likely to drop in this fashion, the output can be clamped with a schottky diode to gnd to reduce the negative excursion. dac inputs d0?4 the dac programs the output voltage. it typically receives a preset digital code from the cpu pins, which are either hardwired to gnd or left open circuit. they can also be driven by digital logic, general-purpose i/o, or an external mux. do not leave d0?4 floating use 1m or less pullups if the inputs may float. d0?4 can be changed while the smps is active, initiating a transition to a new output voltage level. if this mode of dac control is used, connect zmode and sus low. change d0?4 together, avoiding greater than 1? skew between bits. otherwise, incorrect dac readings may cause a partial transition to the wrong voltage level, followed by the intended transition to the correct voltage level, lengthening the overall transition time. the available dac codes and resulting output voltages are listed in table 3. internal multiplexers (zmode, sus) the max1718t has two unique internal vid input multi- plexers (muxes) that can select one of three different vid dac code settings for different processor states. depending on the logic level at sus, the suspend (sus) mode mux selects the vid dac code settings from either the zmode mux or the s0/s1 input decoder. the zmode mux selects one of the two vid dac code settings from the d0?4 pins, based on either voltage on the pins or the output of the imped- ance decoder (figure 9). when sus is high, the suspend mode mux selects the vid dac code settings from the s0/s1 input decoder. the outputs of the decoder are determined by inputs s0 and s1 (table 4). when sus is low, the suspend mode mux selects the output of the zmode mux. depending on the logic level at zmode, the zmode mux selects the vid dac code settings using either the voltage on d0?4 or the output of the impedance decoder (table 5). if zmode is low, the logic-level voltages on d0?4 set the vid dac settings. this is called logic mode. in this mode, the inputs are continuously active and can be dynamically changed by external logic. the logic mode vid dac code setting is typically used for the battery mode state, and the source of this code is sometimes the vid pins of the cpu with suitable pullup resistors. on the rising edge of zmode, during power-up with zmode high or on the falling edge of sus when zmode is high, the impedances at d0?4 are sampled by the impedance decoder to see if a large resistance max1718t notebook cpu step-down controller ______________________________________________________________________________________ 17 bst +5v v batt 5 typ dh lx max1718t figure 8. reducing the switching-node rise time max1718t notebook cpu step-down controller 18 ______________________________________________________________________________________ table 3. output voltage vs. dac codes d4 d3 d2 d1 d0 output voltage (v) pos/neg scale factor 0 0 0 0 0 1.75 0.90 0 0 0 0 1 1.70 0.90 0 0 0 1 0 1.65 0.90 0 0 0 1 1 1.60 0.89 0 0 1 0 0 1.55 0.89 0 0 1 0 1 1.50 0.89 0 0 1 1 0 1.45 0.88 0 0 1 1 1 1.40 0.88 0 1 0 0 0 1.35 0.88 0 1 0 0 1 1.30 0.87 0 1 0 1 0 1.25 0.87 0 1 0 1 1 1.20 0.86 0 1 1 0 0 1.15 0.86 0 1 1 0 1 1.10 0.85 0 1 1 1 0 1.05 0.85 0 1 1 1 1 1.00 0.84 1 0 0 0 0 0.975 0.84 1 0 0 0 1 0.950 0.83 1 0 0 1 0 0.925 0.83 1 0 0 1 1 0.900 0.82 1 0 1 0 0 0.875 0.82 1 0 1 0 1 0.850 0.82 1 0 1 1 0 0.825 0.81 1 0 1 1 1 0.800 0.81 1 1 0 0 0 0.775 0.80 1 1 0 0 1 0.750 0.80 1 1 0 1 0 0.725 0.79 1 1 0 1 1 0.700 0.78 1 1 1 0 0 0.675 0.78 1 1 1 0 1 0.650 0.77 1 1 1 1 0 0.625 0.76 1 1 1 1 1 0.600 0.76 is in series with the pin. this is called impedance mode. if the voltage level on the pin is a logic low, an internal switch connects the pin to an internal 26k pullup for about 4? to see if the pin voltage can be forced high (figure 10). if the pin voltage can be pulled to a logic high, the impedance is considered high and so is the impedance mode logic state. similarly, if the voltage level on the pin is a logic high, an internal switch connects the pin to an internal 8k pulldown to see if the pin voltage can be forced low. if so, the pin is high impedance and its impedance mode logic state is high. in either sampling condition, if the pin? logic level does not change, the pin is determined to be low impedance and the impedance mode logic state is low. a high pin impedance (and logic high) is 100k or greater, and a low impedance (and logic low) is 1k or less. the electrical characteristics table guaranteed levels for these impedances are 95k and 1.05k to allow the use of standard 100k and 1k resistors with 5% tolerance. using the zmode mux there are many ways to use the versatile zmode mux. the preferred method depends on when and how the vid dac codes for the various states are determined. if the output voltage codes are fixed at pcb design time, program both codes with a simple combination of pin- strap connections and series resistors (figure 11). if the output voltage codes are chosen during pcb assembly, both codes can be independently pro- grammed with resistors (figure 12). this matrix of 10 resistor-footprints can be programmed to all possible logic mode and impedance mode code combinations with only five resistors. often the cpu pins provide one set of codes that are typically used with pullup resistors to provide the logic mode vid code, and resistors in series with d0?4 set the impedance mode code. since some of the cpu? vid pins may float, the open-circuit pins can present a problem for the zmode mux? impedance mode. for the impedance mode to work, any pins intended to be low during impedance mode must appear to be low impedance, at least for the 4? sampling interval. this can be achieved in several ways, including the fol- lowing two (figure 13). by using low-impedance pullup max1718t notebook cpu step-down controller ______________________________________________________________________________________ 19 s1 s0 output voltage (v) gnd gnd 0.975 gnd ref 0.950 gnd open 0.925 gnd v cc 0.900 ref gnd 0.875 ref ref 0.850 ref open 0.825 ref v cc 0.800 open gnd 0.775 open ref 0.750 open open 0.725 open v cc 0.700 v cc gnd 0.675 v cc ref 0.650 v cc open 0.625 v cc v cc 0.600 table 4. suspend mode dac codes d0 d1 d2 d3 d4 zmode v cc por zmode mux s0/s1 decoder sel out out 1 in impedance decoder in 0 sus mux sel out dac 1 0 s0 s1 sus figure 9. internal multiplexers functional diagram max1718t resistors with the cpu? vid pins, each pin provides the low impedance needed for the mux to correctly inter- pret the impedance mode setting. unfortunately, the low resistances cause several ma quiescent currents for each of the cpu? grounded vid pins. this quies- cent current can be avoided by taking advantage of the fact that d0?4 need only appear low impedance briefly, not necessarily on a continuous dc basis. high- impedance pullups can be used if they are bypassed with a large enough capacitance to make them appear low impedance for the 4? sampling interval. as noted in figure 13, 4.7nf capacitors allow the inputs to appear low impedance even though they are pulled up with large-value resistors. each sampling depletes some charge from the 4.7nf capacitors. a minimum interval of 2 r pullup 4.7nf is recommended between zmode samples. in some cases, it is desirable to determine the impedance mode code during system boot so that sev- notebook cpu step-down controller 20 ______________________________________________________________________________________ 26k d4 d3 d2 d1 d0 26k 26k 26k 26k 8k 100k 8k 8k 8k 8k 3.0v to 5.5v 100k +5v b-data latch v cc gnd max1718t figure 10. internal mux impedance-mode data test and latch max1718t d4 d3 d2 d1 d0 zmode 3.0v to 5.5v zmode high vid = 01010 1.25v zmode low vid = 01100 1.15v 100k 100k zmode = high = 1.25v zmode = low = 1.15v figure 11. using the internal mux with hardwired logic-mode and impedance-mode dac codes eral processor types can be used without hardware modifications. figure 14 shows one way to implement this function. the desired code is determined by the system bios and programmed into one register of the max1609 using the smbus serial interface. the max1609? other register is left in its power-up state (all outputs high impedance). when smbsus is low, the outputs are high impedance and do not affect the logic- mode vid code setting. when smbsus is high, the pro- grammed register is selected, and the max1609 forces a low impedance on the appropriate vid input pins. the zmode signal is delayed relative to the smbsus pin because the vid pins that are pulled low by the max1609 take significant time to rise when they are released. one additional benefit of using the max1609 for this application is that the application uses only five of the max1609? high-voltage, open-drain outputs. the other three outputs can be used for other purposes. output voltage transition timing the max1718t is designed to perform output voltage transitions in a controlled manner, automatically mini- mizing input surge currents. this feature allows the cir- cuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output volt- age level with the lowest possible peak currents for a given output capacitance. this makes the ic ideal for mobile cpus. mobile cpus operate at multiple clock frequencies, which often require distinct vid settings. when transi- tioning from one clock frequency to the other, the cpu first goes into a low-power state, then the output volt- age and clock frequency are changed. the change must be accomplished in a specified transition time or the system can halt. at the beginning of an output voltage transition, the max1718t blanks the vgate output, preventing it from going low. vgate remains blanked during the transition and is reenabled when the slew-rate controller has set the internal dac to the final value and one additional max1718t notebook cpu step-down controller ______________________________________________________________________________________ 21 max1718t d4 d3 d2 d1 d0 zmode zmode = high = 1.25v zmode = low = 1.15v 1k 1k 100k 1k 100k 2.7v to 5.5v note: use pullup for logic mode 1, pull-down for logic mode 0. use 100k for impedance mode 1, 1k for impedance mode 0. figure 12. using the internal mux with both vid codes resistor programmed zmode sus output voltage determined by gnd gnd logic level of d0?4 v cc gnd impedance of d0?4 xv cc logic levels of s0, s1 table 5. dac mux operation smbus is a trademark of intel corp. max1718t slew-rate clock period has passed. the slew-rate clock frequency (set by resistor r time ) must be set fast enough to ensure that the longest required transition is completed within the allowed interval. the output voltage transition is performed in 25mv steps, preceded by a 4? delay and followed by one additional clock period. the total time for a transition depends on r time , the voltage difference, and the accuracy of the max1718t? slew-rate clock, and is not dependent on the total output capacitance. the greater the output capacitance, the higher the surge current required for the transition. the max1718t automatically controls the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ilim. the transition time is given by: where f slew = 150khz 120k / r time , v old is the original dac setting, and v new is the new dac setting. see time frequency accuracy in the electrical characteristics table for f slew accuracy. the practical range of r time is 47k to 470k , corre- sponding to 2.6? to 26? per 25mv step. although the dac takes discrete 25mv steps, the output filter makes the transitions relatively smooth. the average inductor current required to make an output voltage transition is: i l ? c out 25mv f slew output overvoltage protection the overvoltage protection (ovp) circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the output voltage is continuously monitored for over- voltage. if the output is more than 2v, ovp is triggered and the circuit shuts down. the dl low-side gate-driver output is then latched high until skp/ sdn is toggled or v cc power is cycled below 1v. this action turns on the synchronous-rectifier mosfet with 100% duty and, in turn, rapidly discharges the output filter capacitor and ?+ ? ? ? ? ? ? ? ? ? ? ? ? 4 1 25 s f vv mv slew old new - notebook cpu step-down controller 22 ______________________________________________________________________________________ max1718t d4 d3 d2 d1 d0 zmode *to reduce quiescent current, 1k pullup resistors can be replaced by 1m resistors with 4.7nf capacitors in parallel. zmode high vid = 01010 1.25v cpu vid = 01100 1.15v (zmode low) 1k 1m 1k 1k 1k 1k 4.7nf *optional 3.15v to 5.5v 100k 100k cpu zmode = high = 1.25v zmode = low = 1.15v figure 13. using the internal mux with cpu driving the logic-mode vid code forces the output to ground. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse blows. dl is also kept high continuously when v cc uvlo is active, as well as in shutdown mode (table 6). overvoltage protection can be defeated with a logic high on ovp or through the no fault test mode (see the no fault test mode section). output undervoltage shutdown the output uvp function is similar to foldback current limiting, but employs a timer rather than a variable cur- rent limit. if the max1718t output voltage is under 70% of the nominal value, the pwm is latched off and does not restart until v cc power is cycled or skp/ sdn is tog- gled. to allow startup, uvp is ignored during the under- voltage fault-blanking time (the first 256 cycles of the slew rate after startup). uvp can be defeated through the no fault test mode (see the no fault test mode section). no fault test mode the over/undervoltage protection features can compli- cate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a test mode is provided to disable the ovp, uvp, and thermal shut- down features, and clear the fault latch if it has been max1718t notebook cpu step-down controller ______________________________________________________________________________________ 23 3.3v r = 100k rrrr vid4 vid3 vid2 vid1 vid0 1nf gmuxsel smbsus address smbus data clock add0 add1 0 1 0 1 0 1 1 1 1 1 3.3k zmode cpu max1718t 3.3v max1609 r r r r r figure 14. using the zmode multiplexer max1718t set. the pwm operates as if skp/ sdn were high (skip mode). the no fault test mode is entered by forcing 12v to 15v on skp/ sdn . design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: 1) input voltage range. the maximum value (v in(max) ) must accommodate the worst-case high-ac adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to con- nectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. 2) maximum load current. there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus dri- ves the selection of input capacitors, mosfets, and other critical heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) 80%. 3) switching frequency. this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v in 2 . the optimum frequen- cy is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. 4) inductor operating point. this choice provides trade- offs between size and efficiency. low inductor val- ues cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the cir cuit to operate at the edge of criti- cal conduction (where the inductor current just touch- es zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the max1718t? pulse-skipping algorithm initiates skip mode at the critical conduction point. so, the inductor operating point also determines the load- current value at which pfm/pwm switchover occurs. the optimum point is usually found between 20% and 50% ripple current. 5) the inductor ripple current also impacts transient- response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: notebook cpu step-down controller 24 ______________________________________________________________________________________ skp/ sdn dl mode comment gnd high shutdown low-power shutdown state. dl is forced to v dd , enforcing ovp. i cc + i dd = 2? (typ). 12v to 15v switching no fault test mode with faults disabled and fault latches cleared, includ- ing thermal shutdown. otherwise, normal operation, with auto- matic pwm/pfm switchover for pulse skipping at light loads. open switching run (pwm, low noise) low-noise operation with no automatic switchover. fixed-fre- quency pwm action is forced regardless of load. inductor cur- rent reverses at light-load levels. v cc switching run (pfm/pwm) operation with automatic pwm/pfm switchover for pulse skip- ping at light loads. v cc or open high fault fault latch has been set by ovp, uvp, or thermal shutdown. device remains in fault mode until v cc power is cycled or skp/ sdn is forced low. table 6. operating mode truth table where t off(min) is the minimum off-time (see the electrical characteristics tables) and k is from table 2. inductor selection the switching frequency and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 19a, v in = 7v, v out = 1.25v, f sw = 300khz, 30% ripple current or lir = 0.30: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): i peak = i load(max) + (lir / 2) i load(max) setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the valley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: i limit(low) > i load(max) - (lir / 2) i load(max) where i limit(low) equals the minimum current-limit threshold voltage divided by the r ds(on) of q2. for the max1718t figure 1 circuit, the minimum current-limit threshold with v ilim = 105mv is about 95mv. use the worst-case maximum value for r ds(on) from the mos- fet q2 data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each ? of temper- ature rise. examining the figure 1 example with a q2 maximum r ds(on) = 3.8m at t j = +25? and 5.7m at t j = +125? reveals the following: i limit(low) = 95mv / 5.7m = 16.7a and the required valley current limit is: i limit(low) > 19a - (0.30 / 2) 19a = 16.2a since 16.7a is greater than the required 16.2a, the cir- cuit can deliver the full-rated 19a. when delivering 19a of output current, the worst-case power dissipation of q2 is 1.95w. with a thermal resis- tance of +60?/w and each mosfet dissipating 0.98w, the temperature rise of the mosfets is +60?/w 0.98w = +58?, and the maximum ambient temperature is +125? - +58? = +67?. to operate at a higher ambient temperature, choose lower r ds(on) mosfets or reduce the thermal resistance. raising the current-limit threshold allows for operation with a higher mosfet junction temperature. connect ilim to v cc for a default 100mv current-limit threshold. for an adjustable threshold, connect a resistor- divider from ref to gnd, with ilim connected to the cen- ter tap. the external adjustment range of 0.5v to 3.0v corresponds to a current-limit threshold of 50mv to 300mv. when adjusting the current limit, use 1% toler- ance resistors and a 10? divider current to prevent a significant increase of errors in the current-limit tolerance. output capacitor selection the output filter capacitor must have low enough effective series resistance (esr) to meet output ripple and load- transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the ovp circuit. in cpu v core converters and other applications where the output is subject to violent load transients, the output capacitor? size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: r esr v step / i load(max) the actual microfarad capacitance value required often relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tantalums, os-cons, and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent v sag v li cv soar peak out 2 2 l vv v v lir i out in out in sw load max f = ? () () v ii lk v v t cvk vv v t sag load load out in off min out out in out in off min = ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () () 12 2 2 max1718t notebook cpu step-down controller ______________________________________________________________________________________ 25 max1718t and v soar from causing problems during load tran- sients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag equation in the design procedure section). the amount of overshoot due to stored inductor energy can be cal- culated as: where i peak is the peak inductor current. output capacitor stability considerations stability is determined by the value of the esr zero rela- tive to the switching frequency. the voltage-positioned circuit in this data sheet has the esr zero frequency low- ered due to the external resistor in series with the output capacitor esr, guaranteeing stability. for a voltage-posi- tioned circuit, the minimum esr requirement of the out- put capacitor is reduced by the voltage-positioning resistor value. the boundary condition of instability is given by the fol- lowing equation: (r esr + r droop ) c out 1 / (2 f sw ) where r droop is the effective value of the voltage-posi- tioning resistor (figure 1, r8). for good phase margin, increase the equivalent rc time constant by a factor of two. the standard application circuit (figure 1) operat- ing at 300khz with c out = 1320?, r esr = 2.5m , and r droop = 5m easily meets this requirement. in some applications, the c out and r droop values are suffi- cient to guarantee stability even if r esr = 0. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation: for most applications, nontantalum chemistries (ceramic or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a switch or a connector in series with the battery. if the max1718t is operated as the second stage of a two- stage power-conversion system, tantalum input capaci- tors are acceptable. in either configuration, choose an input capacitor that exhibits less than +10? tempera- ture rise at the rms input current for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>12a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. the high-side mosfet must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of q1. conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of q1. if v in does not vary over a wide range, the minimum power dissipation occurs where the resis- tive losses equal the switching losses. choose a low-side mosfet (q2) that has the lowest possible r ds(on) , comes in a moderate-sized package (i.e., two or more 8-pin sos, dpaks, or d 2 paks), and is reason ably priced. ensure that the max1718t dl gate driver can drive q2; in other words, check that the dv/dt caused by q1 turning on does not pull up the q2 gate due to drain-to-gate capacitance, causing cross- conduction problems. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the buck topology. mosfet power dissipation the high-side mosfet power dissipation due to resis- tance is: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mosfet can be. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages pd q sistive v v ir out in load ds on (re ) () 1 2 = ii vvv v rms load out in out in = () - v li cv soar peak out 2 2 notebook cpu step-down controller 26 ______________________________________________________________________________________ becomes extraordinarily hot when subjected to v in(max) , reconsider your choice of mosfet. calculating the power dissipation in q1 due to switch- ing losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source induc- tance, and pcb layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation and temperature measurements: where c rss is the reverse transfer capacitance of q1 and i gate is the peak gate-drive source/sink current (2a typ). for the low-side mosfet (q2), the worst-case power dissipation always occurs at maximum battery voltage: for both q1 and q2, note the mosfet? maximum junction temperature and the thermal resistance that is realistically achieved with the device packaging and your thermal environment to avoid overheating. the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, you can ?verdesign?the circuit to tolerate: i load = i limit(high) + (lir / 2) i load(max) where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. this means that the mosfets must be very well heatsinked. if short-cir- cuit protection without overload protection is enough, a normal i load value can be used for calculating compo- nent stresses. choose a schottky diode (d1) having a forward voltage low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional and can be removed if efficiency is not critical. applications information voltage positioning powering new mobile processors requires new tech- niques to reduce cost, size, and power dissipation. voltage positioning reduces the total number of output capacitors to meet a given transient response require- ment. setting the no-load output voltage slightly higher allows a larger step down when the output current sud- denly increases, and regulating at the lower output voltage under load allows a larger step up when the out- put current suddenly decreases. allowing a larger step size means that the output capacitance can be reduced and the capacitor? esr can be increased. adding a series output resistor positions the full-load out- put voltage below the actual dac programmed voltage. connect fb directly to the inductor side of the voltage- positioning resistor (r8, 4m ). the other side of the voltage-positioning resistor should be connected directly to the output filter capacitor with a short, wide pcb trace. with a 20a full-load current, r8 causes an 80mv drop. this 80mv is a -6.4% droop. an additional benefit of voltage positioning is reduced power consumption at high load currents. because the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r8. for a nominal 1.25v, 20a output, reducing the output voltage 6.4% gives an output voltage of 1.17v and an output current of 18.7a. given these values, cpu power consumption is reduced from 25w to 21.9w. the addi- tional power consumption of r8 is: 4m 18.7a 2 = 1.4w and the overall power savings is as follows: 25 - (21.9 + 1.4) = 1.7w in effect, 3w of cpu dissipation is saved, and the power supply dissipates some of the power savings, but both the net savings and the transfer of dissipation away from the hot cpu are beneficial. reduced-power-dissipation voltage positioning a key benefit of voltage positioning is reduced power dissipation, especially at heavy loads. in the standard application circuit (figure 1), voltage positioning is accomplished using a droop resistor (r8), which can dissipate over 1w. although the power savings in the processor is much greater than the dissipation in the resistor, 1w of dissipation is still far from ideal. pd q v v ir out in max load ds on () () () 21 2 =? ? ? ? ? ? ? pd q switching cv fi i rss in max sw load gate () () 1 2 = max1718t notebook cpu step-down controller ______________________________________________________________________________________ 27 max1718t the resistor is a necessary component because accu- rate voltage positioning depends on an accurate cur- rent-sense element. but it is not necessary to drop the entire positioning voltage across this resistor. the cir- cuit of figure 15 uses an external op amp to add gain to r8? voltage signal, allowing the resistor value and power dissipation to be divided by the gain factor. the recommended range for the gain is up to about 4, with preferred practical values around 1.5?. there are several difficulties with high gains. if high gain is used, the sense-resistor value is very small (<1m ). the sense signal is also small, potentially causing noise and stability problems. also, output voltage and posi- tioning accuracy are essential. a smaller sense signal reduces accuracy, as does any op-amp input voltage offset, which is increased by the gain factor. the op-amp output directly drives fb. to ensure stabili- ty, the output voltage ripple and the ripple signal across r8 must be delivered with good fidelity. to pre- serve higher harmonics in the ripple signal, the circuit bandwidth should be approximately 10 times the switching frequency. besides lowering power dissipation, the gain stage pro- vides another benefit; it eases the task of providing the required positioning slope, using available discrete val- ues for r8. a lower value resistor can be used and the gain adjusted to deliver the desired slope. sometimes the desired slope is not well known before the final pcb is evaluated. a good practice is to adjust the final gain to deliver the correct voltage slope at the processor pins, adjusting for the actual copper losses in the sup- ply and ground paths. this does not remove the requirement to minimize copper losses because they vary with temperature and pcb production lot. it does, however, provide an easy, practical way to account for their typical expected voltage drops. replacing the droop resistor with a lower value resistor and a gain stage does not affect the max1718t stabili- ty criteria. the ic cannot distinguish one from the other, as long as the required signal integrity is maintained. r8? effective value can be used to guarantee stability with extremely low-esr (ceramic) output capacitors (see the output capacitor stability considerations sec- tion). the effective value is the resistor value that would result in the same signal delivered to the max1718t? fb pin, or r8 times the op-amp circuit? gain. although the op amp should be placed near r8 to mini- mize input noise pickup, power it from the max1718t? quiet v cc supply and analog ground to prevent other noise problems. high-accuracy current limit the max1718t? integrated current limit uses the syn- chronous rectifier? r ds(on) for its current-sense ele- ment. this dependence on a poorly specified resistance with high temperature variation means that the integrated current limit is useful mainly in high-over- load and short-circuit conditions. a moderate overload may be tolerated indefinitely. this arrangement is toler- able because there are other ways to detect overload conditions and take appropriate action. for example, if the cpu draws excessive current (but not enough to activate the current limit) the cpu heats up, and even- tually the system takes notice and shuts down. while this approach is usually acceptable, it is far from optimal. an inaccurate current limit causes component specification difficulties. what values should be used for inductor saturation ratings, mosfet peak current requirements, and power dissipation requirements? an accurate current limit makes these issues more man- ageable. the circuit of figure 16 uses an external op amp, together with the voltage-positioning resistor (r8) to implement an accurate inductor current limit. a voltage-divider from the positive side of r8 creates a threshold several mvs below the output. when the volt- age drop across r8 exceeds the threshold, current lim- iting occurs. the op amp causes current limiting by lowering the voltage on the ilim pin. this lowers the current-limit threshold of the ic? internal current-limit circuit, which uses the mosfet r ds(on) as usual. the op-amp output swing has the ability to adjust the ic? internal valley current limit from a value much higher than ever needed (given the mosfet? r rd(on) ) to a notebook cpu step-down controller 28 ______________________________________________________________________________________ dl dh 510 r5 1k r6 1k a = 2 max1718t r8 v cc v out 1.25v, 19a fb max4322 figure 15. lowering voltage-positioning power dissipation value much lower than required to support a normal load. the bandwidth of the ilim pin is not high, so the speed of the op amp is not critical. any op amp or comparator could be acceptable, as long as its input offset does not degrade current-limit accuracy excessively, has input common-mode range to ground, and has rail-to- rail output swing. because the bandwidth is low, the circuit responds to the average inductor current rather than the peak or valley current, eliminating the current limit? dependence on inductor ripple current. similar to a foldback current limit, this circuit must be carefully designed to guarantee startup. the op amp must be incapable of setting the current limit to zero or else the power supply may be unable to start. the three-way divider from ref to ground to the op-amp output allows the op amp to vary the max1718t? inter- nal current-limit threshold from 21mv (severely limiting current) to 182mv (more than guaranteeing the maxi- mum required output current). these divider resistors should be chosen with the required current and the synchronous rectifier? r rd(on) in mind to ensure that the op-amp adjustment range is high enough to guar- antee the required output current. the voltage at the ilim pin is given by: where v comp is the voltage at the output of the com- parator. the minimum v ilim is calculated when v comp is at the v ol of the comparator. the maximum v ilim is calculated when v comp = v oh at the minimum v cc . the valley current-limit threshold is set at 10% of the voltage v ilim . c13 should be picked to give approxi- mately 10? time constant at the ilim input. the actual threshold at which the op amp begins to limit current is determined by r8 and the r10/r11 divider values and is very easy to set. ideally, i out(max) r8 = v fb r10 / (r10 + r11). in practice, some margin must be added for resistor accuracy, op- amp input offset, and general safety. with the op amp shown and ?% resistors, 10% margin is adequate. an additional benefit of this circuit is that the current- limit value is proportional to the output voltage setting (v fb ). when the output voltage setting is lowered, the current limit automatically adjusts to a more appropriate level, providing additional protection without compro- mising performance since the reduction of the required load current is greater than that of the output voltage setting. in some cases, the current required to slew the output capacitor may be large enough to require the current limit to be increased beyond what is necessary to support the load. this circuit is completely compatible with the circuit of figure 15. if the two circuits are used together, the max4326 dual op amp in a ?ax package can replace the two single devices, saving space and cost. if both are used, the reduced r8 value makes the op-amp input offset more significant. additional margin might be needed, depending on the magnitude of r8? reduction. although the op amp should be placed near r8 to mini- mize input noise pickup, power it from the max1718t? quiet v cc supply and analog ground to prevent other noise problems. using skip mode during suspend (skp/ sdn = v cc ) typically, for the max1718t? intended application, the minimum output currents are too high to benefit from pulse-skipping operation in all active cpu modes. furthermore, skip mode can be a hindrance to properly executing downward output voltage transitions (see the forced-pwm mode section). however, processor sus- pend currents can be low enough that skip mode oper- ation provides a real benefit. in the circuit of figure 17, skp/ sdn remains biased at 2v in every state except suspend and shutdown. in addition, upon entering suspend (sus going high), the pin remains at 2v for about 200? before it eventually v rrv rrv rr rr rr ilim ref comp = + [] ++ [] ()( ) ()()() 12 13 13 14 12 14 12 13 13 14 max1718t notebook cpu step-down controller ______________________________________________________________________________________ 29 dl dh r10 1.5k 1nf max1718t r8 4m v cc v out 1.25v, 19a ilim ref fb max4322 r14 100k r13 20k r11 20k r12 30k figure 16. improving current-limit accuracy rail-to-rail is a registered trademark of nippon motorola, ltd. max1718t goes high. this causes the max1718t to remain in pwm mode long enough to correctly complete the neg- ative output voltage transition to the suspend state volt- age. when skp/ sdn goes high, the max1718t enters its low-quiescent-current skip mode. dropout performance the output voltage adjust range for continuous-conduc- tion operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot (375ns max at 1000khz). for best dropout performance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k-factor. this error is greater at higher frequencies (table 2). also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the vsag equa- tion in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down is an indicator of ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but this may be adjusted up or down to allow tradeoffs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths, respectively (see the on-time one-shot (ton) section), t off(min) is from the electrical characteristics tables, and k is taken from table 2. the absolute minimum input voltage is cal- culated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipat- ed, calculate v sag to be sure of adequate transient response. dropout design example: v out = 1.6v fsw = 550khz k = 1.8?, worst-case k = 1.58? t off(min) = 500ns v drop1 = v drop2 = 100mv h = 1.5 v in(min) = (1.6v + 0.1v) / (1-0.5? 1.5/1.58?) + 0.1v - 0.1v = 3.2v calculating again with h = 1 gives the absolute limit of dropout: v in(min) = (1.6v + 0.1v) / (1-1.0 0.5?/1.58?) - 0.1v + 0.1v = 2.5v therefore, v in must be greater than 2.5v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.2v. adjusting v out with a resistor-divider the output voltage can be adjusted with a resistor- divider rather than the dac if desired (figure 18). the drawback is that the on-time does not automatically receive correct compensation for changing output voltage levels. this can result in variable switching frequency as the resistor ratio is changed, and/or excessive switching frequency. the equation for adjusting the output voltage is: where v fb is the currently selected dac value. in resistor-adjusted circuits, the dac code should be set as close as possible to the actual output voltage in order to minimize the shift in switching frequency. one-stage (battery input) vs. two-stage (5v input) applications the max1718t can be used with a direct battery con- nection (one stage) or can obtain power from a regulat- ed 5v supply (two stage). each approach has advantages, and careful consideration should go into the selection of the final design. the one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5v supply. the transient response of the single stage is better due to the ability to ramp up the inductor current faster. the total efficiency of a sin- gle stage is better than the two-stage approach. vv r r out fb =+ ? ? ? ? ? ? 1 1 2 v vv t xh k vv in min out drop off min drop drop () () = + () ? ? ? ? ? ? + 1 21 1- - notebook cpu step-down controller 30 ______________________________________________________________________________________ the two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipa- tion. the power supply can be placed closer to the cpu for better regulation and lower i 2 r losses from pcb traces. although the two-stage design has worse transient response than the single stage, this can be offset by the use of a voltage-positioned converter. ceramic output capacitor applications ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. they are also expensive and brittle, and their ultra-low esr char- acteristic can result in excessively high esr zero fre- quencies (affecting stability in nonvoltage-positioned circuits). in addition, their relatively low capacitance value can cause output overshoot when going abruptly from full-load to no-load conditions, unless the inductor value can be made small (high-switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. in some cases, there may be no room for electrolytics, necessitating a ceramic-only dc-to-dc design. the max1718t can take full advantage of the small size and low esr of ceramic output capacitors in a voltage- positioned circuit. adding the positioning resis- tor increases the ripple at fb, lowering the effective esr zero frequency of the ceramic output capacitor. output overshoot (v soar ) determines the minimum out- put capacitance requirement (see the output capacitor selection section). often the switching frequency is increased to 550khz or 1000khz, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. the efficiency penalty for operating at 550khz is about 2% to 3% and about 5% at 1000khz when compared to the 300khz voltage-positioned circuit, primarily due to the high-side mosfet switching losses. pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 19). if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for good pcb layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 2) all analog grounding is done to a separate solid cop- per plane, which connects to the max1718t at the gnd pin. this includes the v cc , ref, and cc capacitors, the time resistor, as well as any other resistor-dividers. 3) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mil- liohm of excess trace resistance causes a measur- able efficiency penalty. max1718t notebook cpu step-down controller ______________________________________________________________________________________ 31 30k 3.3v 5v shutdown to skp/sdn sus skp/sdn ~ 200 s ~ 200 s 0v 2.0v to sus v cc 0.01 f v cc 120k 80k figure 17. using skip mode during suspend (skp/ sdn = v cc ) dl dh fb v batt v out r1 r2 max1718t v out = v fb ? ( 1 + ) r1 r2 figure 18. adjusting v out with a resistor-divider max1718t 4) lx and gnd connections to q2 for current limiting must be made using kelvin-sense connections to guarantee the current-limit accuracy. with 8-pin so mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while connecting gnd and lx inside (underneath) the 8-pin so package. 5) when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet or between the inductor and the output filter capacitor. 6) ensure the fb connection to the output is short and direct. in voltage-positioned circuits, the fb connection is at the junction of the inductor and the positioning resistor. 7) route high-speed switching nodes away from sensitive analog areas (cc, ref, ilim). make all pin-strap control input connections (skp/ sdn , ilim, etc.) to ana- log ground or v cc rather than power ground or v dd . layout procedure 1) place the power components first, with ground termi- nals adjacent (q2 source, cin-, cout-, d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to mosfet q2, preferably on the back side opposite q2 in order to keep lx-gnd current-sense lines and the dl drive line short and wide. the dl gate trace must be short and wide, measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-to-dc controller ground connections as shown in figure 19. this diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the gnd plane, where the gnd pin and v dd bypass capacitors go; and an analog ground plane where sensitive analog components go. the analog ground plane and gnd plane must meet only at a single point directly beneath the ic. these two planes are then connected to the high-power output ground with a short connection from gnd to the source of the low- side mosfet q2 (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (vcore and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. place the entire dc-to-dc converter circuit as close to the cpu as is practical. notebook cpu step-down controller 32 ______________________________________________________________________________________ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dh lx bst d0 d1 d2 gnd d3 d4 ovp zmode sus v dd dl vgate pos ilim ref ton v cc s1 s0 cc neg fb time skp/sdn v+ qsop top view max1718t pin configuration max1718t notebook cpu step-down controller ______________________________________________________________________________________ 33 chip information transistor count: 7190 d1 q2 v batt gnd in cout via to fb and fbs via to lx via to source of q2 via to gnd near q2 source inductor discharge path has low-dc resistance gnd out v out l1 q1 cc v cc v dd ref all analog grounds connect to local plane only note: ?tar?ground is used. d1 is directly across q2. connect local analog ground plane directly to gnd from the side opposite the v dd capacitor gnd to avoid v dd ground currents from flowing in the analog ground plane. max1718t cin r6 gnd figure 19. power-stage pcb layout example package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 28 qsop e28-1 21-0055 note: the max1718t does not have a heat slug. max1718t notebook cpu step-down controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 34 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 11/02 initial release 1 10/08 removal of patent pending on page 1 1 |
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