? semiconductor components industries, llc, 2006 may, 2006 ? rev. 5 1 publication order number: NLSF1174/d NLSF1174 hex d flip?flop with common clock and reset this device consists of six d flip?flops with common clock and reset inputs. each flip?flop is loaded with a low?to?high transition of the clock input. reset is asynchronous and active low. all inputs/outputs are standard cmos compatible. features ? output drive compatibility: 10 lsttl loads ? outputs directly interface to cmos ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? msl level 1 ? chip complexity: 162 fet ? pb?free package is available* 1 2 3 4 q5 v cc 16 15 14 13 56 7 8 9 10 11 12 d3 d5 d4 q2 q0 d0 reset q3 clock gnd q4 d2 q1 d1 figure 1. pin assignment (top view) center pad on bottom may be connected to v cc of device. this pad must be isolated or connected to v cc . *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com inputs output reset clock d q function table l h h h h l xx no change no change h l x x l h l device package shipping ? ordering information NLSF1174mnr2 qfn?16 3000 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. NLSF1174mnr2g qfn?16 (pb?free) 3000 / tape & ree l NLSF1174 = device code a = assembly location l = wafer lot y = year w = work week = pb?free package (note: microdot may be in either location) marking diagram qfn?16 mn suffix case 485g 16 nlsf 1174 alyw 1 ??? ???
NLSF1174 http://onsemi.com 2 figure 2. logic diagram d0 d1 d2 d3 d4 d5 q0 q1 q2 q3 q4 q5 clock reset data inputs noninverting outputs design/value table design criteria value unit internal gate count* 40.5 ea internal gate propagation delay 1.5 ns internal gate power dissipation 5.0 w speed power product .0075 pj *equivalent to a two?input nand gate. maximum ratings parameter symbol value unit dc supply voltage (referenced to gnd) v cc 0.5 to 7.0 v dc input voltage (referenced to gnd) v in 1.5 to v cc 1.5 v dc output voltage (referenced to gnd) (note 1) v out 0.5 to v cc 0.5 v dc input current, per pin i in 20 ma dc output current, per pin i out 25 ma dc supply current, v cc and gnd pins i cc 50 ma storage temperature range t stg 65 to 150 c lead temperature, 1 mm from case for 10 seconds pdip, soic, tssop t l 260 c junction temperature under bias t j 150 c thermal resistance qfn ja 80 c/w power dissipation in still air at 85 c qfn p d 800 mw moisture sensitivity msl level 1 flammability rating oxygen index: 30 to 35 f r ul 94 v?0 @ 0.125 in esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) v esd 2000 100 500 v latchup performance above v cc and below gnd at 85 c (note 5) i latchup 300 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. i o absolute maximum rating must be observed. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. 5. tested to eia/jesd78. 6. for high frequency or heavy load considerations, see the on semic onductor high?speed cmos data book (dl129/d).
NLSF1174 http://onsemi.com 3 recommended operating conditions parameter symbol min max unit ??????????????????????? ??????????????????????? dc supply voltage (referenced to gnd) ????? ????? ??? ??? ???? ???? ?? ?? ??????????????????????? ??????????????????????? ????? ????? ??? ??? ???? ???? ?? ?? ??????????????????????? ??????????????????????? ????? ????? ??? ??? 55 ???? ???? 125 ?? ?? c ??????????????????????? ? ????????????????????? ? ??????????????????????? input rise and fall time (figure 4) v cc = 2.0 v v cc = 4.5 v v cc = 6.0 v ????? ? ??? ? ????? t r , t f ??? ? ? ? ??? 0 0 0 ???? ? ?? ? ???? 1000 500 400 ?? ?? ?? dc electrical characteristics (voltages referenced to gnd) parameter test conditions v cc v guaranteed limit uni t symbol 55 c to 25 c 85 c 125 c ??????????? ? ????????? ? ??????????? minimum high?level input voltage ???????? ? ?????? ? ???????? v out = 0.1 v or v cc ? 0.1 v |i out | 20 a v ih ??? ?? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 1.5 3.15 4.2 ??? ? ? ? ??? 1.5 3.15 4.2 ???? ? ?? ? ???? 1.5 3.15 4.2 ?? ?? ?? ??????????? ? ????????? ? ??????????? maximum low?level input voltage ???????? ? ?????? ? ???????? v out = 0.1 v or v cc ? 0.1 v |i out | 20 a v il ??? ?? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 0.5 1.35 1.8 ??? ? ? ? ??? 0.5 1.35 1.8 ???? ? ?? ? ???? 0.5 1.35 1.8 ?? ?? ?? ??????????? ? ????????? ? ? ????????? ? ? ????????? ? ??????????? minimum high?level output voltage ???????? ? ?????? ? ???????? v in = v ih or v il |i out | 20 a v oh ??? ?? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 1.9 4.4 5.9 ??? ? ? ? ??? 1.9 4.4 5.9 ???? ? ?? ? ???? 1.9 4.4 5.9 ?? ?? ?? ?? ?? ???????? ? ?????? ? ???????? v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma ??? ?? ? ??? 4.5 6.0 ????? ? ??? ? ????? 3.98 5.48 ??? ? ? ? ??? 3.84 5.34 ???? ? ?? ? ???? 3.7 5.2 ??????????? ? ????????? ? ? ????????? ? ? ????????? ? ??????????? maximum low?level output voltage ???????? ? ?????? ? ???????? v in = v ih or v il |i out | 20 a v ol ??? ?? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 0.1 0.1 0.1 ??? ? ? ? ??? 0.1 0.1 0.1 ???? ? ?? ? ???? 0.1 0.1 0.1 ?? ?? ?? ?? ?? ???????? ? ?????? ? ???????? v in = v ih or v il |i out | 4.0 ma |i out | 5.2 ma ??? ?? ? ??? 4.5 6.0 ????? ? ??? ? ????? 0.26 0.26 ??? ? ? ? ??? 0.33 0.33 ???? ? ?? ? ???? 0.4 0.4 ??????????? ??????????? ???????? ???????? ??? ??? ????? ????? 0.1 ??? ??? 1.0 ???? ???? 1.0 ?? ?? a ??????????? ? ????????? ? ??????????? maximum quiescent supply current (per package) ???????? ? ?????? ? ???????? v in = v cc or gnd i out = 0 a i cc ??? ?? ? ??? 6.0 ????? ? ??? ? ????? 4.0 ??? ? ? ? ??? 40 ???? ? ?? ? ???? 160 ?? ?? ?? a 8. information on typical parametric values, along with high frequency or heavy load considerations, can be found in the on semi conductor high?speed cmos data book (dl129/d). ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) parameter v cc v guaranteed limit uni t symbol 55 c to 25 c 85 c 125 c ?????????????????? ? ???????????????? ? ?????????????????? maximum clock frequency (50% duty cycle) (figures 4 and 7) f max ??? ? ? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 6.0 30 35 ??? ? ? ? ??? 4.8 24 28 ????? ? ??? ? ????? 4.0 20 24 ?? ?? ?? ?????????????????? ? ???????????????? ? ?????????????????? maximum propagation delay, clock to q (figures 5 and 7) t plh t phl ??? ? ? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 110 22 19 ??? ? ? ? ??? 140 28 24 ????? ? ??? ? ????? 165 33 28 ?? ?? ?? ?????????????????? ? ???????????????? ? ? ???????????????? ? ?????????????????? maximum propagation delay, reset to q (figures 2 and 7) t plh t phl ??? ? ? ? ? ? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ? ??? ? ????? 110 21 19 ??? ? ? ? ? ? ? ??? 140 28 24 ????? ? ??? ? ? ??? ? ????? 160 32 27 ?? ?? ?? ?? ?????????????????? ? ???????????????? ? ?????????????????? maximum output transition time, any output (figures 4 and 7) t tlh t thl ??? ? ? ? ??? 2.0 4.5 6.0 ????? ? ??? ? ????? 75 15 13 ??? ? ? ? ??? 95 19 16 ????? ? ??? ? ????? 110 22 19 ?? ?? ?? ?????????????????? ?????????????????? ??? ??? ????? ????? ??? ??? ????? ????? ?? ?? typical @ 25 c, v cc = 5.0 v pf 62 9. for propagation delays with loads other than 50 pf, and information on typical parametric values, see the on semic onductor high?speed cmos data book (dl129/d). 10. used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see the on semiconductor high?speed cmos data book (dl129/d).
NLSF1174 http://onsemi.com 4 timing requirements (c l = 50 pf, input t r = t f = 6.0 ns) parameter figure symbo l v cc v guaranteed limit uni t 55 c to 25 c 85 c 125 c min max min max min max ?????????????? ? ???????????? ? ?????????????? minimum setup time, data to clock ??? ? ? ? ??? 6 t su ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 50 10 9.0 ??? ? ? ? ??? ??? ? ? ? ??? 65 13 11 ??? ? ? ? ??? ??? ? ? ? ??? 75 15 13 ??? ? ? ? ??? ?? ?? ?? ns ?????????????? ? ???????????? ? ?????????????? minimum hold time, clock to data ??? ? ? ? ??? 6 t h ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ?? ?? ?? ns ?????????????? ? ???????????? ? ?????????????? minimum recovery time, reset inactive to clock ??? ? ? ? ??? 5 t rec ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ??? ? ? ? ??? 5.0 5.0 5.0 ??? ? ? ? ??? ?? ?? ?? ns ?????????????? ? ???????????? ? ?????????????? minimum pulse width, clock ??? ? ? ? ??? 4 t w ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 75 15 13 ??? ? ? ? ??? ??? ? ? ? ??? 95 19 16 ??? ? ? ? ??? ??? ? ? ? ??? 110 22 19 ??? ? ? ? ??? ?? ?? ?? ns ?????????????? ? ???????????? ? ?????????????? minimum pulse width, reset ??? ? ? ? ??? 5 t w ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? 75 15 13 ??? ? ? ? ??? ??? ? ? ? ??? 95 19 16 ??? ? ? ? ??? ??? ? ? ? ??? 110 22 19 ??? ? ? ? ??? ?? ?? ?? ns ?????????????? ? ???????????? ? ?????????????? maximum input rise and fall times ??? ? ? ? ??? 4 t r , t f ??? ? ? ? ??? 2.0 4.5 6.0 ??? ? ? ? ??? ??? ? ? ? ??? 1000 500 400 ??? ? ? ? ??? ??? ? ? ? ??? 1000 500 400 ??? ? ? ? ??? ??? ? ? ? ??? 1000 500 400 ?? ?? ?? figure 3. expanded logic diagram c q d r c q d r c q d r c q d r c q d r
NLSF1174 http://onsemi.com 5 50% v cc gnd v cc gnd 50% clock q reset t phl figure 4. switching waveform figure 5. switching waveform 1/f max clock q t r t f v cc gnd 90% 50% 10% 90% 50% 10% t plh t phl t tlh t thl t w t w t rec 50% data clock v cc v cc gnd valid gnd t su t h *includes all probe and jig capacitance c l * test point device under test output figure 6. switching waveform figure 7. test circuit 50% figure 8. user direction of feed pin1/product orientation carrier tape
NLSF1174 http://onsemi.com 6 package dimensions 16 pin qfn case 485g?01 issue c 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ?? ?? ?? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 NLSF1174/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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