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? semiconductor components industries, llc, 2008 october, 2008 ? rev. 0 publication order number: nus6189mn/d nus6189mn low profile overvoltage protection ic with integrated mosfet this device represents a new level of safety and integration by combining an overvoltage protection circuit (ovp) with a 30 v p ? channel power mosfet, a low v ce(sat) transistor, and low r ds(on) power mosfet or charging. the ovp is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. during such events, the ic quickly disconnects the input supply from the load, thus protecting it. the integration of the additional transistor and power mosfet reduces layout space and promotes better charging performance. the ic is optimized for applications that use an external ac ? dc adapter or a car accessory charger to power a portable product or recharge its internal batteries. features ? overvoltage turn ? off time of less than 1.0 s ? accurate voltage threshold of 6.85 v, nominal ? undervoltage lockout protection; 2.8 v, nominal ? high accuracy undervoltage threshold of 2.0% ? ? 30 v integrated p ? channel power mosfet ? low r ds(on) = 50 m @ ? 4.5 v ? high performance ? 12 v p ? channel power mosfet ? single ? low v ce(sat) transistors as charging power mux ? compact 3.0 x 4.0 mm qfn package ? maximum solder reflow temperature @ 260 c ? this is a pb ? free device benefits ? provide battery protection ? integrated solution offers cost and space savings ? integrated solution improves system reliability ? optimized for commercial pmus from top suppliers applications ? portable computers and pdas ? cell phones and handheld products ? digital cameras qfn22 case 485at device package shipping ? ordering information marking diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. NUS6189MNTWG qfn22 (pb ? free) 3000 / tape & reel http://onsemi.com (note: microdot may be in either location) 1 nus 6189 alyw nus6189 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package
nus6189mn http://onsemi.com 2 batt base collector collector collector batt batt control gnd batt (top view) collector 1 22 6 711 12 17 18 source2 gate2 emitter collector v cc ovp out v in batt source1 gate1 batt figure 1. pinout ovp out ovp out ovp out qualcomm qsc60xx adapter input ovp chg ctl vsense vchg vsense vbat bat fet battery figure 2. typical charging solution for qualcomm qsc60xx 12 mosfet2 8 bjt mosfet1 4,5,6,7 2,16,17,21,22 18 3 19 10 1 blocks integrated in nus6189 ovp out gnd v in base batt batt collector source1 gate1 emitter 9, 11, 13 v cc 14 15 source2
nus6189mn http://onsemi.com 3 functional pin descriptions pin function description 1 source 1 this pin is the source of mosfet1 and connects to the more negative vsense pin of the pmic and to the more negative side of the current sense resistor. 2, 16, 17, 21, 22 batt these pins are the drain of mosfet2 and connect to the battery and the vbat pin of the pmic. 3 base the base of the internal bipolar transistor is connected to this pin. it connects to the charge control pin of the pmic. 4, 5, 6, 7 collector the collector of the internal bipolar transistor connects to these pins and should be connected to the more positive side of the current sense resistor as well as the more positive vsense pin of the pmic. 8 emitter this pin is connected to the emitter of the bipolar transistor. it should be connected externally to the ovp out pins. 9, 11, 13 ovp out these pins are the output of the ovp circuit. internally they connect to the drain of mosfet2. these pins connect externally to the vcharge pin of the pmic. 10 gate2 this pin is the gate of mosfet2. it is not normally connected to external circuitry. 12 source 2 the source of the ovp fet is connected to this pin. this pin needs to be connected to pins 14 & 15. 14 v cc this pin is the v cc pin of the ovp chip. it needs to be connected to pins 12 and 15. 15 v in this pin senses the output voltage of the charger. if the voltage on this input rises above the over- voltage threshold (v th ), the ovp out pin will be driven to within 1.0 v of v in , thus disconnecting the fet. the nominal threshold level is 6.85 v. this pin needs to be connected to pins 12 and 14. 18 gate1 this pin is the gate of mosfet1. it connects to the bat fet pin of the pmic. 19 gnd this is the ground reference pin for the ovp chip. 20 control this logic signal is used to control the state of ovp out and turn ? on/off the p ? channel mosfet. a logic level high results in the ovp out signal being driven to within 1.0 v of vcc which turns off mosfet2. if this pin is not used, it should be connected to ground.
nus6189mn http://onsemi.com 4 maximum ratings rating symbol value unit v in to ground v in -0.3 to 30 v gate2 voltage to ground v g2 -0.3 to 30 v control pin to ground v cntrl -0.3 to 13 v shunt voltage (ovp out to batt) v shunt 12 v maximum power dissipation (t a = 50 c, notes 1 & 3) p d 1.2 w thermal resistance, junction-to-air (note 1) average for chip, minimum copper maximum for power device, minimum copper average , for chip (note 2) maximum for power device (note 1) average for chip (note 1) maximum for power device (note 1) j-a 137 145 98 103 77 82 c/w operating case temperature (note 4) t cmax 125 c operating ambient temperature (p d = 0.5 w, note 1) t amb 109 c operating junction temperature (all dice) t jmax 150 c thermal resistance junction ? to ? case (note 4) jc 30 c/w storage temperature range t stg -65 to 150 c continuous input current (t a = 50 c, notes 1 & 3) i max 2.6 a gate-to-source voltage mosfet1 v gs1 8.0 v drain-to-source voltage mosfet1 v ds1 ? 12 v drain-to-source voltage mosfet2 v ds2 ? 30 v collector-emitter voltage bjt v ceo ? 20 v collector-base voltage bjt v cbo ? 20 v emitter-base voltage bjt v ebo ? 7.0 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. surface ? mounted on fr4 board using 1 inch sq pad size (cu area = 1.127 in sq [1 oz] including traces). 2. surface ? mounted on fr4 board using 0.25 inch sq pad size (cu area = 0.37 in sq [1 oz] including traces). 3. v in = 6.0 v, all power devices fully enhanced. 4. surface ? mounted on fr4 board using 400 mm sq pad size, 4 oz cu, p d < 800 mw.
nus6189mn http://onsemi.com 5 electrical characteristics (t j = 25 c, cntrl 1.5 v, v cc = 6.0 v, unless otherwise specified) characteristic symbol min typ max unit ovp threshold input threshold (v in increasing) v th 6.65 6.85 7.08 v input hysteresis (v in decreasing) v hyst 50 150 200 mv input impedance (v in = v th ) r in 70 150 ? k control input control voltage high (output on) v cntrlhi 1.50 ? ? v control voltage low (output off) v cntrllo ? ? 0.50 v control current high (v ih = 5.0 v) i ih ? 95 200 a control current low (v il = 0.5 v) i il ? 10 ? a ovp gate drive voltage gate2 voltage high (v in = 8.0 v; i source = 10 ma) gate2 voltage high (v in = 8.0 v; i source = 0.25 ma) gate2 voltage high (v in = 8.0 v; i source = 0 ma) v oh v in ? 1.0 v in ? 0.25 v in ? 0.1 ? ? ? ? ? ? v gate2 voltage low (v in = 6.0 v; i sink = 0 ma, control = 0 v) v ol ? ? 0.10 v gate2 sink current (v in < v th , ovp out = 1.0 v, note 5) i sink 10 33 50 a timing turn on delay ? input (v in stepped down from 8 to 6 v; measured at 50% point of ovp out , note 5) t on_in ? ? 10 s turn off delay ? input (v in stepped up from 6.0 to 8.0 v; c l = 12 nf output > v in ? 1.0 v) t off_in ? 0.5 1.0 s turn on delay ? control (control signal stepped down from 2.0 to 0.5 v; measured to 50% point of ovp out , note 5) t on_ct ? ? 10 s turn off delay ? control (control signal stepped up from 0.5 to 2.0 v; c l = 12 nf output > v in ? 1.0 v) t off_ct ? 1.0 2.0 s total device v in operating voltage range (note 5) v in 3.0 4.8 25 v input bias current i bias ? 0.75 1.0 ma undervoltage lockout (v in decreasing) v lock 2.5 2.8 3.0 v ovp fet (mosfet2) (t j = 25 c, v cc = 6.0 v, unless otherwise specified) voltage drop (v in to ovp out , v gs = -4.5 v) i load = 0.6 a i load = 1.0 a i load = 1.0 a, t j = 150 c (note 5) v ovp ? ? ? 33 66 90 54 100 135 mv on resistance i load = 0.6 a i load = 1.0 a i load = 1.0 a, t j = 150 c (note 5) r ds(on) ? ? ? 50 52 90 90 100 135 m off state leakage current t j = 125 c i leak ? ? -0.1 ? -1.0 -100 a charging bjt (t j = 25 c, unless otherwise specified) collector-emitter cutoff current (v ces = -20 v, note 5) i ces ? ? -0.1 a dc current gain (i b = -2.0 ma, v ce = -2.0 v, note 6) h fe 180 ? ? ? collector-emitter saturation voltage i c = -1.0 a, i b = -0.01 a i c = -1.0 a, i b = -0.1 a v ce(sat) ? ? -0.10 -0.069 -0.12 -0.09 v
nus6189mn http://onsemi.com 6 electrical characteristics (t j = 25 c, cntrl 1.5 v, v cc = 6.0 v, unless otherwise specified) characteristic unit max typ min symbol input capacitance (v eb = -0.5 v, f = 1.0 mhz, note 5) c ibo ? 240 400 pf output capacitance (v cb = -3.0 v, f = 1.0 mhz, note 5) c obo ? 50 100 pf charging fet (mosfet1) (t j = 25 c, unless otherwise specified) voltage drop across fet v gs = -4.5 v, i load = 1.0 a v gs = -2.5 v, i load = 1.0 a v gs = -4.5 v, i load = 1.0 a, t j = 150 c (note 5) v ds ? ? ? 32 44 62 40 50 70 mv on resistance v gs = -4.5 v, i load = 1.0 a v gs = -2.5 v, i load = 1.0 a v gs = -4.5 v, i load = 1.0 a, t j = 150 c, (note 5) r ds(on) ? ? ? 32 44 62 40 50 70 mv off state leakage current (note 5) t j = 125 c i leak ? ? ? 0.1 ? ? 1.0 ? 10 a input capacitance c iss ? 1330 ? pf output capacitance c oss ? 200 ? pf reverse transfer capacitance c rss ? 115 ? pf total gate charge (note 5) q g(tot) ? 13 15.7 nc threshold gate charge q g(th) ? 1.5 ? nc gate-to-source charge q gs ? 2.2 ? nc gate-to-drain charge q gd ? 2.9 ? nc gate resistance r g ? 14.4 ? forward transconductance (v ds = -6 v, i d = 1.0 a) g fs ? 0.9 ? s gate threshold voltage (v gs = v ds , i d = -250 a) v gs(th) ? 0.45 ? 0.67 ? 1.1 v negative threshold temperature coefficient v gs(th) /t j ? 2.7 ? mv/ c 5. guaranteed by design. 6. pulsed condition: pulse width = 300 us, duty cycle < 2%.
nus6189mn http://onsemi.com 7 typical characteristics ? 12v, p ? channel mosfets (mosfet1 ? charging) figure 3. on ? region characteristics figure 4. transfer characteristics ? v ds , drain ? to ? source voltage (v) ? v gs , gate ? to ? source voltage (v) 6 5 4 3 2 1 0 0 1 2 3 4 5 6 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 figure 5. on ? resistance vs. drain current figure 6. on ? resistance vs. drain current and gate voltage ? i d , drain current (a) ? i d , drain current (a) 6 5 4 3 2 1 0.02 0.03 0.04 0.05 6 5 4 3 2 1 0.02 0.03 0.04 0.05 figure 7. on ? resistance variation with temperature figure 8. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) ? v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.6 0.8 1.0 1.2 1.4 1.6 12 10 8 6 4 2 100 1,000 10,000 ? i d , drain current (a) ? i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) ? i dss , leakage (na) t j = 25 c v gs = ? 1.4 v ? 1.5 v ? 1.6 v ? 1.7 ? ? 8.0 v v ds ? 10 v v gs = 4.5 v t j = 100 c t j = 25 c t j = ? 55 c t j = 100 c t j = 25 c t j = ? 55 c v gs = ? 2.5 v t j = 25 c v gs = ? 4.5 v 150 i d = ? 3 a v gs = ? 4.5 v t j = 150 c t j = 100 c v gs = 0 v
nus6189mn http://onsemi.com 8 typical characteristics ? 12v, p ? channel mosfets (mosfet1 ? charging) figure 9. capacitance variation figure 10. gate ? to ? source and drain ? to ? source voltage vs. total charge gate ? to ? source or drain ? to ? source voltage (v) q g , total gate charge (nc) 12 8 6 4 2 0 ? 2 ? 4 0 400 800 1200 1600 2000 2400 2800 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 figure 11. resistive switching time variation vs. gate resistance figure 12. diode forward voltage vs. current r g , gate resistance ( ) ? v sd , source ? to ? drain voltage (v) 100 10 1 1 10 100 1,000 1.0 0.8 0.6 0.4 0.2 0 0.01 0.1 1 10 figure 13. maximum rated forward biased safe operating area ? v ds , drain ? to ? source voltage (v) 100 10 1 0.1 0.01 0.1 1 10 100 c, capacitance (pf) ? v gs , gate ? to ? source voltage (v) t, time (ns) ? i s , source current (a) ? i d , drain current (a) 10 t j = 25 c v ds = 0 v c iss c rss c oss i d = ? 3 a t j = 25 c t d(off) t d(on) t f t r v gs = 0 v t j = 25 c t j = 150 c t j = ? 55 c 100 s 1 ms 10 ms dc mounted on 2 sq. fr4 board (0.5 sq. 2 oz. cu single sided) with mosfet die operating. single pulse t c = 25 c r ds(on) limit thermal limit package limit v dd = ? 12 v i d = ? 3.0 a v gs = ? 4.5 v q t v ds v gs q gd q gs 12 10 8 6 4 2 0 ? v ds , drain ? to ? source voltage (v) c iss v gs = 0 v ? v gs ? v ds
nus6189mn http://onsemi.com 9 typical characteristics ? 12v, p ? channel mosfets (mosfet1 ? charging) figure 14. fet thermal response t, time (s) 1e+00 1e ? 01 1e ? 03 1e ? 04 1e ? 02 1e ? 05 1e ? 06 0.001 0.01 0.1 1 r ja , effective transient thermal response 1e+01 1e+02 1e+03 single pulse d = 0.5 0.2 0.1 0.05 0.02 0.01
nus6189mn http://onsemi.com 10 typical characteristics ? single pnp transistor (bjt ? charging) ? 55 c v ce(sat) = 150 c ic/ib = 10 25 c figure 15. collector emitter saturation voltage vs. collector current figure 16. collector emitter saturation voltage vs. collector current i c , collector current (a) 10 1.0 0.1 0.01 0.001 0 0.05 0.1 0.15 0.2 0.25 figure 17. dc current gain vs. collector current figure 18. base emitter saturation voltage vs. collector current i c , collector current (a) i c , collector current (a) 10 1.0 0.1 0.01 0.001 100 150 300 350 500 700 750 800 10 1.0 0.1 0.01 0.001 0.3 0.4 0.5 0.6 0.7 0.8 1.0 1.1 figure 19. base emitter turn ? on voltage vs. collector current figure 20. saturation region i c , collector current (a) i b , base current (ma) 10 1.0 0.1 0.01 0.001 0.1 0.2 0.3 0.4 0.5 0.8 0.9 1.0 100 10 1.0 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 v ce(sat) , collector emitter saturation voltage (v) h fe , dc current gain v be(sat) , base emitter saturation voltage (v) v be(on) , base emitter turn ? on voltage (v) v ce , collector ? emitter voltage (v) ic/ib = 100 25 c ? 55 c i c , collector current (a) 10 1.0 0.1 0.01 0.001 0 0.05 0.1 0.15 0.2 0.35 v ce(sat) , collector emitter saturation voltage (v) v ce(sat) = 150 c 0.25 0.3 650 600 550 200 250 400 450 0.9 150 c (5.0 v) 150 c (2.0 v) 25 c (5.0 v) 25 c (2.0 v) ? 55 c (5.0 v) ? 55 c (2.0 v) 25 c ? 55 c 150 c 0.6 0.7 25 c ? 55 c 150 c v ce = ? 2.0 v v ce (v) i c = 500 ma 300 ma 10 ma 100 ma ic/ib = 10
nus6189mn http://onsemi.com 11 typical characteristics ? single pnp transistor (bjt ? charging) 10 ms 100 ms 1 s thermal limit 1 ms c ibo (pf) figure 21. input capacitance figure 22. output capacitance v eb , emitter base voltage (v) 4.0 3.0 2.0 1.0 0 125 150 300 325 350 figure 23. safe operating area v ce (v dc ) 100 1.0 0.1 0.01 0.01 0.1 10 c ibo , input capacitance (pf) i c (a) v cb , collector base voltage (v) 16 8.0 6.0 0 50 70 90 130 170 c obo , output capacitance (pf) 150 6.0 5.0 200 225 250 275 175 c obo (pf) 2.0 4.0 14 12 10 1.0 10 110
nus6189mn http://onsemi.com 12 typical performance curves ? overvoltage protection ic (t a = 25 c, unless otherwise specified) 1.0 0.9 0.8 0.7 0.6 0.5 ? 40 ? 25 ? 10 5 203550658095 temperature ( c) 7.05 7.00 6.95 6.90 6.85 6.80 6.75 6.70 ? 40 ? 25 ? 10 5 203550658095 ambient temperature ( c) voltage (v) i supply (ma) figure 24. typical v th threshold variation vs. temperature figure 25. typical supply current vs. temperature i cc i in , v cc 6 v 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 figure 26. typical maximum drain peak current vs pulse width (non ? repetitive single pulse, v gs = 10 v, t a = 25 c) pulse width ( s) i dpk , amps (a)
nus6189mn http://onsemi.com 13 typical performance curves ? 30v, p ? channel mosfet (mosfet2 ? ovp) (t a = 25 c, unless otherwise specified) ? 8 v 0 12 9 1.2 0.8 ? v ds , drain ? to ? source voltage (volts) ? i d, drain current (amps) 3 0 0.4 figure 27. on ? region characteristics figure 28. on ? resistance vs. gate ? to ? source voltage 15 1000 100 figure 29. drain ? to ? source leakage current vs. voltage ? v ds , drain ? to ? source voltage (volts) ? i dss, leakage current (na) 210 0.1 figure 30. diode forward voltage vs. current ? v gs, gate voltage (volts) t j = 25 c 100000 5 v gs = 0 v r ds(on), drain ? to ? source resistance ( ) ? 3 v 25 30 ? 3.2 v ? 3.4 v ? 4.5 v 0.2 1.6 2 10000 468 0 6 10 t j = 100 c t j = 150 c 9 357 t j = 25 c i d = ? 3.7 a 20 11 8 2 5 10 7 1 4 3.2 2.8 2.4 3.6 4 ? 3.6 v ? 3.8 v ? 4 v ? 4.2 v ? 10v ? 6 v ? 5 v ? 5.5 v 0.9 1 ? v sd , source ? to ? drain voltage (volts) ? i s , source current (amps) t j = 25 c 1.0 0.4 0.3 10 0.5 0.8 0.6 0.1 0.7 1.1 v gs = 0 v t j = ? 55 c t j = 150 c t j = 100 c
nus6189mn http://onsemi.com 14 package dimensions qfn22, 3x4, 0.5p case 485at ? 01 issue b soldering footprint* 0.50 0.52 22x dimensions: millimeters pitch 22x 1 4.30 1.47 1.47 1.55 0.925 3.30 1.47 1.21 1.58 0.39 1.14 0.30 package outline pin 1 reference a b c 0.15 c 0.15 2x 2x a c c 0.08 25x c 0.10 side view top view e4 d4 bottom view b 22x l 1 18 12 7 d e a3 a1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pads as well as the terminals. dim min nom millimeters a 0.80 0.90 a1 0.00 0.025 a3 0.20 ref b 0.20 0.25 d 3.00 bsc d2 1.45 1.50 e 4.00 bsc e2 1.05 1.10 e 0.50 bsc k 0.25 ??? l 0.30 0.325 0.10 b 0.05 a c c note 3 22x k 16x l1 detail a l optional constructions l note 4 seating plane detail b l1 ??? ??? g 1.35 1.40 g1 0.95 1.05 g2 0.855 0.885 e3 1.30 1.35 e4 1.40 1.45 d3 0.52 0.57 d4 1.02 1.07 ??? ??? a1 a3 1.00 0.05 0.30 1.55 1.15 ??? 0.35 0.15 1.50 1.15 0.915 1.40 1.50 0.62 1.12 max on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. nus6189mn/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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