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nippon precision circuits inc. nippon precision circuits-1 SM5903BF compression and non compression type shock-proof memory controller overview - 2-channel processing - serial data input ? 2s complement, 16-bit/msb first, right-justified format ? wide capture function (up to 3 speed input rate) - system clock input ? 384fs (16.9344 mhz) - shock-proof memory controller ? adpcm compression method ? 4-level compression mode selectable 4-bit compression mode 2.78 s/mbit 5-bit compression mode 2.22 s/mbit 6-bit compression mode 1.85 s/mbit full-bit non compression mode 0.74 s/mbit ? 4 external dram configurations selectable 1 16m dram (4m 4 bits, refresh cycle = 2048 cycle) 1 or 2 4m dram (1m 4 bits) 1 1m dram (256k 4 bits) - microcontroller interface ? serial command write and status read-out ? data residual detector: 15-bit operation, 16-bit output ? forced mute - extension i/o microcontroller interface for external control using 5 extension i/o pins - +2.4 to +3.6 v operating voltage range - schmitt inputs all input pins (including i/o pins) except clk (system clock) - reset signal noise elimination approximately 3.8 s or longer (65 system clock pulses) continuous low-level reset - 44-pin lqfp package (0.8 mm pin pitch) the SM5903BF is a compression and non com- pression type shock-proof memory controller lsi for compact disc players. the compression level can be set in 4 levels, and external memory can be selected from 4 options (1m, 4m, 4m 2, 16m). it operates from a 2.4 to 3.6 v supply voltage range. features ordering information SM5903BF 44-pin lqfp
nippon precision circuits-2 SM5903BF package dimensions (unit : mm) 44-pin lqfp weight : 0.38g pinout (top view) 0.20 0.10 (1.40) 12.80 0.30 0.35 0.10 12.80 0.30 0.17 0.05 0 to 10 0.60 0.20 4 c0.7 10.00 0.30 10.00 0.30 0.80 0.10 0.05 0.10 1.50 0.10 0.20 m (1.40) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 vdd2 uc1 uc2 uc3 uc4 uc5 n.c ntest clk vss ysrdata nwe d1 d0 d3 d2 ncas a10/ ncas2 ymclk ymdata ymld ydmute ylrck ysck zsck zlrck zsrdata yflag yfclk yblkck nreset zsense vdd1 a3 a2 a1 a0 a4 a5 a6 a7 a8 a9 nras sm590 3bf
nippon precision circuits-3 SM5903BF pin description pin number pin name i/o function setting hl 1 vdd2 - vdd supply pin 2 uc1 ip/o microcontroller interface extension i/o 1 3 uc2 ip/o microcontroller interface extension i/o 2 4 uc3 ip/o microcontroller interface extension i/o 3 5 uc4 ip/o microcontroller interface extension i/o 4 6 uc5 ip/o microcontroller interface extension i/o 5 7 n.c - 8 ntest ip test pin test 9 clk i 16.9344 mhz clock input 10 vss - ground 11 ysrdata i audio serial input data 12 ylrck i audio serial input lr clock left channel right channel 13 ysck i audio serial input bit clock 14 zsck o audio serial output bit clock 15 zlrck o audio serial output lr clock left channel right channel 16 zsrdata o audio serial output data 17 yflag i signal processor ic ram overflow flag overflow 18 yfclk i crystal-controlled frame clock 19 yblkck i subcode block clock signal 20 nreset i system reset pin reset 21 zsense o microcontroller interface status output 22 vdd1 - vdd supply pin 23 ydmute i forced mute pin mute 24 ymld i microcontroller interface latch clock 25 ymdata i microcontroller interface serial data 26 ymclk i microcontroller interface shift clock 27 a10 o dram address 10 (ncas2) o dram2 cas control (with 2 drams) 28 ncas o dram cas control 29 d2 i/o dram data input/output 2 30 d3 i/o dram data input/output 3 31 d0 i/o dram data input/output 0 32 d1 i/o dram data input/output 1 33 nwe o dram we control 34 nras o dram ras control 35 a9 o dram address 9 36 a8 o dram address 8 37 a7 o dram address 7 38 a6 o dram address 6 39 a5 o dram address 5 40 a4 o dram address 4 41 a0 o dram address 0 42 a1 o dram address 1 43 a2 o dram address 2 44 a3 o dram address 3 ip : input pin with pull-up resistor ip/o : input/output pin (with pull-up resistor when in input mode)
parameter pin symbol condition rating unit min typ max current consumption vdd i dd (*a)shprf on 4.5 8.0 ma (*a)through mode 1.8 3.0 ma input voltage clk h level v ih1 0.7v dd v l level v il1 0.3v dd v v inac ac coupling 1.0 v p-p (*2,3,4) h level v ih2 0.7v dd v l level v il2 0.3v dd v (*5) h level v ih3 0.6v dd v l level v il3 0.2v dd v output voltage (*4,6) h level v oh1 i oh = - 0.5 ma v dd - 0.4 v l level v ol1 i ol = 0.5 ma 0.4 v (*5,7) h level v oh2 i oh = - 0.5 ma v dd - 0.4 v l level v ol2 i ol = 0.5 ma 0.4 v input current clk i ih1 v in = v dd 5 15 115 a i il1 v in = 0v 5 15 115 a (*3,4) i il2 v in = 0v 1 2.5 15 a input leakage current (*2,3,4,5) i lh v in = v dd 1.0 a (*2,5) i ll v in = 0v 1.0 a (*a) v dd1 = v dd2 = 3 v, clk input frequency f xti = 384fs = 16.9344 mhz, all outputs unloaded, shprf: shock-proof, typical values are for v dd1 = v dd2 = 3 v. note. refer to pin summary on the next page. nippon precision circuits-4 SM5903BF parameter symbol rating unit supply voltage v dd - 0.3 to 4.6 v input voltage v i v ss - 0.3 to v dd + 0.3 v storage temperature t stg - 55 to 125 ?c power dissipation p d 350 mw (v ss = 0v, vdd1, vdd2 pin voltage = v dd ) note. values also apply for supply inrush and switch-off. parameter symbol rating unit supply voltage v dd 2.4 to 3.6 v operating temperature t opr - 40 to 85 ? c (v ss = 0v, vdd1, vdd2 pin voltage = v dd ) electrical characteristics recommended operating conditions dc characteristics standard voltage:(v dd1 = v dd2 = 3.0 to 3.6 v, v ss = 0 v, ta = - 40 to 85 ?c) absolute maximum ratings
nippon precision circuits-5 SM5903BF (*1) pin function clock input pin (ac input) pin name clk (*2) pin function schmitt input pins pin name ysrdata, ylrck, ysck, yflag, yfclk, nreset, yblkck, ydmute, ymld, ymdata, ymclk (*3) pin function schmitt input pin with pull-up pin name ntest (*4) pin function i/o pins (schmitt input with pull-up in input state) pin name uc1, uc2, uc3, uc4, uc5 (*5) pin function i/o pins (schmitt input in input state) pin name d0, d1, d2, d3 (*6) pin function outputs pin name zsck, zlrck, zsrdata, zsense (*7) pin function outputs pin name ncas, nwe, nras, a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10 low-voltage:(v dd1 = v dd2 = 2.4 to 3.0 v, v ss = 0 v, ta = - 20 to 70 ?c) parameter pin symbol condition rating unit min typ max current consumption vdd i dd (*b)shprf on 4.5 8.0 ma (*b)through mode 1.8 3.0 ma input voltage clk h level v ih1 0.7v dd v l level v il1 0.3v dd v v inac ac coupling 1.0 v p-p (*2,3,4) h level v ih2 0.7v dd v l level v il2 0.3v dd v (*5) h level v ih3 0.6v dd v l level v il3 0.2v dd v output voltage (*4,6) h level v oh1 i oh = - 0.5 ma v dd - 0.4 v l level v ol1 i ol = 0.5 ma 0.4 v (*5,7) h level v oh2 i oh = - 0.5 ma v dd - 0.4 v l level v ol2 i ol = 0.5 ma 0.4 v input current clk i ih1 v in = v dd 5 15 115 a i il1 v in = 0v 5 15 115 a (*3,4) i il2 v in = 0v 1 2.5 15 a input leakage current (*2,3,4,5) i lh v in = v dd 1.0 a (*2,5) i ll v in = 0v 1.0 a (*b) v dd1 = v dd2 = 3 v, clk input frequency f xti = 384fs = 16.9344 mhz, all outputs unloaded, shprf: shock-proof, typical values are for v dd1 = v dd2 = 3 v. note. refer to pin summary below.
nippon precision circuits-6 SM5903BF cwh t cwl t cy t 0.5v dd clk parameter symbol rating unit condition min typ max ysck pulsewidth (high level) t bcwh 75 ns ysck pulsewidth (low level) t bcwl 75 ns ysck pulse cycle t bcy 150 ns ysrdata setup time t ds 50 ns ysrdata hold time t dh 50 ns last ysck rising edge to ylrck edge t bl 50 ns ylrck edge to first ysck rising edge t lb 50 ns 0 3fs memory system on ylrck pulse frequency (mson=h) see note below. fs fs memory system off (mson=l) note. when the memory system is off (through mode), the input data rate is synchronized to the system clock input (384fs), so i nput data needs to be at 1/384 of this frequency. but, this ic can tolerate a certain amount of jitter. for details, refer to throug h-mode operation. ysck ysrdata ylrck bcy t ds t dh t bcwh t bcwl t lb t bl t 0.5v dd 0.5v dd 0.5v dd serial input (ysrdata, ylrck, ysck pins) ac characteristics standard voltage: v dd1 = v dd2 = 3.0 to 3.6 v, v ss = 0 v, ta = -40 to 85 ?c low-voltage: v dd1 = v dd2 = 2.4 to 3.0 v, v ss = 0 v, ta = -20 to 70 ?c (*) typical values are for fs = 44.1 khz system clock (clk pin) parameter symbol condition rating unit system clock min typ max clock pulsewidth (high level) t cwh 26 29.5 125 ns clock pulsewidth (low level) t cwl 26 29.5 125 ns clock pulse cycle t cy 384fs 58 59 250 ns system clock input
nippon precision circuits-7 SM5903BF parameter symbol rating unit min typ max ymclk low-level pulsewidth t mcwl 30 + 2 t cy ns ymclk high-level pulsewidth t mcwh 30 + 2 t cy ns ymdata setup time t mds 30 + t cy ns ymdata hold time t mdh 30 + t cy ns ymld low-level pulsewidth t mlwl 30 + 2 t cy ns ymld setup time t mls 30 + t cy ns ymld hold time t mlh 30 + t cy ns rise time t r 100 ns fall time t f 100 ns zsense output delay t pzs 100 + 3 t cy ns note. t cy is the system clock cycle time (59ns typ). ymdata ymclk zsense ymld ymdata ymclk ymld mds t mdh t mcwl t mls t mcwh t mlh t mlwl t pzs t 0.5v dd 0.5v dd 0.5v dd 0.5v dd 0.5v dd 0.5v dd 0.3 v dd 0.3 v dd 0.7 v dd 0.7 v dd f t r t reset input (nreset pin) parameter symbol rating unit min typ max first high-level after supply voltage rising edge t hnrst 0 t cy (note) nreset pulsewidth t nrst 64 t cy (note) note. t cy is the system clock (clk) input (384fs) cycle time. t cy = 59 ns, t nrst (min) = 3.8 s when fs = 44.1 khz nreset vdd1,vdd2 hnrst t t nrst microcontroller interface (ymclk, ymdata, ymld, zsense pins)
nippon precision circuits-8 SM5903BF parameter symbol condition rating unit min typ max zsck pulsewidth t scow 15 pf load 1/96fs zsck pulse cycle t scoy 15 pf load 1/48fs zsrdata and zlrck output delay time t dhl 15 pf load 0 60 ns t dlh 15 pf load 0 60 ns dram access timing (nras, ncas, ncas2, nwe, a0 to a10, d0 to d3) parameter symbol condition rating unit min typ max nras pulsewidth t rasl 15 pf load 5 t cy (note) t rash 15 pf load 3 t cy nras falling edge to ncas falling edge t rcd 15 pf load 2 t cy ncas pulsewidth t cash 15 pf load 5 t cy t casl 15 pf load 3 t cy nras setup time t rads 15 pf load 1 t cy falling edge to address hold time t radh 15 pf load 1 t cy ncas setup time t cads 15 pf load 1 t cy falling edge to address hold time t cadh 15 pf load 5 t cy ncas setup time t cwds 15 pf load 3 t cy falling edge to data write hold time t cwdh 15 pf load 3 t cy ncas input setup t crds 40 ns rising edge to data read input hold t crdh 0ns nwe pulsewidth t wel 15 pf load 6 t cy nwe falling edge to ncas falling edge t wcs 15 pf load 3 t cy non compression 1.5 ms refresh cycle 1m 6-bit compression 3.7 ms (fs = 44.1 khz playback) dram 5-bit compression 4.4 ms t ref 1 4-bit compression 5.5 ms memory system on non compression 3.0 ms decode sequence operation 4m 6-bit compression 7.3 ms (rden=h) dram 5-bit compression 8.8 ms 1 or 2 4-bit compression 10.9 ms non compression 5.9 ms 16m 6-bit compression 14.6 ms dram 5-bit compression 17.5 ms 1 4-bit compression 21.8 ms note. t cy is the system clock (clk) input (384fs) cycle time. t cy = 59 ns when fs = 44.1 khz zsck zsrdata 0.5v dd dlh zlrck 0.5v dd dhl tt dlh scow t t scow t scoy t serial output (zsrdata, zlrck, zsck pins)
nippon precision circuits-9 SM5903BF dram access timing (with single dram) the nwe terminal output is fixed high during read timing. dram access timing (with double drams) the nwe terminal output is fixed high during read timing. ncas terminal output is fixed high when selecting "dram2". ncas2 terminal output is fixed high when selecting "dram1". ncas a0 to a10 d0 to d3 (write) nras d0 to d3 (read) nwe (write) 3 wcs t 6 crdh t crds t cwdh t cwds t 33 5 cadh t cads t radh t rads t 111 5 3 2 t rcd t casl cash t rash t 3 t cy 5 rasl t t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy wel t ncas (dram1 select) a0 to a9 nras d0 to d3 (read) ncas2 (dram2 select) d0 to d3 (write) nwe (write) 5 3 25 3 1 1 1 3 3 5 25 3 3 rash t rasl t rcd tt casl cash t cash t t casl rdc t t rads radh t cads t cadh t cwdh t cwds t crds t crdh t wcs t t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy t cy wel t 6 t cy wcs t
nippon precision circuits-10 SM5903BF control input 1 control input 2 micro- controller interface general port output interface input interface input buffer decoder encoder dram interface yblkck yfclk yflag ymdata ymclk ymld zsense uc1 to uc5 ydmute nreset ntest clk nras ncas ncas2 nwe a0 to a10 d0 to d3 through mode compression mode zlrck zsck zsrdata ylrck ysck ysrdata sm5903 block diagram
nippon precision circuits-11 SM5903BF write command format (commands 80 to 85) SM5903BF has two modes of operation; shock- proof mode and through mode. the operating sequences are controlled using com- mands from a microcontroller. d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 command 8bit data 8bit ymdata ymclk ymld b7 b6 b5 b4 b3 b2 b1 b0 command 8bit ymdata ymclk ymld s7 s6 s5 s4 s3 s2 s1 s0 status 8bit zsense b7 b6 b5 b4 b3 b2 b1 b0 command 8bit ymdata ymclk ymld s7 s6 s1 s0 residual data 16bit zsense m1 m2 m7 m8 functional description read command format (command 92 (memory residual read)) read command format (commands 90, 91, 93) microcontroller interface command format commands from the microcontroller are input using 3-wire serial interface inputs; data (ymdata), bit clock (ymclk) and load signal (ymld). in the case of a read command from the microcon- troller, bit serial data is output (zsense) synchro- nized to the bit clock input (ymclk).
nippon precision circuits-12 SM5903BF bit name function h operation reset level d7 mswren encode sequence start/stop start l d6 mswacl write address reset reset l d5 msrden decode sequence start/stop start l d4 msracl read address reset reset l d3 msdcn2 msdcn2=h, msdcn1=h: 3-pair comparison start l msdcn2=h, msdcn1=l: 2-pair comparison start d2 msdcn1 msdcn2=l, msdcn1=h: direct-connect start l msdcn2=l, msdcn1=l: connect operation stop d1 waqv q data valid valid l d0 mson memory system on on l 1000 0000 b0 b1 b2 b3 b4 b5 b6 b7 80hex = shock-proof memory system settings bit name function h operation reset level d7 d6 d5 d4 uc5oe extension i/o port uc5 input/output setting output l d3 uc4oe extension i/o port uc4 input/output setting output l d2 uc3oe extension i/o port uc3 input/output setting output l d1 uc2oe extension i/o port uc2 input/output setting output l d0 uc1oe extension i/o port uc1 input/output setting output l 1000 0001 b0 b1 b2 b3 b4 b5 b6 b7 81hex = extension i/o port input/output settings bit name function h operation reset level d7 d6 d5 d4 uc5wd extension i/o port uc5 output data setting h output l d3 uc4wd extension i/o port uc4 output data setting h output l d2 uc3wd extension i/o port uc3 output data setting h output l d1 uc2wd extension i/o port uc2 output data setting h output l d0 uc1wd extension i/o port uc1 output data setting h output l 1000 0010 b0 b1 b2 b3 b4 b5 b6 b7 82hex = extension port high/low output level a port setting is invalid if that port has already been defined as an input using the 81h command above. command table write command summary ms command 80 extension i/o settings 81 extension i/o output data settings 82
nippon precision circuits-13 SM5903BF bit name function h operation reset level d7 d6 mute forced muting (changes instantaneously) mute on l d5 d4 d3 cmp12 12-bit comparison connect/ 16-bit comparison connect 12-bit comparison l d2 d1 d0 1000 0011 b0 b1 b2 b3 b4 b5 b6 b7 83hex = refer to "force mute", "12-bit comparison connection". bit name function h operation reset level d7 rams1 dram type setting l rams1=0 rams2=0 when 1mdram(256k 4bit) single rams1=1 rams2=0 when 4mdram(1m 4bit) single d6 rams2 rams1=0 rams2=1 when 4mdram(1m 4bit) double l rams1=1 rams2=1 when 16mdram(4m 4bit) single d5 yflgs flag6 set conditions (reset using status read command 90h) l - when yflgs=0, yfckp=0, yfclk input falling edge, yflag=l - when yflgs=0, yfckp=1, yfclk input rising edge, yflag=l d4 yfckp - when yflgs=1, yfckp=0, yflag=l l - when yflgs=1, yfckp=1, yflag=h d3 compfb full-bit compression mode l d2 comp6b 6-bit compression mode h d1 comp5b 5-bit compression mode l d0 comp4b 4-bit compression mode l 1000 0101 b0 b1 b2 b3 b4 b5 b6 b7 85hex = when the number of compression bits is set incorrectly (2 or more bits in d0 to d3 are set to 1 or all bits are set to 0), 6-bit compression mode is selected. mute, cmp12 settings 83 option settings 85
bit name function high-level state s7 flag6 signal processor ic jitter margin exceeded exceeded s6 msovf write overflow (read once only when ra exceeds wa) dram overflow s5 bovf input buffer memory overflow input buffer memory overflow because sampling rate of input data is too fast s4 s3 dcomp data compare-connect sequence operating compare-connect sequence operating s2 mswih encode sequence stop due to internal factors encoding stopped s1 msrih decode sequence stop due to internal factors decoding stopped s0 1001 0000 b0 b1 b2 b3 b4 b5 b6 b7 90hex = refer to "status flag operation summary". bit name function high-level state s7 msemp valid data empty state (always high when ra exceeds vwa) no valid data s6 ovfl write overflow state (always high when wa exceeds ra) memory full s5 encod encode sequence operating state encoding s4 decod decode sequence operating state decoding s3 s2 s1 s0 1001 0001 b0 b1 b2 b3 b4 b5 b6 b7 91hex = refer to "status flag operation summary". nippon precision circuits-14 SM5903BF read command summary shock-proof memory status (1) 90 shock-proof memory status (2) 91
nippon precision circuits-15 SM5903BF shock-proof memory valid data residual 92 extension i/o inputs 93 bit name function high-level state s7 s6 s5 s4 uc5rd s3 uc4rd s2 uc3rd s1 uc2rd s0 uc1rd 1001 0011 b0 b1 b2 b3 b4 b5 b6 b7 93hex = input data entering (or output data from) an extension port terminal is echoed to the microcontroller. (that is, the input data entering an i/o port configured as an input port using the 81h command, or the output data from a pin configured as an output port using the 82h command.) bit name function s7 am21 valid data accumulated vwa-ra (msb) 8m bits s6 am20 s5 am19 s4 am18 s3 am17 s2 am16 s1 am15 s0 am14 m1 am13 m2 am12 m3 am11 m4 am10 m5 am09 m6 am08 m7 am07 m8 am06 1001 0010 b0 b1 b2 b3 b4 b5 b6 b7 92hex = note. the time conversion factor varies depending on the compression bit mode.(m = 1,048,576 k= 1,024) residual time (sec) = valid data residual (mbits) time conversion value k where the time conversion value k (sec/mbit) 2.78(4 bits), 2.22 (5 bits), 1.85 (6 bits) and 0.74 (full bits). 4m bits 2m bits 1m bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 1k bits 4k bits 2k bits 512 bits 256 bits
flag read name method flag6 read meaning - indicates to the cd signal processor dsp (used for error correction, de-interleaving) that a 90h disturbance has exceeded the ram jitter margin. bit 7 set - set according to the yflag input and the operating state of yfckp and yflgs. flag6 set conditions when yflgs=0, yfckp=0, yfclk input falling edge, yflag=l when yflgs=0, yfckp=1, yfclk input rising edge, yflag=l when yflgs=1, yfckp=0, yflag=l when yflgs=1, yfckp=1, yflag=h reset - by 90h status read - by 80h command when mson=on - after external reset msovf read meaning - indicates once only that a write to external dram has caused an overflow. (when reset 90h by the 90h status read command, this flag is reset even if the overflow condition continues.) bit 6 set - when the write address (wa) exceeds the read address (ra) reset - by 90h status read - when a read address clear (msracl) or write address clear (mswacl) command is issued - after external reset bovf read meaning - indicates input data rate was too fast causing buffer overflow and loss of data 90h set - when inputs a data during a buffer memory overflow bit 5 reset - by 90h status read - when a read address clear (msracl) or write address clear (mswacl) command is issued - after external reset dcomp read meaning - indicates that a compare-connect sequence is operating 90h set - when a (3-pair or 2-pair) compare-connect start command is received (msdcn2=1) bit 3 - when a direct connect command is received (msdcn2=0, msdcn1=1) reset - when a (3-pair or 2-pair) comparison detects conforming data - when the connect has been performed after receiving a direct connect command - when a compare-connect stop command (msdcn2=0, msdcn1=0) is received - when a mswren=1 command is received (however, if a compare-connect command is received at the same time, the compare-connect command has priority.) - after external reset mswih read meaning - indicates that the encode sequence has stopped due to internal factors 90h (not microcontroller commands) bit 2 set - when flag6 (above) is set - when bovf (above) is set - when msovf (above) is set reset - when conforming data is detected after receiving a compare-connect start command - when the connect has been performed after receiving a direct connect command - when a read address clear (msracl) or write address clear (mswacl) command is received - after external reset msrih read meaning - indicates that the decode sequence has stopped due to internal factors 90h (not microcontroller commands) bit 1 set - when the valid data residual becomes 0 reset - by 90h status read - when a read address clear (msracl) or write address clear (mswacl) command is issued - after external reset status flag operation summary nippon precision circuits-16 SM5903BF
nippon precision circuits-17 SM5903BF flag read name method msemp read meaning - indicates that the valid data residual has become 0 91h set - when the vwa (final valid data's next address) bit 7 = ra (address from which the next read would take place) reset - whenever the above does not apply ovfl read meaning - indicates a write to external dram overflow state 91h set - when the write address (wa) exceeds the read address (ra). bit 6 (note: this flag is not set when wa=ra through an address initialize or reset operation.) reset - when the read address (ra) is advanced by the decode sequence - when a read address clear (msracl) or write address clear (mswacl) command is issued - after external reset encod read meaning - indicates that the encode sequence (input data entry, encoding, dram write) is operating 91h set - by the 80h command when mswren=1 bit 5 - when conforming data is detected during compare-connect operation - when the connect has been performed after receiving a direct connect command reset - when the flag6 flag=1 (above) - when the ovfl flag=1 (above) - by the 80h command when mswren=0 - by the 80h command when msdcn1=1 or msdcn2=1 (compare-connect start command) - by the 80h command when mson=0 - after external reset note. reset conditions have priority over set conditions. for example, if the 80h command has mswren=1 and msdcn1=1, the encod flag is reset and compare-connect operation starts. decod read meaning - indicates that the decode sequence (read from dram, decoding, 91h attenuation, data output) is operating bit 4 set - by a new 80h command when msrden=1 and the msemp flag=0 (above) reset - whenever the above does not apply
- mswren when 1: encode sequence starts invalid when mson is not 1 within the same 80h command invalid when flag6=1 invalid when ovfl=1 invalid when a compare-connect start command (msdcn2=1 or msdcn1=1) occurs simultaneously direct connect if a compare-connect sequence is already operating when 0: encode sequence stops - mswacl when 1: initializes the write address (wa) when 0: no operation - msrden when 1: decode sequence starts does not perform decode sequence if mson=1.if there is no valid data, decode sequence temporarily stops. but, because the msrden flag setting is maintained as is, the sequence automatically re-starts when valid data appears. when 0: decode sequence stops -msracl when 1: initializes the read address (ra) when 0: no operation - msdcn2, msdcn1 when 1 and 1: 3-pair compare-connect sequence starts when 1 and 0: 2-pair compare-connect sequence starts when 0 and 1: direct connect sequence starts when 0 and 0: compare-connect sequence stops. no operation if a compare-connect sequence is not operating. - waqv when 1: the immediately preceding yblkck falling-edge timing wa (write address) becomes the vwa (valid write address). when 0: no operation - mson when 1: memory system turns on and shock- proof operation starts when 0: memory system turns off and through- mode playback starts. (in this mode, the attenuator is still active.) write command supplementary information 80h (ms command) 81h (extension i/o port settings) 82h (extension i/o port output data settings) nippon precision circuits-18 SM5903BF
nippon precision circuits-19 SM5903BF 85h (option settings) - rams1, rams2 when 0 and 0 : 1m dram (256k 4 bits) single when 1 and 0 : 4m dram (1m 4 bits) single when 0 and 1 : 4m dram (1m 4 bits) double when 1 and 1 : 16m dram (4m 4 bits) single - yflgs, yfckp when 0 and 0: sets flag6 on the falling edge of yfclk when yflag=0 when 0 and 1: sets flag6 on the rising edge of yfclk when yflag=0 when 1 and 0: sets flag6 when yflag=0 when 1 and 1: sets flag6 when yflag=1 - compfb, comp6b, comp5b, comp4b when 0, 0, 0 and 1: selects 4-bit compression mode when 0, 0, 1 and 0: selects 5-bit compression mode when 1, 0, 0 and 0: selects full-bit compression mode in all other cases: selects 6-bit compression mode changing mode without initializing during opera- tion is possible. 83h ( mute, 12-bit comparison connection settings) - mute (forced muting) when 1: outputs are instantaneously muted to 0.(note 1) same effect as taking the ydmute pin high. when 0: no muting(note 1) (note1) effective at the start left-channel output data. - mute, ydmute relationship when all mute inputs are 0, mute is released. - cmp12 (12-bit comparison connection) when 1: performs comparison connection using only the most significant 12 bits of input data. when 0: performs comparison connection using all 16 bits of input data.
nippon precision circuits-20 SM5903BF shock-proof mode is the mode that realizes shock- proof operation using external dram. shock-proof mode is invoked by setting mson=h in microcon- troller command 80h. this mode comprises the following 3 sequences. shock-proof operation overview - encode sequence 1. input data from a signal processor ic is stored in internal buffers. 2. encoder starts after a fixed number of data have been received. 3. the encoder, after the most suitable predicting filter type and quantization steps have been deter- mined, performs adpcm encoding and then writes to external dram. - decode sequence 1. reads compressed data stored in external buffer ram at rate fs. 2. decoder starts, using the predicting filter type and quantization levels used when encoded. 3. outputs the result. - compare-connect sequence 1. encoding immediately stops when either external buffer ram overflows or when a cd read error occurs due to shock vibrations. 2. then, using microcontroller command 80h, the compare-connect start command is executed and compare-connect sequence starts. 3. compares data re-read from the cd with the pro- cessed final valid data stored in ram (confirms its correctness). 4. as soon as the comparison detects conforming data, compare-connect sequence stops and encode sequence re-starts, connecting the data directly behind previous valid data.
nippon precision circuits-21 SM5903BF 13.3ms vwa latch set waqv set vwa(x) vwa(x + 1) yblkck microcontroller data set refer to microcontroller interface vwa values shown are for rate fs. the values are 1/2 those shown at rate 2fs. fig 2. yblkck and vwa relationship the vwa is determined according to the yblkck pin and waqv command. refer to the timing chart below. 1.yblkck is a 75 hz clock(high for 136 s) when used for normal read mode and it is a 150 hz clock when used for double-speed read mode, synchro- nized to the cd format block end timing. when this clock goes low, wa which is the write address of internal encode sequence, is stored (see note 2). 2.the microcontroller checks the subcode and, if confirmed to be correct, generates a waqv com- mand (80h). 3.when the waqv command is received, the previ- ously latched wa is stored as the vwa. (note 2) actually, there is a small time difference, or gap, between the input data and yblkck. this gap serves to preserves the preceding wa to protect against incorrect operation. ram addresses the SM5903BF uses either 1 or 2 external 1m or 4m drams as external buffers. three kinds of addresses are used for external ram control. wa (write address) ra (read address) vwa (valid write address) among these, vwa is the write address for con- forming data whose validity has been confirmed. determination of the correctness of data read from the cd is delayed relative to the encode write pro- cessing, so vwa is always delayed relative to wa. the region available for valid data is the area between vwa-ra. - connect data work area this is an area of memory reserved for connect data. this area is 2k bits if using 1m drams, 4k bits if using 4m drams, or 8k bits if using 16m drams. fig 1. ram addresses ra wa vwa valid data area connect data work area vwa (valid write address)
nippon precision circuits-22 SM5903BF correct data demodulation becomes impossible for the cd signal processor ic when a disturbance exceeding the ram jitter margin occurs. the yflag signal input pin is used to indicate when such a condition has occurred. the yfclk is a 7.35 khz clock synchronized to the cd format frame 1. the ic checks the yflag input and stops the encode sequence when such a disturbance has occurred, and then makes flag6 active. the yflag check method used changes depend- ing on the yflgs flag and yfckp flag (85h com- mand). see table1. if yflags is set to 1, then yfclk should be tied either high or low. yflag, yfclk, flag6 85h command yflgs yfckp flag6 set conditions flag6 reset conditions 1 0 0 when yflag=low on yfclk input falling edge - by status read (90h command) 2 1 when yflag=low on yfclk input rising edge - when mson=low 3 1 0 when yflag=low yfclk be tied either high or low - after system reset 4 1 when yflag=high table 1. yflag signal check method
nippon precision circuits-23 SM5903BF compare-connect sequence the SM5903BF supports three kinds of connect modes; 3-pair compare-connect, 2-pair compare- connect and direct connect. note that the SM5903BF can also operate in 12-bit comparison connect mode using only the most sig- nificant 12 bits of data for connection operation. in 3-pair compare-connect mode, the final 6 valid data (3 pairs of left- and right-channel data input before encode processing) and the most recently input data are compared until three continuous data pairs all conform. at this point, the encode sequence is re-started and data is written to vwa. in 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to con- form with the valid data. at this point, the encode sequence is re-started and data is written to vwa. in direct-connect mode, comparison is not per- formed at all, and encode sequence starts and data is written to the vwa. this mode is for systems that cannot perform compare-connect operation. - compare-connect preparation time 1. comparison data preparation time internally, when the compare-connect start com- mand is issued, a sequence starts to restore the data for comparison. the time required for this preparation after receiving the command is approxi- mately 2.5 (1/fs). (approximately 60 s when fs = 44.1 khz) 2. after the above preparation is finished, data is input beginning from the left-channel data and com- parison starts. 3. if the compare-connect command is issued again, the preparation time above is not necessary and operation starts from step 2. 4. the same sequence takes place in direct-con- nect mode also. however, at the point when 3 words have been input, all data is directly connect- ed as if comparison and conformance had taken place. - compare-connect sequence stop if a compare-connect stop command (80h with msdcn1= 1, msdcn2= 0) is input from the micro- controller, compare-connect sequence stops. if compare-connect sequence was not operating, the compare-connect stop command performs no operation. however, make sure that the other bit settings within the same 80h command are valid.
nippon precision circuits-24 SM5903BF - dram initialization refresh a 15-cycle ras-only refresh is carried out for dram initialization under the following conditions. when mson changes from 0 to 1 using command 80h. when from mson=1, msrden=0 and mswren=0 states only mswren changes to 1. in this case, encode sequence immediately starts and initial data is written (at 2fs rate input) after a delay of 0.7ms. - refresh during shock-proof mode operation in this ic, a data access operation to any address also serves as a data refresh. accordingly, there are no specific refresh cycles other than the initial- ization refresh cycle (described above). this has the resulting effect of saving on dram power dissipation. a data access to dram can occur in an encode sequence write operation or in a decode sequence read operation. write sequence write operation stops during a connect operation whereas a read sequence read operation always continues while data is output to the d/a. the refresh rate for each dram during decode sequence is shown in the table below. the decode sequence, set by mson=1 and msr- den=1, operates when valid data is in dram (when msemp=0). - when mson=0, dram is not refreshed because no data is being accessed. although mson=1, dram is not refreshed if encod=0 and decod=0 (both encode and decode sequence are stopped). dram refresh table 2. decode sequence refresh rate drams used (same for 1 or 2 drams) data compression mode 1m (256k 4 bits) 4m (1m 4 bits) 16m(4m 4 bits) 4 bit 5.44 ms 10.88 ms 21.77ms 5 bit 4.35 ms 8.71 ms 17.42ms 6 bit 3.63 ms 7.26 ms 14.52ms full bit 1.36 ms 2.72 ms 5.81ms encode sequence temporary stop - when ram becomes full, mswren is set low using the 80h command and encode sequence stops. (for details of the stop conditions, refer to the description of the encod flag.) - then, if mswren is set high without issuing a compare-connect start command, the encode sequence re-starts. at this time, new input data is written not to vwa, but to wa. in this way, the data already written to the region between vwa and wa is not lost. - but if the mswren is set high (80h command) after using the compare-connect start command even only once, data is written to vwa. if data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued. after comparison and conformance are detected, no operation is performed because the encode sequence has already been started. however, make sure that the other bit settings within the same 80h command are valid.
nippon precision circuits-25 SM5903BF through-mode operation if mson is set low (80h command), an operating mode that does not perform shock-proof functions becomes active. in this case, input data is passed as-is (except force mute operation) to the output. external dram is not accessed. - in this case, input data needs to be at a rate fs and the input word clock must be synchronized to the clk input (384fs). however, short-range jitter can be tolerated (jitter-free system). - jitter-free system timing starts from the first ylrck rising edge after either (a) a reset (nre- set= 0) release by taking the reset input from low to high or (b) by taking mson from high to low. accordingly, to provide for the largest possi- ble jitter margin, it is necessary that the ylrck clock be at rate fs by the time jitter-free timing starts. the jitter margin is 0.2/ fs (80 clock cycles). this jitter margin is the allowable difference between the system clock (clk) divided by 384 (fs rate clock) and the ylrck input clock. if the timing difference exceeds the jitter margin, irregular operation like data being output twice or, conversely, incomplete data output may occur. in the worst case, a click noise may also be generat- ed. when switching from shock-proof mode to through mode, an output noise may be generated, and it is therefore recommended to use the ydmute set- ting to mute zsrdata until just before data output. force mute serial output data is muted by setting the ydmute pin input high or by setting the mute flag to 1. mute starts and finishes on the leading left-channel bit. when mson is high and valid data is empty (msemp=h), the output is automatically forced into the mute state. 12-bit comparison connection when the cmp12 flag is set to 1, the least signifi- cant 4 bits of the 16-bit comparison connection input data are discarded and comparison connec- tion is performed using the remaining 12 bits. note that if the cmp12 flag is set to 1 during a com- parison connection operation, only the most signifi- cant 12 bits are used for comparison connection from that point on.
nippon precision circuits-26 SM5903BF ylrck 16 lsb msb lsb msb r ch lsb ysck ysrdata l ch 1/(3fs ) 16 9 zlrck 1 33 48 lsb msb lsb msb r ch lsb 1/fs zsck zsrdata l ch 24 timing charts input timing (ysck, ysrdata, ylrck) output timing (zsck, zsrdata, zlrck)
nippon precision circuits-27 SM5903BF ncas a0 to a10 d0 to d3 (write) nras nwe t rash t rasl t t casl cash t cads t radh t t rads cadh t cwds t cwdh t wel t rdc ncas1 (dram1 select) a0 to a9 d0 to d3 (write) nras nwe ncas2 (dram2 select) t casl cash t rash t rasl t wel t cwdh t cwds t rads t radh t cads tt cadh t casl cash t rdc t rdc t dram write timing (nras, ncas, ncas2, nwe, a0 to a10, d0 to d3) write timing (with single dram) write timing (with double drams)
nippon precision circuits-28 SM5903BF ncas a0 to a10 nras d0 to d3 (read) nwe rasl t rash t cash t t casl rcd t rads tt radh cads t cadh t crds t crdh t oel t ncas1 (dram1 select) a0 to a9 nras d0 to d3 (read) nwe ncas2 (dram2 select) rash t rasl t rcd tt casl cash t rads t radh t cads t cadh t crds t crdh t rcd tt casl cash t dram read timing (nras, ncas, ncas2, nwe, a0 to a10, d0 to d3) read timing (with single dram) read timing (with double drams)
nippon precision circuits-29 SM5903BF micro- controller dsp matsushita mn662740 d/a converter sm5903 dram 1 dram 2 ymdata ymclk ymld zsense yblkck yflag yfclk ylrck ysck ysrdata zlrck zsck zsrdata uc1 to uc5 nras nwe a0 to a10 d0 to d3 ncas2 a0 to a9 d0 to d3 a0 to a10 d0 to d3 clk nreset ydmute ncas dsp sony cxd2517 sm5903 dram 1 dram 2 ymdata ymclk ymld zsense yblkck yfclk yflag ylrck ysck ysrdata nras nwe a0 to a10 d0 to d3 ncas2 a0 to a9 d0 to d3 a0 to a10 d0 to d3 clk nreset ydmute ncas scor xrof micro- controller ras we oe cas ras we oe cas ras we oe cas ras we oe cas uc1 to uc5 a d zsck zlrck zsrdata nras nwe a0 to a9 d0 to d3 nras nwe a0 to a9 d0 to d3 connection example note1 - when double drams are used, the dram oe pins should be tied low. - when single dram is used, the dram oe pin should be tied low or controlled by the SM5903BF noe signal. note 2 when cxd 2517 (sony) is used set 85h of microcontroller command (option setting) as setting yflag take in; d5: yflags= 1 d4: yfckp= 0
nippon precision circuits-30 SM5903BF vdd pins deleted functions from sm5902af microcontroller interface extensions microcomputer commands listed below are deleted from sm5902af. compression mode switching 1) dit function 2) digital attenuator function 3) soft mute function 4) noise shaper function during compress encoding 5) compression mode switching function during shock proof operation compression mode switching using 85 h command of SM5903BF can? be changed during shockproof operation. in order to switch compression mode, it is necessary to change it to ?hrough-mode?first and change the compression mode setting, then again set shock- proof mode ( detailed switching procedure is available ). attentions about SM5903BF, soft mute function and attenuation function are deleted. in order not to cause audio output noise, it is necessary to activate soft mute after da converter. pin no. sm5902af SM5903BF 7 pin dit (n.c) device comparison with sm5902af pin differences obsolete commands command bit name function 83h d4 ns noise shaper on/off switch d5 soft soft muting on/off switch d7 att attenuator on/off switch 84h d0 to d7 k0 to k7 attenuation level settings 86h d4 to d7 digital audio interface settings 87h d0 to d11 subcode q data settings 91h s3 qrdy q data write buffer status sml5902af has a built-in level shifter to use 5v darm during ic operation with 3v, therefore, it has 2 electrical power terminals. vdd 1 is an electrical power terminal used for internal ics and vdd 2 is an electrical power terminal used for external dram interface. regarding SM5903BF, vdd can? be set to other voltage due to the different process- ing. therefore, make sure to set vdd 1 and vdd 2 to the same voltage.
nippon precision circuits-31 SM5903BF nc9819be 2000.12 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsib ility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon p recision circuits inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modifica- tion. the products described in this data sheet are not intended to use for the apparatus which influence human lives due to th e failure or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, includ- ing compliance with export controls on the distribution or dissemination of the products. customers shall not export, directly or indirect- ly, any products without first obtaining required licenses and approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2 chome, koto-ku tokyo,135-8430, japan telephon: +81-3-3642-6661 facsimile: +81-3-3642-6698 http://www.npc.co.jp/ email: sales @ npc.co.jp nippon precision circuits inc.

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