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15 february 1999 zoran corporation n 3112 scott blvd. n santa clara, ca 95054 n +1 (408) 919-4111 n fax +1 (408) 919-4122 n www.zoran.com data sheet zr38601 programmable digital audio processor features n standard high performance functions in rom - dolby digital ac-3, 5.1 channel and 2 channel decoding up to 640 kbits per second - dolby pro logic encoding and decoding - mpeg1 and mpeg2 two channel decoding with mpeg2 pes stream parsing, pts decoding and scr handling n downloadable siliconsoftware functions - aureal a3d, dolby virtual surround, harman vmax - qsound qsurround, spatializer n-2-2, home thx - srs trusurround, music modes - bass management and multi-channel downmix n flexible input/output - serial and/or parallel data stream i/o - serial spi, serial z2c or 8-bit parallel host interface - 3 serial input data ports and 4 serial data output ports - formatted s/pdif receiver with up to 96 khz sample rate - sample rates: 32 khz, 44.1 khz, 48 khz or 96 khz - formatted s/pdif ac-3 and mpeg transmitter output n low system cost - host-less operation with no glue chips - separate internal plls for dsp core and audio i/o - no external ram required for 5.1 dolby ac-3/mpeg2 - wait-state generation for low-cost external memory - 100-pin plastic quad flat pack (pqfp) packaging - 3.3 v supply with 5 v compatible i/o for low power n software and hardware pc development environment - assembler/linker/simulator - on-chip ice support with direct pc connection - zr38600db demonstration board with 6 analog outputs, microphone and line inputs, and optional pc connection description the zoran zr38601 is a high performance programmable digital audio signal processor capable of real-time single-chip decoding of dolby digital ac-3 5.1-channel and mpeg2 digital surround algorithms. it is the fourth generation decoder made by zoran, being based on the proven zr38000, zr38500 and zr38600 architectures. hardware block floating-point makes it optimum for dolby ac-3 and complex digital audio signal processing applications. because of its programmable high performance and high level of integration, the zr38601 is unusually flexible in meeting a wide range of system requirements at the lowest possible system cost. at the low end it can provide standard fixed decoding func- tions with only a dac and an optical interface for the s/pdif input in addition to the oscillator crystal. at the high end it can provide eight channels of output, analog input, long-delay mem- ories, custom operating features and the ability to be upgraded with downloaded siliconsoftware product enhancements. yet all of this flexibility comes without design complexity. highly con- figurable standard functions with a simple command structure minimize software development, while a full set of development tools are available for the highly-custom product developer. the zr38601 is suitable for primarily audio applications such as audio/visual home theater receivers, digital audio broadcast (dab), 3-d audio, six-channel speaker systems and karaoke processors; primarily video applications like sdtv and hdtv stereo television receivers, digital cable and satellite tv set-top boxes; and multimedia applications with both audio and video like multimedia pcs and the digital video disk (dvd) players. dac right left right surround left surround s/pdif optical interface s/pdif input xtal zr38601 subwoofer center host processor (optional) spi or z2c serial interface encoded data input decoded audio outputs general purpose control i/o right center left center dac dac dac (optional) figure 1. a typical low-parts-count zr38601 system
2 zr38601 general description the zoran zr38601 is the latest digital audio processing member of the zr38000 high performance programmable digital signal processor product line. it is especially configured with peripherals, i/o capability and software for digital audio. today, quality digital audio starts with a primary decoding function and adds appropriate data stream protocols and inter- faces with i/o configurations to match the application. the zr38601 has these primary decode and protocol software func- tions and yet has processing cycles left for additional product- distinguishing features. the zr38601 also has the necessary flexibility in system i/o and hardware configuration. the zr38601 is pin and instruction-set compatible with the earlier zr38600, but with a higher 50-mips processing rate and larger internal program and data rams and rom. these give new 96-khz sample rate s/pdif decoding and increased pro- cessing cycles and memories for additional functions. new hardware features are a programmable timer, a z2c serial host interface and more support for the 24-bit i/o data formats. functions ac-3 and mpeg with variations are the primary decoding func- tions in use today. the zr38601 has these and their associated test function with the required set-up, operation and system functions to make them usable in an end-user product. in addi- tion, an ever increasing number of siliconsoftware functions can add special enhancing and differentiating features to products. primary decoding and test functions ac-3 the figure shows the simultaneous s/pdif input and 5.1 channel dac (digital-to-analog converter) outputs of this primary digital audio function, the six-channel ac-3 decoder. or with four channels of pro logic output in either of two dac forms: four channels directly or to an analog pro logic decoder. pcm + pro logic with two-channel pcm inputs the choice of functions is four- channel pro logic decoding or two-channel stereo mixing, including upmixing from only one input channel to two. mpeg the mpeg1 decoder accepts either mpeg1 or mpeg2 input streams and produces either pro logic dac outputs or two- channel stereo in dac form. pink noise a six-channel pink pseudo-random noise generator function is included for user testing of speaker balance in their listening space. individual speakers can be enabled in any combination. siliconsoftware functions siliconsoftware is a group of additional functions for the zr38601 provided by zoran or third-party suppliers that can add special features now or provide new functions in the future. 3-d audio currently there are six providers of 3-d audio which gives the effect of a three-dimensional sound field with only two speakers. these functions are aureal a3d, dolby virtual surround, harman vmax, qsound qsurround, spatializer n-2-2 and six-channel ac-3 decoder left right center subwoofer six-channel ac-3 stream left surround right surround s/pdif two-channel ac-3 decoder pro logic decoder left right center surround six- or two- channel ac-3 stream s/pdif lt (pro logic) rt (pro logic) s/pdif six- or two- channel ac-3 stream ac-3 decoder two-channel pcm input pro logic decoder left right center surround s/pdif left right s/pdif one- or two- channel pcm pcm mixer two-channel mpeg1 decoder pro logic decoder left right center surround two-channel mpeg1/mpeg2 stream s/pdif left right s/pdif two-channel mpeg1/mpeg2 stream mpeg1 decoder pink noise generator left right center subwoofer left surround right surround
3 zr38601 srs trusurround. they work with either two- or six-channel inputs and the ac-3 or mpeg decoders. bass management selected low-frequencies can be redirected to different speakers with bass management. useful with all types of decoding to compensate for the types of speakers used. dvd - linear pcm special provisions are included for data formats and synchroni- zation for ac-3/mpeg decoding with 3-d audio and bass management for digital video disk (dvd) applications. hall effects/music modes adds the natural acoustical effects of a performance environ- ment to the original recording environment. home thx5.1 theater thx for use in consumer home entertainment systems. karaoke processing voice cancellation, pitch-shifting and echo and reverberation. custom functions, etc. product designers can always add custom functions and varia- tions, often with very simple software additions. operation and set-up functions these control the simple start and stop operation of the decoding functions and determine the initial hardware operation and configuration. system functions these functions control the real-time operation including inter- face transactions, program loading and in-circuit testing. system configurations the zr38601 is highly self-contained and can work with few external parts as shown in figure 1. however it is very flexible in accommodating the needs of larger, higher performance systems. figure 2 shows all of the possible options that are sup- ported to make a complete system. hosts the zr38601 does not require a host microprocessor but if there is one in the system it may be used to advantage. either the bit-serial spi (small peripheral interface) or z2c interface, or a byte-wide parallel interface may be used. data input/output the encoded digital input data stream can use a bit-serial or byte-parallel interface or s/pdif receiver with the zr38601 either a master or slave. up to six-channels of analog signals can be input in bit-serial adc (analog-to-digital converter) formats in a master or slave mode. six-channel ac-3 decoder six-channel ac-3 stream left right 3-d audio two-channel ac-3/mpeg1 decoder pro logic decoder left right two-channel ac-3/mpeg1/ mpeg2 stream 3-d audio dac right left right surround left surround s/pdif input xtal zr38601 subwoofer center z2c or spi serial interface encoded data input decoded audio outputs general purpose i/o right center left center dac dac dac (optional) figure 2. zr38601 composite system block diagram s/pdif optical interface (optional) lt/rt byte-wide program rom (optional) data ram or rom (optional) host processor (optional) s/pdif optical interface (optional) host processor (optional) s/pdif input bit-serial input adc (optional) analog input parallel input parallel interface left right subwoofer center right surround left surround
4 zr38601 decoded audio outputs can be up to eight channels in bit-serial dac formats or six encoded channels from the s/pdif transmitter. memory external memory is not normally needed but can be added for program and/or digital audio data. additional program storage gives different or additional functions when a host is not used and allows a choice of rom technologies to be employed for future upgradability. external data memory may be required for functions with long acoustical delays, input buffering or large data tables. program memory interfaces are byte-wide to provide minimum cost and parts count. functional description a more complete description of the zr38601 software? opera- tion and configurations and its hardware configurations follows. software - operation one of the major benefits of the zr38601 is its ease of use for the system developer under a broad range of system require- ments. standard functions are easy to use, yet custom features can be added without falling back to custom software develop- ment with complicated real-time operating system considerations or detailed i/o protocols. this follows from the fact that all software functions are supplied with a common command and response sequence for use with a host or an api (application programming interface) for calling from an internal program. and each provides for adding custom functions in not just one but a series of ways which depend upon the complexity of the custom function. this is shown schematically in figure 3 where the operation, set-up, primary, and siliconsoftware functions are shown in the middle. using the system utilities to maintain the communica- tions with the host, the host can issue a sequence of commands with responses to control the zr38601? operation. the utilities issue api calls to the functions. all of the software development can be limited to the host microprocessor even when feature types of variations in operation are based on getting information back from the zr38601? operation. alternatively, the control information in the commands can be entered in a sequence of api calls issued from a custom program running internally on the zr38601 processor. now no host is required. with either a host command/response stream or api calls, custom functions in native zr38001 code can be added without losing the benefits of the ease of use in the common structure. table 1 is a summary of the commands and responses for the standard primary, operation and set-up functions. note there are read and write commands to the zr38601 and responses back from the zr38601 to the host. responses are due to commands during normal operations that are in progress or from certain specific commands with read commands following. set-up b operate b, etc. set-up a custom zr38601 control program host processor with control program function b function c, etc. function a primary decoding, test and siliconsoftware functions command stream play operation cfg set-up, etc. operation and set-up functions setio set-up stop operation apis operate a zr38601 resident control program host resident control program monitor system functions figure 3. zr38601 operation control: commands from a host or calls from a zr38601 resident program set-up a apis utilities system functions response stream response a
5 zr38601 table 1: standard function command and response summary class name description write command commands to zr38601 to perform a specific function primary decoding and test functions ac3 select ac-3 or ac-3 + pro logic decoder function pcmprol select pcm or pro logic decoder functions with pcm input and mixer function mpeg select mpeg or mpeg + pro logic decoder function png select pink noise generator function user select user defined function operation functions play resume selected function operation and unmute audio output mute mute audio output without stopping the selected operation unmute restore muted audio output while continuing the selected operation stop stop operation, retain data in input buffer and mute audio output stopf stop operation, flush the data in the input buffer and mute audio output stat return decoder status information using the read command spdifstat return the s/pdif input channel status getptc return the ptc and stc values for timing synchronization nop not a command, does not affect operation. will return a progress response. set-up functions plltab set the pll programmable registers pllcfg define the pll configuration cfg configure the zr38601 i/o to the specific system hardware setstc set the system time clock and video delay ver return 32-bit rom version number using the read command boot load and execute the n parameter words of bootstrap program spdifcs write the s/pdif output channel status param define parameters for special functions intrp interpret: load and execute four parameter words as a zr38001 instruction setio set, test and return general purpose single-bit i/o registers poke load n 32-bit words to the core processor ram at the given start address peek read n 32-bit words from core processor ram at the given start address read command commands to zr38601 to return reply words to the host read command to zr38601 to return a reply word after specific commands reply response data words returned to the host as the result of sending specific commands followed by read commands ac3statr status and information about the ac-3 stream pcmprolr status and information about the pcm or pro logic stream mpegstatr status and information about the mpeg stream pngstatr status and information about the png stream verr four byte version number of rom read by ver command setior two words of gpioc and gpio registers pllr two bits which indicate the pll lock status peekr n 32-bit words from core processor ram specified by peek command spdifstatr s/pdif input channel status getptcr ptc and stc values of 32 bits each progress response data words returned to host in the normal process of sending any command expect expected number of parameter words still to be received from host istatus interpreter status
6 zr38601 software - functions primary decoding and test functions ac-3 the major modes of operation of the dolby digital ac-3 decoder function are summarized in table 2. choices are for input and output ports and their formats including operation with audio/vid- eo synchronization (avs), constant or request driven pes packetized inputs and the linear pcm of dvd. ac-3 input decoding rates are up to 640 kbits per second. full selection can be made for speaker configuration, dynamic range compression, downmixing, delays, filtering and error conceal- ment strategy. the karaoke downmixing is also supported including with downloaded karaoke coefficients. pcm + pro logic with two-channel pcm inputs, the choice of functions is four- channel pro logic decoding or two-channel stereo mixing. selection can be made for speaker configuration, downmixing, delays and surround filtering. mpeg the mpeg1 decoder function accepts either mpeg1 or mpeg2 input streams and produces either pro logic or two-channel stereo outputs in dac form. selection can be made for speaker configuration, dynamic range compression, downmixing, delays and surround filtering. pink noise this is a six-channel pink (equal energy per constant proportion- al bandwidth) pseudo-random noise generator test function. it is for user testing of speaker balance in a listening space. the six individual speakers can be enabled in any combination at a single adjustable level, with or without a band-limiting filter. siliconsoftware functions 3-d audio there are six third-party providers of 3-d audio using the zr38601. this function gives the effect of a three-dimensional sound field with only two speakers. these certified functions are aureal a3d, dolby virtual surround, harman vmax, qsound qsurround, spatializer n-2-2 and srs trusurround. they work with either two- or six-channel inputs and the ac-3, mpeg and pro logic decoders as shown in table 3. bass management depending upon the speakers used in a listening area, it can be desirable to alter the distribution of the bass frequencies between speakers. a choice of speaker configurations is provided and of low-pass cut-off frequencies for 80, 100 or 120 hertz in the simplest form. the full function allows the low-pass and high-pass filter coefficients to be downloaded along with individual speaker sound levels. bass management works with either two- or six-channel inputs and the ac-3, mpeg and pro logic decoders. it does not work with 3-d audio although some 3-d audio functions include certain bass management features. dvd - linear pcm in addition to the audio/video synchronization (avs) and request driven pes packetized input features of the standard decode functions, this dvd function has 3-d audio capability and bass management. it works with two-, six- or eight-channel pcm inputs and the ac-3, mpeg and pro logic decoders. table 2: primary decoding and test function options summary primary decoding or test function input output data stream serial port a, s/pdif, parallel avs mpeg2 pes packetized dvd pes packetized function serial dac ports s/pdif port g ac3 6-channel ac-3 sa, s/p, p yes yes yes 6-channel ac-3 b,c,d input stream 2-channel pro logic encoded b 2-channel ac-3 sa, s/p, p yes yes yes 4-channel pro logic b,c,d 2-channel ac-3 b pcm + pro logic 2-channel pcm sa, s/p, p no no no 4-channel pro logic b,c,d input stream 2-channel pcm mixed b mpeg mpeg1 sa, s/p, p yes yes yes 4-channel pro logic b,c,d input stream 2-channel mpeg1 b mpeg2 sa, s/p, p yes yes yes 4-channel pro logic b,c,d 2-channel mpeg1 b png - - - - - 6-channel pink noise b,c,d -
7 zr38601 hall effects/music modes short and long term delays and reverberation are added to mul- tichannel pcm inputs with this function. delay coefficients are downloaded to simulate various acoustical environments (concert halls, churches, stadiums, etc.) home thx5.1 this function, when used in a two-chip set connected in cascade, provides the sound of the lucasfilm theater thx in the home listening environment. the input chips runs all of the standard decoding functions and passes its pcm outputs to the second chip for the thx5.1 processing which included full bass management, decorrelation, timbre matching and re-equaliza- tion and individually programmable channel delays. karaoke processing in addition to the karaoke input mixing features of the standard decode functions, this is true karaoke processing with voice cancellation, pitch shifting, voice echo and reverberation and bass management. external data memory may be required for this function. custom functions, etc. the user function allows developers to easily add custom func- tions using their own native zr38001 code, yet retain the ease of control of the command and response structure of the zr38601. operation and set-up functions the operation functions, summarized in table 1, are the real- time start and stop commands needed for system control once the primary decoding function has been selected. also included are commands to get the input channel and decoding status to monitor on-going operation. the ptc and stc time clocks can also be monitored to insure audio and video synchronization. the set-up functions configure both the hardware and software before operation starts or as major operational changes are made. hardware configuration and initialization includes the phase-locked loops (plls), system clocks and the input/output (i/o). software can be put in place through the host processor from its i/o or memory system. it may be in the form of custom commands and their parameters or directly executable native code for the core dsp processor. table 3: siliconsoftware function options summary siliconsoftware function input output serial port a, e or f, s/pdif, parallel standard function source function serial dac ports s/pdif port g 3-d audio: aureal a3d sa, s/p, p ac-3, ac-3 + pro logic, pcm + pro logic, mpeg, mpeg + pro logic 2-channel 3-d audio b input stream dolby virtual surround harman vmax qsound qsurround spatializer n-2-2 srs trusurround bass management sa, s/p, p all of the above redirect low frequencies to different speakers b, c, d input stream dvd sa, p all of the above + 8- channel pcm decoding, 3-d and bass management b, c, d, g input stream unless 8-ch. pcm hall effects/music modes sa, s/p, p pcm add room effects b, c, d input stream home thx5.1 decoding chip sa, s/p, p ac-3, ac-3+pro logic, pcm+pro logic, mpeg, mpeg + pro logic two chip set decodes and produces thx outputs b, c, d input stream thx processing chip sa, se, sf b, c, d - karaoke processing s/p & sf or sa & sf ac-3, pcm, mpeg voice cancellation, pitch shifting, echo and rever- beration and bass management. b, c, d input stream
8 zr38601 system functions the remaining portion of the standard zr38601 functions that reside in every program rom are the system functions, shown schematically in figure 4. monitor this is the simple real-time operating system mini-kernel used by all zr38601 functions in normal operation. utilities system utilities maintain operation of the various i/o interfaces that are shared between functions. these include the serial audio data ports, the serial spi or z2c host interface and the parallel host interface for commands and responses. the utili- ties also include the initial and reset bootstrap routine that determines the start-up rom and executes its initialization process. ice debug for in-circuit emulation debugging using the zr38000 family simulator, the monitor is used in a mode for single-step and breakpoint execution of programs. software - system configurations as a result of the zr38601? ability to be configured from a low- cost, fixed-function device to a very flexible, full capability audio processor, there are many choices as to how the software is configured which are related to the system hardware configura- tion. important considerations are if a host is used and if only standard commands are to be used. table 4 summarizes the most common configurations and their relative benefits. figure 4 illustrates possible sources and residences of the software for different hardware configurations. starting with the on-chip program rom, it can be either the standard version or with custom functions as shown. custom and siliconsoftware functions can be available for downloading into the on-chip program ram from three sources as indicated by the dashed arrows. if there is no host they must be loaded from the external byte-wide program rom. with a host it may be from the host? own non-volatile memory (rom or flash eprom typically) or through its i/o peripherals such as on-line links or movable memory media like floppy disks. hardware - system configurations all of the hardware shown in figure 2, the composite system block diagram on page 3, is supported in the zr38601. the choices for host, data input and output, and external memory are summarized in table 5. those that are supported by the standard functions with the standard commands are noted. indi- vidual siliconsoftware functions support additional configurations. for example, the karaoke processing supports the bit-serial adc data input and the external data ram required for pitch correction and voice reverberation. table 4: software con?urations configuration description benefits host operation using standard commands internal standard rom download program ram with siliconsoft- ware for additional current and future functions. moderate flexibility for current and future functions with only host s/w development. host operation using standard and custom commands and apis internal standard rom download program ram with siliconsoft- ware from host with current, future and custom functions. moderate customization and flexibility for current and future functions. moderate host overhead. internal standard rom + external custom rom download program ram with siliconsoft- ware from external rom for current and custom functions or from host for future functions. maximum customization with maximum flexibility for current and future functions. low host overhead except for future functions. internal custom rom download program ram with siliconsoft- ware from host for future functions. moderate customization with moderate flexibility for future functions. minimum cost and low host overhead except for future functions. stand alone (no host) operation using standard and custom functions with apis internal standard rom + external custom rom standard and custom functions with control through gpio port. low cost, maximum customization. broad choice of rom technologies for flexibility for future. internal custom rom standard and custom functions with control through gpio port. no future flexi- bility without internal rom non-recurring engineering (nre) cost. lowest recurring cost with maximum customization.
9 zr38601 hosts a host microprocessor is not required for the zr38601? opera- tion. a custom program, in either the internal rom or an external rom with the standard internal rom, is sufficient. control of the operation is then through the gpio (general purpose input/out- put) ports. however, the greatest flexibility is available if a host is used. the least costly in external hardware is a serial host interface. the four-wire spi (small peripheral interface) or two-wire z2c signals (see table 6) connect directly to most low-cost micro- controllers. there is no speed penalty with a host serial interface and it leaves the parallel interface free for use with external memories. the zr38601? parallel interface can be used for a byte-wide connection to a microprocessor host along with byte-wide i/o with the standard command support. the full 16-bits of the parallel interface can be used for an i/o connection if called in the developer? software. note that the parallel interface can not be used concurrently for the host and i/o while it is being used for external data or program memory. data input/output the primary data input is the single-wire digital audio interface receiver. this conforms fully to s/pdif, iec-958, aes/ebu and eiaj cp-340 consumer standards. all standard sampling rates are supported for raw or packetized bitstreams as well as the data driven master operation using the dreq signal on the gpio0 port. serial port a or the byte-wide parallel interface may alternately be used for the channel bitstream as master or slave. the parallel interface also provides data driven master opera- tion, but it can not be used concurrently with external memory in the system. up to six channels of bit-serial adc data can be input as master or slave in a wide variety of industry formats when required by siliconsoftware functions. up to eight channels of bit-serial dac data can be output as master or slave in the same variety of industry formats including i 2 s and eiaj with word, frame and frameless synchronization. ports b,c and d are used by standard 6-channel functions with port g in addition for 8-channel siliconsoftware functions. oth- erwise port g serves as a s/pdif master transmitter. external memory the 20 address and 16 data lines of the parallel port allow a wide choice of external memory for program and data storage if needed for siliconsoftware functions or for future flexibility. variable wait-states are supported for slower, lower cost memo- ries. not used concurrently with parallel host or i/o interfaces. hardware - digital audio processor the zr38601 is composed of the interfaces, memories and system clocks that surround the zr38001 dsp core shown in figure 5. the individual signals of each of the interfaces and power supply connection are summarized in table 6. the figure illustrates the sharing of the serial output port g with the s/pdif transmitter and the multiple functions of the parallel port for the external host, i/o and memories. note from table 6 how the un-used of the 16-bit memory data lines are utilized for additional control when the parallel byte-wide interface is employed for the external host and i/o. using standard functions, three of the six gpio signals are ded- icated as a mute input, an i/o data request output, dreq , and an i/o error output, error. figure 4. software memory configurations zr38601 byte-wide program rom host processor ram image program rom program ram program rom or flash eprom i/o dvd home thx bass management siliconsoftware 3-d audio or custom, etc. music modes ram image dvd home thx bass management siliconsoftware 3-d audio custom, etc. music modes ram image dvd home thx bass management siliconsoftware 3-d audio custom, etc. music modes standard rom set-up system operation standard functions pri. decode & test custom rom set-up system operation standard and custom functions decode & test
10 zr38601 internal memories are large: the 20-kwords of 32-bit pro- gram/data rom is augmented with an addition 2-kwords of down-loadable ram. the data only memory is a 10-kword ram in the 20-bit data word precision. the two programmable phase-locked-loops (plls), one for the dsp core (f dsp ) and one for the audio serial ports (f audio ) allow independent selection of these two critical internal clock rates. this is particularly important when the zr38601 system oscilla- tor is not determined by its own external crystal, but rather from a predetermined system clock frequency. having two plls lets the dsp core synchronously operate at its maximum 50 mips rate (f dsp = 100 mhz) for processing while the serial i/o operates at the standard sample rates of 32, 44.1, 48 or 96 khz, regardless of whether the predetermined system clock frequen- cy is a common sub-multiple. the power supply is 3.3 volts for lower power consumption, yet all i/o signals are 5.0 volt tolerant for use in 5.0-volt systems. table 5: system hardware con?urations and standard command support hardware configuration hardware configuration description standard command support host none custom program using parallel and/or gpio interface for control. none. requires custom internal or external program rom. bit-serial interface industry standard four-wire spi duplex or two-wire z2c half- duplex. yes. parallel interface byte-wide selectable for i/o and commands. not possible con- current with external memory. yes. data input s/pdif channel standard single-wire receiver. yes. bit-serial channel serial port a is a flexible slave or data driven master with dreq . yes. parallel channel byte-wide master, slave or data-driven master with dreq . not possible concurrent with external memory. yes. adc bit-serial up to six channels as a flexible master or slave. no. data output dac bit-serial up to eight channels on ports b, c, d and g as flexible master or slave. yes for 6-channel ports b, c and d. s/pdif channel standard single-wire transmitter on port g. master only. yes, port g. external memory program rom byte-wide or 16-bit-wide loading of internal 32-bit program ram. yes, byte-wide only. data ram and/or rom up to 16-bit wide memory for custom functions requiring large delay memory (ram) or parameter tables (rom). not required for standard functions. left/right left/right surround xtal center/subwoofer s/pdif input data/ control a e f address test control general purpose i/o ports host parallel port serial output ports serial input ports b c d figure 5. zr38601 simplified block diagram 4 16 20 serial host spi or z2c interface internal program/ data rom 20k x 32 internal program/ data ram 2k x 32 internal data ram 10k x 20 4 serial audio inputs s/pdif receiver parallel host interface input data fifo 8 x 9 s/pdif transmitter serial audio outputs memory interface ice interface system oscillator & dsp pll audio pll gpio zr38001 dsp core s/pdif or left/right center 4 f dsp f audio 6 f audio g timer
11 zr38601 table 6: zr38601 signal description summary name number type [1] description parallel port (40) a[19:0] 20 o address bus of parallel port d[19:15] 5 i/o data bus of parallel port when selected for external memory (p/m = 0) d14/rdy 1 i/o or o data bus (p/m = 0) or ready output signal of parallel port when selected for parallel i/o (p/m = 1) d13/ c/d 1 i/o or i data bus (p/m = 0) or command/data select input of parallel port when selected for parallel i/o (p/m = 1) d12/err 1 i/o or i data bus (p/m = 0) or error input signal of parallel port when selected for parallel i/o (p/m = 1) d[11:4]/pp[7:0] 8 i/o data bus of parallel port when selected for external memory (p/m = 0) or parallel port i/o (p/m = 1) cs 1 i/o chip select output for external memory or chip select input for parallel i/o rd 1 i/o read enable output for external memory or read enable input for parallel i/o wr 1 i/o write enable output for external memory or write enable input for parallel i/o p/m 1 i parallel i/o or memory select for parallel port. determined at time of reset . serial ports (13) spfrx 1 i s/pdif receiver input port sda, sde, sdf 3 i serial data inputs. ports a, e and f. wsa/fsa 1 i/o word select or frame synchronization for input ports. an output when a master, an input when a slave. scka 1 i/o serial clock for input ports. an output when a master, an input when a slave. sdb 1 o serial left and right data output. port b. also, at reset defines spi/z2c for host serial interface. sdc 1 o serial left and right surround data output. port c. also, at reset defines z2cadr[0] of z2c address. sdd 1 o serial center and sub-woofer data output. port d. also, at reset defines z2cadr[1] of z2c address. sdg/spftx 1 o serial data output. port g or s/pdif transmitter port. also, at reset defines the sckp value. wsb/fsb 1 i/o word select or frame synchronization for output ports. an output when a master, an input when a slave. sckb 1 i/o serial clock for output ports. an output when a master, an input when a slave. sckin 1 i/o serial master clock output or master clock input for output ports general purpose ports (6) mute /gpio5 1 i or i/o mute input signal or can be programmed as general purpose input/output 5 gpio[4:2] 3 i/o can be programmed as general purpose input/output 4, 3 and 2 error/gpio1 1 o or i/o error output signal or can be programmed as general purpose input/output 1 dreq /gpio0 1 o or i/o data request output signal or can be programmed as general purpose input/output 0 serial host interface (4) si 1 i host serial interface data input. also, at reset defines z2cadr[5] of z2c address. so/sda 1 i/o/t spi host serial interface data output or serial data for z2c sck/scl 1 i spi host serial interface clock input or slave clock input for z2c ss 1 i spi host serial interface slave select input. also, at reset defines z2cadr[4] of z2c address. ice interface (4) tdi 1 i ice test interface data input tdo 1 o/t ice test interface data output tck 1 i ice test interface clock input tms 1 i ice test interface mode select system interface (7) int 1 i external interrupt request input reset 1 i reset input to start operation in known state xti 1 i external system clock input or connection to external crystal, at frequency f xti xto 1 o output connection to external crystal clkout 1 o clock output from the zr38601 at frequency f dsp /2 bypass 1 i bypass internal dsp core pll to use external system clock input on xti fltcap 1 i external filter capacitor connection for pll. a value of 47nf is recommended. power (26) vdd 12 power +3.3 volt power supply vdda 1 power +3.3 volt power supply, analog for pll gnd 12 power power supply ground gnda 1 power power supply ground, analog for pll total (100) 1. o = output, i = input, t = tri-state in normal use. may be different at reset time as shown in table 23 on page 42.
12 zr38601 standard functions description the zr38601 standard functions are selected and controlled by the commands and responses shown in tables 7 and 8. these are the commands, parameters and responses sent and received by a microprocessor over the serial host interface or the parallel host interface when a parallel host is used. the applications program interfaces (apis) for the ac-3, pro logic, pink noise, etc. functions are similar. these apis are used by a developers program executing on the core processor. transfers between a host and the zr38601 with the spi are full- duplex with the host being the master. for every command sent a word is received back from the zr38601. transfers with the parallel host interface or the serial z2c interface are half-duplex with the host master. then the host must initiate the read for the response after each command is sent. the commands are sent only from the host and are in the general form shown. there are two classes of commands: those that write to the decoder and those that read back from the decoder. the write commands may have parameter words in addition to the basic operation code. the write commands are of three types as shown in table 7: those that choose primary decoding and test functions (e.g., ac3), those that govern operation (e.g., stop or play) and those that set-up operation (e.g., cfg). 0 1 2 3 4 5 6 7 operation code parameter word n parameter word 1 parameter word 2 table 7: standard function command summary (host to zr38601 transfers) class name operation code (hex) number of parameter words description write command commands to zr38601 to perform a specific function or operation primary decoding and test functions ac3 85 8 select ac-3 and pro logic decoder function, either six- or two-channel output pcmprol 86 8 select pcm or pro logic decoder functions with pcm input and mixer function mpeg 87 8 select mpeg or mpeg + pro logic decoder function png 83 8 select pink noise generator function user 88 8 select user defined function operation functions play 8a 0 resume selected function operation and unmute audio output mute 8b 0 mute audio output without stopping the selected operation unmute 89 0 restore muted audio output while continuing the selected operation stop 8c 0 stop operation, retain data in input buffer and mute audio output stopf 8d 0 stop operation, flush the data in the input buffer and mute audio output stat 8e 0 return decoder status information using the read command spdifstat 8f 0 return the s/pdif input channel status getptc 9a 0 return the ptc and stc values nop 80 0 not a command, does not affect operation. will return a progress response. set-up functions plltab 98 6 set the pll programmable registers pllcfg 99 1 define the pll configuration cfg 82 8 configure the zr38601 i/o to the specific system hardware setstc 97 7 set the system time clock and video delay ver 81 0 return 32-bit rom version number using the read command boot 90 n load and execute the n parameter words of bootstrap program spdifcs 95 4 write the s/pdif output channel status param 96 n define parameters for special functions intrp 91 4 interpret: load and execute four parameter words as a zr38001 instruction setio 92 4 set, test and return general purpose single-bit i/o registers poke 93 7+4n load n 32-bit words to the core processor ram at the given start address peek 94 7 read n 32-bit words from core processor ram at the given start address read command commands to zr38601 to return reply words to the host read 00 0 command to zr38601 to return a reply word after specific commands
13 zr38601 the words received back from the zr38601 when the host ini- tiates a transfer will be of the form: the responses are of two types, a reply to read commands following specific write commands or the progress responses to each write command. the progress response is always the number of still expected parameters (expect) and/or reads, followed by the response and interpreter status (istatus). all responses to commands sent on the spi are delayed by two words as shown in the example of the setio command which has both parameter words (para 1-4) and two reply data words (setior). note that the initial istatuses returned are a response to previous reads sent by the host. there are no delays on the parallel host interface or the serial z2c interface in the normal alternating single-byte transmit/receive protocol. the second example below shows the response to the ver command. the expect value tells the host how many bytes of information are returned by the command. see table 9 on page 23 for a summary of the sequence of com- mands, parameters, reads, responses and status. the following descriptions explain the zr38601? standard func- tions as well as the specifics of the commands used and their responses. they are in the same order as tables 7 and 8. 0 1 2 3 4 5 6 7 data word 0 data word 1 data word n-1 words sent from host 1 setio 2 para1 3 para2 4 para3 5 para4 6 read 7 read 8 read 9 read 10 read words sent from zr38601 istatus istatus 1 exp1=5 2 exp2=4 3 exp3=3 4 exp4=2 5 exp5=1 6 setior1 7 setior2 8 istatus time words sent from host 1 ver 2 read 3 read 4 read 5 read 6 read 7 read 8 read words sent from zr38601 time istatus istatus 1 expect=4 2 a1 3 20 4 10 5 02 6 istatus note that the descriptions on the following pages are meant to be inclusive of all functions that are currently available on the zr38601. some functions require that additional code be downloaded into program ram. likewise, note that command parameter tables are all inclusive. individual program and rom release documents should be consulted to determine the exact functionality for the rom version and program release that is being used. table 8: standard function response summary (zr38601 to host transfers) class name response operation code (hex) number of data words description reply response data words returned to the host as the result of sending specific commands followed by read commands primary decoding and test functions ac3statr 05 16 status and information about the ac-3 stream pcmprolr 04/06 8 status and information about the pcm or pro logic stream mpegstatr 07 12 status and information about the mpeg stream pngstatr 03 8 status and information about the png stream set-up functions verr - 4 four byte version number of rom read by ver command setior - 2 two words of gpioc and gpio registers pllr - 1 two bits which indicate the pll lock status after a pllcfg command peekr - 4n n 32-bit words from core processor ram specified by peek command operation functions spdifstatr - 4 s/pdif input channel status getptcr - 8 ptc and stc values of 32 bits each progress response data words returned to host in the normal process of sending any command expect - 1 expected number of parameter words still to be received from host istatus - 1 interpreter status
14 zr38601 function commands ac-3 decoder + pro logic function ac3 the ac-3 decoder function includes normal six-channel ac-3 and the two-channel ac-3 with pro logic output. selection is made in the command for speaker configuration, dynamic range compression, downmixing, delays and error concealment strategy. pcm + pro logic decoder function pcmprol the pcm or pro logic decoder function decodes two-channel pcm into four-channel pro logic output or transfers to two- channel pcm output. selection is made in the command for speaker configuration, scale factor, mixing and delay. the parameter descriptions are the same as for the ac3 command except for ocfg and with the addition of de. prlg pro logic output: 0 = off, 1 = on, 2 = selected auto- matically based on input stream information. sif serial input format : 0 = non-formatted, 1 = ac-3 s/pdif protocol. comp compression and dialog normalization: 0 = custom mode 0, 1 = custom mode 1, 2 = line mode (dialog nor- malization plus high level compression), 3 = rf modulation mode (peak level compression). dmm dual mono mode output selection when the two input channels are unrelated: 0 = stereo, 1 = mono channel 0 to both, 2 = mono channel 1 to both, 3 = mono channels 0 and 1 summed and scaled to both. sf surround filter for pro logic: 0 = filter enabled, 1 = filter (lp+nr) disabled. ab auto-balance for pro logic output: 0 = on, 1 = off. bcfg bass redirection configuration : 0 = no redirection, 1 = redirect left, center, right to subwoofer for pro-logic. all channels to subwoofer for ac-3, 2 = redirect center to subwoofer for pro-logic. center, left surround and right surround to subwoofer for ac-3, 3 = reserved. sw subwoofer output channel: 0 = off, 1 = on. ocfg output speaker configuration of front/surround number of speakers (for pro logic only ocfg 3-7 can be used): 0 = 2/0 surround compatible, 1 = 1/0, 2 = 2/0 normal, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. in 2/0 configurations, a mono input is directed to both output channels. cdly center delay in one millisecond steps from zero to five. srdly surround delay: 0-15 = 0-15 ms for ac-3,15-30 ms for pro logic in one millisecond steps beyond 15 ms. 16 = zero delay for 3-d sound. 0 1 2 3 4 5 6 7 1 0 1 0 0 0 0 1 dmm comp 0 sif prlg ocfg sw bcfg ab sf srdly cdly hdynrng ldynrng dsn pcmsfh rpc pcmsfl 0 kar parameter 4 parameter 5 parameter 6 parameter 7 parameter 8 parameter 3 parameter 1 parameter 2 command hdynrng high dynamic range scale factor controlling the depth of high-level compression. a two? complement fraction between 0.00 and 0.fe where 00 is no high-level com- pression and 7f is full compression. ldynrng low dynamic range scale factor controlling the depth of low-level compression. a two? complement fraction between 0.00 and 0.fe where 00 is no low-level com- pression and 7f is full compression. dsn data stream number for s/pdif input. selects which stream to decode. range 0 -7. normally zero. kar karaoke mode: 0 = disabled, 1 = enabled. rpc repeat count before muting. maximum number of consecutive block repeats before muting output. pcmsfh pcm scale factor high . output scale factor, 16-bit two? complement fraction between 0.0000 and 0. fffe. the high byte. 0000 equals zero, 7fff equals gain of one. pcmsfl pcm scale factor low . output scale factor low byte. de de-emphasis filter: 0 = filter is disabled, 1 = filter is enabled, 2 = filter is enabled if pre-emphasis is defined in the channel status of the s/pdif input stream. ocfg output speaker configuration of front/surround number of speakers (for pro logic only ocfg 3-7 can be used): 0-2 = pcm, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. 0 1 2 3 4 5 6 7 0 1 1 0 0 0 0 1 dmm de 0 ocfg sw bcfg ab sf srdly cdly 0 0 pcmsfh pcmsfl 0 parameter 4 parameter 5 parameter 6 parameter 7 parameter 8 parameter 3 parameter 1 parameter 2 command
15 zr38601 mpeg decoder function mpeg the mpeg function decodes mpeg1 or mpeg2 data streams into two-channel pcm output. the selection of mpeg1 or 2 is made automatically from the input stream. all parameters are the same as for the ac3 command except the following. pink noise generator function png the pink noise generator function produces pseudo-random noise sequence outputs. selection is made for output channel and scale factor. the parameter descriptions are the same as for ac-3 with the addition of the filter and output channels. user function user the user function passes eight bytes of parameters to a user programmed function that has been downloaded. bcfg bass redirection configuration: 0 = no redirection, 1 = redirect left and right to subwoofer, 2 & 3 = reserved. prlg pro logic output: 0 = off, 1 = on, 2 & 3 = reserved. de de-emphasis filter: 0 =filter is disabled, 1 =filter is enabled, 2 = filter is enabled if pre-emphasis is defined in the mpeg stream. ocfg output speaker configuration. number of front/sur- round speakers. valid configurations for mpeg only is 2/0 and mpeg + pro logic are ocfg = 3-7. 0 & 1 = reserved, 2 = 2/0 normal, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. in 2/0 configurations, a mono input is directed to both output channels. 0 1 2 3 4 5 6 7 1 1 1 0 0 0 0 1 dmm de 0 sif prlg ocfg sw bcfg ab sf srdly cdly 0 0 pcmsfl pcmsfh dsn 0 0 0 parameter 4 parameter 5 parameter 6 parameter 7 parameter 8 parameter 3 parameter 1 parameter 2 command bf bandpass filter . 0 = on, 1 = off. l left channel output. 0 = off, 1 = on. c center channel output. 0 = off, 1 = on. r right channel output. 0 = off, 1 = on. ls left surround channel output. 0 = off, 1 = on. rs right surround channel output. 0 = off, 1 = on. sw subwoofer channel output. 0 = off, 1 = on. 0 1 2 3 4 5 6 7 1 1 0 0 0 0 0 1 0 sw rs ls r c l bf 0 0 pcmsfh pcmsfl parameter 7 parameter 8 parameters 3-6 parameter 1 parameter 2 command 0 1 2 3 4 5 6 7 0 0 0 1 0 0 0 1 command parameter 8 parameter 1 parameter word 1 parameter word 8
16 zr38601 operation commands resume operation play the play command resumes operation of the selected function and unmutes the output after a stop or stopf command. mute operation mute the mute command mutes the output without stopping the operation of the selected function. unmute operation unmute the unmute command restores the muted output while con- tinuing the operation of the selected function. stop operation stop the stop command stops operation of the selected function if the input is request driven and it mutes the output. data in the input buffer is preserved but new data is ignored. stop operation and flush stopf the stopf command stops operation of the selected function if the input is request driven and it mutes the output. data in the input buffer is flushed out and new data is ignored. return status information stat during operation, the stat command allows the n words of decoder status information to be returned to the host by sending n read commands. return s/pdif status information spdifstat the spdifstat command allows the s/pdif receiver channel status information and sprxstt register value to be returned to the host by sending four read commands. return ptc information getptc the getptc command allows the ptc and stc (presentation and system time clock) values be returned to the host by sending eight read commands. no operation nop a nop is not a command and does not affect operation except to cause the zr38601 to return a response word to the host. set-up commands pll table plltab the plltab command sets the pll programmable registers. the audio clock frequency is: where in master mode, the audio clock generates the serial port clocks, including the s/pdif transmitter clock. the dsp clock is: where 0 1 2 3 4 5 6 7 0 1 0 1 0 0 0 1 command 0 1 2 3 4 5 6 7 1 1 0 1 0 0 0 1 command 0 1 2 3 4 5 6 7 1 0 0 1 0 0 0 1 command 0 1 2 3 4 5 6 7 0 0 1 1 0 0 0 1 command 0 1 2 3 4 5 6 7 1 0 1 1 0 0 0 1 command 0 1 2 3 4 5 6 7 0 1 1 1 0 0 0 1 command 0 1 2 3 4 5 6 7 1 1 1 1 0 0 0 1 command 0 1 2 3 4 5 6 7 0 1 0 0 1 0 0 1 command 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 1 command 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 audd [7:0] audm [7:0] dspm dspd 0 audd [12:8] 0 audm [12:8] 0 parameter 4 parameter 5 parameter 6 parameter 3 parameter 1 parameter 2 command f aud io f xti audm audd ------------------ - = audd f xti 10 khz ------------------ < f dsp f xti dspm dspd ------------------ = dspd f xti 1mhz ---------------- - <
17 zr38601 for example, if f xti = 24.576 mhz and f audio is 256x a sample rate of 48 khz, then audm = 1 and audd = 2. for the fastest processor operation if f xti = 24.576 mhz, then f dsp = 99.84 mhz if dspm = 65 and dspd = 16. see the section operation with commands on page 24 for a more complete description of these settings. pll con?uration pllcfg the pllcfg command defines the pll programmable config- uration. it returns the current status of the pll lock (pllr). pllcfg must be given before a cfg command. the next serial host command must be delayed by at least 2000 dsp instruction cycles (40 microseconds at 50 mhz) following a change of f1- f3, as, or ds fields. set con?uration cfg the cfg setup command determines the input, output and external memory configurations for the zr38601. audm audio pll multiplier: 13-bit number audd audio pll divider: 13-bit number dspm dsp pll multiplier: 8-bit number dspd dsp pll divider: 6-bit number sr sampling rate of output: 0 = 48 khz, 1 = 44.1 khz, 2 = 32 khz, 3 = 96 khz. f1 determines input clock source for audio pll: 0 = internal oscil- lator or xti input, 1 = s/pdif mode using spfrx. f2 determines audio clock f audio source: 0 = audio pll, 1 = internal oscillator or xti input at f xti . f3 determines master clock output frequency f sckin : 0 = audio clock frequency f audio , 1 = one-half audio clock frequency (f audio /2). as audio pll set : 0 = no action, 1 = resets audio pll. ds dsp pll set : 0 = no action, 1 = resets dsp core pll parameter 1 0 1 2 3 4 5 6 7 1 0 0 1 1 0 0 1 command ds as f2 f1 f3 sr 0 1 2 3 4 5 6 7 0 1 0 0 0 0 0 1 wait 0 0 0 0 wfb wfa 0 0 ma mb cb dvd 0 pes fra frb cpa cpb osp isp 0 0 epe mpe 0 drq pdi outw inw spo avs sen spas spbs fma fmb 0 parameter 4 parameter 5 parameter 6 parameter 7 parameter 8 parameter 3 parameter 1 parameter 2 command wfa word/frame synchronization for inputs: 0 = frame, 1 = word. wfb word/frame synchronization for outputs: 0 = frame, 1 = word. wait wait-state cycles for external memory: 0 = none, 1 = one, 2 = three, 3 = seven. pes pes packetized input: 0 = disabled, 1 = enabled. dvd dvd mode: 0 = disabled, 1 = enabled. cb clock source for outputs: 0 = sckin input pin, 1 = internal, using the spbs scaler with the audio pll or system clock. mb master mode for output clocking: 0 = slave, 1 = master. ma master mode for input clocking: 0 = slave, 1 = master. cpb serial clock b polarity : 0 = negative, 1 = positive. cpa serial clock a polarity : 0 = negative, 1 = positive. frb frame size (bits) for outputs: 0 = 16, 1 = 32, 2 = 64, 3 = 128, 4 = 192, 5 = 256, 6 = 193, 7 = 24. normal value = 1. fra frame size (bits) for input: 0 = 16, 1 = 32, 2 = 64, 3 = 128, 4 = 192, 5 = 256, 6 = 193, 7 = 24. normal value = 1. drq data request output pin dreq (gpio0): 0 = disabled, 1 = enabled. mpe mute pin enable : 0 = mute determined by host command, 1 = mute determined by mute (gpio5) input pin. epe error pin enable for error output pin (gpio1): 0 = dis- abled, 1 = enabled. isp input word select polarity : 0 = left is ws low, 1 = left is ws high. osp output word select polarity : 0 = left is ws low, 1 = left is ws high. sen s/pdif input selection: 0 = input from sra register, 1 = input from s/pdif receiver sprxdat register. avs audio/video synchronization : 0 = disabled, 1 = enabled. spo s/pdif output : 0 = disabled, 1 = enabled. inw input word : 0 = 20 bits, 1 = 18 bits, 2 = 16 bits, 3 = 24 bits. outw output word : 0 = 20 bits, 1 = 18 bits, 2 = 16 bits, 3 = 24 bits. pdi parallel data interface for data input stream: 0 = serial, 1 = parallel. spas group a internal clock divider. spbs group b internal clock divider. fmb format of serial ports group b: 0-5 = delay bits, 6 = tdm mode, 7 = right justified mode (maximum delay is 64). fma format of serial ports group a: 0-5 = delay bits, 6 = tdm mode, 7 = right justified mode (maximum delay is 64).
18 zr38601 set stc setstc the setstc command sets the system time clock and video delay for a/v synchronization. return version number ver the ver command allows the four words of the rom version number (verr) to be returned to the host by sending four read commands. load program boot the boot command allows serial loading and running of a program from the host. (the format is given in appendix a of the processor functional description and includes the start address, number of words and instructions). execution transfers to the start address with no further action by the rom resident executive. s/pdif channel status spdifcs this command defines the output status information for the s/pdif transmitter. it must be sent before the function command is sent. the spo bit in the cfg command enables the s/pdif transmitter. special function parameter param this command defines parameters for special functions that require more then 8 bytes of information. the specific meaning and value of the command parameters are determined by the function that is using it. any number of parameters can be spec- ified depending on the function. each parameter contains three bytes which are stored as a single 24-bit word to memory (par 12 is the most significant byte). if the destination memory is 20 bits the four most significant bits of par i2 are ignored. avs audio/video synchronization : 0 = passive synchroniza- tion, 1 = active synchronization. scu system clock update: 0 = when su flag is set, 1 = immediately. stc system time clock: a 32-bit number in units of 90 khz. vdy video delay : a 16-bit two?-complement number in units of 90 khz. 0 1 2 3 4 5 6 7 1 1 1 0 1 0 0 1 0 0 avs scu stc [31:24] stc [23:16] stc [15:8] stc [7:0] vdy [15:8] vdy [7:0] parameter 4 parameter 5 parameter 6 parameter 7 parameter 3 parameter 1 parameter 2 command 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 1 command parameter 1 0 1 2 3 4 5 6 7 0 0 0 0 1 0 0 1 command program word 0 program word n-1 parameter n sr sample rate of output: 0 = 44.1 khz, 2 = 48 khz, 3 = 32 khz. all other values reserved. cc category code . the bit order in this parameter is reversed, i.e. bit 0 of iec-958 category code is the right- most bit. pe pre-emphasis when p = 0: 0 = none, 1 = 50/15 ?. c copyright indication. p pcm : 0 = pcm encoded audio, 1 = non-pcm encoded audio. ext opcode extension: 0-255 identification number. par ij parameter number: i = 1 through n parameter number, j = 2 through 0 byte index. 0 1 2 3 4 5 6 7 1 0 1 0 1 0 0 1 sr 0 cc [7:0] 0 p c pe 0 0 parameter 4 parameter 3 parameter 1 parameter 2 command 0 1 2 3 4 5 6 7 0 1 1 0 1 0 0 1 ext par 12 par 10 par 22 par 11 par 21 .... .... parameter 4 parameter 5 parameter 0 parameter 3 parameter 1 parameter 2 command
19 zr38601 interpret instruction intrp the intrp set-up command allows loading and running of a single zr38601 core processor instruction from the host. after the single execution, control transfers to the rom resident exec- utive with further commands possible from the host. set and return i/o registers setio the setio set-up command allows changing and reading the six single-bits of the general purpose i/o registers gpio and gpioc. for the bits set in the gpio mask field, the correspond- ing bits in the gpio register will be updated to the values set in the gpio field. the same is true for the gpioc mask field and gpioc register and field. the setior response returns the state of the two registers after the setio command. load memory data poke the poke set-up command allows serial loading of data and program from the host to the zr38601 memory. n 32-bit words are loaded at a 20-bit start address where bits [23:20] are ignored. after the loading, control transfers to the rom resident executive with further commands possible from the host. return memory data peek the peek command allows serial reading of data and program from the zr38601 memory to the host. n 32-bit words are read from a 20-bit start address where bits [23:20] are ignored and where n is a 20-bit number. 4n read commands must be sent from the host to transfer all peekr reply data. after reading, control transfers to the rom resident executive with other commands possible from the host. read command read read the read command returns a single reply word to the host after the stat, ver, setio, pllcfg, peek, getptc, nop or spdifstat commands have been issued. one or more read commands must be issued after the above commands. gpioc mask a set bit i of this gpioc mask field enables updating the bit i of the gpioc register. gpioc the value of bit i in the gpioc register is updated to the value of bit i in this gpioc field if bit i in the gpioc mask field is set. gpioc[ i ] = 0 for an input, gpioc[ i ] = 1 for an output. gpio mask a set bit i of this gpio mask field enables updating the bit i of the gpio register. gpio the value of bit i in the gpio register is updated to the value of bit i in this gpio field if bit i in the gpio mask field is set. parameter 4 parameter 3 parameter 1 parameter 2 0 1 2 3 4 5 6 7 1 0 0 0 1 0 0 1 command instruction [31:24] instruction [23:16] instruction [15:8] instruction [7:0] parameter 4 parameter 3 parameter 1 parameter 2 0 1 2 3 4 5 6 7 0 1 0 0 1 0 0 1 command gpioc mask 0 gpioc 0 gpio mask 0 gpio 0 parameter 7+4n parameter 8 parameters 1-3 parameters 4-7 0 1 2 3 4 5 6 7 1 1 0 0 1 0 0 1 command start address [23:0] number of words (n) [31:0] data word 0 [31:24] data word n-1 [7:0] 0 1 2 3 4 5 6 7 0 0 1 0 1 0 0 1 start address [23:16] number of words (n) [31:24] start address [7:0] start address [15:8] number of words (n) [23:16] number of words (n) [15:8] number of words (n) [7:0] parameter 4 parameter 5 parameter 6 parameter 7 parameter 3 parameter 1 parameter 2 command 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 command
20 zr38601 reply responses the first word returned is always expect, the number of expected status words, followed by the status words followed by the interpreter status istatus. ac3 status reply ac3statr this reply is a response to the stat command during the ac3 function operation. pcmprol status reply pcmprolr this reply is a response to the stat command during the pcm or pro logic function operation. the status fields are the same as for ac3statr except: status global status of operation in progress: 0 = no errors, 1 = updated status information is not yet available (a new command has been received and is being processed), 2 = operation error (see status word 2 for details). rst run status: 0 = running, 1 = stopped, 2 & 3 = reserved. ac3dst ac-3 decode status returned by routine: 0 = no errors, 1 = input status nonzero, last output block was repeat- ed, 2 = input status nonzero, outputs were muted, 3 = unsupported bitstream identification revision, 4 = unsupported number of channels in input stream, 5 = unsupported number of input streams. ac3ist ac-3 frame information status returned by routine: 0 = no errors, 1 = invalid frame sync, 2 = invalid sample rate, 3 = invalid data rate, 4-6 = reserved, 7 = input underflow. dift[15:0] difference time. signed difference between ptc and stc in units of the 90-khz clock. for packetized inputs. sr sample rate: 0 = 48 khz, 1 = 44.1 khz, 2 = 32 khz. idr input data rate in kbits per second: 0 = 32, 1 = 40, 2 = 48, 3 = 56, 4 = 64, 5 = 80, 6 = 96, 7 = 112, 8 = 128, 9 = 160, 10 = 192, 11 = 224, 12 = 256, 13 = 320, 14 = 384, 15 = 448, 16 = 512, 17 = 576, 18 = 640. 0 1 2 3 4 5 6 7 status word 16 status word 1 status word 6 status word 7 status word 8 status word 9 status word 4 status word 2 status word 3 status word 5 status word 10 status word 11 status word 12 status word 13 status word 14 status word 15 05 status rst ac3ist ac3dst 0 0 dift [15:8] dift [7:0] sr ew idr 0 ccfg ef bsm bsid or c ds sm cm dn2 0 dn 0 lc lc2 ml p rt ml2 p2 rt2 ew extra word packed: 0 = no, 1 = yes for 44.1 khz sample rate only. ef effects channel for low frequency: 0 = no, 1 = yes. ccfg coding configuration : 0 = dual mono mode, 1 = 1/0, 2 = 2/0, 3 = 3/0, 4 = 2/1, 5 = 3/1, 6 = 2/2, 7 = 3/2. bsid bit-stream identification number of five bits. bsm bit-stream mode : 0 = main audio service, 1 = main audio service minus dialog, 2 = associated service; visually impaired, 3 = associated service; hearing impaired, 4 = associated service; dialog, 5 = associated service; commentary, 6 = associated service; emergen- cy flash. cm center mix level: 0 = -3 db, 1 = -4.5 db, 2 = -6 db. sm surround mix level: 0 = -3 db, 1 = -6 db, 2 = none. ds dolby surround mode: 0 = no indication, 1 = not dolby surround encoded, 2 = dolby surround encoded. c copyright: 0 = not copyright protected, 1 = copyright protected. or original: 0 = copy of an original bit-stream, 1 = original bit-stream. dn2 dialog normalization for channel 2 in dual mono. dn dialog normalization value for normal operation. lc2 language code for channel 2 in dual mono. lc language code for normal operation. p2 production information for channel 2 in dual mono operation. 0 = does not exist, 1 = does exist. rt2 room type for channel 2 in dual mono operation. 0 = not indicated, 1 = large, 2 = small. ml2 mix level for channel 2 in dual mono operation. p production information in normal operation: 0 = does not exist, 1 = does exist. rt room type in normal operation: 0 = not indicated, 1 = large, 2 = small. ml mix level value in normal operation. version version number of the pcmprol function. 0 1 2 3 4 5 6 7 status word 1 status word 8 status words 3-6 status word 2 status word 7 04/06 status rst 0 0 version 0
21 zr38601 mpeg status reply mpegstatr this reply is a response to the stat command during the mpeg function operation. png status reply pngstatr this reply is a response to the stat command during operation of the png function. version number reply verr the verr reply is a response to the ver command. it is four data words of the version number of the rom resident executive transferred by using four read commands. set i/o register reply setior the setior reply is a response to the setio command. it is two data words with the most recent contents of the gpio and gpioc registers. pllcfg reply pllr the pllr reply is a response to a read following the pllcfg command. returns one byte indicating the status of pll locking. data memory reply peekr the peekr reply is a response to the peek command. it is n data words with the contents of the specified zr38601 memory locations that is transferred by 4n read commands. mpgst mpeg-1 decode status returned by routine: 0 = no errors, 1 = invalid frame sync, 2 = crc error, 3 = invalid sample rate, 4 = invalid data rate, 5 = input underflow. id algorithm id : 0 = reserved, 1 = mpeg. lay layer type: 0 = reserved, 1 = layer iii, 2 = layer ii, 3 = layer i. prt protection bit: 0 = crc word present, 1 = no crc word. br bit-rate index (see iso-mpeg document cd 11172-3, part 3). sfr sampling frequency : 0 = 44.1 khz, 1 = 48 khz, 2 = 32 khz. pad padding bit. prv private bit. mode encoding mode: 0 = stereo, 1 = joint-stereo, 2 = dual channel, 3 = single channel. mext mode extension (see iso-mpeg document). cpr copyright : 0 = none, 1 = copyrighted. org original /home: 0 = copy, 1 = original. emph emphasis : 0 = none, 1 = 50/15 ?, 2 = reserved, 3 = ccitt j.17. version version number of the pink noise functions. 0 1 2 3 4 5 6 7 status word 1 status word 6 status word 7 status word 8 status word 9 status word 4 status word 2 status word 3 status word 5 status words 10-12 07 status rst mpgst 0 0 0 dift [15:8] dift [7:0] 0 prt id lay br pvr sfr pad emph org crp mext mode 0 0 1 2 3 4 5 6 7 status word 1 status word 8 status words 3-6 status word 2 status word 7 03 status rst 0 0 version 0 pa pll for audio : 0 = not locked, 1 = locked. pd pll for dsp core: 0 = not locked, 1 = locked. 0 1 2 3 4 5 6 7 rom version number [31:24] rom version number [23:16] rom version number [15:8] rom version number [7:0] data word 0 data word 2 data word 3 data word 1 0 1 2 3 4 5 6 7 status word 1 status word 2 gpioc register 0 0 gpio register 0 1 2 3 4 5 6 7 pd 0 pa status word 1 0 1 2 3 4 5 6 7 memory data word 0 [31:24] memory data word n-1 [7:0] data word 0 data word n-1
22 zr38601 s/pdif status reply spdifstatr the spdifstatr reply provides the following s/pdif receiver status information in response to the spdifstat command: getptc reply getptcr the getptcr reply is a response to eight read commands following the getptc command. progress responses expected parameters response expect expect is a progress response to any command sent from the host. it is one data word returned to the host with the number of parameter words still expected by the zr38601 at the time it was sent, or the number of words still to be returned by a reply response. it is not sent when the expected number is zero. interpreter status response istatus the last word returned by the device after receiving a host command is a status word. the istatus field flags any errors detected during decoding and interpretation of the host command. note that the host commands are executed only after all param- eters have been received and correctly decoded. therefore the status word does not show the outcome of the command execu- tion, but only the result of command interpretation. if the host issues a new command before the previous one has been executed the device ignores the new command and returns istatus = 83. the host command stat can be used to get information on the current execution status of a function. sr sample rate of input: 0 = 44.1 khz, 2 = 48 khz or 96 khz, 3 = 32 khz. all other values reserved. cc category code . the bit order in this parameter is bit- reversed from the standard iec-958 category code where bit 0 is the left-most. here bit 0 is the right-most bit. pe pre-emphasis when p = 0: 0 = none, 1 = 50/15 ?. c copyright indication. p pcm : 0 = pcm encoded audio, 1 = non-pcm encoded. sprxstt s/pdif receiver status. seven bits indicating l/r channel, loss of synchronization, beginning of a new block and errors for preamble, parity, biphase and invalid input. ptc presentation time clock. least significant 32 bits in units of 90 khz. most significant byte first. stc system time clock. least significant 32 bits in units of 90 khz. most significant byte first. 0 1 2 3 4 5 6 7 status word 1 status word 3 status word 4 status word 2 sr 0 cc [7:0] 0 p c pe 0 sprxstt [7:0] 0 1 2 3 4 5 6 7 status words 1-4 status words 5-8 ptc [31:0] stc [31:0] istatus interpreter status (hex): 80 = no errors, 81 = invalid opcode, 82 = invalid parameters, 83 = not ready to accept new commands, 84 = command overflow, 85 = ready to accept new commands. 0 1 2 3 4 5 6 7 status word 1 number of expected parameter words 0 1 2 3 4 5 6 7 status word 1 istatus
23 zr38601 table 9: sequence of commands and responses summary class command - a single word number of parameter words p number of read words r response to command + p+ r response to stat command + (s + 1) reads number of status words s command description function ac3 8 - 8 expect + istatus expect + ac3statr + istatus 16 ac-3 and pro logic decoder pcmprol 8 - 8 expect + istatus expect + pcmprolr + istatus 8 pcm or pro logic decoder mpeg 8 - 8 expect + istatus expect + mpegstatr + istatus 12 mpeg or mpeg + pro logic decoder png 8 - 8 expect + istatus expect + pngstatr + istatus 8 pink noise generator user 8 - 8 expect + istatus user defined + istatus user defined user defined function operation play 0 - istatus - - resume operation mute 0 - istatus - - mute audio output unmute 0 - istatus - - restore muted output stop 0 - istatus - - stop operation stopf 0 - istatus - - stop operation, flush data stat 0 see under functions return decoder status spdifstat 0 4 + 1 expect + spdifstatr + istatus - 4 return the s/pdif input channel status getptc 0 8 + 1 expect + getptcr + istatus - 8 return the ptc value nop 0 istatus - - no operation set-up plltab 6 - 6 expect + istatus - - set the pll tables pllcfg 1 1 expect + pllr + istatus - 1 define the pll configuration cfg 8 - 8 expect + istatus - - configure the i/o setstc 7 - 7 expect + istatus - - set system time clock ver 0 4 + 1 expect + verr + istatus - 4 return rom version number boot 4n - 4n expect + istatus - - load and execute n-word bootstrap program spdifcs 4 - 4 expect + istatus - - write the s/pdif output channel status param 1 + 3n - 1 + 3n expect + istatus - - define n parameter data words for special functions intrp 4 - 4 expect + istatus - - interpret parameters as zr38001 instruction setio 4 - 2 expect + setior + istatus - 2 set, test and return gpio registers poke 7 + 4n - 7 + 4n expect + istatus - - load n core processor ram locations peek 7 4n 7 expect + peekr + istatus - 4n read n core processor ram locations
24 zr38601 operation with commands this section describes operation principles when using the command structure and its configuration choices. start-up after being reset by the system reset signal, the zr38601 will check for an external program rom to load. not finding this it will start execution from the internal rom and await commands from the host. normal host operation would confirm the rom version number and then configure the zr38601 to match the system and desired operation. the command configuration sequence plltab, pllcfg, cfg is mandatory and must precede any decoding function selection. the pll configuration two phase-locked-loops (plls) allow independent selection of the core processor clock rate (f dsp ) and the serial digital audio clock rate (f audio ) for a variety of system clock frequencies (f xti ) and sources. figure 6 shows the system oscillator, the two plls, the serial i/o divider chains and the interconnection selec- tions. these are configured with the plltab, pllcfg and the cfg commands. the dspm and dspd fields in the plltab command (see page 16) determine the core processor clock rate to allow a choice between processing performance and lower power at lower clock rates. table 10 shows some representative values for common system clock frequencies. the audm and audd fields in the plltab command deter- mine the serial digital audio master clock rate for the i/o dividers. table 11 shows some representative and recommended values for common sample rates and master clock multiples. ?dspd x dspm mux ?2 ?audd x audm mux ?spbs ?2 system crystal oscillator crystal or external system clock input (4-40 mhz) xti xto dsp core clock (60-100 mhz) audio clock cb f psb f psa = f audio spas=1 scka input clock mb spbs=1 f b bypass system clock output (30-50 mhz) clkout spfrx master clock sckin sckb scka serial clocks sckb output clock input word/ frame sync. output word/frame sync. 0 1 0 1 01 figure 6. the system clock oscillator, the dsp pll and the audio pll with serial i/o divider chains system clock oscillator dsp pll audio pll serial i/o dividers mux 0 1 mux ?spas ?2 01 mux mux 1 0 ma f a mux 1 0 ?frb ?fra mb wsb/fsb wsa/fsa mux 1 0 ma mux 1 0 f1 f2 mux mux f3 ?2 0 0 1 1 f xti f xti f clkout f spfrx f dsp f audio (f sckin ) (f b ) (f a ) b group a group frame size dividers word/frame selects s/pdif receiver
25 zr38601 input/output configuration the cfg configuration command (see page 17) and the setio command (see page 19) determine the digital input and output configuration. connections to the data stream input, the output dacs and the single-bit general purpose registers are made through the input/output ports. there are seven digital audio input and output ports (port a, e and f are inputs and ports b, c, d and g are outputs). there are six single-bit general purpose user defined i/o ports: gpio[5:0]. serial ports the bit-serial ports serve a variety of peripheral device conven- tions. their operation is determined solely by the cfg configuration command. the input port group a (serial inputs a, e, f) and output port group b (serial outputs b, c, d and g) have separate clocking systems and may be individually selected with the zr38601 acting as a master or a slave (port f can be activated with the clocking systems of port group b). the system clock (f xti ), the audio pll locked to the system clock or the s/pdif receiver can generate a master audio clock f audio . this can be used to generate the two internal input and output bit-rate clocks when they are masters. see figure 6. if input port group a is a master, scka is at a frequency f a = f psa /(2 spas) where f psa is the audio clock f audio . in the case where spas equals one, f a is equal to f psa . the divider spas is a field in the cfg command. likewise, when output port group b is master, sckb is at a frequency f b = f psb /(2 spbs) where f psb is the internal audio clock f audio or an external clock f sckin received through the sckin pin. in the case where spbs equals one, f b is equal to f psb .the outputs are unique in that when operating as a master their clock outputs can also be derived from an externally supplied master clock input (sckin) with the programmable divider rate spbs. this selection is made with the cb field in the cfg command. some of these choices are summarized in table 12. table 10: representative values for dspm and dspd in the plltab command system clock frequency f xti nominal processor core clock frequency f dsp 66 mhz 72 mhz 80 mhz 100 mhz dspm/ dspd actual f dsp dspm/ dspd actual f dsp dspm/ dspd actual f dsp dspm/ dspd actual f dsp 12.288 mhz 27/5 66.35 mhz 41/7 72 mhz 13/2 79.9 mhz 65/8 99.8 mhz 16.9344 mhz 27/7 65.3 mhz 17/4 72 mhz 14/3 79 mhz 35/6 98.8 mhz 18.432 mhz 18/5 66.35 mhz 27/7 71 mhz 13/3 79.9 mhz 65/12 99.8 mhz 24.576 mhz 35/13 66.17 mhz 47/16 72.2 mhz 39/12 79.9 mhz 65/16 99.8 mhz 27.0 mhz 22/9 66.0 mhz 8/3 72.0 mhz 80/27 80.0 mhz 100/27 100.0 mhz 32.0 mhz 33/16 66.0 mhz 9/4 72.0 mhz 5/2 80.0 mhz 25/8 100.0 mhz table 11: representative and recommended* values for audm/audd in the plltab command system clock frequency f xti serial audio master clock frequency f audio 8.192 mhz (256 x 32 khz) 11.2896 mhz (256 x 44.1 khz) 12.288 mhz (256 x 48 khz) (384 x 32 khz) 16.9344 mhz (384 x 44.1 khz) 18.432 mhz (384 x 48 khz) 12.288 mhz 3/2* 147/160 1/1* 441/320 3/2* 16.9344 mhz 1280/2646 2/3* 640/882 1/1* 960/882 24.576 mhz 1/3* 294/640 1/2* 882/128 3/4* 27.0 mhz 1024/3375 784/1875 512/1125 392/625 256/375 32.0 mhz 32/125 441/1250 48/125* 1323/2500 72/125
26 zr38601 table 13 shows some representative values for both spbs and audm/audd for different output sample frequencies (f s ) and master clock multiples of the sample frequency. they are for the common choice of a system clock frequency of 24.576 mhz. serial port formats many choices are possible for the bit-serial port formats and word sizes. the five most commonly used formats are summa- rized in table 15 along with the selectable word sizes. waveforms for each are illustrated in figures 7-11. note the various frame durations indicated. clocking for both master and slave operation is shown. the transitions marked are the edges where data changes when the zr38601 is a master or where the data is sampled when it is a slave. settings for the appropriate fields in the cfg command are also summarized. word select (ws) or frame synchronization (fs) is chosen with the wfa and wfb fields. the polarity of the ws signal is chosen with the isp and osp fields. either polarity is acceptable on any of the word select formats. through the fma field the frameless input operation of format 3 can be chosen. the input then is sampled every scka and an interrupt generated after 16 bits has been received. note that when a master the fs signal shown is, in fact, generated and if fs is asserted when a slave it will re-synchronize the data as shown. this format may not be accepted by some function operating modes. table 12: serial ports a & b clocking summary in the cfg and pllcfg commands function input port group a output port group b audio pll source from s/pdif or system clock f1 audio clock source from audio pll or system clock f2 external master clock input sckin pin (f sckin ) none cb field = 0 internal master clock (f psb = f audio ) and master external clock output pin none cb field = 1 master or slave clocking mode ma field mb field internal 12-bit master clock scalers for scka and sckb. ls 8-bit fields. spas field (f a = f ps a / [2?pas]) spbs field (f b = f psb / [2?pbs]) bypass of clock scalers f a = f psa if spas=1 f b = f psb if spbs=1 data latched/sent out on rising/falling edge of clock cpa = 0 cpb = 0 data latched/sent out on falling/rising edge of clock cpa = 1 cpb = 1 table 13: example spbs and audm/audd settings with a 24.576 mhz system clock f xti f s f audio f audio (sckin output) audm/audd spbs sckb output (64 f s ) 48 khz 256 f s 12.288 mhz 1/2 2 3.07 mhz 48 khz 384 f s 18.432 mhz 3/4 3 48 khz 512 f s 24.576 mhz 1/1 4 96 khz 256 f s 24.576 mhz 1/1 2 6.144 mhz
27 zr38601 digital audio receiver the digital audio receiver function of the zr38601 is fully com- pliant with the iec-958, s/pdif, aes/ebu and eiaj cp-340 consumer mode interface standards. it will lock on to the incoming bitstream and extract the clock and data information. the data is supplied to the processor for decoding and the clock is multiplied to yield a 256x or 384x sample rate, as required by the dacs. this master clock signal is available on the sckin pin as an output. for correct operation of the s/pdif receiver the following initial- ization steps are required: the audd variable in the plltab command should be set to approximately 128 x f xti , where f xti is the clock input fre- quency expressed in mhz (i.e. if f xti = 12.288 mhz, then audd equals the integer portion of 12.288 x 128 = 1572). audm should be set to 4 or 6, for 256x or 384x sample rate audio clock output, respectively. the f1 field in the pllcfg command should be set to 1. the sen field in the cfg command should be set to 1. other representative values for audm/audd, f3 and spbs when using the s/pdif receiver are given in table 14 for various sample rates and master clock rates. they are for the common choice of a system clock frequency (f xti ) of 24.576 mhz . digital audio transmitter the digital audio transmitter of the zr38601 is fully compatible with iec-958, s/pdif, aes/ebu and eaij cp-340 consumer mode standards. this function enables the transmission of digital audio bitstreams to an external decoder for processing in all modes of operation, i.e. ac-3, mpeg or pcm. the transmit- ter is enabled by setting the spo bit in the cfg command. the channel status information required by iec-958 should be supplied to the zr38601 through the spdifcs command see the section s/pdif channel status spdifcs on page 18. it is important to set the channel status bits for an external decoder to operate correctly. when the s/pdif output is enabled, the fourth serial port sdg is disabled. note that the output frame size must be 32 bits (frb = 1) when using the s/pdif output. general purpose ports there are six single-bit general purpose ports gpio[5:0] normally configured as inputs at reset. gpio5 is normally used as the mute input and gpio0 as the dreq output. gpio1 is normally the error output signal. gpio[5:0] may be config- ured as user defined outputs by setting the gpioc field in the setio command. inputs pins, the ones that are defined as inputs from gpio[5:0], are sampled and read from the gpio register by the host with the setio command. at the same time it can set the state of the pins that are configured as output pins. decoder operation a typical decoder function selection command sequence would be: ac3, unmute...mute...prol, unmute... where ac-3 is selected first, then followed by a switch to prologic at a later time. if the drq bit in command cfg is set, the command sequence must include a play: ac3, play, unmute...mute, stop...mpeg, play, unmute.... table 14: example spbs, audm/audd and f3 settings using the s/pdif receiver and a 24.576 mhz system clock f xti f s master clock master clock f sckin f3 audio clock (f audio ) audm/audd spbs sckb output (64 f s ) 48 khz 256 f s 12.288 mhz 0 12.288 mhz 4/3416 2 3.072 mhz 44.1 khz 384 f s 16.9344 mhz 0 16.9344 mhz 6/3416 3 2.8224 mhz 32 khz 256 f s 8.192 mhz 0 8.192 mhz 4/3416 2 2.048 mhz 96 khz 128 f s 12.288 mhz 1 24.576 mhz 4/3416 2 6.144 mhz
28 zr38601 table 15: input and output format selections in the cfg command format figure cfg con?uration command fields wfa or wfb frame/word isp or osp word polarity fma or fmb format cpa or cpb clock polarity inw or outw input or output word size 0i 2 s71010 16, 18, 20, 24 bits 1 eiaj 8 1170 16, 18, 20, 24 bits 2 non-delayed 9 1000 16, 18, 20, 24 bits 3 frameless 10 006116 bits 4 frame sync 11 0011 16, 18, 20, 24 bits figure 7. i 2 s input/output - format 0 ws left channel right channel sda, sdb frame sckb (output) scka (input) ms 18 17 16 3 2 1 ls 321ls 14 15 16 ms ms 14 13 12 3 2 1 ls 321ls 321ls 321ls ms 18 17 16 14 15 16 ms ms 14 13 12 figure 8. eiaj input/output - format 1 ws left channel right channel sd sckb (output) scka (input) frame 21ls 21ls 21ls 21ls 21ls 21ls ms 18 17 16 ms 16 15 14 ms 14 13 12 ms 18 17 16 ms 16 15 14 ms 14 13 12 ms ms ms ms ms ms
29 zr38601 figure 9. non-delayed input/output - format 2 ws left channel right channel sd sckb (output) scka (input) frame ms 18 17 1 ls 1ls 1ls 1ls 1ls 1ls ms 18 17 ms 16 15 ms 14 13 ms 14 13 ms 16 15 figure 10. frameless input - format 3 scka (input) sckb (output) fs sd ms 14 13 1 ls ms 14 13 1 ls ms 14 13 1 ls ms 14 13 scka (input) sckb (output) fs sd ms 18 17 1 ls ms 18 17 figure 11. frame sync input/output - format 4 frame ms 14 13 1 ls ms 14 13 1 ls 1ls
30 zr38601 processor general description with its versatile internal architecture, general purpose instruc- tion set and high speed, the zr38601? core processor is also capable of executing many other types of algorithms for a wide variety of dsp applications. these algorithms can add differen- tiating product features to the basic audio decoding functions. with the zr38601? state-of-the-art performance these addition- al features take little processing time or program memory. a high level of performance is made possible by the 32-bit wide instruction set which allows the device to perform a large number of concurrent operations. for example, in a single instruction cycle the following operations can be performed: fetch two source operands from registers, execute an arith- metic operation and store the result in a register. update two data address pointers perform two parallel data move operations generate the next program address fetch the next program instruction. individual bit and immediate data instructions along with the zr38601? four-level zero-overhead loop and repeat instruc- tions, produce very compact code. most instructions execute in a single cycle. the zr38601 uses an internal clock rate of up to 100 mhz to achieve 50-million instructions per second (50-mips) perfor- mance. this allows accessing internal data memory twice per instruction cycle. an internal programmable phase-locked loop (pll) multiplier/divider circuit permits any external crystal or input clock to be used (in the range of 12-50 mhz). the zr38601? optimized 20-bit (120 db) data precision make it particularly well suited for compact disk-quality audio applica- tions including audio equalization, special effects and audio mixing where the 16-bit data precision of conventional fixed- point dsps is insufficient. furthermore, by providing high perfor- mance support for block floating-point operations to extend dynamic range (including one cycle exponent detection and two cycle normalization), zr38601-based systems are inherently more cost effective to implement than 24-bit precision fixed- point dsps which expand dynamic range solely via extended data precision. high performance block floating-point is due to the zr38601? bi-directional barrel shifter, a feature unavailable on most conventional 16- and 24-bit fixed-point dsps. to ease programming and increase speed, the zr38601 archi- tecture provides a general purpose data register file which can provide up to four source registers and two destination registers per instruction. a total of eight 20-bit data registers are provided, with two registers extended to 48-bits for use as accumulator registers with 8-bit overflow protection. the zr38601 also provides a dual address generator and register file capable of generating two independent addresses per instruction cycle. the address generator supports modulo and bit-reversed addressing, in addition to a complete set of pre- and post-modify addressing modes. the zr38601 has many built-in memory resources. a large 2k x 32-bit program/data ram is available on-chip in additional to the many coded functions in the mask programmable 20k x 32-bit rom. the already large internal 10k x 20-bit data ram can be extended off-chip via the 16-bit external data bus and 20-bit memory address bus, allowing it to address up to 1m data words in a unified address space. programmable wait-states accom- modate lower-cost slow external memories and byte-wide configurations can be used for lower chip count if desired. processor functional description architectural overview figure 12 shows the detailed functional units of the zr38601 processor. the data path consists of the arithmetic unit, the portions of memory used for data, and its associated address generation unit. the control path is the instruction unit, the portions of memory used for program, and its associated program sequence unit. the remainder are the input/output ports and the system interface. data flow between data path units is over the single 20-bit data bus with a corresponding 20-bit data address bus. control flow is over the single 32-bit program data bus with a corresponding 20-bit program address bus. these dual data and address buses are multiplexed to smaller single external buses for external data memory. this simple space-efficient bus structure maintains high performance as each internal bus makes two transfers per instruction cycle and each unit is self-contained with its own local memory. the high performance of the zr38601 is apparent from the power of the data functional units with their attendant instruc- tions and their being matched by the power of the control functional units and their instructions. both are described in turn. data and control paths are assured of working together in parallel because of the fast interconnecting bus structure and the wide-word instruction set controlling both. this view of the operation by function and instruction can confirm basic bench- mark performance. in actual designs, the powerful assembler and simulator show the details of the pipelined operations and intermeshing of functions and transfers to assure balanced operation. arithmetic unit the arithmetic unit performs all data path operations in the pro- cessor, using a full-function alu, a bi-directional barrel shifter and a 20 x 20-bit multiplier, all operating out of the multiport register file. the seven ports allow two transfers in or out of the
31 zr38601 20 a0-7, i0-7, m0-7, sp address register file 3 x 8 x 20 1 x 20 aalu 20 20 20 a i m 20 20 data bus 32 program data bus dbx 12 20 mux 20 data address bus 14 program address bus 20 mux loop start stack program counter increment 32 general registers aux. registers oscillator, plls & clocks reset external interrupt xtal reset int 2 d0-d1 d2-d7 data register file 2 x 48 6 x 20 multiplier 20 x 20 shifter mux ds 48 2 data shifter 20 ms 1 48 20 48 status alu barrel shifter 48 mux 2 x 48 sd 1 48 48 20 mux instruction unit program sequence unit address generation unit memory system interface arithmetic unit input/output ports figure 12. zr38601 detailed block diagram 20 20 demux 32 14 10 mux ice i/f 4 test serial host i/f 4 host gpioc[5:0] 32 data 4 parallel port 12 mux 42 48 adder 48 20 instruction register repeat count loop count stack compare loop end stack sde srg gpio[5:0] e input f input g output/ serial ports a input b output c output d output gpio[5:0] sda sdb sdc general purpose ports 16 data 20 addr program/data rom 20k x 32 data ram 10k x 20 program/data ram 2k x 32 s/pdif input sdd sra srb src srd sre srf sdf sdg memory control interface port host control parallel data fifo 8 x 9 9 2 s/pdif transmitter s/pdif output 18 control 3 clocks & control s/pdif receiver crcc packreg 20 8 spmode 2 3 20 control inputs outputs intr. mask reset & intr. timer
32 zr38601 register file from memory in parallel with a three operand multi- plier and alu operation, including storing the result, every instruction cycle. in addition to the basic two?-complement arithmetic and logical operations, the 48-bit alu also can find minimums and maxi- mums, normalize, determine exponents for block floating-point, support multiple precisions and perform division primitives. a further refinement is a butterfly primitive that computes both a product sum and difference using an auxiliary adder. this fetching of four operands, doing a multiply, addition and subtrac- tion and storing two results facilitates a very fast 4-cycle radix-2 fft butterfly. alu results set appropriate status register bits in the system interface, which has sticky bits for multiple precision and array computations. a large class of immediate data logical and arithmetic instructions free register space and reduce instruction count in the bit operations so common in communica- tions coding applications. the multiplier provides both signed and unsigned operations with an optional one-bit left shift on the output determined by the ms bit in the mode register. this shift for fractional number align- ment preserves the maximum 42 bits of shifted products. the 48-bit barrel shifter does both logical and arithmetic shifts; the sd bit in the mode register allows a positive shift operator to be interpreted as either a left or a right direction shift. a third data shifter provides arithmetic shifts, rounding and limiting when transferring data from the register file onto the data bus. the shifting range of 1 bit to the right through to 2 bits to the left is determined by the ds bits in the mode register. two of the eight registers of the register file (d0 & d1) are 48 bits, the remaining six are 20 bits and align as shown in figure 13. in general all arithmetic unit operations are for implicit 20-bit operands with data being overflowed, limited, rounded or truncated accordingly for registers d2-d7. however when d0 or d1 are the source or destination, then the operations are such as to preserve the full 48-bit precision results in these registers. likewise, transfers in and out of d0 & d1 with the data buses are extended or reduced based on their being 48-bit operands. these two registers usually serve as the high precision accumu- lators which are central to most signal processing algorithms. any of the three fields can be explicitly addressed if the implicit operands are not the desired ones. address generation unit data operated on by the arithmetic unit is read from and restored to the data register file. register file locations are directly addressed by register fields within the operate field of the instructions. for data transfers with the larger internal and external memories and registers, direct addressing can also be used, but indirect addressing by the address generation unit is often faster and more program memory efficient. the address generator can sequentially produce two 20-bit addresses for the two bus transfers possible per cycle and post-modify the same two addresses in the same instruction cycle. the indirect addresses generated can be linearly incremented or decremented, indexed, bit-reverse indexed or circular with an arbitrary modulus m. this is done in the address generation unit by the address alu (aalu) and the address register file which is organized as in figure 14. the next address is produced in a postmodify operation using the appropriate sum of the address register ax with index register ix and a compare with modulus register mx. the five addressing modes in their assem- bler notation are: note there is no indexing or circular addressing for the stack pointer sp. for m = hex fffff the corresponding a register is incremented in a bit-reverse manner for doing the radix-2 fft. for an n-point fft the incrementing index register must be loaded with n/2. the address register file is accessible on the data bus and can be used for general purpose registers. further, they can be loaded with immediate data from the program data bus. memory internal there are three internal on-chip memories, a 10k x 20-bit ram, a 2k x 32-bit program ram and a 20k x 32-bit mask-program- d1 d0 high middle low figure 13. data register file 47 d1h 40 39 20 d1m 19 0 d1l 47 d0h 40 39 20 d0m 19 0 d0l 19 0 d2 19 0 d3 19 0 d4 19 0 d5 19 0 d6 19 0 d7 (ax) at the address in address register ax with no postmodify operation (ax)+ with a postincrement by one (ax)- with a postdecrement by one (ax)+i with a postincrement by the value in index register ix (ax)-i with a postdecrement by the value in index register ix address figure 14. data register file 19 0 a0 index 19 0 i0 modulus 19 0 m0 19 0 a1 19 0 i1 19 0 m1 19 0 a2 19 0 i2 19 0 m2 19 0 a3 19 0 i3 19 0 m3 19 0 a4 19 0 i4 19 0 m4 19 0 a5 19 0 i5 19 0 m5 19 0 a6 19 0 i6 19 0 m6 19 0 a7 19 0 i7 19 0 m7 stack pointer program counter
33 zr38601 mable rom. the 20-bit wide ram is used exclusively as data memory, it transfers on the data bus and is addressed only from the data address bus. it is always located in lowest memory address space starting at hex 00000 up to 027ff. the other ram and the rom are 32-bits wide and can be used for both data and program memory. they are addressable by both the program and data address buses and are sources, and the ram a destination, for transfers on both data and program data buses. when the program ram is written to the most significant 12 bits are loaded at the same time from the data bus extension (dbx) register. when the program ram is read as data the dbx register is loaded with the most significant 12 bits of data. the dbx register can also be loaded or read as a general register with data in the least significant 12 bits. the rom is always at locations hex e0000 to e4fff in memory space on both address buses. the standard zr38601 product has the rom coded with the digital audio decoder functions and a bootstrap program for accepting commands from a host or loading an operating program into ram from a byte-wide external rom. note that the external rom data is on d[11-4]. the program/data ram is always at locations hex d0000 to d07ff in memory space on both address buses. it provides fast internal memory without the cost of a mask programmed internal rom when the zr38601 is used with an external byte-wide bootstrap rom or host microcontroller. all internal memories have a single port, but consistent with the buses, all can perform two complete operations per instruction cycle. the memories can operate in parallel provided buses are available. each internal address bus has its own address space, but since the internal memories do not overlap and external memories share a common address bus, all memories can be considered to be in one address space as shown in figure 15. external data memory is extended externally on the parallel port in the address spaces shown in figure 15. internal data buses are multiplexed into single smaller bus for external memory. thus only one external data transfer can take place at a time. also, only a single transfer can be made in each instruction cycle due to the slower external memories. this memory cycle-time can be lengthened by inserting wait-states to allow the use of lower-cost slow memories. the number of wait-states is determined by the cfg command so that external memory operations take one, three or seven instruction-cycle-times. the addresses shown are the internal 20-bit ones. the optional external bootstrap rom is 8-bits wide and connect- ed to d[11-4]. various widths of memory can be used for an external ram if required. the choices are 8 or 16 bits. the data must be left justified on the data bus. reset and interrupt memory locations the reset and interrupt vectors occupy a reserved block of memory of 64 (hex 40) locations. as shown in figure 15 these can be located at the lowest portion of the on-chip 20k x 32-bit rom or 2k x 32-bit ram. this is selected by the pm bit in the mode register as follows: program sequence unit all processor operation is governed by the decoded instruction in the instruction register (ir). the control flow of the processor is the sequence of instructions that are presented to the ir. the program sequence unit determines this flow by generating the program address to fetch instructions from program memory. this unit in the zr38601 is a powerful address generator also, often producing a long sequence of operations with a minimum of program memory transfers. examples of this are the repeat and loop instructions which allow repeated single and multiple instructions respectively with no instruction overhead. in addition to these instructions, major changes in the control flow are determined by the reset operation, interrupts, branches and subroutines to which the program sequence unit responds. reset and interrupt operation operation of the processor starts with the system asserting the reset pin. when reset is asserted, the mode register is set to hex 00038 and the status register is set to hex 00000. the serial port data registers are all cleared, as are the shift registers for the output serial ports, and the serial port shift register pointers are reset. the modulus registers and the loop end reg- isters are cleared. the program counter is set to hex e0000 before unconditionally jumping to the beginning of the reset and reset & interrupts location c 02800 00000 e0000 e0040 e5000 reset & interrupts location a 10k x 20 internal data ram external data memory 20k x 32 internal program/data rom figure 15. program/data memory map memory address (hex) d0000 d0040 d0800 2k x 32 internal program/data ram reserved for decoder functions 40000 4ffff bootstrap rom 64k x 8 d11 d4 d0 d19 d4 d11 table 16: reset and interrupt start locations pm bit reset & interrupts location start address (hex) 0 a - internal rom e0000 1 c - internal ram d0000
34 zr38601 interrupt block (shown in table 17) to start executing the reset service routine. the complete service routine may be read from an external bootstrap device and in turn, executed. assertion of reset does not affect the stack pointer, loop start register, loop and repeat count registers, address and index reg- isters, internal ram and the data registers. the 15 hardware interrupts and the software interrupt, have their corresponding vector addresses and the priority shown in table 17. the priority reflects only the order of servicing when more than one request is pending, and does not determine whether or not a currently executing interrupt service routine will itself be interrupted. all interrupts are collectively disabled with the ie bit and individually enabled with their own mask bits in the auxiliary interrupt mask register (imr). before an interrupt service routine is executed, the processor clears the ie bit to disable further interrupts and then pushes the return address and status register contents on to the stack. repeat and loop instructions the repeat instruction allows the single instruction that follows it to be repeated with no instruction overhead beyond the initial single repeat instruction. the repeat count (rc) register in the program sequence unit allows up to 2 20 repeated opera- tions. likewise, the loop instruction allows zero overhead for repeating multiple instruction sequences. the loop count (lc), the loop start (ls) and the loop end (le) registers implement this instruction. loops may be nested up to four deep with these registers automatically being pushed on their individual stacks. the rc, lc, ls and le can be a source or destination for general register data transfers, with each transfer in or out of the le register being the appropriate push or pop operation respec- tively for their stacks. subroutines and stack operations an operational stack is maintained in data memory to service context switches caused by changes in control flow. interrupts as well as the push, pop and jump subroutine instruction macros use the stack. the stack pointer (sp) in the address generation unit determines the stack location, usually in the internal data or program/data ram for highest speed. instruction unit pipeline each instruction is fetched from program memory (either internal ram or rom), decoded in the instruction register and finally executed. this three stage instruction pipeline takes a minimum of three instruction cycles, but is generally transparent to the user. the delayed branch instructions, however clearly exhibit this pipeline? delay. the pipeline is extended, in effect, whenever there is a requirement for multiple simultaneous accesses to a particular memory resource that cannot be resolved in a single cycle. this occurs, for example, when an instruction fetch and a dual data move all require access to the internal program/data ram or rom. instruction set each of the instructions of the zr38601 is a single word in length and except for program flow control instructions, all generally execute in a single cycle unless multiple external memory accesses are required. much of the power of the processor lies in the parallel operations that go on within one instruction. instructions are named for the dominant operation that exe- cutes, usually an arithmetic unit operation or a program sequence unit operation. the instruction set names are sum- marized in table 18 by the functional unit. also listed are the instruction macros which the assembler generates from the basic instructions. table 17: reset and interrupt block memory map interrupt number priority offset interrupt type mask 01 (highest) 0x00 reset service routine no 1 2 0x04 ice interrupt service routine no 2 3 0x08 breakpoint interrupt service routine no 3 10 0x0c hreg interrupt service routine yes 4 5 0x10 int external interrupt service routine yes 5 6 0x14 serial port group a service routine yes 6 0x18 reserved 7 8 0x1c serial port group b service routine yes 8 0x20 reserved 9 9 0x24 serial host interrupt service routine yes 10 0x28 reserved 11 7 0x2c audio receiver error interrupt service routine yes 12 4 0x30 data fifo interrupt service routine yes 13 11 0x34 timer service routine yes 14 0x38 reserved 15 16 0x3c jump to software interrupt service routine no
35 zr38601 the instructions divide into eight classes or bit-pattern formats summarized in table 19. it is here that the full power of the zr38601 is most evident. the first three classes provide the full function of the arithmetic unit with its operate fields (opcode and operand), but also simultaneous parallel operations. the parallel operate fields (parallel opcode and parallel operand) specify single and double, direct and indirect transfers with the sources and destinations along with address generation modify operations. the bit instructions are also parallel operations. the last five classes of instructions are for the large-field direct data transfers and program control. for classes iv and v the possible source or destination register is a general register. for parallel operations, the possible source and destination registers include the auxiliary registers as well as the general registers. table 19: instruction class summary table for parallel transfer operations there are the following six sub- classes: with the most powerful being the last which can do the following four types of sequential dual transfers: all memory references in this subclass are indirect and with possible address modification. table 18: instruction set summary instructions arithmetic unit address generati on unit program sequence unit arithmetic logic multiplier abs and, andi bfy move delayed branch add, addi dec madd conditional db ashift, ashi inc mneg jump to sw interrupt cmp, cmpi lshift, lshi msub loop cmpa or, ori mul, muli repeat cmpz xor, xori mulsu divs nop muluu divu clrbit movemax setbit movemin tstbit neg norm normmax sub macros clear pop do push jump conditional jump unconditional jump subroutine return interrupt return subroutine i. single operand alu operations with parallel transfer operations class code op- code oper- and parallel opcode parallel operands ii. two operand alu operations with parallel transfer operations class opcode operands parallel opcode parallel operands iii. three operand alu operations with parallel transfer operations opcode operands parallel opcode parallel operands iv. load/store direct class code register address v. load immediate class code register data vi. conditional delayed branch class code condition code address vii. repeat immediate class code data viii. software jump to interrupt immediate class code interrupt # i register-to-register transfers, single ii load register immediate (6-bits), single iii register-to-memory transfers, single iv memory-to-register transfers, single v address modify, single and dual vi single and dual transfers including memory-to-memory (through a register) and with optional address modify. first transfer second transfer data register to memory data register to memory data register to memory memory to data register memory to data register data register to memory memory to data register memory to data register
36 zr38601 input/output ports connections to external memory and peripherals are made through the input/output ports. there is a single 16-bit parallel data port, eight serial data ports and six single-bit general purpose i/o ports (gpio). these last can be configured by the user as outputs or inputs. parallel port the zr38601 parallel port works in two separate modes which are selected by the pin p/m at reset . it can work as a data parallel port which is used to load data, instructions and programs to the chip and read status and other information from the chip, or it may work as an external memory interface. the external memory interface consists of the 20-bit address bus a[19:0], the 16-bit bi-directional data bus d[19:4], and the control signals cs , rd and wr . the data parallel port interface consists of the 8-bit bi-directional data bus pp[7:0], and the control signals cs , rd , wr , err, c/d , rdy. the rdy, c/d , and err signals are d[14:12] and pp[7:0] are d[11:4] also. when controlling the external memory interface (p/m = 0), cs is asserted low whenever there is an access to external memory. rd is asserted during an external read cycle, and can be used as an output enable for memory. wr is asserted during an external write cycle and can be used as a write enable for memory. the zr38601 can generate wait-states for use with slow external memory using the wait field of the cfg command. in access cycles with wait-states, the timing relationship of the transitions of the memory interface signals remain the same as in a zero-wait cycle, but all are stretched by the specified number of instruction clock periods (1, 3 or 7). during an instruction cycle in which there is no external data access, the rd and wr signals are not active. however, the address bus continues to be driven with the internal instruction fetch address. when the parallel i/o interface is selected (p/m = 1), an internal fifo is used to enable the host to write data in long bursts. the rdy output signal indicate when the fifo is ready to receive more data (rdy = 1) or when the fifo is almost full and not ready to accept data (rdy = 0). the err signal is an input to indicate for each data byte received if there is an error in the data. the c/d input signal distinguishes between input data and instructions or status which use the hregin/hregout regis- ters. when c/d = 1 transfers are a host command or reply status and therefore are written to the hregin register or read from the hregout register. when c/d = 0 then all data from the host is written to the internal fifo. cs , rd and wr are always inputs when p/m = 1. when reset is asserted, the address and data buses and control signals cs , rd and wr are all set to a high-impedance state. serial dac and adc ports the serial ports are flexible on the zr38601 to serve a wide variety of applications and peripheral devices. the three adc input and four dac outputs may be variously grouped to share two sets of common control signals, each being a master or a slave. other selections are word or frame synchronization, frame size and either 16, 18, 20 or 24-bit word transfers. a master clock output which can be generated internally and two group programmable rate clocks. the i 2 s format, the frame-less time-division-multiplex (tdm) format and the lsb justified frame of the eiaj format are all supported. ports a, e, f are always adc data inputs, while b, c, d are always dac data outputs. port g can be a dac data output or the s/pdif transmitter output. they may be configured in two groups with shared clocking: all inputs and all outputs, or as two groups with one of the inputs in the outputs group. this selection is made by the ab bit in the mode register. the b group is unique in that when operating as a source to dacs, its clock outputs can also be derived from an externally supplied master clock input (sckin). transfers are on the positive- or negative-going edge of the bit- rate clocks (scka and sckb) with the most significant bit being shifted first into or out of the double buffered shift registers. word boundaries are signaled by a single-bit-duration frame signal (fsa and fsb) for each word or an alternating word signal (wsa and wsb) indicating left or right channel, even or odd word. the signal type is selected independently for each group as is the word length of 16, 18, 20 or 24 bits and the frame size of 16 to 256 bits per frame. the word select bits in the status register reflect when the left or right channel is being transferred for each group. the ws/fs signals maybe advanced by one or more bit intervals for the non-i 2 s format. completed frame trans- fers for each group are indicated to the processor by a vectored interrupt when individually enabled. an exception is for tdm where there is an interrupt for each word within a frame. each group can be a source or a slave as selected in the auxil- iary serial port mode register. when a source, the clock rates are independently programmable sub-multiples of the internally generated master clock. the b group clocks can come from the external master clock input (sckin) as well. if this input is not used the pin may be selected as an output for the internally gen- erated master clock. s/pdif serial ports the spfrx signal is the single-wire input to the s/pdif digital audio receiver. in use, the audio pll locks on the incoming spfrx bitstream to determine the audio master clock sckin and to recover the digital input data. the serial output port g is the single-wire s/pdif digital audio transmitter output when not used as a dac data output. its sdg/spftx signal is used to output s/pdif encoded data for decoding in other peripheral devices.
37 zr38601 general purpose ports six single-bit general purpose ports may be individually selected as an input or output in the gpioc auxiliary register. if config- ured as an input, its sampled state may be read in the gpio general register, or if an output, its state may be set by writing to the gpio register. system interface the system interface consists of all external signal functions other than input/output ports plus the general and auxiliary reg- isters which are associated with functional units and i/o operation. general registers in addition to the primary data flow and control flow of instruc- tions between functional units on the two data buses, there is the secondary control flow between the general and auxiliary regis- ters for initialization and maintenance of operation. the following general registers are directly addressable on the data bus for register-to-register, memory-to-register or register-to-memory parallel transfers. some of the more important general registers are described next in detail. table 20: adc and dac serial ports function summary function a group b group grouping: ab = 0 3 inputs (a, e, f) 4 outputs (b, c, d, g) grouping: ab = 1 2 inputs (a, e) 1 input (f), 4 outputs (b, c, d, g) word size 16, 18, 20, 24 bits 16, 18, 20, 24 bits frame size (bits/frame) 16, 24, 32, 64, 128, 192, 193, 256 16, 24, 32, 64, 128, 192, 193, 256 synchronization word or frame word or frame source and slave clocking modes yes yes latching on rising or falling edge of clock yes yes (when port f belongs to port group b) transmitting data on rising or falling edge of clock yes yes external master clock input no yes internal master clock output yes yes internal clock scaler 12-bit counter 12-bit counter i 2 s format yes yes tdm format yes yes left/right justified formats yes yes table 21: the general registers name bits description d0-7 48 data registers 0-7 a0-1 20 address registers 0-7 m0-7 20 modulus registers 0-7 i0-7 20 index registers 0-7 d0l 20 data register 0 low d0m 20 data register 0 middle d0h 8 data register 0 high srg_spf 20 s/pdif transmitter data register d1l 20 data register 1 low d1m 20 data register 1 middle d1h 8 data register 1 high rc 20 repeat count register lc 20 loop count register. stack of four. ls 20 loop start register. stack of four. le 20 loop end register. stack of four. status 20 status register mode 20 mode register pc 20 program counter sp 20 stack pointer z 20 z register for jsr and jsrq sra 20 serial port a data register srb 20 serial port b data register src 20 serial port c data register srd 20 serial port d data register packreg 20 pack register dbx 12 data bus extension register ds 2 data shifter ie 1 interrupt enable sre 20 serial port e data register srf 20 serial port f data register gpio 6 general purpose i/o data register wait 2 external memory wait-states table 21: the general registers (continued) name bits description
38 zr38601 mode register the mode register is a source or destination register containing 18 fields that define the basic processor configuration. they tend to be set once at initialization and not change. the interrupt enable (ie), the wait-state selection (wait), and the register file data shifter (ds) bits that may change during processing are also individually addressable as registers. the ie, im, am and bm bits are also accessible in the interrupt mask register (imr). the mode register is defined as shown below. status register the status register is a source or destination register containing fields that reflect the state of the processor following each instruction cycle. they affect the conditional program control of the processor. the least significant 8 bits reflect arithmetic and logical operation results from the alu, multiplier, barrel shifter or on transfers that involve scaling or limiting. the other eight involve word identification on the serial and host ports, status of the plls and configuration of the chip. the status register is defined below. 19 ie 13 14 15 16 17 18 am bm 0 0 pm 0 wfa crcr 8 9 10 11 12 im 1 2 3 4 5 6 7 0 wait ms ds sd wba ab aw bw mode ie interrupt enable when set enables all unmasked interrupts. when cleared, disables all interrupts. im int mask when set enables the external interrupt input. am a mask when set enables the a group serial ports interrupt. bm b mask when set enables the b group serial ports interrupt. pm program memory selection. when set the reset and interrupt block is located in internal ram. when cleared it is in internal rom. crcr crc r eset register flag. a transition from ??to ??of this flag resets the crcc register to zero in the next cycle. set to zero u pon reset . wfa word/frame a group serial port synchronization mode bit. word synchronization when set, frame synchronization when cleared. wfb word/frame b group serial port synchronization mode bit. word synchronization when set, frame synchronization when cleared. ab a/b groupings of serial ports. when set, a group is ports a, e and b group is ports b, c, d, f, g. when cleared, a group is port a , e, f and b group is ports b, c, d & g. aw a word precision. together with the aw1 bit in the spmode register defines the precision of group a data words. for [aw,aw1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. bw b word precision. together with the bw1 bit in the spmode register defines the precision of group b data words. for [bw,bw1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. wait wait-state selection for external memory. 0 = no wait-states, 1 = one wait-state, 2 = three wait-states, 3 = seven wait-states (a total o f eight instruction cycles for an external memory operation). ms multiplier shifter. when set specifies 1-bit left arithmetic shift on multiplier output, when cleared there is no shifting. ds data shifter on transfers from the data register file to memory. 00 = no shift, 01 = left shift by one, 10 = left shift by two, 11 = right shift by one. sd shift direction on the barrel shifter. when cleared a positive shift code corresponds to a left shift, when set a positive shift code corre- sponds to a right shift. 19 0 13 14 15 16 17 18 0 0 plocka p/m sie 0 1 plockd 8 9 10 11 12 0 1 2 3 4 5 6 7 ss sl sv v c n z hwr wsa wsb q status plocka audio pll lock status . setting rstaud resets the audio pll. this clears plocka indicating that the audio pll is not locked. when the audio pll is locked on the acquired frequency it sets plocka again. read only. p/m parallel port/memory status. the p/m status flag reflects this pin? state at reset indicating whether the parallel port is configured for parallel i/o or memory. read only. sie store interrupt enable status flag. this flag stores the ie value in the mode register upon entering an interrupt processing sequence, simultaneously with resetting ie flag. read only. plockd dsp pll lock status . setting rstdsp resets the dsp pll this clears plockd indicating that the pll is not locked. when the dsp pll is locked on the acquired frequency it sets plockd again. read only. hwr host write indicated the host interrupt is due to a write operation to the host register. read only.
39 zr38601 dbx register the data bus extension register (dbx) is a 12-bit register that permits full use of the 32-bit internal memories for data. when reading data from 32-bit wide internal memory to a 20-bit regis- ter, the least significant 20 bits are loaded into the destination register. the most significant 12 bits are loaded into the dbx register. when writing data from a 20-bit register to the 32-bit internal ram, the least significant 20 bits are driven by the spec- ified source register, while the most significant 12 bits are driven by the dbx register. when the dbx is specified as the destina- tion or source in a transfer, the least significant 12 bits are read into or loaded from the dbx. auxiliary registers in addition to the primary data flow and control flow of instruc- tions between functional units on the two data buses, there is the secondary control flow with the general and auxiliary registers for initialization and maintenance operations. the auxiliary reg- isters are accessed by register-to-register parallel transfers only wsa word select a bit indicates left channel data is being input if cleared or right channel data if set, on the a group serial ports. wsb word select b bit indicates left channel data is being output if cleared or right channel data if set, on the b group serial ports. q quotient bit is used with the divide iteration instructions. ss sticky scaling bit is set if any data transferred through the data shifter has a magnitude of greater than 0.25. a typical use is to indicate the potential for overflow in the next pass of an fft. it is cleared by a reset or by an explicit instruction to clear it. sl sticky limiting bit is set whenever limiting takes place in the arithmetic unit or during a data transfer through the data shifter. it is cleared by a reset or by an explicit instruction to clear it. sv sticky overflow bit is set whenever the overflow bit is set except for the compare instructions. it is cleared by a reset or by an explicit instruction to clear it. v overflow bit is set if an overflow results from any operation in the arithmetic unit. overflow is determined if any number can not be properly represented in its destination register. c carry bit is set if a carry results from an addition or a borrow results from a subtraction in the alu, or results from shifts in th e barrel shifter of the arithmetic unit. n negative bit is set if the most significant bit of the destination register is set, otherwise it is cleared. z zero bit is set if the entire result of an arithmetic unit operation in its destination register is zero. table 22: the auxiliary registers name bits description hregout 8 host register output hregin 8 host register input (ro) isr 1 ice host status register irr 20 ice host response register bkp1 20 instruction address breakpoint register 1 bkp2 20 instruction address breakpoint register 2 bkp3 20 data address breakpoint register 3 bct1 20 breakpoint 1 counter bct2 20 breakpoint 2 counter bcr 4 breakpoint control register bsr 3 breakpoint status register imr 20 interrupt mask register gpioc 6 general purpose i/o control register spmode 20 serial ports mode register audm 13 audio pll multiply register spas 12 serial ports a group scaler register spbs 12 serial ports b group scaler register spitx/sctx 8 serial host interface transmit register, spi/z2c spirx/scrx 8 serial host interface receive register, spi/z2c (ro) spimo- de/scmode 2 serial host interface mode register, spi/z2c spistat/sc stat 7 serial host interface status register, spi or z2c (ro) spdel 12 serial port bit delay a and b spfaud 7 s/pdif transmitter auxiliary audio register spfstt 1 s/pdif transmitter status register (ro) spfchs 20 s/pdif transmitter channel status register dspdm 14 dsp pll divide/multiply register audd 13 audio pll divide register icr 13 ice command register (ro) idr 20 ice data register (ro) testmode 12 test mode data register sprxdat 20 s/pdif receiver data register (ro) sprxaux 6 s/pdif receiver auxiliary register (ro) sprxchs 20 s/pdif receiver channel status (ro) sprxstt 8 s/pdif receiver status register (ro) sprxmode 4 s/pdif receiver mode register crcc 16 cyclic redundancy check code register clkmode 7 clock mode register. dfifo 20 parallel port data fifo register (ro) dffcnt 20 parallel port data fifo counter (ro) timer 18 timer register z2cadr 7 z2c address table 22: the auxiliary registers (continued) name bits description
40 zr38601 one of the more generally important auxiliary registers is described next in detail. serial ports mode register the serial ports mode register is an auxiliary source or destina- tion register containing fields that determine the serial ports operation and configuration. the fields are defined below. timer the zr38601 timer is an 18-bit programmable counter auxiliary register. once loaded, it counts down at the instruction cycle rate of f clkout or f dsp /2. at a count of one it issues an interrupt and reloads to continue counting the next interval. serial host interface the serial host interface provides a low-cost, low-bandwidth interface to a host processor for down-loading ram programs and basic operating commands. the zr38601 always operates as a slave and transfers are internal program interrupt driven. there are the two industry standard signals and protocols sup- ported, spi (serial peripheral interface) and z2c (zoran two conductor interface). transfers are bit-serial with parallel eight- bit data registers. the standard function rom can accept commands or down-load ram program through the serial host interface if it does not find an external byte-wide eprom at reset time. the serial host signals and protocol are determined by spi/z2c , the state of the sdb pin at reset. spi/z2c = 0 for z2c if sdb is tied to a pull-down resistor. spi/z2c = 1 for spi if sdb relies on the internal pull-up resistor or uses an external one. the shared interface signals are data input (si), data output or slave data (so/sda), serial clock input (sck/scl) and slave select (ss ), where sda and scl are for the two-wire z2c interface. four auxiliary registers receive data (spirx/scrx), transmit data (spitx/sctx), govern operation (spimode/scmode) and provide control flags (spistat/scstat) for the interrupt driven operation with the two protocols. an additional auxiliary register z2cadr holds the seven-bit z2c address determined at reset from the si, ss , sdd and sdc pins for z2cadr[5,4,1,0] respectively. z2cadr[6,3,2] are always zero. in spi operation, transfers are full-duplex with a single byte transmitted to the host for every byte received. the polarity of the sck clock is defined by the sckp bit in the spimode register which is determined by the state of sdg/spftx pin at reset. when sckp = 1 the output data on the so signal changes after the falling edge of sck and the input data on the si line is sampled on the rising edge of sck. when sckp = 0 the output data on so line changes after the rising edge of sck and input data on the si line is sampled on the falling edge of sck. when ss is not asserted, the sck line should be at the high level if sckp = 1 and at the low level if sckp = 0. the 19 spfen 13 14 15 16 17 18 0 0 0 bw1 aw1 0 mb cb 8 9 10 11 12 0 1 2 3 4 5 6 7 cpa frb fra ma tb ta cpb spmode spfen s/pdif output enable . setting spfen enables port g as the s/pdif output. clearing it makes port g serial i/o. bw1 b word precision. together with the bw bit in the mode register defines the precision of group b data words. for [bw,bw1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. aw1 a word precision. together with the aw bit in the mode register defines the precision of group a data words. for [aw,aw1]: 0,0 = 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation. cb clock b source. selects the group b clock source. setting cb selects the audio pll and sckin is an output. clearing cb selects sckin as the group b clock. mb master b. setting mb makes group b outputs masters with sckb an output. clearing mb makes group b slaves with sckb an input. ma master a. setting ma makes group a inputs masters with scka an output. clearing ma makes group a slaves with scka an input. tb tdm b. setting tb selects tdm (time division multiplexing) mode for group b outputs with a frame size determined by the frb field. clearing tb disables the tdm mode. ta tdm a. setting ta selects tdm (time division multiplexing) mode for group a inputs with a frame size determined by the fra field. clearing ta disables the tdm mode. cpb clock polarity b determines the group b serial outputs clock polarity. when cpb is set, data is output with the rising edge of the clock. when cpb is cleared, data is output with the falling edge of the clock. cpa clock polarity a determines the group a serial inputs clock polarity. when cpa is set, data is input on the falling edge of the clock. when cpa is cleared, data is input on the rising edge of the clock. frb frame b size. determines the frame size of the group b serial output ports in master mode: 0 = 16 bits, 1 = 32 bits, 2 = 64 bits, 3 = 128 bits, 4 = 192 bits, 5 = 256 bits, 6 = 193 bits, 7 = 24 bits. fra frame a size. determines the frame size of the group a serial input ports in master mode: 0 = 16 bits, 1 = 32 bits, 2 = 64 bits, 3 = 128 bits, 4 = 192 bits, 5 = 256 bits, 6 = 193 bits, 7 = 24 bits.
41 zr38601 sckp bit in the spimode register is set at reset if the sdg/spftx pin is tied to a pull-up resistor, or cleared if the pin is pulled down. in z2c operation, byte transfers are half-duplex with the zr38601 either a slave-receiver or slave-transmitter. figure 16 shows a normal read operation by the host master. normal oper- ation is in the alternating single-byte transmit/receive protocol, but the transmit-only protocol can be used to speed program downloading. the 400 kbit/second fast mode transfer rate is supported as well as standard mode of 100 kbit/second. in circuit emulation interface the zr38601? in circuit emulation (ice) capability for both hardware and software debugging is provided through four test pins (tdi, tdo, tck, tms) using a standard jtag interface. this interface is serviced by routines in the on-chip pro- gram/data rom and the highest priority interrupt. this provides register and memory read and set commands for hardware debugging. three breakpoint address-detection registers and two count registers with interrupt additionally provide for real- time program debugging capability in the ice. reset and initialization the processor can be reset only by asserting the reset signal input pin externally. on the initial power-up it must be asserted for a minimum of 160 clock cycles with proper supply voltage operating conditions. operation starts 16 cycles after the rising edge. after power-up, any reset must be asserted for at least 16 clock cycles but less than 128 clock cycles if there is no need to reset the plls. if the user wishes to reset the plls the reset signal must be active for at least 160 clock cycles. operation starts 16 cycles after the rising edge at the selected reset service routine location in memory. the processor will not, however, accept a serial host command and return a response until 200 instruction cycles have elapsed. in order for the decoder to operate correctly, the following sequence of commands should be supplied: plltab, pllcfg, cfg, ac-3 (if ac-3 mode is required) unmute. the states of pins after reset that are tri-state or can be either input or output are given in table 23. external interrupts the external interrupt input signal int is edge-sensitive and must remain asserted for two clock cycles to set the internal int flag. this flag is cleared as the interrupt service routine starts so that any new interrupt condition must allow int to go high and then low again for another interrupt to be generated. oscillator and clock inputs the xti and xto signals jointly supply the oscillator clock f xti either as an input from a ttl system clock or as the crystal con- nection to enable the internal oscillator. the maximum frequency f xti is 40 mhz and the minimum is 4 mhz. an internal phase-locked-loop (pll) generates from this a dsp core clock f dsp . this internal dsp clock can be in the range of 4-100 mhz. (for low f dsp frequencies, care should be taken because the spi data rate is slowed down proportionally). after reset but before pll lock, f dsp = f xti . the external clock is applied to xti, while the external crystal connection is as shown in figure 17. a parallel-resonant funda- mental-mode crystal should be used with two 20-pf capacitors. sda addr6 addr4 addr3 addr2 addr1 r ack addr5 msb addr0 ack lsb 1 345678 2 1234 6 5 989 7 scl zr38650 is slave receiver (sr) st sr sr stop start zr38650 is slave transmitter (st) figure 16. a z2c host interface read operation by a master host
42 zr38601 signal description summary table 23 summarizes information about all pins on the zr38601. during reset all t type pins are tri-state and i/o pins are inputs. pin states immediately after reset are shown in the reset state column. all unused input pins should be connected to v dd if active low, or gnd if active high unless internally pulled low. unused tri-state pins should be resistively pulled-up to vdd. unused outputs should be left unconnected. internal pull-downs are 50 ? maximum current sinks and pull- ups are 50 ? maximum current sources, both are connected only when configured as an input. the pull-downs on d[19:15] are connected only when p/m = 1. table 23: zr38601 signal description summary signal name number of pins type [1] reset state [1] internally pulled description parallel port (40) a[19:0] 20 o/t o - address bus of parallel port d[19:15] 5 i/o/t i down [2] data bus of parallel port when selected for external memory (p/m = 0) d14/rdy 1 i/o/t or o i or o - data bus (p/m = 0) or ready output signal of parallel port when selected for parallel i/o (p/m = 1) d13/ c/d 1 i/o/t or i i - data bus (p/m = 0) or command/data select input of parallel port when selected for parallel i/o (p/m = 1) d12/err 1 i/o/t or i i - data bus (p/m = 0) or error input signal of parallel port when selected for parallel i/o (p/m = 1) d[11:4]/pp[7:0] 8 i/o/t i - data bus of parallel port when selected for external memory (p/m = 0) or parallel port i/o (p/m = 1) cs 1 i/o/t o or i up chip select output for external memory or chip select input for parallel i/o rd 1 i/o/t o or i up read enable output for external memory or read enable input for parallel i/o wr 1 i/o/t o or i up write enable output for external memory or write enable input for parallel i/o p/m 1 i i - parallel i/o or memory select for parallel port. determined at time of reset . serial ports (13) spfrx 1 i i - s/pdif receiver input port sda 1 i i - serial data input. port a. sde 1 i i - serial data input. port e. sdf 1 i i - serial data input. port f. wsa/fsa 1 i/o i down word select or frame synchronization for input ports. an output when a master, an input when a slave. scka 1 i/o i down serial clock for input ports. an output when a master, an input when a slave. sdb 1 o o up serial left and right data output. port b. also, at reset defines spi/z2c for host serial interface. sdc 1 o o up serial left and right surround data output. port c. also, at reset defines z2cadr[0] of z2c address. sdd 1 o o up serial center and sub-woofer data output. port d. also, at reset defines z2cadr[1] of z2c address. sdg/spftx 1 o o - serial data output. port g or s/pdif transmitter port. also, at reset defines the sckp value. wsb/fsb 1 i/o i down word select or frame synchronization for output ports. an output when a master, an input when a slave. sckb 1 i/o i down serial clock for output ports. an output when a master, an input when a slave. sckin 1 i/o i - serial master clock output or master clock input for output ports
43 zr38601 general purpose ports (6) mute /gpio5 1 i or i/o i - mute input signal or can be programmed as general purpose input/output 5 gpio4 1 i/o i - can be programmed as general purpose input/output 4 gpio3 1 i/o i - can be programmed as general purpose input/output 3 gpio2 1 i/o i - can be programmed as general purpose input/output 2 error/gpio1 1 i/o i - error output signal or can be programmed as general purpose input/output 1 dreq /gpio0 1 i/o i - data request output signal or can be programmed as general purpose input/output 0 serial host interface (4) si 1 i i - host serial interface data input. also, at reset defines z2cadr[5] of z2c address. so/sda 1 i/o/t t - spi host serial interface data output or serial data for z2c sck/scl 1 i i - spi host serial interface clock input or slave clock input for z2c ss 1 i i - spi host serial interface slave select input. also, at reset defines z2cadr[4] of z2c address. ice interface (4) tdi 1 i i - ice test interface data input tdo 1 o/t t - ice test interface data output tck 1 i i - ice test interface clock input tms 1 i i - ice test interface mode select system interface (7) int 1 i i - external interrupt request input reset 1 i i - reset input to start operation in known state xti 1 i i - external system clock input or connection to external crystal, at frequency f xti xto 1 o - - output connection to external crystal clkout 1 o o - clock output from the zr38601 at frequency f dsp /2 bypass 1 i i - bypass internal dsp core pll to use external system clock input on xti fltcap 1 i - - external filter capacitor connection for pll. a value of 47nf is recommended. power (26) vdd 12 power - - +3.3 volt power supply vdda 1 power - - +3.3 volt power supply, analog for pll gnd 12 power - - power supply ground gnda 1 power - - power supply ground, analog for pll total (100) 1. o = output, i = input, t = tri-state. 2. when p/m = 1. table 23: zr38601 signal description summary (continued) signal name number of pins type [1] reset state [1] internally pulled description
44 zr38601 typical configurations stand alone (no host) figure 17 shows a zr38601 in a typical low-cost stand-alone configuration without a host microprocessor. a byte-wide rom may be used for loading an optional user written program that governs the decoder operation. the compressed data stream is input through the internal s/pdif receiver which also acts as a clock master for the output dacs. this master clock can be selected to be 256 x sr or 384 x sr. the internal clock divider on the zr38601 generates the clocking for the three slave dacs that provide the six- channel audio output. the standard zr38601, without being custom ordered with a user? program, has a reset bootstrap loading routine in its internal rom. the internal loading routine reads the pro- gram/data from an external byte-wide rom (shown) at address location hex 40000. the boot-strap recognizes the external rom rather than waiting for commands from a host that does not exist in this configuration. note that the pll capacitor connected to fltcap, and the bypass capacitors on vdda, should all be mounted close to the zr38601 package with short leads over the gnda analog ground plane, using normal good design practice for high- frequency mixed-signal circuits. figure 17. zr38601 typical stand-alone configuration 8k x 8 bootstrap rom optical to ttl s/pdif input 20 pf 20 pf xtal 4-40 mhz xti xto gnd gnda fltcap 47 nf 0.1? 47 ? tant. vdda vdd +3.3v 27 w spfrx gpio 6 a[12:0] 13 cs rd d[11:4] 8 acs oe d reset int system reset system interrupt sckin wsb sckb sdb sdc sdd zr38601 dac dac dac left right left surround right surround center subwoofer data data data l/r l/r l/r dclk dclk dclk clk clk clk f s 64 f s 256 f s
45 zr38601 serial host and serial data figure 18 and figure 19 show a zr38601 in typical system con- figurations with a host controller. at reset time the internal rom bootstrap will check for the byte-wide external rom. a resistive pull-up on any one data line d[11-4] assures that an external rom will not be found. not finding that, it will then expect to receive program commands from the host through the selected serial connection. note the optional pull-up on sdb in figure 18 to select the spi and the pull-down for the z2c in figure 19. the resistive pull-ups/pull-downs on si, ss , sdc and sdd in figure 19 determine the zr38601? z2c address at reset time. host microprocessor 20 pf 20 pf xtal 4-40 mhz xti xto gnd gnda fltcap 47 nf 0.1? 47 ? tant. vdda vdd +3.3v 27 w spfrx gpio5 si so/ sda sck/ scl ss so si sck ss reset int system reset system interrupt sckin wsb sckb sdb sdc sdd zr38601 dac dac dac left right left surround right surround center subwoofer data data data l/r l/r l/r dclk dclk dclk clk clk clk f s 64 f s 256 f s rs422 receiver mute d11 vdd figure 18. zr38601 typical configuration with the spi serial interface to a host controller vdd scl host microprocessor 20 pf 20 pf xtal 4-40 mhz xti xto gnd gnda fltcap 47 nf 0.1? 47 ? tant. vdda vdd +3.3v 27 w spfrx gpio5 si so/ sda sck/ scl ss reset int system reset system interrupt sckin wsb sckb sdb sdc sdd zr38601 dac dac dac left right left surround right surround center subwoofer data data data l/r l/r l/r dclk dclk dclk clk clk clk f s 64 f s 256 f s rs422 receiver mute d11 vdd figure 19. zr38601 typical configuration with the z2c serial interface to a host controller sda
46 zr38601 parallel host and parallel data figure 20 shown the connections for using the parallel port as the interface to a host controller for both control with commands and for the parallel data stream input. the zr38601 appears in the controller? address space as three registers: an 8-bit read/write command/response register, a 9-bit data input write-only register and as a 3-bit read-only flag regis- ter. the flag register permits getting error messages from the zr38601 (error) and the dreq and rdy bits are for pro- grammed transfers when the zr38601 is respectively a master or slave on the input data stream. or the rdy signal may be used directly for a hardware i/o transfer as shown when the zr38601 is a slave. figure 20. zr38601 connections with parallel port interface to host for commands and data input d14/rdy p/m vdd rd wr cs d[11:4]/pp[7:0] error/gpio1 wr rd host bus address address decode dreq /gpio0 d13/ c/d d12/err data rdy tri-state buffer host processor a d c cs command/data register error dreq 3 rdy flag register data data 8 zr38601 cs oe
47 zr38601 product support documentation this data sheet is a summary description of the zr38601? functional operation and command and response operation as well as electrical, timing and physical specifications. the complete source of information on its physical function and pro- grammed operation including instruction set is the ?r38650 users hardware manual? also available are the ?r38000 family simulator user? manual?and the ?r38000 family assembler/linker user? manual.? the following application notes are currently available that contain additional design related information: ?esigning with the zr38600 audio processor ?ass redirection for the zr38600 audio processor ?udio source type detection for the zr38600 audio processor? new application notes are added on a regular basis and are available from sales representatives. demonstration board the zr38600 demonstration board is a stand-alone dolby ac- 3 and mpeg audio decoder. the demonstration board is equipped with three high-quality, stereo 20-bit dacs and one stereo 20-bit adc for microphone or line input. the input bit- stream is fed to the board in s/pdif format. both optical and coaxial interfaces are supported. decoding and operation func- tions are selected via push buttons and a large lcd display is provided for status information. the demonstration board is equipped with a pc interface for controlling operation with the standard function commands and responses and for loading of custom programs. an ice interface is also available on the board. software development kit two software development tools provide all that is necessary to write, assemble, link, simulate, and debug programs in native zr38001 code for the zr38601. they run on a pentium pc under microsoft windows 95. the zr38000 family assem- bler/linker translates the assembly language code, including macros, to object code which can be linked with data files and other object code to generate a complete executable program file. the zr38000 family simulator accurately executes the program file while permitting full displays of registers and memory along with single-step operation and breakpoints for debugging. both are of modern design being highly interactive and with macro and symbolic naming support throughout. the zr38601 is software compatible with zoran? previous gen- eration zr38000 family devices.
48 zr38601 specifications - absolute maximum ratings storage temperature........................................ -65? to +150? supply voltage to ground potential continuous ........................................-0.5 to +4.5 volts dc voltage applied to outputs for high impedance output state..........................-0.5 to +5.5 volts dc input voltage ................................................ -0.5 to 5.5 volts dc output current, into outputs (not to exceed 200 ma total) ................................. 20 ma/output dc input current ................................................. -10 to +3.0 ma note: stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. specifications - operating range temperature .................................................... 0? t a +70? supply voltage ....................................... 3.15 v cc 3.45 volts specifications - dc characteristics symbol parameter min typ max units test conditions v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage 0.4 v i ol = 2 ma v oh output high voltage 2.4 v i oh = 0.4 ma i cc power supply current 300 350 ma f clkout = 50 mhz, v cc = 3.45 v i li input leakage current -- -- + 10 ? i pui input internal pull-up current source 50 ? i pdi input internal pull-down current sink 50 ? i lo output leakage current -- -- + 10 ? c in input capacitance 10 pf c io i/o and output capacitance 10 pf device under test 1.5v 2.4v 0.45v output input during ac testing, inputs are driven at 0.4v and 2.4v levels. unless otherwise specified, switching times are measured from the 1.5v level of dclk to the 0.8v or 2.0v levels at the input/output. 2.0v 0.8v 0.8v 2.0v figure 21. ac testing input, output 1.5v test point from output under test 50 pf figure 22. normal ac test load
49 zr38601 specifications - ac characteristics memory read ( f clkout = 50 mhz) parameter min max units notes output timing 1 read cycle duration 25 ns [1] 2 address hold from rd rising edge 1 ns 3 address setup to rd falling edge 2 ns 4rd pulse duration 11 ns [1] 5 rd after rd recovery time 6 ns 6wr after rd recovery time 6 ns input timing 7 data in hold from rd rising edge 0 ns 8rd low to data valid 4 ns 9 address stable, cs low to data valid 7 ns [1] 1. these speci?ations are for zero wait-state operation. for operation with wait states, add 1 or 7 external clock periods, as appropriate. figure 23. memory read a rd d wr cs 3 4 2 1 5 8 7 9 6
50 zr38601 memory write ( f clkout = 50 mhz) parameter (output timing) min max units notes 10 write cycle duration 25 ns [1] 11 address setup to wr falling edge 2 ns 12 wr pulse duration 11 ns [1] 13 address hold from wr rising edge 1 ns 14 data out setup to wr rising edge 6 ns [1] 15 data out hold from wr rising edge 1 ns 16 wr low to data out enabled 3 ns 17 wr after wr recovery time 6 ns 18 rd after wr recovery time 6 ns 19 data disable to rd after wr 4ns 20 wr falling edge to data valid 5 ns 21 address valid to wr rising edge 13 ns 1. these speci?ations are for zero wait-state operation. for operation with wait states, add 1 or 7 internal clock periods, as ap propriate. figure 24. memory write a wr d rd 11 12 13 10 17 14 15 19 18 20 16 21
51 zr38601 a-group serial ports (frame sync mode) parameter min max units notes input timing 22 scka high duration t clkout ns slave mode (ma = 0) 23 scka low duration t clkout ns slave mode (ma = 0) 24 fsa setup time to scka falling edge 15 ns slave mode (ma = 0) 25 fsa hold time from scka falling edge 15 ns slave mode (ma = 0) 26 sda, sde, sdf setup time to scka falling edge 15 ns 27 sda, sde, sdf hold time from scka falling edge 15 ns output timing 29 fsa output delay from scka rising edge 25 ns master mode (ma = 1) 30 scka period 8 t clkout 4096 t clkout ns master mode (ma = 1) figure 25. a-group serial ports (frame sync mode) scka fsa slave mode fsa master mode 24 24 25 26 27 25 22 23 30 29 29 1. mode ab = 0 sda,sde,sdf [1]
52 zr38601 a-group serial ports (word select mode) parameter min max units notes input timing 22 scka high duration t clkout ns slave mode (ma = 0) 23 scka low duration t clkout ns slave mode (ma = 0) 31 wsa setup time to scka rising edge 15 ns slave mode (ma = 0) 32 wsa hold time from scka rising edge 15 ns slave mode (ma = 0) 33 sda, sde, sdf setup time to scka rising edge 15 ns 36 sda, sde, sdf hold time from scka rising edge 15 ns output timing 30 scka period 8 t clkout 4096 t clkout ns master mode (ma = 1) 73 wsa output delay from scka falling edge 25 ns master mode (ma = 1) figure 26. a-group serial ports (word select mode) scka wsa slave mode wsa master mode sda, sde, sdf (note 1) 33 36 22 23 30 31 73 32 1. mode ab = 0
53 zr38601 b-group serial ports (frame sync mode) parameter min max units notes input timing 41 sckin low duration t clkout ns cb = 0 42 sckin high duration t clkout ns cb = 0 75 sckb high duration t clkout ns slave mode (mb = 0) 76 sckb low duration t clkout ns slave mode (mb = 0) 48 sdf setup time to sckb falling edge 15 ns mode ab = 1, cpb = 1 49 sdf hold time from sckb falling edge 15 ns mode ab = 1, cpb = 1 78 fsb setup time to sckb falling edge 15 ns slave mode (mb = 0), cpb = 1 79 fsb hold time from sckb falling edge 15 ns slave mode (mb = 0), cpb = 1 output timing 40 sckin period (t sckin )t clkout ns cb = 1 43 sckb period t sckin 8192 t sckin ns master mode (mb = 1), cb = 0 t audio 8192 t audio ns master mode (mb = 1), cb = 1 44 fsb delay from sckb rising edge 25 ns master mode (mb = 1) 45 sdb, sdc delay from sckb rising edge 25 ns figure 27. b-group serial ports (frame sync mode) sckin fsb slave mode fsb master mode sdf sckb 41 75 76 42 40 78 79 43 44 45, 47 48 49 79 78 1. mode ab = 0 2. mode ab = 1 sdb,sdc,sdd,sdg (note 1) (note 2)
54 zr38601 b-group serial ports (word select mode) parameter min max units notes input timing 50 sdf setup time to sckb rising edge 15 ns mode ab = 1 51 sdf hold time from sckb rising edge 15 ns mode ab = 1 52 wsb setup to sckb rising edge 15 ns slave mode (mb = 0) 53 wsb hold from sckb rising edge 15 ns slave mode (mb = 0) output timing 80 wsb delay from sckb falling edge 25 ns master mode (mb = 1) 81 sdb, sdc, sdd delay from sckb falling edge 25 ns figure 28. b-group serial ports (word select mode) wsb slave mode wsb master mode sdb, sdc, sdd, sdg sdf sckb 53 80 52 50 51 81 (note 2) (note 1) 1. mode ab = 0 2. mode ab = 1
55 zr38601 parallel host interface timing characteristics min max units notes 99 rd , wr high time 2 t clkout ns 100 rd , wr low time 2 t clkout ns 101 rd , wr cycle time 3 t clkout ns 102 data hold time from wr high 3 ns 103 data setup time to wr high 11 ns write cycle 104 data out delay from rd low 30 ns read cycle 105 cs setup to falling edge of rd , wr 0ns 106 cs hold from rising edge of rd , wr 1ns 107 cs low to cs low 30 ns 108 wr to rd , rd to wr timing 60 109 data hold time from rising edge of rd 16 ns 110 rdy delay time 2 t clkout ns figure 29. parallel host interface timing rd cs 107 106 wr 101 99 100 99 100 101 108 d[7:0], err, c/d (write cycle) 103 102 d[7:0] (read cycle) 104 109 rdy 110 105
56 zr38601 z2c serial host interface timing parameter min max units notes 201 scl/sck clock period 2.5 s 202 scl/sck clock high duration 0.6 s 203 scl/sck clock low duration 1.3 s 204 start condition setup time 0.6 s 205 start condition hold time 0.6 s 206 data setup time to scl/sck active edge 100 ns 207 data hold time from scl/sck active edge 0.0 ns 208 rise time of scl/sck and sda/so 300 ns 209 fall time of scl/sck and sda/so 300 ns 210 stop condition setup time 0.5 s 211 free time between stop and start condition 1.3 s figure 30. z2c serial host interface timing scl/sck sda/so 205 206 start 202 210 207 204 stop 203 209 208 201 211 start
57 zr38601 spi serial host interface timing external clocks parameter min max units notes 111 sck/scl clock period 6 t clkout ?s [1] 112 sck/scl clock high duration 3 t clkout ?s 113 sck/scl clock low duration 3 t clkout ?s 114 ss setup time to first sck/scl edge 10 ns 115 ss hold time from last edge of sck/scl 10 ns 116 si setup time to sck/scl active edge 10 ns 117 si hold time from sck/scl active edge 10 ns 118 ss negation to data hi-z 10 ns 119 so/sda delay from sck/scl active edge 20 ns 1. sck polarity is controlled by field sckp of register spimode. the polarity shown in figure 31 corresponds to sckp=0. figure 31. spi serial host interface timing ss sck/scl (sckp=0) so/sda si 114 119 116 113 112 111 115 118 117 parameter min max units notes 56 xti period (t xti ) 25 250 ns 57 xti high duration 10 ns 58 xti low duration 10 ns 55 clkout period (t clkout ) 20 250 ns figure 32. external clocks clkout 55 57 xti 58 56
58 zr38601 external interrupt reset timing parameter min max units notes 63 int setup time 6 ns [1] 64 int hold time 5 ns [1] 65 int duration 2 t clkout ns 1. for testing only. synchronous operation is not required. figure 33. external interrupt clkout int 63 64 65 parameter min max units notes 59 reset duration, warm reset 16 t xti 127 t xti ns 60 reset duration, cold reset 200 t xti ns [1] 61 memory bus enable after reset rising edge, warm reset t xti +10 2 t xti +15 ns 62 memory bus disable after reset falling edge t xti +10 2 t xti +15 ns 1. applies to the power-up sequence. the rising edge of reset must occur after the crystal oscillator or external clock frequency and amplitude have stabilized. after the rising edge of a cold reset , 4096 clock cycles are required for initialization of the internal phase locked loop, during which the processor is inactive. any sub- sequent reset pulse of 128 clocks or longer is interpreted as a cold reset and will start a new initialization of the phase loc ked loop. figure 34. warm/cold reset 62 xti 59, 60 reset cs 61
59 zr38601 ice interface timing parameter min max units notes 121 tck clock period 4 t clkout ?s 122 tck clock high duration 2 t clkout ?s 123 tck clock low duration 2 t clkout ?s 124 tdo negation to data hi-z 15 ns 125 tdo delay from falling edge of tck 15 ns 126 tdi hold time from rising edge of tck 10 ns 127 tdi setup time to rising edge of tck 10 ns 128 tms hold time from rising edge of tck 10 ns 129 tms setup time to rising edge of tck 10 ns figure 35. ice interface timing tdi tms 122 123 121 tck tdo 125 126 128 127 129 124
60 zr38601 pinout information table 24: 100-pin pqfp pin assignment by pin number pin # pin name pin # pin name pin # pin name pin # pin name pin # pin name 1 a0 21 a6 41 d7/pp3 61 spfrx 81 vdd 2 gnd 22 d11/pp7 42 d6/pp2 62 p/m 82 reset 3 ss 23 gpio3 43 a14 63 xto 83 sda 4 tms 24 a7 44 gnd 64 xti 84 vdd 5 int 25 a8 45 vdd 65 gnd 85 sde 6 vdd 26 d10/pp6 46 a15 66 sckin 86 tck 7 d14/rdy 27 a9 47 d5/pp1 67 vdd 87 sck/scl 8 gnd 28 a10 48 d4/pp0 68 gnda 88 tdi 9 a1 29 gnd 49 a16 69 fltcap 89 si 10 a2 30 vdd 50 rd 70 vdda 90 gnd 11 a3 31 a11 51 wr 71 gnd 91 scka 12 vdd 32 d9/pp5 52 cs 72 clkout 92 wsa/fsa 13 d13/ c/d 33 d8/pp4 53 gnd 73 d19 93 vdd 14 mute /gpio5 34 so/sda 54 sdd 74 d18 94 sdf 15 d12/err 35 vdd 55 vdd 75 a17 95 wsb/fsb 16 a4 36 gnd 56 gpio2 76 a18 96 d17 17 vdd 37 gnd 57 error/gpio1 77 a19 97 sckb 18 gpio4 38 a12 58 dreq /gpio0 78 gnd 98 d16 19 gnd 39 tdo 59 vdd 79 sdc 99 sdg/spftx 20 a5 40 a13 60 bypass 80 sdb 100 d15 table 25: 100-pin pqfp pin assignment by alphabetical signal name pin name pin # pin name pin # pin name pin # pin name pin # pin name pin # a0 1 bypass 60 error/gpio1 57 p/m 62 tdo 39 a1 9 clkout 72 fltcap 69 rd 50 tms 4 a10 28 cs 52 gnd 2 reset 82 vdd 6 a11 31 d10/pp6 26 gnd 8 sck/scl 87 vdd 12 a12 38 d11/pp7 22 gnd 19 scka 91 vdd 17 a13 40 d12/err 15 gnd 29 sckb 97 vdd 30 a14 43 d13/ c/d 13 gnd 36 sckin 66 vdd 35 a15 46 d14/rdy 7 gnd 37 sda 83 vdd 45 a16 49 d15 100 gnd 44 sdb 80 vdd 55 a17 75 d16 98 gnd 53 sdc 79 vdd 59 a18 76 d17 96 gnd 65 sdd 54 vdd 67 a19 77 d18 74 gnd 71 sde 85 vdd 81 a2 10 d19 73 gnd 78 sdf 94 vdd 84 a3 11 d4/pp0 48 gnd 90 sdg/spftx 99 vdd 93 a4 16 d5/pp1 47 gnda 68 si 89 vdda 70 a5 20 d6/pp2 42 gpio2 56 so/sda 34 wr 51 a6 21 d7/pp3 41 gpio3 23 spfrx 61 wsa/fsa 92 a7 24 d8/pp4 33 gpio4 18 ss 3 wsb/fsb 95 a8 25 d9/pp5 32 int 5 tck 86 xti 64 a9 27 dreq /gpio0 58 mute /gpio5 14 tdi 88 xto 63
61 zr38601 table 26: 100-pin pqfp pin assignment by functional signal name name number name number name number name number name number parallel port (40) a19 77 a11 31 a3 11 d15 100 d7/pp3 41 a18 76 a10 28 a2 10 d14/rdy 7 d6/pp2 42 a17 75 a9 27 a1 9 d13/ c/d 13 d5/pp1 47 a16 49 a8 25 a0 1 d12/err 15 d4/pp0 48 a15 46 a7 24 d19 73 d11/pp7 22 cs 52 a14 43 a6 21 d18 74 d10/pp6 26 rd 50 a13 40 a5 20 d17 96 d9/pp5 32 wr 51 a12 38 a4 16 d16 98 d8/pp4 33 p/m 62 serial ports (13) spfrx 61 sdf 94 sdb 80 sdg/spftx 99 sckin 66 sda 83 wsa/fsa 92 sdc 79 wsb/fsb 95 sde 85 scka 91 sdd 54 sckb 97 general purpose ports (6) mute /gpio5 14 gpio3 23 error/gpio1 57 gpio4 18 gpio2 56 dreq /gpio0 58 serial host interface (4) si 89 so/sda 34 sck/scl 87 ss 3 ice interface (4) tdi 88 tdo 39 tck 86 tms 4 system interface (7) int 5 xti 64 clkout 72 fltcap 69 reset 82 xto 63 bypass 60 power (26) vdd 6 vdd 55 vdda 70 gnd 37 gnd 90 vdd 12 vdd 59 gnd 2 gnd 44 gnda 68 vdd 17 vdd 67 gnd 8 gnd 53 vdd 30 vdd 81 gnd 19 gnd 65 vdd 35 vdd 84 gnd 29 gnd 71 vdd 45 vdd 93 gnd 36 gnd 78
62 zr38601 a0 gnd ss tms int vdd d14/rdy gnd a1 a2 a3 vdd d13/ c/d mute /gpio5 d12/err a4 vdd gpio4 gnd a5 a6 d11/pp7 gpio3 a7 a8 d10/pp6 a9 a10 gnd vdd a11 d9/pp5 d8/pp4 so/sda vdd gnd a12 tdo a13 d7/pp3 d6/pp2 a14 gnd vdd a15 d5/pp1 d4/pp0 a16 rd gnd sdb sdc gnd a19 a18 a17 d18 d19 clkout gnd vdda fltcap gnda vdd sckin gnd xti xto p/m spfrx bypass vdd dreq /gpio0 error/gpio1 gpio2 vdd sdd gnd cs wr d15 sdg/spftx d16 sckb d17 wsb/fsb sdf vdd wsa/fsa scka gnd si tdi sck/scl tck sde vdd sda reset vdd pin 1 index mark, notched corner, or both zr38601 (top view) 1 30 51 80 100 31 50 81 figure 36. zr38601 pin out diagram
63 zr38601 .012 .004 (.30 .1) .0256 typ (.65 .15) .782 .010 (20.00 .20) .551 .008 (14.00 .20) .007 +.0015/-.003 (.18 +.04/-.08) .031 .008 (.8 .2) seating plane .705 .015 (17.9 .4) .118 .014 (3.00 .35) .015 +.005/-.015 (.38 +.13/-.38) top view .941 .015 (23.9 .4) pin 1 index area (note 1) 0.106 .01 (2.69 0.25 notes: 1. 2. 3. pin 1 index may be corner chamfer, dot or both. principal dimensions in inches, dimensions in brackets in (millimeters). top and bottom mold marks shown for indication only. location may very except for pin 1 index area. .006 (.15) figure 37. zr38601 plastic quad flat pack dimensions
ds38601-0299 the material in this product brief is for information only. zoran corporation assumes no responsibility for errors or omissions and reserves the right to change, without notice, product speci?ations, operating characteristics, packaging, etc. zoran corporation assumes no liability for damage resulting from the use of information contained in this document. all brand, product, and company names are trademarks or registered trademarks of their respective companies. zr38601 ordering information sales offices zr 38601 pq c screening key package part number prefix package screening key c - 0 c to +70 c (v cc = 3.15 v to 3.45 v) pq - plastic quad flat pack (eiaj) note: dolby licensing: ac-3 and pro logic usage is available only to licensees of dolby laboratories licensing corporation, san francisco, ca 94111, u sa, +1 (415) 558-0200, from whom licensing and application information must be obtained. dolby is a registered trade-mark of dolby laboratories licensing corporation. u.s. headquarters n zoran corporation 3112 scott blvd. santa clara, ca 95054 usa telephone: +1 (408) 919-4111 fax: +1 (408) 919-4122 israel operations n zoran microelectronics, ltd. advanced technology center p.o. box 2495 haifa, 31024 israel telephone: +972 4 8545-777 fax: +972 4 8551-550 canada n zoran toronto labs 2157 queen street east suite 302 toronto, ontario, canada m4e 1es telephone: +1 (416) 690-3356 fax: +1 (416) 690-3363 japan n zoran sales of?e 2-26-2 sasazuka shibuya-ku, tokyo 151 japan telephone: +81 3 5352-0971 fax: +81 3 5352-0972 p. r. china n zoran china of?e (shenzhen) suite 1706, grand skylight hotel 8 central shennan road shenzhen, guangdong 518041 p. r. china telephone: +86 755-3363225 mobile phone: +86 139-2704950 fax: +86 755-3363256

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