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2486ls?avr?10/03 features high-performance, low-power avr ? 8-bit microcontroller advanced risc architecture ? 130 powerful instructions ? most single-clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier nonvolatile program and data memories ? 8k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 1k byte internal sram ? programming lock for software security peripheral features ? two 8-bit timer/counters with separate prescaler, one compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? three pwm channels ? 8-channel adc in tqfp and mlf package six channels 10-bit accuracy two channels 8-bit accuracy ? 6-channel adc in pdip package four channels 10-bit accuracy two channels 8-bit accuracy ? byte-oriented two-wire serial interface ? programmable serial usart ? master/slave spi serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise reduction, power-save, power-down, and standby i/o and packages ? 23 programmable i/o lines ? 28-lead pdip, 32-lead tqfp, and 32-pad mlf operating voltages ? 2.7 - 5.5v (ATMEGA8L) ? 4.5 - 5.5v (atmega8) speed grades ? 0 - 8 mhz (ATMEGA8L) ? 0 - 16 mhz (atmega8) power consumption at 4 mhz, 3v, 25 c ? active: 3.6 ma ? idle mode: 1.0 ma ? power-down mode: 0.5 a 8-bit with 8k bytes in-system programmable flash atmega8 ATMEGA8L summary rev. 2486ls?avr?10/03 note: this is a summary document. a complete document is available on our web site at www.atmel.com.
2 atmega8(l) 2486ls?avr?10/03 pin configurations 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (int1) pd3 (xck/t0) pd4 gnd vcc gnd vcc (xtal1/tosc1) pb6 (xtal2/tosc2) pb7 pc1 (adc1) pc0 (adc0) adc7 gnd aref adc6 avcc pb5 (sck) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (t1) pd5 (ain0) pd6 (ain1) pd7 (icp1) pb0 (oc1a) pb1 (ss/oc1b) pb2 (mosi/oc2) pb3 (miso) pb4 pd2 (int0) pd1 (txd) pd0 (rxd) pc6 (reset) pc5 (adc5/scl) pc4 (adc4/sda) pc3 (adc3) pc2 (adc2) tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (reset) pc6 (rxd) pd0 (txd) pd1 (int0) pd2 (int1) pd3 (xck/t0) pd4 vcc gnd (xtal1/tosc1) pb6 (xtal2/tosc2) pb7 (t1) pd5 (ain0) pd6 (ain1) pd7 (icp1) pb0 pc5 (adc5/scl) pc4 (adc4/sda) pc3 (adc3) pc2 (adc2) pc1 (adc1) pc0 (adc0) gnd aref avcc pb5 (sck) pb4 (miso) pb3 (mosi/oc2) pb2 (ss/oc1b) pb1 (oc1a) pdip 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 mlf top view (int1) pd3 (xck/t0) pd4 gnd vcc gnd vcc (xtal1/tosc1) pb6 (xtal2/tosc2) pb7 pc1 (adc1) pc0 (adc0) adc7 gnd aref adc6 avcc pb5 (sck) (t1) pd5 (ain0) pd6 (ain1) pd7 (icp1) pb0 (oc1a) pb1 (ss/oc1b) pb2 (mosi/oc2) pb3 (miso) pb4 pd2 (int0) pd1 (txd) pd0 (rxd) pc6 (reset) pc5 (adc5/scl) pc4 (adc4/sda) pc3 (adc3) pc2 (adc2)
3 atmega8(l) 2486ls?avr?10/03 overview the atmega8 is a low-power cmos 8-bit microcontroller based on the avr risc architecture. by executing powerful instructions in a single clock cycle, the atmega8 achieves throughputs approaching 1 mips per mhz, allowing the system designer to optimize power consumption versus processing speed. block diagram figure 1. block diagram internal oscillator oscillator watchdog timer mcu ctrl. & timing oscillator timers/ counters interrupt unit stack pointer eeprom sram status register usart program counter program flash instruction register instruction decoder programming logic spi adc interface comp. interface portc drivers/buffers portc digital interface general purpose registers x y z alu + - portb drivers/buffers portb digital interface portd digital interface portd drivers/buffers xtal1 xtal2 control lines vcc gnd mux & adc agnd aref pc0 - pc6 pb0 - pb7 pd0 - pd7 avr cpu twi reset
4 atmega8(l) 2486ls?avr?10/03 the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega8 provides the following features: 8k bytes of in-system programmable flash with read-while-write capabilities, 512 bytes of eeprom, 1k byte of sram, 23 general purpose i/o lines, 32 general purpose working registers, three flexible timer/counters with compare modes, internal and external interrupts, a serial program- mable usart, a byte oriented two-wire serial interface, a 6-channel adc (eight channels in tqfp and mlf packages) where four (six) channels have 10-bit accuracy and two channels have 8-bit accuracy, a programmable watchdog timer with internal oscillator, an spi serial port, and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hard- ware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crys- tal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low-power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the flash program memory can be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self- programmable flash on a monolithic chip, the atmel atmega8 is a powerful microcon- troller that provides a highly-flexible and cost-effective solution to many embedded control applications. the atmega8 avr is supported with a full suite of program and system development tools, including c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized.
5 atmega8(l) 2486ls?avr?10/03 pin descriptions vcc digital supply voltage. gnd ground. port b (pb7..pb0) xtal1/ xtal2/tosc1/tosc2 port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. depending on the clock selection fuse settings, pb6 can be used as input to the invert- ing oscillator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pb7 can be used as output from the inverting oscillator amplifier. if the internal calibrated rc oscillator is used as chip clock source, pb7..6 is used as tosc2..1 input for the asynchronous timer/counter2 if the as2 bit in assr is set. the various special features of port b are elaborated in ?alternate functions of port b? on page 56 and ?system clock and clock options? on page 23. port c (pc5..pc0) port c is an 7-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. pc6/reset if the rstdisbl fuse is programmed, pc6 is used as an i/o pin. note that the electri- cal characteristics of pc6 differ from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pc6 is used as a reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 15 on page 36. shorter pulses are not guaranteed to generate a reset. the various special features of port c are elaborated on page 59. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega8 as listed on page 61. reset reset input. a low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 15 on page 36. shorter pulses are not guaranteed to generate a reset.
6 atmega8(l) 2486ls?avr?10/03 avc c avcc is the supply voltage pin for the a/d converter, port c (3..0), and adc (7..6). it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. note that port c (5..4) use digital supply voltage, v cc . aref aref is the analog reference pin for the a/d converter. adc7..6 (tqfp and mlf package only) in the tqfp and mlf package, adc7..6 serve as analog inputs to the a/d converter. these pins are powered from the analog supply and serve as 10-bit adc channels.
7 atmega8(l) 2486ls?avr?10/03 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c 9 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 11 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 11 0x3c (0x5c) reserved 0x3b (0x5b) gicr int1 int0 ? ? ? ? ivsel ivce 47, 65 0x3a (0x5a) gifr intf1 intf0 ? ? ? ? ? ?66 0x39 (0x59) timsk ocie2 toie2 ticie1 ocie1a ocie1b toie1 ? toie0 70, 100, 120 0x38 (0x58) tifr ocf2 tov2 icf1 ocf1a ocf1b tov1 ? tov0 71, 101, 120 0x37 (0x57) spmcr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen 209 0x36 (0x56) twcr twint twea twsta twsto twwc twen ?twie 167 0x35 (0x55) mcucr se sm2 sm1 sm0 isc11 isc10 isc01 isc00 31, 64 0x34 (0x54) mcucsr ? ? ? ? wdrfborfextrf porf 39 0x33 (0x53) tccr0 ? ? ? ? ? cs02 cs01 cs00 70 0x32 (0x52) tcnt0 timer/counter0 (8 bits) 70 0x31 (0x51) osccal oscillator calibration register 29 0x30 (0x50) sfior ? ? ? ? acme pud psr2 psr10 56, 73, 121, 189 0x2f (0x4f) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b wgm11 wgm10 95 0x2e (0x4e) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 98 0x2d (0x4d) tcnt1h timer/counter1 ? counter register high byte 99 0x2c (0x4c) tcnt1l timer/counter1 ? counter register low byte 99 0x2b (0x4b) ocr1ah timer/counter1 ? output compare register a high byte 99 0x2a (0x4a) ocr1al timer/counter1 ? output compare register a low byte 99 0x29 (0x49) ocr1bh timer/counter1 ? output compare register b high byte 99 0x28 (0x48) ocr1bl timer/counter1 ? output compare register b low byte 99 0x27 (0x47) icr1h timer/counter1 ? input capture register high byte 100 0x26 (0x46) icr1l timer/counter1 ? input capture register low byte 100 0x25 (0x45) tccr2 foc2 wgm20 com21 com20 wgm21 cs22 cs21 cs20 115 0x24 (0x44) tcnt2 timer/counter2 (8 bits) 117 0x23 (0x43) ocr2 timer/counter2 output compare register 117 0x22 (0x42) assr ? ? ? ? as2 tcn2ub ocr2ub tcr2ub 117 0x21 (0x41) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 41 0x20 (1) (0x40) (1) ubrrh ursel ? ? ? ubrr[11:8] 154 ucsrc ursel umsel upm1 upm0 usbs ucsz1 ucsz0 ucpol 152 0x1f (0x3f) eearh ? ? ? ? ? ? ? eear8 18 0x1e (0x3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 18 0x1d (0x3d) eedr eeprom data register 18 0x1c (0x3c) eecr ? ? ? ? eerie eemwe eewe eere 18 0x1b (0x3b) reserved 0x1a (0x3a) reserved 0x19 (0x39) reserved 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 63 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 63 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 63 0x15 (0x35) portc ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 63 0x14 (0x34) ddrc ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 63 0x13 (0x33) pinc ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 63 0x12 (0x32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 63 0x11 (0x31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 63 0x10 (0x30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 63 0x0f (0x2f) spdr spi data register 128 0x0e (0x2e) spsr spif wcol ? ? ? ? ?spi2x 128 0x0d (0x2d) spcr spie spe dord mstr cpol cpha spr1 spr0 126 0x0c (0x2c) udr usart i/o data register 149 0x0b (0x2b) ucsra rxc txc udre fe dor pe u2x mpcm 150 0x0a (0x2a) ucsrb rxcie txcie udrie rxen txen ucsz2 rxb8 txb8 151 0x09 (0x29) ubrrl usart baud rate register low byte 154 0x08 (0x28) acsr acd acbg aco aci acie acic acis1 acis0 190 0x07 (0x27) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 201 0x06 (0x26) adcsra aden adsc adfr adif adie adps2 adps1 adps0 203 0x05 (0x25) adch adc data register high byte 204 0x04 (0x24) adcl adc data register low byte 204 0x03 (0x23) twdr two-wire serial interface data register 169 0x02 (0x22) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 170
8 atmega8(l) 2486ls?avr?10/03 notes: 1. refer to the usart description for details on how to access ubrrh and ucsrc. 2. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 0x01 (0x21) twsr tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 169 0x00 (0x20) twbr two-wire serial interface bit rate register 167 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
9 atmega8(l) 2486ls?avr?10/03 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1 / 2 / 3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1 / 2 / 3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 mnemonics operands description operation flags #clocks
10 atmega8(l) 2486ls?avr?10/03 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 mnemonics operands description operation flags #clocks instruction set summary (continued)
11 atmega8(l) 2486ls?avr?10/03 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued)
12 atmega8(l) 2486ls?avr?10/03 ordering information note: this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa tion and minimum quantities. speed (mhz) power supply ordering code package operation range 8 2.7 - 5.5 ATMEGA8L-8ac ATMEGA8L-8pc ATMEGA8L-8mc 32a 28p3 32m1-a commercial (0 c to 70 c) ATMEGA8L-8ai ATMEGA8L-8pi ATMEGA8L-8mi 32a 28p3 32m1-a industrial (-40 c to 85 c) 16 4.5 - 5.5 atmega8-16ac atmega8-16pc atmega8-16mc 32a 28p3 32m1-a commercial (0 c to 70 c) atmega8-16ai atmega8-16pi atmega8-16mi 32a 28p3 32m1-a industrial (-40 c to 85 c)
13 atmega8(l) 2486ls?avr?10/03 package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm micro lead frame package (mlf)
14 atmega8(l) 2486ls?avr?10/03 packaging information 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note
15 atmega8(l) 2486ls?avr?10/03 28p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p3 , 28-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 28p3 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb b2 (4 places) common dimensions (unit of measure = mm) symbol min nom max note a 4.5724 a1 0.508 d 34.544 ? 34.798 note 1 e 7.620 8.255 e1 7.112 7.493 note 1 b 0.381 0.533 b1 1.143 1.397 b2 0.762 1.143 l 3.175 3.429 c 0.203 0.356 eb 10.160 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 atmega8(l) 2486ls?avr?10/03 32m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32m1-a , 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm micro lead frame package (mlf) c 32m1-a 01/15/03 common dimensions (unit of measure = mm) symbol min nom max note pin 1 id d1 d e1 e e b a3 a2 a1 a d2 e2 0.08 c l 1 2 3 p p 0 1 2 3 a 0.80 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d 5.00 bsc d1 4.75 bsc d2 2.95 3.10 3.25 e 5.00 bsc e1 4.75bsc e2 2.95 3.10 3.25 e 0.50 bsc l 0.30 0.40 0.50 p ? ? 0.60 ? ? 12 o notes: 1. jedec standard mo-220, fig. 2 (anvil singulation), vhhd-2. top view side view bottom view 0 pin 1 id
17 atmega8(l) 2486ls?avr?10/03 erratas the revision letter in this section refers to the revision of the atmega8 device. atmega8 rev. d, e, f, and g ckopt does not enable internal capacitors on xtaln/toscn pins when 32 khz oscillator is used to clock the asynchronous timer/counter2 1. ckopt does not enable internal capacitors on xtaln/toscn pins when 32 khz oscillator is used to clock the asynchronous timer/counter2 when the internal rc oscillator is used as the main clock source, it is possible to run the timer/counter2 asynchronously by connecting a 32 khz oscillator between xtal1/tosc1 and xtal2/tosc2. but when the internal rc oscillator is selected as the main clock source, the ckopt fuse does not control the internal capacitors on xtal1/tosc1 and xtal2/tosc2. as long as there are no capacitors con- nected to xtal1/tosc1 and xtal2/tosc2, safe operation of the oscillator is not guaranteed. problem fix/workaround use external capacitors in the range of 20 - 36 pf on xtal1/tosc1 and xtal2/tosc2. this will be fixed in atmega8 rev. g where the ckopt fuse will control internal capacitors also when internal rc oscillator is selected as main clock source. for atmega8 rev. g, ckopt = 0 (programmed) will enable the internal capacitors on xtal1 and xtal2. customers who want compatibility between rev. g and older revisions, must ensure that ckopt is unprogrammed (ckopt = 1).
18 atmega8(l) 2486ls?avr?10/03 datasheet change log for atmega8 this document contains a log on the changes made to the datasheet for atmega8. changes from rev. 2486k-08/03 to rev. 2486l-10/03 all page numbers refers to this document. 1. removed ?preliminary? and tbds from the datasheet. 2. renamed icp to icp1 in the datasheet. 3. removed instructions call and jmp from the datasheet. 4. updated t rst in table 15 on page 36, v bg in table 16 on page 40, table 100 on page 238 and table 102 on page 240. 5. replaced text ?xtal1 and xtal2 should be left unconnected (nc)? after table 9 in ?calibrated internal rc oscillator? on page 28. added text regard- ing xtal1/xtal2 and ckopt fuse in ?timer/counter oscillator? on page 30. 6. updated watchdog timer code examples in ?timed sequences for changing the configuration of the watchdog timer? on page 43. 7. removed bit 4, adhsm, from ?special function io register ? sfior? on page 56. 8. added note 2 to figure 103 on page 211. 9. updated item 4 in the ?serial programming algorithm? on page 232. 10. added t wd_fuse to table 97 on page 233 and updated read calibration byte, byte 3, in table 98 on page 234. 11. updated absolute maximum ratings* and dc characteristics in ?electrical characteristics? on page 236. changes from rev. 2486j-02/03 to rev. 2486k-08/03 all page numbers refers to this document. 1. updated v bot values in table 15 on page 36. 2. updated ?adc characteristics? on page 242. 3. updated ?atmega8 typical characteristics? on page 243. 4. updated ?erratas? on page 17. changes from rev. 2486i-12/02 to rev. 2486j-02/03 all page numbers refers to this document. 1. improved the description of ?asynchronous timer clock ? clkasy? on page 24. 2. removed reference to the ?multipurpose oscillator? application note and the ?32 khz crystal oscillator? application note, which do not exist.
19 atmega8(l) 2486ls?avr?10/03 3. corrected ocn waveforms in figure 38 on page 88. 4. various minor timer 1 corrections. 5. various minor twi corrections. 6. added note under ?filling the temporary buffer (page loading)? on page 212 about writing to the eeprom during an spm page load. 7. removed adhsm completely. 8. added section ?eeprom write during power-down sleep mode? on page 21. 9. removed xtal1 and xtal2 description on page 5 because they were already described as part of ?port b (pb7..pb0) xtal1/ xtal2/tosc1/tosc2? on page 5. 10. improved the table under ?spi timing characteristics? on page 240 and removed the table under ?spi serial programming characteristics? on page 235. 11. corrected pc6 in ?alternate functions of port c? on page 59. 12. corrected pb6 and pb7 in ?alternate functions of port b? on page 56. 13. corrected 230.4 mbps to 230.4 kbps under ?examples of baud rate setting? on page 155. 14. added information about pwm symmetry for timer 2 in ?phase correct pwm mode? on page 111. 15. added thick lines around accessible registers in figure 76 on page 165. 16. changed ?will be ignored? to ?must be written to zero? for unused z-pointer bits under ?performing a page write? on page 212. 17. added note for rstdisbl fuse in table 87 on page 219. 18.updated drawings in ?packaging information? on page 14. changes from rev. 2486h-09/02 to rev. 2486i-12/02 1.added errata for rev d, e, and f on page 17. changes from rev. 2486g-09/02 to rev. 2486h-09/02 1.changed the endurance on the flash to 10,000 write/erase cycles. changes from rev. 2486f-07/02 to rev. 2486g-09/02 all page numbers refers to this document. 1 updated table 103, ?adc characteristics,? on page 242.
20 atmega8(l) 2486ls?avr?10/03 changes from rev. 2486e-06/02 to rev. 2486f-07/02 all page numbers refers to this document. 1 changes in ?digital input enable and sleep modes? on page 53. 2 addition of ocs2 in ?mosi/oc2 ? port b, bit 3? on page 57. 3 the following tables has been updated: table 51, ?cpol and cpha functionality,? on page 129, table 59, ?ucpol bit set- tings,? on page 154, table 72, ?analog comparator multiplexed input(1),? on page 191, table 73, ?adc conversion time,? on page 196, table 75, ?input chan- nel selections,? on page 202, and table 84, ?explanation of different variables used in figure 103 and the mapping to the z-pointer,? on page 217. 5 changes in ?reading the calibration byte? on page 229. 6 corrected errors in cross references. changes from rev. 2486d-03/02 to rev. 2486e-06/02 all page numbers refers to this document. 1 updated some preliminary test limits and characterization data the following tables have been updated: table 15, ?reset characteristics,? on page 36, table 16, ?internal voltage refer- ence characteristics,? on page 40, dc characteristics on page 236, table , ?adc characteristics,? on page 242. 2 changes in external clock frequency added the description at the end of ?external clock? on page 30. added period changing data in table 99, ?external clock drive,? on page 238. 3 updated twi chapter more details regarding use of the twi bit rate prescaler and a table 65, ?twi bit rate prescaler,? on page 169. changes from rev. 2486c-03/02 to rev. 2486d-03/02 all page numbers refers to this document. 1 updated typical start-up times. the following tables has been updated: table 5, ?start-up times for the crystal oscillator clock selection,? on page 26, table 6, ?start-up times for the low-frequency crystal oscillator clock selection,? on page 26, table 8, ?start-up times for the external rc oscillator clock selec- tion,? on page 27, and table 12, ?start-up times for the external clock selection,? on page 30. 2 added ?atmega8 typical characteristics? on page 243. changes from rev. 2486b-12/01 to rev. 2486c-03/02 all page numbers refers to this document. 1 updated twi chapter. more details regarding use of the twi power-down operation and using the twi as master with low twbrr values are added into the datasheet. added the note at the end of the ?bit rate generator unit? on page 166.
21 atmega8(l) 2486ls?avr?10/03 added the description at the end of ?address match unit? on page 166. 2 updated description of osccal calibration byte. in the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 mhz oscillator selections. this is now added in the following sections: improved description of ?oscillator calibration register ? osccal? on page 29 and ?calibration byte? on page 220. 3 added some preliminary test limits and characterization data. removed some of the tbd?s in the following tables and pages: table 3 on page 24, table 15 on page 36, table 16 on page 40, table 17 on page 42, ?ta = -40c to 85c, vcc = 2.7v to 5.5v (unless otherwise noted)? on page 236, table 99 on page 238, and table 102 on page 240. 4 updated programming figures. figure 104 on page 221 and figure 112 on page 231 are updated to also reflect that avcc must be connected during programming mode. 5 added a description on how to enter parallel programming mode if reset pin is disabled or if external oscillators are selected. added a note in section ?enter programming mode? on page 223.
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