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1 1 meg x 16 edo dram d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram products and specifications discussed herein are subject to change by micron without notice. key timing parameters speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 15ns 8ns -6 104ns 60ns 25ns 30ns 17ns 10ns features ? jedec- and industry-standard x16 timing, functions, pinouts, and packages ? high-performance cmos silicon-gate process ? single power supply (+3.3v 0.3v or 5v 10%) ? all inputs, outputs and clocks are ttl-compatible ? refresh modes: ras#-only, cas#-before-ras# (cbr), hidden; optional self refresh (s) ? byte write access cycles ? 1,024-cycle refresh (10 row, 10 column addresses) ? extended data-out (edo) page mode access ? 5v-tolerant inputs and i/os on 3.3v devices options marking ? voltages 1 3.3v lc 5v c ? refresh addressing 1,024 (1k) rows e5 ? packages plastic soj (400 mil) dj plastic tsop (400 mil) tg ? timing 50ns access -5 60ns access -6 ? refresh rates standard refresh (16ms period) none self refresh (128ms period) s 2 ? operating temperature range commercial (0 o c to +70 o c) none extended (-20 o c to +80 o c) et part number example: mt4lc1m16e5tg-6 note: 1. the third field distinguishes the low voltage offering: lc desig- nates vcc = 3.3v and c designates vcc = 5v. 2. available only on mt4lc1m16e5 (3.3v) pin assignment (top view) 44/50-pin tsop 42-pin soj 1 meg x 16 edo dram part numbers part number vcc refresh package refresh mt4lc1m16e5dj-x 3.3v 1k 400-soj standard mt4lc1m16e5dj-x s 3.3v 1k 400-soj self mt4lc1m16e5tg-x 3.3v 1k 400-tsop standard mt4lc1m16e5tg-x s 3.3v 1k 400-tsop self mt4c1m16e5dj-x 5v 1k 400-soj standard mt4c1m16e5tg-x 5v 1k 400-tsop standard note: -x indicates speed grade marking under timing options. edo dram mt4c1m16e5 C 1 meg x 16, 5v mt4lc1m16e5 C 1 meg x 16, 3.3v for the latest data sheet, please refer to the micron web site: www.micron.com/products/datasheets/sdramds.html note: the "#" symbol indicates signal is active low. v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc nc nc we# ras# nc nc a0 a1 a2 a3 v cc 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc nc casl# cash# oe# a9 a8 a7 a6 a5 a4 v ss v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc nc we# ras# nc nc a0 a1 a2 a3 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc casl# cash# oe# a9 a8 a7 a6 a5 a4 v ss general description the 1 meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration. the 1 meg x 16 has both byte write and word write access cycles via two cas# pins (casl# and cash#). these function like a single cas# found on other drams in that either casl# or cash# will generate an internal cas#. the cas# function and timing are determined by the first cas# (casl# or cash#) to transition low and the last cas# to transition back high. using only one
2 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram figure 1 oe# control of dqs v v ih il casl#/cash# v v ih il ras# v v ih il addr row column (a) column (b) dont care undefined v v ih il oe# v v ioh iol open dq t od valid data (b) valid data (a) column (c) valid data (a) t oe valid data (c) column (d) valid data (d) t od t oehc t od t oep t oes the dqs go back to low-z if t oes is met. the dqs remain high-z until the next cas# cycle if t oehc is met. the dqs remain high-z until the next cas# cycle if t oep is met. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we or cas# (casl# or cash#), whichever occurs last. an early write occurs when we is taken low prior to either cas# falling. a late write or read-modify- write occurs when we falls after cas# (casl# or cash#) was taken low. during early write cycles, the data outputs (q) will remain high-z, regardless of the state of oe#. during late write or read- modify-write cycles, oe# must be taken high to disable the data outputs prior to applying input data. if a late write or read-modify-write is attempted while keeping oe# low, no write will occur, and the data outputs will drive read data from the accessed location. the 16 data inputs and 16 data outputs are routed through 16 pins using common i/o. pin direction is controlled by oe# and we#. the 1 meg x 16 dram must be refreshed periodi- cally in order to retain stored data. of the two signals results in a byte write cycle. casl# transitioning low selects an access cycle for the lower byte (dq0-dq7), and cash# transitioning low se- lects an access cycle for the upper byte (dq8-dq15). each bit is uniquely addressed through the 20 ad- dress bits during read or write cycles. these are entered 10 bits (a0-a9) at a time. ras# is used to latch the first 10 bits and cas#, the latter 10 bits. the cas# function also determines whether the cycle will be a refresh cycle (ras# only) or an active cycle (read, write or read-write) once ras# goes low. the casl# and cash# inputs internally generate a cas# signal that functions like the single cas# input on other drams. the key difference is each cas# input (casl# and cash#) controls its corresponding eight dq inputs during write accesses. casl# controls dq0-dq7, and cash# controls dq8-dq15. the two cas# controls give the 1 meg x 16 both byte read and byte write cycle capabilities. general description (continued)
3 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram v v ih il casl#/cash# v v ih il ras# v v ih il addr row column (a) dont care undefined v v ih il we# v v ioh iol open dq t wpz the dqs go to high-z if we# falls, and if t wpz is met, will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). v v ih il oe# valid data (b) t whz we# may be used to disable the dqs to prepare for input data in an early write cycle. the dqs will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). t whz column (d) valid data (a) column (b) column (c) input data (c) figure 2 we# control of dqs page access page operations allow faster data operations (read, write or read-modify-write) within a row- address-defined page boundary. the page cycle is al- ways initiated with a row address strobed in by ras#, followed by a column address strobed in by cas#. ad- ditional columns may be accessed by providing valid column addresses, strobing cas# and holding ras# low, thus executing faster memory cycles. returning ras# high terminates the page mode of operation, i.e., closes the page. edo page mode the 1 meg x 16 provides edo page mode, which is an accelerated fast-page-mode cycle. the primary advantage of edo is the availability of data-out even after cas# returns high. edo provides for cas# precharge time ( t cp) to occur without the output data going invalid. this elimination of cas# output control provides for pipelined reads. fast-page-mode drams have traditionally turned the output buffers off (high-z) with the rising edge of cas#. edo-page-mode drams operate like fast-page-mode drams, except data will remain valid or become valid after cas# goes high during reads, provided ras# and oe# are held low. if oe# is pulsed while ras# and cas# are low, data will toggle from valid data to high-z and back to the same valid data. if oe# is toggled or pulsed after cas# goes high while ras# remains low, data will transition to and remain high-z (refer to figure 1). we# can also perform the function of disabling the output drivers under cer- tain conditions, as shown in figure 2. during an application, if the dq outputs are wire ord, oe# must be used to disable idle banks of drams. alternatively, pulsing we# to the idle banks during cas# high time will also high-z the outputs. inde- pendent of oe# control, the outputs will disable after t off, which is referenced from the rising edge of ras# or cas#, whichever occurs last. byte access cycle the byte writes and byte reads are determined by the use of casl# and cash#. enabling casl# se- lects a lower byte access (dq0-dq7). enabling cash# selects an upper byte access (dq8-dq15). enabling both casl# and cash# selects a word write cycle. the 1 meg x 16 may be viewed as two 1 meg x 8 drams that have common input controls, with the ex- ception of the cas# inputs. figure 3 illustrates the byte write and word write cycles. additionally, both bytes must always be of the same mode of operation if both bytes are active. a cas# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. for ex- ample, an early write on one byte and a late write on the other byte are not allowed during the same cycle.
4 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram stored data 1 1 0 1 1 1 1 1 ras# casl# we# x = not effective (don't care) address 1 address 0 0 1 0 1 0 0 0 0 word write lower byte write cash# input data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x input data 1 1 0 1 1 1 1 1 input data stored data 1 1 0 1 1 1 1 1 input data stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x 1 0 1 0 1 1 1 1 upper byte (dq8-dq15) of word lower byte (dq0-dq7) of word figure 3 word and byte write example however, an early write on one byte and a late write on the other byte, after a cas# precharge has been satisfied, are permissible. dram refresh preserve correct memory cell data by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr or hidden) so that all 1,024 combinations of ras# addresses are executed within t ref (max), regardless of sequence. the cbr, extended and self refresh cycles will invoke the internal refresh counter for automatic ras# addressing. an optional self refresh mode is available on the s version. the self refresh feature is initiated by per- forming a cbr refresh cycle and holding ras# low for the specified t rass. the s option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended re- fresh period of 128ms, or 125s per row, when using a distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low-to- high transition. if the dram controller uses a distrib- uted refresh sequence, a burst refresh is not required upon exiting self refresh. however, if the dram con- troller utilizes a ras#-only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. standby returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. the chip is preconditioned for the next cycle during the ras# high time.
5 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram casl# cas# ras# 10 10 no. 2 clock generator refresh controller no. 1 clock generator 1,024 x 1,024 x 16 memory array v dd v ss 10 oe# dq0 dq15 refresh counter cash# a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 1,024 1,024 x 16 16 10 10 sense amplifiers i/o gating 1,024 data-out buffer we# 16 row- address buffers (10) row decoder column- address buffer data-in buffer column decoder 16 functional block diagram
6 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram dc electrical characteristics and operating conditions (notes: 1; notes appear on pages 10-11) 3.3v 5v parameter/condition symbol min max min max units notes supply voltage v cc 3.0 3.6 4.5 5.5 v input high voltage: valid logic 1; all inputs, i/os and any nc v ih 2.0 5.5 2.4 v cc + 1 v input low voltage: valid logic 0; all inputs, i/os and any nc v il -1.0 0.8 -0.5 0.8 v input leakage current: any input at v in (0v v in v ih [max]) ; i i -2 2 -2 2 a 4 all other pins not under test = 0v output high voltage: i out = -2ma(3.3v), -5ma(5v) v oh 2.4 C 2.4 C v output low voltage: i out = 2ma(3.3v), 4.2ma(5v) v ol C 0.4 C 0.4 v output leakage current: any output at v out (0v v out 5.5v); i oz -5 5 -5 5 a dq is disabled and in high-z state absolute maximum ratings* voltage on v cc pin relative to v ss 3.3v ......................................................... -1v to +4.6v 5v ............................................................... -1v to +7v voltage on nc, inputs or i/o pins relative to vss: 3.3v ......................................................... -1v to +5.5v 5v ............................................................... -1v to +7v operating temperature t a (commercial) .................................. 0oc to +70oc t a (extended) ................................... -20oc to +80oc storage temperature (plastic) ........... -55oc to +150oc power dissipation ........................................................ 1w short circuit output current ................................ 50ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
7 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram i cc operating conditions and maximum limits (notes: 1, 2, 3, 5, 8; notes appear on pages 10-11); (v cc [min] v cc v cc [max]) parameter/condition symbol speed 3.3v 5v units notes standby current: ttl i cc 1 all 1 2 ma (ras# = cas# = v ih ) standby current: cmos (non-s version only) i cc 2 all 500 500 a (ras# = cas# = other inputs = v dd - 0.2v) standby current: cmos (s version only) i cc 2 all 150 150 a (ras# = cas# = other inputs = v dd - 0.2v) operating current: random read/write i cc 3 -5 180 190 ma 6 average power supply current -6 170 180 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: edo page mode i cc 4 -5 140 150 ma 6 average power supply current (ras# = v il , cas#, -6 130 140 address cycling: t pc = t pc [min]) refresh current: ras#-only i cc 5 -5 180 190 ma average power supply current -6 170 180 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr i cc 6 -5 180 180 ma 7, 9 average power supply current -6 170 170 (ras#, cas#, address cycling: t rc = t rc [min]) refresh current: extended (s version only) i cc 7 all 300 300 a 7, 9 average power supply current: cas# = 0.2v or cbr cycling; ras# = t ras (min); we# = v dd - 0.2v; a0-a10, oe# and d in = v dd - 0.2v or 0.2v (d in may be left open); t rc = 125s refresh current: self (s version only) i cc 8 all 300 300 a 7, 9 average power supply current: cbr with ras# ? t rass (min) and cas# held low; we# = v dd - 0.2v; a0-a10, oe# and d in = v dd - 0.2v or 0.2v (d in may be left open)
8 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram capacitance (notes: 1, 2, 3, 5, 8; notes appear on pages 10-11) parameter symbol max units notes input capacitance: addresses c i 1 5pf input capacitance: ras#, casl#,cash#, we#, oe# c i 2 7pf input/output capacitance: dq c io 7pf ac electrical characteristics (notes: 2, 3, 9, 10, 11, 12; notes appear on pages 10-11); (v cc [min] v cc v cc [max]) ac characteristics -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column-address setup to cas# precharge t ach 12 15 ns column-address hold time (referenced to ras#) t ar 38 45 ns column-address setup time t asc 0 0 ns 25 row-address setup time t asr 0 0 ns 25 column address to we# delay time t awd 42 49 ns 13 access time from cas# t cac 13 15 ns 14, 25 column-address hold time t cah 8 10 ns 25 cas# pulse width t cas 8 10,000 10 10,000 ns 27 cas# low to dont care during self refresh t chd 15 15 ns cas# hold time (cbr refresh) t chr 8 10 ns 7, 26 last cas# going low to first cas# to return high t clch 5 5 ns 28 cas# to output in low-z t clz 0 0 ns 26 data output hold after next cas# low t coh 3 3 ns cas# precharge time t cp 8 10 ns 15, 30 access time from cas# precharge t cpa 28 35 ns 26 cas# to ras# precharge time t crp 5 5 ns 26 cas# hold time t csh 38 45 ns 26 cas# setup time (cbr refresh) t csr 5 5 ns 7, 25 cas# to we# delay time t cwd 28 35 ns 13, 25 write command to cas# lead time t cwl 8 10 ns 26 data-in hold time t dh 8 10 ns 16, 25 data-in setup time t ds 0 0 ns 16, 25 output disable t od 0 12 0 15 ns output enable t oe 12 15 ns 17 oe# hold time from we# during t oeh 8 10 ns 18 read-modify-write cycle oe# high hold from cas# high t oehc 5 10 ns 18 oe# high pulse width t oep 5 5 ns oe# low to cas# high setup time t oes 4 5 ns output buffer turn-off delay t off 0 12 0 15 ns 20, 26
9 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram ac electrical characteristics (continued) (notes: 2, 3, 9, 10, 11, 12; notes appear on pages 10-11); (v cc [min] v cc v cc [max]) ac characteristics -5 -6 parameter symbol min max min max units notes oe# setup prior to ras# t ord 0 0 ns during hidden refresh cycle edo-page-mode read or write cycle time t pc 20 25 ns 31 edo-page-mode read-write cycle time t prwc 47 56 ns 31 access time from ras# t rac 50 60 ns 19 ras# to column-address delay time t rad 9 12 ns 21 row address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 50 125,000 60 125,000 ns ras# pulse width during self refresh t rass 100 100 s random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 22, 25 read command hold time (referenced to cas#) t rch 0 0 ns 23, 27 read command setup time t rcs 0 0 ns 25 refresh period (1,024 cycles) t ref 16 16 ms refresh period (1,024 cycles) s version t ref 128 128 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns ras# precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras#) t rrh 0 0 ns 23 ras# hold time t rsh 13 15 ns 32 read-write cycle time t rwc 116 140 ns ras# to we# delay time t rwd 67 79 ns 13 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns 32 write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns 13, 25 output disable delay from we# t whz 0 12 0 15 ns write command pulse width t wp 5 5 ns we# pulse to disable at cas# high t wpz 10 10 ns we# hold time (cbr refresh) t wrh 8 10 ns we# setup time (cbr refresh) t wrp 8 10 ns
10 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram notes 1. all voltages referenced to v ss . 2. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0oc t a 70oc for commercial) and (-20oc t a 80oc for extended) is ensured. 3. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#- only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 4. nc pins are assumed to be left floating and are not tested for leakage. 5. i cc is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 6. column address changed once each cycle. 7. enables on-chip refresh and address counters. 8. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 9. ac characteristics assume t t = 2.5ns. 10.v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 11.in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 12.measured with a load equivalent to two ttl gates and 100pf; and v ol = 0.8v and v oh = 2v. 13. t wcs, t rwd, t awd, and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd and t cwd apply to read-modify-write cycles. if t wcs ? t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit through- out the entire cycle. if t wcs < t wcs (min) and t rwd ? t rwd (min), t awd ? t awd (min) and t cwd ? t cwd (min), the cycle is a read- modify-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. oe# held high and we# taken low after cas# goes low results in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 14.assumes that t rcd ? t rcd (max). 15.if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas# must be pulsed high for t cp. 16.these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 17.if oe# is tied permanently low, late write, or read-modify-write operations are not permissible and should not be attempted. additionally, we# must be pulsed during cas# high time in order to place i/o buffers in high-z. 18.late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously read data if cas# remains low and oe# is taken back low after t oeh is met. if cas# goes high prior to oe# going back low, the dqs will remain open. 19.assumes that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 20. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . it is referenced from the rising edge of ras# or cas#, whichever occurs last. 21.the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac, and t cac must always be met. 22.the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 23.either t rch or t rrh must be satisfied for a read cycle. 24.the first cas#x edge to transition low. 25.output parameter (dqx) is referenced to corre- sponding cas# input; dq0-dq7 by casl# and dq8-dq15 by cash#.
11 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram notes (continued) 26.each cas#x must meet minimum pulse width. 27.the last cas#x edge to transition high. 28.last falling cas#x edge to first rising cas#x edge. 29.last rising cas#x edge to first falling cas#x edge. 30.last rising cas#x edge to next cycles last rising cas#x edge. 31.last cas#x to go low. 32.a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high.
12 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns read cycle note: 1. t off is referenced from rising edge of ras# or cas#, whichever occurs last. t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# casl#/cash# t clch note 1 t ach dont care undefined t oe 12 15 n s t off 0 12 0 15 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t r s h 13 15 n s -5 -6 symbol min max min max units
13 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram early write cycle dont care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh t clch we# casl#/cash# t ach timing parameters -5 -6 symbol min max min max units t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns -5 -6 symbol min max min max units t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rp 30 40 n s t r s h 13 15 n s t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns
14 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram read-write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas, clch t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach casl#/cash# t dont care undefined timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t a w d 42 49 n s t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t c w d 28 35 n s t cwl 8 10 ns t dh 8 10 ns -5 -6 symbol min max min max units t ds 0 0 ns t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t r s h 13 15 n s t rwc 116 140 ns t r w d 67 79 n s t rwl 13 15 n s t wp 5 5 ns
15 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram edo-page-mode read cycle ach valid data valid data valid data column column column row row dont care undefined t od t cah t asc t cp t rsh t cp t cp t cas, clch t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t rad t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# casl#/cash# we# t coh t oep t oehc t oes t oes tt cas, clch tt cas, clch t t ach t ach t -5 -6 symbol min max min max units t oe 12 15 n s t oehc 5 10 ns t oep 5 5 ns t oes 4 5 ns t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 1ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t r s h 13 15 n s timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t clz 0 0 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns
16 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram timing parameters -5 -6 symbol min max min max units t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns edo-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t rsh t cp t cp t cas, clch t rcd t crp t pc t csh t rasp t rp v v ih il casl#/cash# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# oe# v v ih il dont care undefined t ach t ach t ach tt cas, clch tt cas, clch t -5 -6 symbol min max min max units t pc 20 25 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rp 30 40 n s t r s h 13 15 n s t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns
17 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram edo-page-mode read-write cycle (late write and read-modify-write cycles) dont care undefined t t od t oe t od t oe t od t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t rsh t cp t rp t rasp t cp t rcd t csh t pc t crp row column column column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t prwc oeh t cas, t clch t cas, t clch t cas, t clch we# casl#/cash# note 1 note: 1. t pc is for late write cycles only. timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t clz 0 0 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t c w d 28 35 n s t cwl 8 10 ns t dh 8 10 ns -5 -6 symbol min max min max units t ds 0 0 ns t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t pc 20 25 n s t prwc 47 56 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t r s h 13 15 n s t r w d 67 79 n s t rwl 13 15 n s t wp 5 5 ns
18 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram edo-page-mode read early write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas, t clch t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid d in t rcs t rch t wcs t oe valid d out valid d out t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach casl#/cash# t cas, t clch t cas, t clch t cp t cp dont care undefined -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t dh 8 10 ns t ds 0 0 ns t oe 12 15 n s t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t r s h 13 15 n s t wch 8 10 ns t wcs 0 0 ns t whz 0 12 0 15 ns
19 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas, clch t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz casl#/cash# t dont care undefined read cycle (with we#-controlled disable) timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clch 5 5 ns t clz 0 0 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns t oe 12 15 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t whz 0 12 0 15 ns t wpz 10 10 n s -5 -6 symbol min max min max units
20 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram ras#-only refresh cycle (oe# and we# = dont care) row v v ih il v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open q v v oh ol t rpc casl#/cash# cbr refresh cycle (addresses and oe# = dont care) t rp v v ih il ras# t ras open t chr t csr v v ih il casl#/cash# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# dont care undefined v v oh ol note 1 timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t chr 8 10 ns t cp 8 10 ns t crp 5 5 ns t csr 5 5 ns t rah 9 10 ns -5 -6 symbol min max min max units t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rp 30 40 n s t rpc 5 5 ns t wrh 8 10 ns t wrp 8 10 ns note: 1. end of first cbr refresh cycle.
21 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram t oe 12 15 n s t off 0 12 0 15 ns t ord 0 0 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rp 30 40 n s t r s h 13 15 n s dont care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rc t rp t chr t ras dqx v v ioh iol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord casl#/cash# hidden refresh cycle (we# = high; oe# = low) timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t chr 8 10 ns t clz 0 0 ns t crp 5 5 ns t od 0 12 0 15 ns -5 -6 symbol min max min max units
22 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram self refresh cycle (addresses and oe# = dont care) v v ih il ras# t rass open v v ih il v v oh ol dq t rpc t chd t rps t rpc t rp t cp casl#/ cash# t wrh t wrp we# v v ih il t wrh t wrp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note 1 t csr dont care undefined t cp note 2 ( ) ( ) ( ) ( ) timing parameters -5 -6 symbol min max min max units t c h d 15 15 n s t clch 5 5 ns t cp 8 10 ns t csr 5 5 ns t rass 100 100 s -5 -6 symbol min max min max units t rp 30 40 n s t rpc 5 5 ns t rps 90 105 ns t wrh 8 10 ns t wrp 8 10 ns note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed.
23 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram 44/50-pin plastic tsop (400 mil) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. see detail a .024 (0.60) .016 (0.40) .008 (0.20) .002 (0.05) detail a .010 (0.25) .032 (0.80) typ .007 (0.18) .005 (0.13) .047 (1.20) max .004 (0.10) .031 (0.80) typ 1 50 25 .018 (0.45) .012 (0.30) .828 (21.04) .822 (20.88) .467 (11.86) .459 (11.66) .402 (10.21) .398 (10.11) pin #1 index seating plane .029 (0.75) typ
24 1 meg x 16 edo dram micron technology, inc., reserves the right to change products or specifications without notice. d52_b.p65 C rev. b; pub. 3/01 ?2001, micron technology, inc 16mb: 1 meg x16 edo dram 42-pin plastic soj (400 mil) .148 (3.76) .138 (3.51) 1.000 (25.40) 1.079 (27.41) 1.073 (27.25) seating plane .380 (9.65) .360 (9.14) .030 (0.76) min pin #1 index .050 (1.27) typ .445 (11.30) .435 (11.05) .405 (10.29) .399 (10.13) .095 (2.40) .080 (2.02) .020 (0.51) .015 (0.38) .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark and the micron logo and the m logos are trademarks of micron technology, inc.

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