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features applications description tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 expresscard? power interface switch 24-pin powerpad? htssop (single) meets the expresscard? standard available in a 32-pin powerpad? htssop (expresscard|34 or expresscard|54) (dual) compliant with the expresscard? compliance checklists notebook computers fully satisfies the expresscard? desktop computers implementation guidelines personal digital assistants (pdas) supports systems with wake function digital cameras ttl-logic compatible inputs tv and set top boxes short circuit and thermal protection ?40c to 85c ambient operating temperature range available in a 20-pin tssop, a 20-pin qfn, or the tps2231 and tps2236 expresscard power interface switches provide the total power management solution required by the expresscard specification. the tps2231 and tps2236 expresscard power interface switches distribute 3.3 v, aux, and 1.5 v to the expresscard socket. each voltage rail is protected with integrated current-limiting circuitry. the tps2231 supports systems with single-slot expresscard|34 or expresscard|54 sockets. the tps2236 supports systems with dual-slot expresscard sockets. end equipment for the tps2231 and tps2236 include notebook computers, desktop computers, personal digital assistants (pdas), and digital cameras. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments. expresscard is a trademark of personal computer memory card international association. production data information is current as of publication date. copyright ? 2004?2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. rgp pw pwp dap www .ti.com auxin3.3vin 1.5vin auxout 3.3vout1.5vout perst cppe cpusb shdn stby sysrst oc tps2231 host connector expresscard connector gnd rclken refclk+ refclk? express card host power source hostchip set/lock circuits
absolute maximum ratings dissipation ratings (thermal resistance = c/w) tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. available options packaged devices (1) t a number of channels tssop powerpad htssop qfn tps2231rgp single tps2231pw tps2231pwp ?40c to 85c tps2231mrgp (2) dual tps2236dap (1) the package is available taped and reeled. add an r suffix to device types (e.g., tps2231pwpr). (2) the tps2231mrgp is identical to the tps2231rgp with the exception of the powerpad dimensions. see the thermal pad mechanical data portion of this data sheet for specific information. over operating free-air temperature range (unless otherwise noted) (1) tps223x unit v i(3.3vin) ?0.3 to 6 v input voltage range for card v i v i(1.5vin) ?0.3 to 6 v power v i(auxin) ?0.3 to 6 v logic input/output voltage ?0.3 to 6 v v o(3.3vout) ?0.3 to 6 v v o output voltage range v o(1.5vout) ?0.3 to 6 v v o(auxout) ?0.3 to 6 v continuous total power dissipation see dissipation rating table i o(3.3vout) internally limited i o output current i o(auxout) internally limited i o(1.5vout) internally limited oc sink current 10 ma perst sink/source current 10 ma t j operating virtual junction temperature range ?40 to 120 c t stg storage temperature range ?55 to 150 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c tps2231 2 kv human body model tps2236, all pins except electrostatic discharge (hbm) mil-std-883c perstx and ocx esd protection tps2236, perstx and ocx 1.5 kv charge device model (cdm) 500 v (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. t a 25c derating factor t a = 70c t a = 85c package power rating above t a = 25c power rating power rating pw (20) (1) 704.2 mw 7.41 mw/c 370.6 mw 259.5 mw pwp (24) (1) 3153 mw 33.19 mw/c 1659.5 mw 1161.6 mw (1) these devices are mounted on an jedec low-k board (2-oz. traces on surface), (the table is assuming that the maximum junction temperature is 120c). the power pad on the device must be soldered down to the power pad on the board if best thermal performance is needed. 2 submit documentation feedback www .ti.com
recommended operating conditions electrical characteristics tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 dissipation ratings (thermal resistance = c/w) (continued) t a 25c derating factor t a = 70c t a = 85c package power rating above t a = 25c power rating power rating rgp (20) (2) 3277.5 mw 34.5 mw/c 1725 mw 1207.3 mw dap (32) (1) 993.4 mw 10.46 mw/c 522.8 mw 366 mw powerpad not soldered down dap (32) (1) 4040.8 mw 42.55 mw/c 2126.8 mw 1488.7 mw (2) tis device is mounted on a jedec jeso51.5 high-k board (2 signal, 2 plane). the values assume a maxium junction temperature of 120c. min max unit v i(3.3vin) 3.3vin is only required for its respective functions 3 3.6 v i(1.5vin) input voltage 1.5vin is only required for its respective functions 1.35 1.65 v v i(auxin) auxin is required for all circuit operations 3 3.6 i o(3.3vout) 0 1.3 a i o(1.5vout) continuous output current t j = 120c 0 650 ma i o(auxout) 0 275 ma t j operating virtual junction temperature ?40 120 c t j = 25c, v i(3.3vin) = v i(auxin) = 3.3 v, v i(1.5vin) = 1.5 v, v i(/shdnx) , v i(/stbyx) = 3.3 v, v i(/cppex) = v i(/cpusbx) = 0 v, v i(/sysrst) = 3.3 v, ocx and rclkenx and perstx are open, all voltage outputs unloaded (unless otherwise noted) parameter test conditions min typ max unit power switch t j = 25c, i = 1300 ma each 45 3.3vin to 3.3vout with two m w switches on for dual t j = 100c, i = 1300 ma each 68 t j = 25c, i = 650 ma each 46 power switch 1.5vin to 1.5vout with two m w resistance switches on for dual t j = 100c, i = 650 ma each 70 t j = 25c, i = 275 ma each 120 auxin to auxout with two m w switches on for dual t j = 100c, i = 275 ma each 200 r (dis_fet) discharge resistance on 3.3v/1.5v/aux outputs v i(/shdnx) = 0 v, i (discharge) = 1 ma 100 500 w i os(3.3vout) (steady-state value) 1.35 2 2.5 a short-circuit t j (?40, 120c]. output powered into i os i os(1.5vout) (steady-state value) 0.67 1 1.3 a output current (1) a short i os(auxout) (steady-state value) 275 450 600 ma rising temperature, not in 155 165 overcurrent condition trip point, t j c thermal shutdown overcurrent condition 120 130 hysteresis 10 v o(3.3vout) with 100-m w short 43 100 v o(1.5vout) with 100-m w short, 100 140 from short to the 1 st threshold tps2231 current-limit within 1.1 times of final current s response time v o(1.5vout) with 100-m w short, limit, t j = 25c 110 150 tps2236 v o(auxout) with 100-m w short 38 100 (1) pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. 3 submit documentation feedback www .ti.com
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 electrical characteristics (continued) t j = 25c, v i(3.3vin) = v i(auxin) = 3.3 v, v i(1.5vin) = 1.5 v, v i(/shdnx) , v i(/stbyx) = 3.3 v, v i(/cppex) = v i(/cpusbx) = 0 v, v i(/sysrst) = 3.3 v, ocx and rclkenx and perstx are open, all voltage outputs unloaded (unless otherwise noted) parameter test conditions min typ max unit i i(auxin) 125 200 normal operation i i(3.3vin) 17.5 25 a of tps2236 outputs are unloaded, i i(1.5vin) 5.5 15 operation input t j [?40, 120c] (does not include i i quiescent current cppex and cpusbx logic pullup i i(auxin) 85 150 currents) normal operation i i(3.3vin) 10 15 a of tps2231 i i(1.5vin) 2.5 10 i i(auxin) 200 320 normal operation i i(3.3vin) 17.5 25 a of tps2236 outputs are unloaded, t j [?40, i i(1.5vin) 5.5 15 120c] (include cppex and cpusbx i i(auxin) 120 210 logic pullup currents) normal operation i i(3.3vin) 10 15 a of tps2231 i i(1.5vin) 2.5 10 total input i i quiescent current i i(auxin) 250 440 shutdown mode of i i(3.3vin) 3.5 20 a cpusb = cppe = 0 v shdn = 0 v tps2236 (discharge fets are on) (include i i(1.5vin) 0.1 20 cppex and cpusbx logic pullup i i(auxin) 144 270 currents and shdn pullup current) shutdown mode of t j [?40, 120c] i i(3.3vin) 3.5 10 a tps2231 i i(1.5vin) 0.5 10 i i(auxin) 40 100 shdn = 3.3 v, tps2236 i i(3.3vin) 0.1 100 a cpusb = cppe = 3.3 v (no card i i(1.5vin) 0.1 100 forward leakage present, discharge fets are on); i lkg(fwd) current current measured at input pins i i(auxin) 20 50 t j = 120c, includes rclken tps2231 i i(3.3vin) 0.1 50 a pullup current i i(1.5vin) 0.1 50 t j = 25c 0.1 10 i i(auxout) a t j = 120c 50 v o(auxout) = v o(3.3vout) = 3.3 v; reverse leakage t j = 25c 0.1 10 v o(1.5vout) = 1.5 v; all voltage inputs i lkg(rvs) current (tps2236 i i(3.3vout) a are grounded (current measured t j = 120c 50 and tps2231) from output pins going in) t j = 25c 0.1 10 i i(1.5vout) a t j = 120c 50 logic section ( sysrst, shdnx, stbyx, perstx, rclkenx, ocx, cpusbx, cppex) sysrst = 3.6 v, sinking 0 1 i (/sysrst) input a sysrst = 0 v, sourcing 10 30 shdnx = 3.6 v, sinking 0 1 i (/shdnx) input a shdnx = 0 v, sourcing 10 30 logic input stbyx = 3.6 v, sinking 0 1 supply current i (/stbyx) input a stbyx = 0 v, sourcing 10 30 i (rclkenx) input rclkenx = 0 v, sourcing 10 30 a cpusb or cppe = 0 v, sinking 0 1 i (/cpusbx) or inputs a i (/cppex) cpusb or cppe = 3.6 v, sourcing 10 30 high level 2 logic input v voltage low level 0.8 rclen output low voltage output i o(rclken) = 60 a 0.4 v 4 submit documentation feedback www .ti.com
switching characteristics tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 electrical characteristics (continued) t j = 25c, v i(3.3vin) = v i(auxin) = 3.3 v, v i(1.5vin) = 1.5 v, v i(/shdnx) , v i(/stbyx) = 3.3 v, v i(/cppex) = v i(/cpusbx) = 0 v, v i(/sysrst) = 3.3 v, ocx and rclkenx and perstx are open, all voltage outputs unloaded (unless otherwise noted) parameter test conditions min typ max unit 3.3vout falling 2.7 3 perst assertion threshold of output voltage ( perst asserted when any output voltage falls below the auxout falling 2.7 3 v threshold) 1.5vout falling 1.2 1.35 3.3vout, auxout, or 1.5vout perst assertion delay from output voltage 500 ns falling 3.3vout, auxout, and 1.5vout perst de-assertion delay from output voltage 4 10 20 ms rising within tolerance max time from sysrst asserted or perst assertion delay from sysrst 500 ns de-asserted 3.3vout, auxout, or 1.5vout t w(perst) perst minimum pulse width falling out of tolerance or triggered 100 250 s by sysrst perst output low voltage 0.4 v i o(perst) = 500 a perst output high voltage 2.4 v oc output low voltage i o(/oc) = 2 ma 0.4 v oc leakage current v o(/oc) = 3.6 v 1 a falling into or out of an overcurrent oc deglitch 6 20 ms condition undervoltage lockout (uvlo) 3.3vin level, below which 3.3vin 3.3vin uvlo 2.6 2.9 and 1.5vin switches are off 1.5vin level, below which 3.3vin 1.5vin uvlo 1 1.25 v and 1.5vin switches are off auxin level, below which all auxin uvlo 2.6 2.9 switches are off uvlo hysteresis 100 mv t j = 25c, v i(3.3vin) = v i(auxin) = 3.3 v, v i(1.5vin) = 1.5 v, v i(/shdnx) , v i(/stbyx) = 3.3 v, v i(/cppex) = v i(/cpusbx) = 0 v, v i(/sysrst) = 3.3 v, ocx and rclkenx and perstx are open, all voltage outputs unloaded (unless otherwise noted) parameter test conditions min typ max unit 3.3vin to 3.3vout c l(3.3vout) = 0.1 f, i o(3.3vout) = 0 a 0.1 3 auxin to auxout c l(auxout) = 0.1 f, i o(auxout) = 0 a 0.1 3 1.5vin to 1.5vout c l(1.5vout) = 0.1 f, i o(1.5vout) = 0 a 0.1 3 t r output rise times ms 3.3vin to 3.3vout c l(3.3vout) = 100 f, r l = v i(3.3vin) /1 a 0.1 6 auxin to auxout c l(auxout) = 100 f, r l = v i(auxin) /0.250 a 0.1 6 1.5vin to 1.5vout c l(1.5vout) = 100 f, r l = v i(1.5vin) /0.500 a 0.1 6 3.3vin to 3.3vout c l(3.3vout) = 0.1 f, i o(3.3vout) = 0 a 10 150 auxin to vauxout c l(auxout) = 0.1 f, i o(auxout) = 0 a 10 150 s output fall times 1.5vin to 1.5vout c l(1.5vout) = 0.1 f, i o(1.5vout) = 0 a 10 150 when card removed t f (both cpusb and 3.3vin to 3.3vout c l(3.3vout) = 20 f, i o(3.3vout) = 0 a 2 30 cppe de-asserted) auxin to vauxout c l(auxout) = 20 f, i o(auxout) = 0 a 2 30 ms 1.5vin to 1.5vout c l(1.5vout) = 20 f, i o(1.5vout) = 0 a 2 30 5 submit documentation feedback www .ti.com
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 switching characteristics (continued) t j = 25c, v i(3.3vin) = v i(auxin) = 3.3 v, v i(1.5vin) = 1.5 v, v i(/shdnx) , v i(/stbyx) = 3.3 v, v i(/cppex) = v i(/cpusbx) = 0 v, v i(/sysrst) = 3.3 v, ocx and rclkenx and perstx are open, all voltage outputs unloaded (unless otherwise noted) parameter test conditions min typ max unit 3.3vin to 3.3vout c l(3.3vout) = 0.1 f, i o(3.3vout) = 0 a 10 150 auxin to vauxout c l(auxout) = 0.1 f, i o(auxout) = 0 a 10 150 s output fall times 1.5vin to 1.5vout c l(1.5vout) = 0.1 f, i o(1.5vout) = 0 a 10 150 when shdn t f asserted (card is 3.3vin to 3.3vout c l(3.3vout) = 100 f, r l = v i(3.3vin) /1 a 0.1 5 present) auxin to vauxout c l(auxout) = 100 f r l = v i(auxin) /0.250 a 0.1 5 ms 1.5vin to 1.5vout c l(1.5vout) = 100 f, r l = v i(1.5vin) /0.500 a 0.1 5 3.3vin to 3.3vout c l(3.3vout) = 0.1 f, i o(3.3vout) = 0 a 0.1 1 auxin to vauxout c l(auxout) = 0.1 f, i o(auxout) = 0a 0.05 0.5 1.5vin to 1.5vout c l(1.5vout) = 0.1 f, i o(1.5vout) = 0 a 0.1 1 turn-on propagation t pd(on) ms delay 3.3vin to 3.3vout c l(3.3vout) = 100 f, r l = v i(3.3vin) /1 a 0.1 1.5 auxin to vauxout c l(auxout) = 100 f, r l = v i(auxin) /0.250 a 0.05 1 1.5vin to 1.5vout c l(1.5vout) = 100 f, r l = v i(1.5vin) /0.500 a 0.1 1.5 3.3vin to 3.3vout c l(3.3vout) = 0.1 f, i o(3.3vout) = 0 a 0.1 1.5 auxin to vauxout c l(auxout) = 0.1 f, i o(auxout) = 0 a 0.05 0.5 1.5vin to 1.5vout c l(1.5vout) = 0.1 f, i o(1.5vout) = 0 a 0.1 1.5 turn-off propagation t pd(off) ms delay 3.3vin to 3.3vout c l(3.3vout) = 100 f, r l = v i(3.3vin) /1 a 0.1 1.5 auxin to vauxout c l(auxout) = 100 f, r l = v i(auxin) /0.250 a 0.05 0.5 1.5vin to 1.5vout c l(1.5vout) = 100 f, r l = v i(1.5vin) /0.500 a 0.1 1 6 submit documentation feedback www .ti.com
pin assignments tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 terminal functions terminal tps2231 tps2236 i/o description name no. name no. pw pwp rgp dap 3.3vin 4, 5 5, 6 2 3.3vin 8, 9 i 3.3-v input for 3.3vout 1.5vin 15, 16 18, 19 12 1.5vin 24, 25 i 1.5-v input for 1.5vout auxin 18 21 17 auxin 15 i aux input for auxout and chip power gnd 10 11 7 gnd 21 ground switched output that delivers 0 v, 3.3 v or high impedance to 3.3vout 6, 7 7, 8 3 3.3vout1 7 o card switched output that delivers 0 v, 1.5 v or high impedance to 1.5vout 13, 14 16, 17 11 1.5vout1 26 o card switched output that delivers 0 v, aux or high impedance to auxout 17 20 15 auxout1 14 o card 7 submit documentation feedback www .ti.com 12 3 4 5 6 7 8 9 10 11 12 2423 22 21 20 19 18 17 16 15 14 13 nc sysrst shdn stby 3.3vin3.3vin 3.3vout3.3vout perst nc gnd nc ncoc rclkenauxin auxout 1.5vin 1.5vin 1.5vout 1.5vout cppe cpusb nc tps2231 pwp package (top view) nc - no internal connection 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 sysrst shdn stby 3.3vin3.3vin 3.3vout3.3vout perst nc gnd oc rclkenauxin auxout 1.5vin 1.5vin 1.5vout 1.5vout cppe cpusb tps2231 pw package (top view) 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3231 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cppe1 cppe2 cpusb1 ncnc cpusb2 3.3vout1 3.3vin3.3vin 3.3vout2 perst2 nc perst1 auxout1 auxin auxout2 rclken1rclken2 sysrst ncstby1 stby2 1.5vout11.5vin 1.5vin 1.5vout2 nc gnd oc2 oc1 shdn2 shdn1 tps2236 dap package (top view) tps2231 rgp package (top view) ncnc 3.3vin 3.3vout 1.5vin auxout nc nc 1.5vout shdn oc rclken auxin nc sysrst gnd perst cpusb cppe stby 12 3 4 5 1514 13 12 1 1 6 7 8 9 10 16 17 18 19 20
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 terminal functions (continued) terminal tps2231 tps2236 i/o description name no. name no. pw pwp rgp dap switched output that delivers 0 v, 3.3 v or high impedance to 3.3vout2 10 o card switched output that delivers 0 v, 1.5 v or high impedance to 1.5vout2 23 o card switched output that delivers 0 v, aux or high impedance to auxout2 16 o card system reset input ? active low, logic level signal. internally sysrst 1 2 6 sysrst 30 i pulled up to auxin. card present input for pci express cards. internally pulled up to cppe 12 15 10 cppe1 1 i auxin cpusb 11 14 9 cpusb1 3 i card present input for usb cards. internally pulled up to auxin. card present input for pci express cards. internally pulled up to cppe2 2 i auxin. cpusb2 6 i card present input for usb cards. internally pulled up to auxin. perst 8 9 8 perst1 13 o a logic level power good to slot 0 (with delay) perst2 11 o a logic level power good to slot 1 (with delay) shutdown input ? active low, logic level signal. internally pulled shdn 2 3 20 shdn1 17 i up to auxin. shutdown input ? active low, logic level signal. internally pulled shdn2 18 i up to auxin. standby input ? active low, logic level signal. internally pulled up stby 3 4 1 stby1 28 i to auxin. standby input ? active low, logic level signal. internally pulled up stby2 27 i to auxin. reference clock enable signal. as an output, a logic level power good to host for slot 0 (no delay ? open drain). as an input, if rclken 19 22 18 rclken1 32 i/o kept inactive (low) by the host, prevents perst from being de-asserted. internally pulled up to auxin. reference clock enable signal. as an output, a logic level power good to host for slot 1 (no delay ? open drain). as an input, if rclken2 31 i/o kept inactive (low) by the host, prevents perst from being de-asserted. internally pulled up to auxin. oc 20 23 19 oc1 19 o overcurrent status output for slot 0 (open drain) oc2 20 o overcurrent status output for slot 1 (open drain) 1, 10, 4, 5, 4, 5, nc 9 12, 13, 13, 14, nc 12, 22, no connection 24 16 29 8 submit documentation feedback www .ti.com
functional block diagram single expresscard power switch tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 9 submit documentation feedback www .ti.com pg cs s1 s4 pg cs s2 s5 pg cs s3 s6 current limit thermal limit control logic uvlo por fault auxin delay pwr_good_all 3.3voutauxout 1.5vout oc rclkenperst sysrst 3.3vin auxin 1.5vin cpusb cppe stby shdn gnd auxin note a: pg = power goodnote b: cs = current sense (note a) (note b)
dual expresscard power switch tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 functional block diagram (continued) 10 submit documentation feedback www .ti.com pg1 cs s1 s4 s2 s5 s3 s6 current limit thermal limit control logic uvlo por channel-1 fault auxin delay pwr_good_all_2 3.3vout1auxout1 1.5 vout1 oc1 rclken1perst1 sysrst 3.3vin auxin 1.5vin cpusb1 cppe1 stby1 shdn1 gnd s7 s10 s8 s11 s9 s12 3.3vout2auxout2 1.5vout2 delay pwr_good_all_1 channel-2 fault rclken2perst2 oc2 cpusb2 cppe2 stby2 shdn2 pg1 cs pg1 cs pg2 cs pg2 cs pg2 cs
detailed pin descriptions cppe cpusb shdn stby rclken perst tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 a logic low level on this input indicates that the card present supports pci express functions. cppe connects to the auxin input through an internal pullup. when a card is inserted, cppe is physically connected to ground if the card supports pci express functions. a logic low level on this input indicates that the card present supports usb functions. cpusb connects to the auxin input through an internal pullup. when a card is inserted, cpusb is physically connected to ground if the card supports usb functions. when asserted (logic low), this input instructs the power switch to turn off all voltage outputs and the discharge fets are activated. shdn has an internal pullup connected to auxin. when asserted (logic low) after the card is inserted, this input places the power switch in standby mode by turning off the 3.3-v and 1.5-v power switches and keeping the aux switch on. if asserted prior to the card being present, stby places the power switch in off mode by turning off the aux, 3.3-v, and 1.5-v power switches. stby has an internal pullup connected to auxin. this pin serves as both an input and an output. on power up, a discharge fet keeps this signal at a low state as long as any of the output power rails are out of their tolerance range. once all output power rails are within tolerance, the switch releases rclken allowing it to transition to a high state (internally pulled up to auxin). the transition of rclken from a low to a high state starts an internal timer for the purpose of deasserting perst. as an input, rclken can be kept low to delay the start of the perst internal timer. because rclken is internally connected to a discharge fet, this pin can only be driven low and should never be driven high as a logic input. when an external circuit drives this pin low, rclken becomes an input; otherwise, this pin is an output. rclken can be used by the host system to enable a clock driver. on power up, this output remains asserted (logic level low) until all power rails are within tolerance. once all power rails are within tolerance and rclken has been released (logic high), perst is deasserted (logic high) after a time delay as shown in the parametric table. on power down, this output is asserted whenever any of the power rails drop below their voltage tolerance. the perst signal is an output from the host system and an input to the expresscard module. this signal is only used by pci express-based modules and its function is to place the expresscard module in a reset state. during power up, power down, or whenever power to the expresscard module is not stable or not within voltage tolerance limits, the expresscard standard requires that perst be asserted. as a result, this signal also serves as a power-good indicator to the expresscard module, and the relationship between the power rails and perst are explicitly defined in the expresscard standard. the host can also place the expresscard module in a reset state by asserting a system reset sysrst. this system reset generates a perst to the expresscard module without disrupting the voltage rails. this is what is normally called a warm reset. however, in a cold start situation, the system reset can also be used to extend the length of time that perst is asserted. 11 submit documentation feedback www .ti.com
sysrst oc functional truth tables truth table for voltage outputs truth table for logic outputs tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 detailed pin descriptions (continued) this input is driven by the host system and directly affects perst. asserting sysrst (logic low) forces perst to assert. rclken is not affected by the assertion of sysrst. sysrst has an internal pullup connected to auxin. this pin is an open-drain output. when any of the three power switches (aux, 3.3v, and 1.5v) is in an overcurrent condition, oc is asserted (logic low) by an internal discharge fet with a deglitch delay. otherwise, the discharge fet is open, and the pin can be pulled up to a power supply through an external resistor. voltage inputs (1) logic inputs voltage outputs (2) mode (3) auxin 3.3vin 1.5vin shdn stby cp (4) auxout 3.3vout 1.5vout off x x x x x off off off off on x x 0 x x gnd gnd gnd shutdown on x x 1 x 1 gnd gnd gnd no card on on on 1 0 0 on off off standby on on on 1 1 0 on on on card inserted (1) for input voltages, on means the respective input voltage is higher than its turnon threshold voltage; otherwise, the voltage is off (for aux input, off means the voltage is close to zero volt). (2) for output voltages, on means the respective power switch is turned on so the input voltage is connected to the output; off means the power switch and its output discharge fet are both off; gnd means the power switch is off but the output discharge fet is on so the voltage on the output is pulled down to 0 v. (3) mode assigns each set of input conditions and respective output voltage results to a different name. these modes are referred to as input conditions in the following truth table for logic outputs. (4) cp = cpusb and cppe? equal to 1 when both cpusb and cppe signals are logic high, or equal to 0 when either cpusb or cppe is low. input conditions logic outputs mode sysrst rclken (1) perst rclken (2) off shutdown x x 0 0 no card standby 0 hi-z 0 1 0 0 0 0 card inserted 1 hi-z 1 1 1 0 0 0 (1) rclken as a logic input in this column. rclken is an i/o pin and it can be driven low externally, left open, or connected to high-impedance terminals, such as the gate of a mosfet. it must not be driven high externally. (2) rclken as a logic output in this column. 12 submit documentation feedback www .ti.com
power states discharge fets tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 if auxin is not present, then all input-to-output power switches are kept off ( off mode). if auxin is present and shdn is asserted (logic low), then all input-to-output power switches are kept off and the output discharge fets are turned on ( shutdown mode). if shdn is asserted and then de-asserted, the state on the outputs is restored to the state prior to shdn assertion. if 3.3vin, auxin and 1.5vin are present at the input of the power switch and no card is inserted, then all input-to-output power switches are kept off and the output discharge fets are turned on ( no card mode). if 3.3vin, auxin and 1.5vin are present at the input of the power switch prior to a card being inserted, then all input-to-output power switches are turned on once a card-present signal ( cpusb and/or cppe) is detected ( card inserted mode). if a card is present and all output voltages are being applied, then the stby is asserted (logic low); the auxout voltage is provided to the card, and the 3.3vout and 1.5vout switches are turned off ( standby mode). if a card is present and all output voltages are being applied, then the 1.5vin, or 3.3vin is removed from the input of the power switch; the auxout voltage is provided to the card and the 3.3vout and 1.5vout switches are turned off ( standby mode). if prior to the insertion of a card, the auxin is available at the input of the power switch and 3.3vin and/or 1.5vin are not, or if stby is asserted (logic low), then no power is made available to the card ( off mode). if 1.5vin and 3.3vin are made available at the input of the power switch after the card is inserted and stby is not asserted, all the output voltages are made available to the card ( card inserted mode). the discharge fets on the outputs are activated whenever the device detects that a card is not present ( no card mode). activation occurs after the input-to-output power switches are turned off (break before make). the discharge fets de-activate if either of the card-present lines go active low, unless the shdn pin is asserted. the discharge fets are also activated whenever the shdn input is asserted and stay asserted until shdn is de-asserted. 13 submit documentation feedback www .ti.com
parameter measurement information typical characteristics tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 figure 1. test circuits and voltage waveforms table of graphs figure output voltage when card is inserted vs time 2 rclken and perst voltage during power up vs time 3 rclken and perst voltage during power down vs time 4 perst asserted by sysrst when power is on vs time 5 perst de-asserted by sysrst when power is on vs time 6 output voltage when 3.3vin is removed vs time 7 output voltage when 1.5vin is removed vs time 8 oc response when powered into a short (3.3vout) vs time 9 supply current of auxin vs junction temperature 10 static drain-source on-state resistance vs junction temperature 11 3.3-v power switch current limit vs junction temperature 12 1.5-v power switch current limit vs junction temperature 13 aux power switch current limit vs junction temperature 14 3.3-v power switch current limit trip vs junction temperature 15 1.5-v power switch current limit trip vs junction temperature 16 aux power switch current limit trip vs junction temperature 17 14 submit documentation feedback www .ti.com i o(3.3vout/auxout) vin vin load circuit load circuit 50% 10% volt age w aveforms 10% 90% c l i o(1.5vout) c l t pd(off) t pd(on) vin v o(3.3vout/auxout) v i(3.3v/auxin) gnd v i(3.3v) gnd 50% 10% 90% t pd(off) t pd(on) vin v o(1.5vout) v i(1.5v) gnd v i(1.5v) gnd 90% propagation delay (1.5vout) propagation delay (3.3vout/auxout) t r t f v o(3.3vout/auxout) v i(3.3v) gnd 10% 90% t r t f v o(1.5vout) gnd v i(1.5v) rise/fall t ime (1.5vout) rise/fall t ime (3.3vout/auxout) 50% 10% t off t on vin v o(3.3vout/auxout) v i(3.3v) gnd v i(3.3v) gnd 90% 50% 10% t off t on vin v o(1.5vout) v i(1.5v) gnd v i(1.5v) gnd 90% t urn on/off t ime (1.5vout) t urn on/off t ime (3.3vout/auxout) r l r l
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 output voltage when card is inserted rclken and perst voltage during power up vs vs time time figure 2. figure 3. rclken and perst voltage during power down perst asserted by sysrst when power is on vs vs time time figure 4. figure 5. 15 submit documentation feedback www .ti.com v o(3.3vout) v o(rclken) v o(perst) t ? t ime ? 5 ms/div 2 v/div2 v/div 2 v/div v i(cpxx) v o(3.3vout) v o(1.5vout) v o(auxout) t ? t ime ? 1 ms/div 2 v/div2 v/div 2 v/div 2 v/div v o(auxout) v o(rclken) v o(perst) t ? t ime ? 1 ms/div 2 v/div2 v/div 2 v/div v o(perst) t ? t ime ? 500 ns/div v i(sysrst) 2 v/div2 v/div
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 perst de-asserted by sysrst when power is on output voltage when 3.3vin is removed vs vs time time figure 6. figure 7. oc response when powered into a short output voltage when 1.5vin is removed (3.3vout) vs vs time time figure 8. figure 9. 16 submit documentation feedback www .ti.com v o(perst) t ? t ime ? 100 s/div v i(sysrst) 2 v/div2 v/div v o(3.3vout) v o(1.5vout) v o(auxout) v i(3.3vin) r l(3.3vout) = 3.6 r l(1.5vout) = 2.7 r l(auxout) = 12 c l(3.3v/1.5v/auxout) = 68 f t ? t ime ? 500 s/div 2 v/div2 v/div 2 v/div 2 v/div v o(3.3vout) v o(1.5vout) v i(1.5vin) t ? t ime ? 500 s/div v o(auxvout) r l(3.3vout) = 3.6 r l(1.5vout) = 2.7 r l(auxout) = 12 c l(3.3v/1.5v/auxout) = 68 f 2 v/div 2 v/div2 v/div 2 v/div v o(oc) 2 v/div i o(3.3vout) 0.5 a/div t ? t ime ? 5 ms/div
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 supply current of auxin static drain-source on-state resistance vs vs junction temperature junction temperature figure 10. figure 11. 3.3-v power switch current limit 1.5-v power switch current limit vs vs junction temperature junction temperature figure 12. figure 13. 17 submit documentation feedback www .ti.com 0 20 40 60 80 100 120 140 160 180 ?40 ?20 0 20 40 60 80 100 120 3.3v_aux 1.5vin 3.3vin on?state resistance ? t j ? junction t emperature ? c w r ds(on) ? static drain-source m 0 50 100 150 200 250 ?40 ?20 0 20 40 60 80 100 120 auxin + cpxx + shdn + rclken auxin + cpxx auxin cc i supply current ? ? a m t j ? junction t emperature ? c 1.90 1.95 2 2.05 2.10 ?40 ?20 0 20 40 60 80 100 120 current limit ? a t j ? junction t emperature ? c 900 910 920 930 940 950 960 970 980 990 1000 ?40 ?20 0 20 40 60 80 100 120 current limit ? ma t j ? junction t emperature ? c
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 aux power switch current limit 3.3-v power switch current limit trip vs vs junction temperature junction temperature figure 14. figure 15. 1.5-v power switch current limit trip aux power switch current limit trip vs vs junction temperature junction temperature figure 16. figure 17. 18 submit documentation feedback www .ti.com 390 400 410 420 430 440 450 460 470 480 490 500 ?40 ?20 0 20 40 60 80 100 120 current limit ? ma t j ? junction t emperature ? c 2.50 2.60 2.70 2.80 2.90 3 3.10 3.20 ?40 ?20 0 20 40 60 80 100 120 current limit t rip threshold ? a t j ? junction t emperature ? c 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 ?40 ?20 0 20 40 60 80 100 120 current limit t rip threshold ? ma t j ? junction t emperature ? c 600 640 680 720 760 800 ?40 ?20 0 20 40 60 80 100 120 current limit t rip threshold ? ma t j ? junction t emperature ? c
application information introduction to expresscard expresscard power requirements expresscard power switch operation tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 an expresscard module is an add-in card with a serial interface based on pci express and/or universal serial bus (usb) technologies. an expresscard comes in two form factors defined as expresscard|34 or expresscard|54. the difference, as defined by the name, is the width of the module, 34 mm or 54 mm, respectively. host systems supporting the expresscard module can support either the expresscard|34 or expresscard|54 or both. regardless of which expresscard module is used, the power requirements as defined in the expresscard standard apply to both on an individual slot basis. the host system is required to supply 3.3 v, 1.5 v, and aux to each of the expresscard slots. however, the voltage is only applied after an expresscard is inserted into the slot. the expresscard connector has two pins, cppe and cpusb, that are used to signal the host when a card is inserted. if the expresscard module itself connects the cppe to ground, the logic low level on that signal indicates to the host that a card supporting pci express has been inserted. if cpusb is connected to ground, then the expresscard module supports the usb interface. if both pci express and usb are supported by the expresscard module, then both signals, cppe and cpusb, must be connected to ground. in addition to the card present signals ( cppe and cpusb), the host system determines when to apply power to the expresscard module based on the state of the system. the state of the system is defined by the state of the 3.3 v, 1.5 v, and aux input voltage rails. for the sake of simplicity, the 3.3-v and 1.5-v rails are defined as the primary voltage rails as oppose to the auxiliary voltage rail, aux. the expresscard power switch resides on the host, and its main function is to control when to send power to the expresscard slot. the expresscard power switch makes decisions based on the card present inputs and on the state of the host system as defined by the primary and auxiliary voltage rails. the following conditions define the operation of the host power controller: 1. when both primary power and auxiliary power at the input of the expresscard power switch are off, then all power to the expresscard connector is off regardless of whether a card is present. 2. when both primary power and auxiliary power at the input of the expresscard power switch are on, then power is only applied to the expresscard after the expresscard power switch detects that a card is present. 3. when primary power (either +3.3 v or +1.5 v) at the input of the expresscard power switch is off and auxiliary power at the input of the expresscard power switch is on, then the expresscard power switch behaves in the following manner: a. if neither of the card present inputs is detected (no card inserted), then no power is applied to the expresscard slot. b. if the card is inserted after the system has entered this power state, then no power is applied to the expresscard slot. c. if the card is inserted prior to the removal of the primary power (either +3.3 v or +1.5 v or both) at the input of the expresscard power switch, then only the primary power (both +3.3 v and +1.5 v) is removed and the auxiliary power is sent to the expresscard slot. figure 18 through figure 23 illustrate the timing relationships between power/logic inputs and outputs of expresscard. 19 submit documentation feedback www .ti.com
express card timing diagrams tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 application information (continued) figure 18. timing signals - card present before host power is on figure 19. timing signals - host power is on prior to card insertion 20 submit documentation feedback www .ti.com b tpd min max units a b 100 c d e 100 f 4 20 ms g 10 ms a g c d e f sysrst cpxx host power (auxin, 3.3vin, and 1.5vin) card power (auxin, 3.3vout , and 1.5vout) rclken perst refclk system dependent system dependentsystem dependent s s a b c d e sysrst cpxx host power (auxin, 3.3vin, and 1.5vin) card power (auxin, 3.3vout , and 1.5vout) rclken perst refclk tpd min max units ab 100 cd e 4 20 ms 10 ms system dependent system dependent s
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 application information (continued) figure 20. timing signals - host system in standby prior to card insertion figure 21. timing signals - host-controlled power down 21 submit documentation feedback www .ti.com sysrst cpxx rclken perst refclk (either t ri-stated or off) host power (auxin) host power (3.3vin and 1.5vin) card power (auxin, 3.3vout , and 1.5vout) note: once 3.3 v and 1.5 v are applied, the power switch follows the power-up sequence of figure 18 or figure 19. sysrst cpxx rclken refclk host power (auxin, 3.3vin, and 1.5vin) card power (auxout , 3.3vout , and 1.5vout) perst c d e a a tpd min max units ab 500 cd e 500 ns system dependent system dependent ns load dependent
tps2231 tps2236 slvs536e ? july 2004 ? revised september 2006 application information (continued) figure 22. timing signals - controlled power down when shdn asserted figure 23. timing signals - suprise card removal 22 submit documentation feedback www .ti.com e f a d f shdn cpxx rclken refclk host power (auxin, 3.3vin, and 1.5vin) card power (auxout , 3.3vout , and 1.5vout) perst tpd min max units ab c d e f 500 ns system dependent system dependentsystem dependent 500 load dependent ns c tpd min max units ab 500 ns cd 500 a d b c load dependent system dependent ns sysrst cpxx rclken refclk host power (auxin, 3.3vin, and 1.5vin) card power (auxout , 3.3vout , and 1.5vout) perst
package option addendum 28 ? sep ? 2006 addendum page 1 package information orderable device status (1) pkg type pkg drawing pins pkg qty eco plan (2) lead/ ball finish msl peak temp (3) tps2231mrgpr pre_prod qfn rgp 20 3000 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231mrgpt pre_prod qfn rgp 20 250 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231pw active tssop pw 20 70 green (rohs & no sb/ br) cu nipdau level - 1 - 260c - unlim tps2231pwg4 active tssop pw 20 70 green (rohs & no sb/ br) cu nipdau level - 1 - 260c - unlim tps2231pwp ac tive htssop pwp 24 60 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231pwpg4 active htssop pwp 24 60 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231pwpr active htssop pwp 24 2000 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231pwprg4 active htssop pwp 24 2000 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231pwr active tssop pw 20 2000 green (rohs & no sb/ br) cu nipdau level - 1 - 260c - unlim tps2231pwrg4 active tssop pw 20 2000 green (rohs & no sb/ br) cu nipdau level - 1 - 260c - unlim tps2231rgpr active qfn rgp 20 3000 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231rgprg4 active qfn rgp 20 3000 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231rgpt active qfn rgp 20 250 green ( rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year tps2231rgptg4 active qfn rgp 20 250 green (rohs & no sb/ br) cu nipdau level - 2 - 260c - 1 year (1) the marketing status values are defined as follows: active : product device recommended for new designs. lifeb uy : ti has announced that the device will be discontinued, and a lifetime - buy period is in effect. nrnd : not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. prev iew : device has been announced but is not in production. samples may or may not be available. obsolete : ti has discontinued the production of the device. (2) eco plan - the planned eco - friendly classification: pb - free (rohs), pb - free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd : the pb - free/green conversion plan has not been defined. pb - free (rohs) : ti's terms "lead - free" or "pb - fre e" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb - fr ee products are suitable for use in specified lead - free processes. pb - free (rohs exempt) : this component has a rohs exemption for either 1) lead - based flip - chip solder bumps used between the die and package, or 2) lead - based die adhesive used between the d ie and lead frame . the component is otherwise considered pb - free (rohs compatible) as defined above. green (rohs & no sb/br) : ti defines "green" to mean pb - free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications and peak solder temperature. important information and disclaimer : the information p rovided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. effort s are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materi als and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. cu stomers should obtain the latest relevant information before placing orders and should verify that such info rmation is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and othe r quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by governm ent requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti component s. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implie d, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are us ed. information published by ti regarding third-party products or services does not consti tute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the pat ents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, lim itations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements diffe rent from or beyond the parameters stated by ti for that product or service voids all express and any imp lied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.c om audio www.ti.com/audio data converters dataconverter.ti.co m automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 6553 03 dallas, texas 75265 copyright ? 2007, texas instruments incorporated

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