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1998 data sheet m pd3719 mos integrated circuit the m pd3719 is a color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the m pd3719 has 3 rows of 10600 pixels, and each row has a single-sided readout type of charge transfer register. it has reset feed-through level clamp circuits and voltage amplifiers. moreover, a large dynamic range is realized by using a large saturation voltage and a low-noise amplifier. therefore, it is suitable for 1200 dpi/a4 professional color image scanners and so on. features ? valid photocell : 10600 pixels 3 ? photocell's pitch : 7 m m ? line spacing : 70 m m (10 lines) red line-green line, green line-blue line ? color filter : primary colors (red, green and blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 48 dot/mm a4 (210 297 mm) size (shorter side) 1200 dpi us letter (8.5 11) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 2 mhz max. ? power supply : +15 v ? on-chip circuits : reset feed-through level clamp circuits voltage amplifiers ordering information part number package m pd3719d ccd linear image sensor 36-pin ceramic dip (600 mil) document no. s13492ej1v0ds00(1st edition) date published september 1998 n cp(k) printed in japan 10600 pixels 3 color ccd linear image sensor the information in this document is subject to change without notice.
m pd3719 2 block diagram 33 35 2 34 32 15 25 24 23 21 14 13 12 4 5 6 d14 d64 d65 d66 s10599 s10600 s1 s2 photocell (blue) transfer gate ccd analog shift register d67 d14 d64 d65 d66 s10599 s10600 s1 s2 photocell (green) transfer gate ccd analog shift register d67 d14 d64 d65 d66 s10599 s10600 s1 s2 photocell (red) transfer gate ccd analog shift register d67 tg f gnd rb f v rd v od 2 f 1 f 2 f 1 f gnd gnd v out 3 (red) v out 2 (green) v out 1 (blue) 22 gnd gnd 3 31 gnd gnd clb f
m pd3719 3 pin configuration (top view) ccd linear image sensor 36-pin ceramic dip (600 mil) 1 2 3 4 5 6 10 11 12 13 14 35 34 33 32 31 27 26 25 24 23 36 nc nc v out 2 v out 1 nc 1 f tg f no connection no connection output signal 2 (green) output signal 1 (blue) ground no connection shift register clock 1 ground nc v out 3 v rd nc 1 f output drain voltage reset drain voltage output signal 3 (red) ground reset gate clock shift register clock 2 no connection no connection shift register clock 1 10600 10600 10600 red green blue 1 1 1 no connection transfer gate clock gnd nc 2 f 2 f shift register clock 2 gnd ground gnd f v od rb gnd 7 8 9 15 16 17 18 30 29 28 22 21 20 19 nc nc nc nc nc nc gnd nc no connection no connection no connection no connection no connection ground no connection no connection f clb gnd nc nc nc nc gnd ground no connection reset feed-through level clamp clock no connection no connection no connection ground
m pd3719 4 photocell structure diagram photocell array structure diagram (line spacing) blue photocell array 7 m m green photocell array 7 m m red photocell array 7 m m 10 lines (70 m) m 10 lines (70 m) m m 7 m m 4 m m m 3 channel stopper aluminum shield
m pd3719 5 absolute maximum ratings (t a = +25 c) parameter symbol ratings unit output drain voltage v od C0.3 to +16 v reset drain voltage v rd C0.3 to +16 v shift register clock voltage v f 1 , v f 2 C0.3 to +8 v reset gate clock voltage v f rb C0.3 to +8 v reset feed-through level clamp clock voltage v f clb C0.3 to +8 v transfer gate clock voltage v f tg C0.3 to +8 v operating ambient temperature t a C25 to +60 c storage temperature t stg C40 to +100 c caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. recommended operating conditions (t a = +25 c) parameter symbol min. typ. max. unit output drain voltage v od 14.0 15.0 16.0 v reset drain voltage v rd 14.0 v od v od v shift register clock high level v f 1h , v f 2h 4.5 5.0 5.5 v shift register clock low level v f 1l , v f 2l C0.3 0 +0.5 v reset gate clock high level v f rbh 4.5 5.0 5.5 v reset gate clock low level v f rbl C0.3 0 +0.5 v reset feed-through level clamp clock high level v f clbh 4.5 5.0 5.5 v reset feed-through level clamp clock low level v f clbl C0.3 0 +0.5 v transfer gate clock high level v f tgh 4.5 v f 1h note v f 1h note v transfer gate clock low level v f tgl C0.3 0 +0.3 v data rate f f rb C 1 2 mhz note when transfer gate clock high level (v f tgh ) is higher than shift register clock high level (v f 1h ), image lag can increase.
m pd3719 6 electrical characteristics t a = +25 c, v od = 15 v, v rd = 15 v, data rate (f f rb ) = 2 mhz, storage time = 5.5 ms, light source: 3200 k halogen lamp +c-500s (infrared cut filter, t = 1mm), input signal clock = 5 v p-p parameter symbol test conditions min. typ. max. unit saturation voltage v sat 4.0 5.0 C v saturation exposure red ser 0.52 lx?s green seg 0.57 lx?s blue seb 0.94 lx?s photo response non-uniformity prnu v out = 2.5 v 6 20 % average dark signal ads light shielding 0.8 3.0 mv dark signal non-uniformity dsnu light shielding 1.5 5.0 mv power consumption p w 400 600 mw output impedance z o 0.5 1 k w response red r r 6.8 9.7 12.6 v/lx?s green r g 6.2 8.8 11.4 v/lx?s blue r b 3.8 5.3 6.8 v/lx?s image lag il v out = 2.5 v 2.0 5.0 % offset level note1 v os 8.8 10.8 12.8 v output fall delay time note2 t d v out = 2.5 v 70 ns total transfer efficiency tte v out = 2.5 v 92 98 % response peak red 630 nm green 540 nm blue 460 nm dynamic range dr1 v sat /dsnu 3333 times dr2 v sat / s 10000 times reset feed-through noise note1 rftn light shielding 0 1500 2500 mv random noise s light shielding C 0.5 C mv notes 1. refer to timing chart 2 . 2. when the fall time of f 1 (t1) is the typ. value (refer to timing chart 2 ).
m pd3719 7 input pin capacitance (t a = +25 c, v od = v rd = 15 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c f 1 f 1 13 1600 pf 24 1600 pf shift register clock pin capacitance 2 c f 2 f 2 12 1600 pf 25 1600 pf reset gate clock pin capacitance c f rb f rb 5 15 pf reset feed-through level clamp clock pin capacitance c f clb f clb 31 15 pf transfer gate clock pin capacitance c f tg f tg 23 200 pf remark pins 13 and 24 ( f 1), 12 and 25 ( f 2) are each connected inside of the device.
m pd3719 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 61 62 63 64 65 66 10663 10664 10665 10666 10667 10668 10669 note note optical black (49 pixels) invalid photocell (2 pixels) valid photocell (10600 pixels) invalid photocell (3 pixels) tg f 1 2 f f rb f v out 1 to f clb v out 3 timing chart 1 (for each color) note input the f rb and f clb pulses continuously during this period, too.
m pd3719 9 f v out 1 to v out 3 clb f rb f 2 f 1 90 % 10 % 90 % 10 % 90 % 10 % 90 % 10 % rftn v os t2 t1 t4 t6 t3 t5 t10 t8 t7 t9 t11 t d timing chart 2 (for each color) 10 %
m pd3719 10 f tg, f 1, f 2 timing chart symbol min. typ. max. unit t1, t2 0 25 ns t3 30 50 ns t4 70 150 ns t5, t6 0 25 ns t7 30 75 ns t8, t9 0 25 ns t10 10 20 ns t11 5 10 ns t12, t13 0 50 ns t14 3000 10000 ns t15, t16 900 1000 ns remark typ. is an example of at 1 mhz data rate (f f rb ) operation. f 1, f 2 cross points remark adjust cross points of f 1 and f 2 with input resistance of each pin. 1 f 2 f t15 90 % 10 % 90 % tg f t12 t14 t13 t16 2 f 1 f 2 v or more 2 v or more
m pd3719 11 definitions of characteristic items 1. saturation voltage: v sat output signal voltage at which the response linearity is lost. 2. saturation exposure: se product of intensity of illumination (i x ) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity: prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. 4. average dark signal: ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. 5. dark signal non-uniformity: dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. ads (mv) = d j : dark signal of valid pixel number j 10600 s j=1 10600 d j d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j - ads ? j = 1 to 10600 x register dark dc level v out d x ads dsnu register dark dc level v out prnu (%) = x = x j : output voltage of valid pixel number j d x d x : maximum of ? x j - x ? x 10600 s j=1 10600 x j 100
m pd3719 12 6. output impedance: z o impedance of the output pins viewed from outside. 7. response: r output voltage divided by exposure (ix?s). note that the response varies with a light source (spectral characteristic). 8. image lag: il the rate between the last output voltage and the next one after read out the data of a line. 9. random noise: s random noise s is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). v i : a valid pixel output signal among all of the valid pixels for each color this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling). v 1 il (%) = 100 v out s (mv) = , v = s i=1 100 (v i ?v) 2 s i=1 100 v i 100 100 1 v out f tg light v out on off v 1 v 1 v 100 v 2 ? ? line 2 line 100 line 1 v out
m pd3719 13 standard characteristic curves dark output temperature characteristic storage time output voltage characteristic (t a = +25 ?) operating ambient temperature t a (?) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 400 500 600 700 800 100 80 60 40 20 0 b b g r g response ratio (%) wavelength (nm) total spectral response characteristics (without infrared cut filter) (t a = +25 ?)
m pd3719 14 application circuit example remark the inverters shown in the above application circuit example are the 74hc04. nc nc v out 2 gnd v out 3 gnd v od rb v rd nc nc nc v out 1 gnd clb nc nc nc nc nc nc 2 nc 2 1 nc gnd gnd nc nc 1 tg gnd gnd nc nc m f f f f f f pd3719 f + 10 m f/16 v 0.1 m f + 47 m f/25 v 0.1 m f +5 v +15 v + 10 m f/16 v 0.1 m f +5 v b3 b2 b1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 4.7 w 4.7 w 4.7 w 4.7 w 4.7 w 47 w 47 w 10 w 1 f tg f clb f rb f 2 f + 47 m f/25 v 47 f/25 v b1 to b3 equivalent circuit + m 15 v 100 w 100 w ccd v out 2sc945 2 k w
m pd3719 15 package drawing name dimensions refractive index glass cap 93.0 13.6 1.0 1.5 1 the 1st valid pixel the center of the pin1 2 the 1st valid pixel the center of the package 3 the surface of the chip the top of the glass cap (reference) 4 the bottom of the package the surface of the chip 36d-1ccd-pkg-1 ccd linear image sensor 36-pin ceramic dip (600mil) the 1st valid pixel 2.54 20.32 15.24 94.00 0.50 0.46 0.05 1.27 0.05 (4.33) 3.50 0.5 2.0 0.3 4 0.25 0.05 0.97 0.3 3.30 0.35 88.9 0.6 14.99 0.3 8.1 0.6 1 36.4 0.6 2 (2.33) 3 (unit : mm)
m pd3719 16 notes on the use of the package the application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. when mounting the package, use a circuit board which will not subject the package to bending stress, or use a socket. for this product, the reference value for the three-point bending strength note is 30 kg. avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body (ceramic). note three-point bending strength test distance between supports: 70 mm, support r: r 2 mm, loading rate: 0.5 mm / min. load load 70 mm 70 mm
m pd3719 17 [memo]
m pd3719 18 [memo]
m pd3719 19 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd3719 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

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