uc1572 uc2572 uc3572 description the uc3572 is a negative output flyback pulse width modulator which con - verts a positive input voltage to a regulated negative output voltage. the chip is optimized for use in a single inductor negative flyback switching con - verter employing an external pmos switch. the block diagram consists of a precision reference, an error amplifier configured for voltage mode opera - tion, an oscillator, a pwm comparator with latching logic, and a 0.5a peak gate driver. the uc3572 includes an undervoltage lockout circuit to insure sufficient input supply voltage is present before any switching activity can occur, and a pulse-by-pulse current limit. output current can be sensed and limited to a user determined maximum value. the uvlo circuit turns the chip off when the input voltage is below the uvlo threshold. in addition, a sleep comparator interfaces to the uvlo circuit to turn the chip off. this re - duces the supply current to only 50 a, making the uc3572 ideal for battery powered applications. negative output flyback pulse width modulator features ? simple single inductor flyback pwm for negative voltage generation ? drives external pmos switch ? contains uvlo circuit ? includes pulse-by-pulse current limit ? low 50 a sleep mode current slus275a - march 1999 - revised august 2001 block diagram udg-94094-2
2 uc1572 uc2572 uc3572 absolute maximum ratings vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35v eainv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6v to vcc i eaout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma ramp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4v cs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7a to 0.7a i 3vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15ma storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . -65c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . +300c currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. dil-8, soic-8 (top view) d, n or j packages connection diagram temperature range package uc1572 ?55c to +125c j uc2572 ?40c to +85c d, n or j uc3572 0c to +70c d or n ordering information electrical characteristics: unless otherwise specified, vcc = 5v, ct = 680pf, t a =t j . parameter test conditions min typ max units reference section 3vref 2.94 3 3.06 v line regulation vcc = 4.75 to 30v 1 10 mv load regulation i 3vref = 0v to ?5ma 1 10 mv oscillator section frequency vcc = 5v to 30v 85 100 115 khz error amp section eainv eaout = 2v ?10 0 10 mv i eanv = ?1ma ?0.2 ?0.9 v i eainv eaout = 2v ?0.2 ?1.0 a avol eaout = 0.5v to 3v 65 90 db eaout high eainv = ?100mv 3.6 4 4.4 v eaout low eainv = 100mv 0.1 0.2 v i eaout eainv = ?100mv, eaout = 2v ?350 ?500 a eainv = 100mv, eaout = 2v 7 20 ma unity gain bandwidth t j = 25c, f = 10khz 0.6 1 mhz current sense comparator section threshold 0.185 0.205 0.225 v input bias current cs = 0 ?0.4 ?1 a cs propogation delay 300 ns
3 uc1572 uc2572 uc3572 electrical characteristics: unless otherwise specified, vcc = 5v, ct = 680pf, t a =t j . parameter test conditions min typ max units gate drive output section out high saturation i out = 0 0 0.3 v i out = ? 10ma 0.7 1.5 v i out = ? 100ma 1.5 2.5 v out low saturation i out = 10ma 0.1 0.4 v i out = 100ma 1.5 2.2 v rise time t j = 25 c, c load = 1nf + 3.3 ohms 30 80 ns fall time t j = 25 c, c load = 1nf + 3.3 ohms 30 80 ns pulse width modulator section maximum duty cycle eainv = +100mv, vcc = 5v to 30v 92 96 % minimum duty cycle eainv = ? 100mv, vcc = 5v to 30v 0 % modulator gain eaout = 1.5v to 2.5v 45 55 65 %/v undervoltage lockout section start threshold 3.5 4.2 4.5 v hysteresis 100 200 300 mv sleep mode section threshold 1.8 2.2 2.6 v supply current section ivcc vcc = 5v, 30v 9 15 ma vcc = 30, cs = 3v 50 150 a figure 1. typical waveforms. udg-94095
4 uc1572 uc2572 uc3572 4 8 7 1 2 6 5 3 r sleep1 56k r sleep2 33k r comp r ref rv sense 40k rsleep3 1meg r cs c in 10 f cout 100 f vout gnd ? 12v out d flyback l flyback m switch c ramp 680pf cv cc 10 f m sleep gnd sleep vin vcc 3vref ramp eainv eaout gnd cs out uc1572 c3v ref 100nf c comp figure 2. typical application: +5v to ?12v flyback converter. udg-99057 pin descriptions 3vref: precision 3v reference. bypass with 100nf ca - pacitor to gnd. cs: current limit sense pin. connect to a ground refer - enced current sense resistor in series with the flyback in - ductor. out will be held high (pmos switch off) if cs exceeds 0.2v. eainv: inverting input to error amplifier. summing junc - tion for 3vref and vout sense. the non-inverting input of the error amplifier is internally connected to gnd. this pin will source a maximum of 1ma. eaout: output of error amplifier. use eaout and eainv for loop compensation components. gnd: circuit ground. out: gate drive for external pmos switch connected between v cc and the flyback inductor. out drives the gate of the pmos switch between v cc and gnd. ramp: oscillator and ramp for pulse width modulator. frequency is set by a capacitor to gnd by the equation f kc ramp = ? 1 15 recommended operating frequency range is 10khz to 200khz. vcc: input voltage supply to chip. range is 4.75 to 30v. bypass with a 1 f capacitor.
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