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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7677 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 16-bit, 1 lsb inl, 1 msps differential adc functional block diagram control logic and calibration circuitry clock ob/ 2c 16 data[ 15:0] busy cs ser/ par ognd ovdd dgnd dvdd serial port p arallel interface byteswap rd av d d a gnd ref refgnd pd reset cnvst in switched cap dac ad7677 in+ impulse w arp pulsar selection type/ksps 100?50 500?70 1000 pseudo ad7660 ad7650 differential ad7664 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 features throughput: 1 msps inl: 1 lsb max ( 0.0015% of full scale) 16 bits resolution with no missing codes s/(n+d): 94 db typ @ 45 khz thd: ?10 db typ @ 45 khz differential input range: 2.5 v both ac and dc specifications no pipeline delay parallel (8 bits/16 bits) and serial 5 v/3 v interface single 5 v supply operation 115 mw typical power dissipation, 15 w @ 100 sps power-down mode: 7 w max packages: 48-lead quad flatpack (lqfp) 48-lead frame chip scale (lfcsp) pin-to-pin compatible upgrade of the ad7664/ad7675/ ad7676 applications ct scanners data acquisition instrumentation spectrum analysis medical instruments battery-powered systems process control general description the ad7677 is a 16-bit, 1 msps, charge redistribution sar, fully differential, analog-to-digital converter that operates from a single 5 v power supply. the part contains a high speed 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. the ad7677 is hardware factory calibrated and comprehen- sively tested to ensure such ac parameters as signal-to-noise ratio (snr) and total harmonic distortion (thd), in addition to the more traditional dc parameters of gain, offset, and linear ity. it features a very high sampling rate mode (warp); a fast mode (normal) for asynchronous conversion rate applica- tions; and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. the ad7677 is available in a 48-lead lqfp or a tiny 48-lead lfcsp w ith operation specified from ?0 c to +85 c. product highlights 1. excellent inl the ad7677 has a maximum integral nonlinearity of 1 lsb with a no missing 16-bit code. 2. superior ac performances the ad7677 has a minimum dynamic of 92 db, 94 db typi cal. 3. fast throughput the ad7677 is a 1 msps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 4. single-supply operation the ad7677 operates from a single 5 v supply and typically dissipates only 115 mw. its power dissipation decreases with the throughput. it consumes 7 w maximum when in power- down. 5. serial or parallel interface versatile parallel (8 bits or 16 bits) or 2-wire serial inter- face arrangement compatible with both 3 v or 5 v logic. * patent pending
rev. a e2e ad7677especifications (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise stated.) parameter conditions min typ max unit resolution 16 bits analog input voltage range v in+ e v ine ev ref +v ref v operating input voltage v in+, v ine to agnd e0.1 +3 v analog input cmrr f in = 10 khz 85 db input current 1 msps throughput 11 a input impedance see analog input section throughput speed complete cycle in warp mode 1 s throughput rate in warp mode 0.001 1 msps time between conversions in warp mode 1 ms complete cycle in normal mode 1.25 s throughput rate in normal mode 0 800 ksps complete cycle in impulse mode 1.5 s throughput rate in impulse mode 0 666 ksps dc accuracy integral linearity error e1 +1 lsb 1, 2 differential linearity error e1 +1 lsb 2 no missing codes 16 bits transition noise 0.35 lsb +full-scale error 3 in warp mode e25 +25 lsb efull scale error 3 in warp mode e20 +20 lsb zero error 3 in warp mode e15 +15 lsb +full-scale error 3 in impulse or normal mode e40 +40 lsb efull scale error 3 in impulse or normal mode e20 +20 lsb zero error 3 in impulse or normal mode e23 +23 lsb power supply sensitivity avdd = 5 v 5% 1.4 lsb ac accuracy signal-to-noise f in = 20 khz 92 94 db 2, 4 f in = 45 khz 94 db spurious free dynamic range f in = 20 khz 104.5 110 db 2 f in = 45 khz 110 db total harmonic distortion f in = 20 khz e110 e103.5 db 2 f in = 45 khz e110 db signal-to-(noise+distortion) f in = 20 khz 92 94 db 2 f in = 45 khz 94 f in = 45 khz, e60 db input 34 db e3 db input bandwidth 15.8 mhz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd e 1.85 v external reference current drain 1 msps throughput 37 a digital inputs logic levels v il e0.3 +0.8 v v ih 2.0 dvdd + 0.3 v i il e1 +1 a i ih e1 +1 a digital outputs data format parallel or serial 16-bit conversion pipeline delay results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = e100 a ovdd e 0.6 v
rev. a e3e ad7677 parameter conditions min typ max unit power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 5 v operating current 2 1 msps throughput avdd 16.7 ma dvdd 6 6.4 ma ovdd 6 69 a power dissipation 6 666 ksps throughput 7 87 98 mw 100 sps throughput 7 15 w 1 msps throughput 2 115 130 mw in power-down mode 8 7 w temperature range 9 specified performance t min to t max e40 +85 c notes 1 lsb means least significant bit. with the 2.5 v input range, one lsb is 76.3 v. 2 in warp mode. 3 tested with v ref = 2.5 v. see definition of specifications section. these specifications do not include the error contribution from the external reference. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full scale unless o therwise specified. 5 the max should be the minimum of 5.25 v and dvdd + 0.3 v. 6 tested in parallel reading mode. 7 in impulse mode. 8 with ovdd below dvdd + 0.3 v and all digital inputs forced to dvdd or dgnd, respectively. 9 contact factory for extended temperature range. specifications subject to change without notice.
rev. a ad7677 e4e timing specifications symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5ns time between conversions t 2 1/1.25/1.5 note 1 s (warp mode/normal mode/impulse mode) cnvst shihd shiha 2 src (ni ad 2 csd ct 2 (ni at 2 rstp r(pi cnvst datavd 2 (ni datavsd ardatav 2 rt r(si 2 cs sncvd cs iscvd cs sdtd cnvst sncd(rdc 222 (ni sncascd iscp 2 ischih 2 2 isc 2 sdtvst 22 sdtvht 2 2 scsncd 2 cs hihsnchi 2 cs hihischi 2 cs hihsdthi 2 shihsrac 2 sti cnvst sncad 2 2 (ni sncdsd 2 r2(ssi scst scasdtd 2 sdinst sdinht scp 2 schih sc nts i 2 isncscsdtc isti s ( c cavdddvdd vvdd2v2v
rev. a ad7677 e5e ordering guide model temperature range package description package option ad7677ast e40 c to +85 cq uad flatpack (lqfp) st-48 ad7677astrl e40 c to +85 cq uad flatpack (lqfp) st-48 AD7677ACP e40 c to +85 cc hip scale (lfcsp) cp-48 AD7677ACPrl e40 c to +85 cc hip scale (lfcsp) cp-48 eval-ad7677cb 1 evaluation board eval-control brd2 2 controller board notes 1 this board can be used as a stand-alone evaluation board or in conjunction with the eval-control brd2 for evaluation/ demonstration purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7677 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 analog inputs in+ 2 , ine 2 , ref, refgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avdd + 0.3 v to agnd e 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . e0.3 v to +7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v digital inputs . . . . . . . . . . . . . . . . . e0.3 v to dvdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. 4 specification is for device in free air: lfcsp: ja = 26 c/w to output pin c l 60pf 1 500 a i oh 1.6ma i ol 1.4v in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. note 1 figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l =10pf 0.8v 2v 2v 0.8v t dela y 2v 0.8v t delay figure 2. voltage reference levels for timings table i. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] 0 1 0 1 unit sync to sclk first edge delay minimum t 18 3171717ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period maximum t 19 40 70 140 280 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7214999ns sdout valid setup time minimum t 22 4181818ns sdout valid hold time minimum t 23 24 30 89 ns sclk last edge to sync delay minimum t 24 360 140 300 ns busy high width maximum (warp) t 24 1.5 2 3 5.25 s busy high width maximum (normal) t 24 1.75 2.25 3.25 5.55 s busy high width maximum (impulse) t 24 2 2.5 3.5 5.75 s
rev. a ad7677 e6e pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p analog power pin. nominally 5 v. 3, nc no connect 40e42, 44e48 4 byteswap di parallel mode selection (8-bit/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d [7:0]. 5ob/ 2c di stc 2c hih s arp di shihips ips di shiharp i sr par di spsihih data data d ppdsr par hih 2 data2 di sr par 2ppd divsc sr par hiht int rdcsdin t i data di sr par ppd t int sr par hih t int sct int hih zsc data di sr par ppd invsnc sr par hih sncsnchihhihsnc data di sr par ppd invsc sr par hihsc i data di sr par ppd rdcsdin sr par hih t int t int hihrdcsdin adcsdttsdin datasct int rdcsdinrdcsdinhih sdtrdcsdin sdt nd p iidp vdd p iidpn (vv
rev. a ad7677 e7e pin function descriptions (continued) pin no. mnemonic type description 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground 21 data[8] do when ser/ par ppd sdt sr par hih zscctad stdata 2c it int sdt scit int hihiinvsc sdtsciinvsc hihsdtsc 22 data di sr par ppd sc sr par hih t int t sdtinvsc 2 data d sr par ppd snc sr par hih z(t int invsncsnchihhih sdtinvsnchih sncsdt 2 data d sr par ppd rdrrr sr par hiht int hih i rdrrr 22 data2 d 2ppdt sr par 2 s d thihhih t s dnd p rd di rd cs rd 2 cs di cs cs rd cs rst di rihihadc pd di pdihih cnvst di sca cnvst i(ipshiharp cnvst ( and p ta r ai riv rnd ai ria in ai dnai in ai dpai nts aiai didi did dd pp
rev. a ad7677 e8e definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a best-fit line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. +full-scale error t he last transition (from 011 . . . 10 to 011 . . . 11 in two?s c omplement coding) should occur for an analog voltage 1 1/2 lsb below the nominal +full scale (2.499886 v for the 2.5 v range). the +full-scale error is the deviation of the actual level of the last transition from the ideal level. efull-scale error the first transition (from 100 . . . 00 to 100 . . . 01 in two?s c omplement coding) should occur for an analog voltage 1/2 lsb above the nominal efull scale (e2.499962 v for the 2.5 v range). the efull-scale error is the deviation of the actual level of the first transition from the ideal level. zero error the zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: enob s n d db =+ [] () /e./. 176 602 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic com ponents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst transintrspns tad pincniratin p (st 2 2 2 2 2 2 2 2 22 2 2 2 2 2 pin idntiir tp vi (ns a nd cnvst pd rst cs rd dnd a nd av d d nc tsap 2c arp ips ncncnnct sr par d d d2divsc s d d d ad ddivsc d2 nc nc nc nc nc in nc nc nc in rnd r dt int dinvsnc dinvsc drdcsdin nd vdd dvdd dnd dsdt dsc dsnc drdrrr
rev. a e9e t ypical performance characteristicsead7677 code 1.00 0 16384 32768 49152 65536 inl e lsb 0.75 0.25 0.00 e0.50 e1.00 0.50 e0.25 e0.75 tpc 1. integral nonlinearity vs. code code in hexa 9000 7ffb 0 counts 8000 6000 4000 2000 0000 7000 3000 1000 5000 7ffc 0 7ffd 0 7ffe 10 7fff 8287 8000 8066 8001 21 8002 0 8003 0 8004 0 tpc 2. histogram of 16,384 conversions of a dc input at the code transition positive inl e lsb 20 0.1 number of units 16 8 0 12 4 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 0.0 1.0 tpc 3. typical positive inl distribution (199 units) code 1.00 0 16384 32768 49152 65536 dnl e lsb 0.75 0.25 0.00 e0.50 e1.00 0.50 e0.25 e0.75 tpc 4. differential nonlinearity vs. code code in hexa 16000 7ffb 0 counts 14000 8000 4000 0000 12000 6000 2000 10000 7ffc 0 7ffd 1 7ffe 994 7fff 8000 1037 8001 0 8002 0 8003 0 8004 0 7ffa 0 14352 tpc 5. histogram of 16,384 conversions of a dc input at the code center negative inl e lsb 20 e0.9 number of units 16 8 0 12 4 e0.8 e0.7 e0.6 e0.5 e0.4 e0.3 e0.2 e0.1 1.0 e1.0 0.0 tpc 6. typical negative inl distribution (199 units)
rev. a ad7677 e10e frequency e khz 0 amplitude e db of full scale e100 e180 e60 e140 100 200 300 500 0 400 e20 e40 e120 e80 e160 f s = 1msps f in = 45.01khz snr = 93.5db thd = e109.5db sfdr = 109db sinad = 93db tpc 7. fft plot frequency e khz 100 snr and s/[n+d] e db 90 70 80 10 1000 1 100 95 85 75 16.0 enob e bits 15.0 13.0 14.0 15.5 14.5 13.5 snr sinad enob tpc 8. snr, s/(n+d), and enob vs. frequency input level e db 96 snr (referred to full scale) e db 88 92 e40 0 e60 e20 94 90 snr sinad e50 e30 e10 tpc 9. snr and s/(n+d) vs. input level temperature e c 96 snr e db 84 90 25 125 e55 93 87 snr thd e35 65 45 5 105 e15 85 e104 thd e db e112 e108 e106 e110 tpc 10. snr, thd vs. temperature c l e pf 50 t 12 delay e ns 0 20 200 0 40 10 100 50 150 30 ov dd = 5.0v @ 25 c ov dd = 5.0v @ 85 c ov dd = 2.7v @ 25 c ov dd = 2.7v @ 85 c tpc 11. typical delay vs. load capacitance c l sampling rate e sps 1m operating currents e a 0.001 1m 10k 1k 100 10 1 0.1 0.01 100k 10k 1k 100 10 av dd, warp/normal dv dd, warp/normal av d d, impulse dvdd, impulse ovdd, all modes tpc 12. operating currents vs. sample rate
rev. a ad7677 e11e temperature e c 250 power-down operating currents e na 0 100 e15 105 e55 45 150 50 dvdd e35 5 85 25 65 200 ovdd av d d tpc 13. power-down operating currents vs. temperature circuit information the ad7677 is a very fast, low power, single-supply, precise, 16-bit analog-to-digital converter (adc). the ad7677 features different modes to optimize performances according to the applications. in warp mode, the ad7677 is capable of converting 1,000,000 samples per second (1 msps). the ad7677 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. the ad7677 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp package that combines space savings and flexible configurations as either serial or parallel interface. the ad7677 is a pin-to-pin compatible upgrade of the ad7664, ad7675, and ad7676. converter operation the ad7677 is a successive approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac con- sists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparator?s input are connected to agnd via sw + and sw e . all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on in+ and ine inputs. when the acquisition phase is complete and the cnvst s s t rndt inin rndr (v r 2v r v r ts a adcs tadn i in r rnd in 2c c s c 2c c c s s sitchs cntr 2c c s c 2c c c s s s tpt cd cnvst cntr ic cp adcss tpratr c s 2 2 s st s tpc dt
rev. a ad7677 e12e the warp mode allows the fastest conversion rate up to 1 msps. however, in this mode, and this mode only, the full specified accu- racy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two consecutive conver sions is longer than 1 ms, for instance, after power-up, the first con ver- sion result should be ignored. this mode makes the ad7677 ideal for applications where fast sample rates are required. the normal mode is the fastest mode (800 ksps) without any limitation about the time between conversions. this mode m akes the ad7677 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput in this mode is 666 ksps. when operating at 100 sps, for ex ample, it typically consumes only 15 w. this feature makes the ad7677 ideal for battery-powered applications. transfer functions using the ob/ 2c ad t ad anainpt ss s s ss s ss adccds adcit tpicacnnctindiara ad d ai ad av d d a nd dnd dvdd vdd nd sr par cnvst s sdt sc rd cs rst pd rnd c r 2vr nt r d cc ad c pdsp sriaprt diitaspp (vrv ana spp (v dvdd 2c nt tsap dvdd in anainpt c c 2 nt nt ad2 nt2 nt nt adr2 in anainpt c c 2 2 nt nt ad2 nts svtarrncinptsctin 2ithth rcnddvta rrncs c r is schaptrvtarrncinptsctin ptinacircitrrhardaraincairatin thad2isrcnddsdrivrapiirchicsctin sanainptsctin ptinsprsppsctin ptinaittr cnvst scnvrsincntrsctin tcd
rev. a ad7677 e13e in+ ine a gnd av d d r+ = 168 c s c s re = 168 figure 6. simplified analog input the diodes shown in figure 6 provide esd protection for the inputs. care must be taken to ensure that the analog input sig- nal never exceeds the absolute ratings on these inputs. this will cause these diodes to become forward-biased and start conduct- ing current. these diodes can handle a forward-biased current of 120 ma maximum. this condition could eventually occur when the input buffer?s (u1) or (u2) supplies are different from avdd. in such case, an input buffer with a short-circuit current limitation can be used to protect the part. this analog input structure is a true differential structure. by using these differential inputs, signals common to both inputs are rejected as shown in figure 7, which represents the typical cmrr over frequency. frequency e hz 90 cmrr e db 45 75 10k 10m 1k 1m 80 65 100k 55 85 70 60 50 figure 7. analog input cmrr vs. frequency during the acquisition phase, for ac signals, the ad7677 be haves like a one-pole rc filter consisting of the equivalent resis- tance r+ , re, and c s . the resistors r+ and re are typically 168 v and are lumped components made up of some serial resistors and the on resistance of the switches. the capacitor c s is typically 60 pf and is mainly the adc sampling capacitor. this one-pole filter with a typical e3 db cutoff frequency of 15.8 mhz reduces undesirable aliasing effect and limits the noise com- ing from the inputs. because the input impedance of the ad7677 is very high, the ad7677 can be driven directly by a low impedance source with out gain error. that allows the user to input, as shown in figure 5, an external one-pole rc filter between the output of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the ad7677 analog input circuit. however, the source impedance has to be kept low b ecause it affects the ac performances, especially the total har- monic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades proportionally to the source impedance. single to differential driver for applications using unipolar analog signals, a single-ended- to-differential driver will allow for a differential input into the part. the schematic is shown in figure 8. u2 590 590 2.5v ref c c ad8021 590 ad7677 in+ ine ref 2.5v ref u1 analog input (unipolar) c c ad8021 590 figure 8. single-ended-to-differential driver circuit this configuration, when provided an input signal of 0 to v ref , will produce a differential 2.5 v with midscale at 1.25 v. if the application can tolerate more noise, the ad8138 can be used. driver amplifier choice although the ad7677 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the ad7677 analog input circuit have to be able together to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifier?s data sheet, the settling at 0.1% or 0.01% is more commonly specified. it could significantly differ from the settling time at a 16-bit level and, therefore, it should be verified prior to the driver selection. the tiny op-amp, ad8021, which combines ultralow noise and a high gain bandwidth, meets this settling time requirement even when used with a high gain up to 13. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi- tion noise performance of the ad7677. the noise coming from the driver is filtered by the ad7677 analog input circuit one-pole, low-pass filter made by r+, re, and c s . the snr degradation due to the amplifier is: snr log fne loss db n = + () 20 28 784 4 3 2 e where f e3 db is the e3 db input bandwidth in mhz of the ad7677 (15.8 mhz) or the cutoff frequency of the input filter if any used. n is the noise factor of the amplifiers (1 if in buffer con- figu ration). e n is the equivalent input noise voltage of each opamp in nv / (hz) 1/2 .
rev. a ad7677 e14e for instance, a driver with an equivalent input noise of 2 nv/ hz (ad2 snr 2 tthd ad tad2 tad2 t np tad22 tad2ad tad2( hzi 2 tad vri tad2vt rad t r rndt sr rrnd tadr2ad t adr2 t ad2 ad ad c c s c nv r avddvs v r vv snr t (22d z tad v rnchz psrr psrr ps tad v avddvdvdd vddtvdd 2v dvddvt ( dvddrc t ad vdd dvddv a prdissipatin iiad d tad i t (dvdddndvdd dvddv sapinratsps prdissipatin arpnra ips pdsr
rev. a ad7677 e15e conversion control figure 11 shows the detailed timing diagrams of the conversion process. the ad7677 is controlled by the signal cnvst pd t cnvst cs rd iii cnvst sad cnvst ad i sa cnvst iad i spst n cnvst 2 d acir cnvrt acir cnvrt s ct acnvst snrcnvst s cnvst rst data s cnvst 2 rstt diitaintrac tad tt advv vddad 2c t cs rd cs ad ad rd cnvst s data s cs rd prviscnvrsindata ndata pdtr (cr paraintrac tad( sr par t t data s 2 s cs rd crrnt cnvrsin spdtr(r ac cs cnvst rd prvis cnvrsin data s 2 s spdtr(r dc
rev. a ad7677 e16e the byteswap pin allows a glueless interface to an 8-bit bus. as shown in figure 16, the lsb byte is output on d[7:0] and the msb is output on d[15:8] when byteswap is low. when byteswap is high, the lsb and msb bytes are swapped and the lsb is output on d[15:8] and the msb is output on d[7:0]. by connecting byteswap to an address line, the 16 bits of data can be read in 2 bytes on either d[15:8] or d[7:0]. cs rd byte pins d[15:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 12 t 12 t 13 figure 16. 8-bit parallel interface t 3 busy cs , rd cnvst sync sclk sdout 123 141516 d15 d14 d2 d1 d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 14 t 20 t 15 t 16 t 22 t 23 t 29 t 28 t 18 t 19 t 21 t 30 t 25 t 24 t 26 t 27 figure 17. master serial data timing for reading (read after convert) rdc/sdin = 1 invsclk = invsync = 0 d15 d14 d2 d1 d0 x 123 141516 busy sync sclk sdout cs , rd cnvst t 3 t 1 t 17 t 14 t 15 t 19 t 20 t 21 t 16 t 22 t 23 t 24 t 27 t 26 t 25 t 18 ext/ int = 0 figure 18. master serial data timing for reading (read previous conversion during convert)
rev. a ad7677 e17e serial interface the ad7677 is configured to use the serial interface when the ser/par is held high. the ad7677 outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on the sclk pin. master serial interface internal clock the ad7677 is configured to generate and provide the serial data clock sclk when the ext/ int p tad snc tscsnc t drdc sdin ad i s s i z t divsc savsriaintrac c tad sct int i t cs cs rd t cs t a cs sc sdt d d d d d s sdin invsc 2 t int rd 2 ssdtr(rac cnvst sdt sc d d d d d 2 s invsc cs t int rd 2 2 ssdtr(rpcdc
rev. a ad7677 e18e normally high or normally low when inactive. figure 19 and figure 20 show the detailed tim ing diagrams of these methods. while the ad7677 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degra- dation of the conversion result could occur. this is particularly important during the second half of the conversion phase because the ad7677 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conver- sion phase. for this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion this mode is the most recommended of the serial slave modes. figure 19 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs rd ts a a hz ad rdcsdin t a 2s cnvst irdcsdin sc sdths s sc s s ad 2(pstra ad (dnstra rdcsdin sdt cnvst cs sc rdcsdin sdt cnvst cs sc data t scin csin cnvstin s t 2 taddcc cdrdc 2 dcsrd t s t irdrrr t rdcsdin t 2hzi 2hzhz i t hzi 2hzn2hz icrprcssrintracin tad t ad i a ad adctad spiadsp2 adsp2 spii(chc 22ad spichct ad t t t (s ts pi(spi chc (strcp(cpc p(cphaspi (spi spicr (spcrtir (irptinr ad chc sr par ir issdi sc iprt s sdt sc cnvst t int cs rd invsc dvdd additinapinsittdrcarit 22 iadspii adsp2si a2ad adsp2 t (divsc
rev. a ad7677 e19e the ad7677 is configured for the internal clock mode (ext/ int t aadsp2 tsadsp2 tadsp 2 (irs (cr(irsas rsr(rst adsp2 (srctadsp2sharc adsp2 adsp2 z ad adsp2 sharc sr par rs dr rc arts snc sdt sc cnvst rdcsdin rd t int cs dvdd additinapinsittdrcarit invsnc invsc 2 iadsp2 s appicatinhints tad h tad t d ad adiad ad i t ad cnvst c t t t ad ad d avdddvddvdd a sr adc t dvddad avdd vdd dvdd avddrc vdd dvdd tadrnd and dndndrnd and adct dnd nd t tadc z adp aad adt pc crd2
rev. a e20e c02632e0e7/02(a) printed in u.s.a. ad7677 outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc sq compliant to jedec standards ms-026bbc 48-lead frame chip scale package [lfcsp] 7 mm 7 mm body (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 4.70 2.25 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 1.00 0.90 0.80 5.50 ref seating plane 0.05 max 0.02 nom coplanarity 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vkkd-2 paddle connected to agnd revision history location page 7/02?data sheet changed from rev. 0 to rev. a. added 48-lead lfcsp to features and general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added pulsar selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 edits to notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 additions to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to power supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 added 48-lead frame chip scale package (lfcsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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