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address /w /e /cm dq (15?0) (16 ) i/o buffer s control cam array 2 n words x64bits comparand mask 1 mask 2 2 n x 2 validity bits priority encoder commands & status n mux data (16) demux source and destination seg ment counters vcc gnd instruction (w/o)* next free ad dress (r/o ) control segment control address status (15?0 ) (r/o )* status (3 1?16) (r/ o ) reg ister s et 2 match addr, /mf /m m, /f f data (16) (16 ) data (64) data (64) address decoder /rese t /mf /mm n+1 /ff list-xl family 13 june 2001 rev 13 june 2001 rev 13 june 2001 rev 13 june 2001 rev 13 june 2001 rev . 2 . 2 . 2 . 2 . 2 block diagram block diagram block diagram block diagram block diagram distinctive characteristics distinctive characteristics distinctive characteristics distinctive characteristics distinctive characteristics data sheet data sheet data sheet data sheet data sheet 256 word and 512 word by 64-bit content- 256 word and 512 word by 64-bit content- 256 word and 512 word by 64-bit content- 256 word and 512 word by 64-bit content- 256 word and 512 word by 64-bit content- addressable memory (cam) addressable memory (cam) addressable memory (cam) addressable memory (cam) addressable memory (cam) compare any data with all the entries stored in the compare any data with all the entries stored in the compare any data with all the entries stored in the compare any data with all the entries stored in the compare any data with all the entries stored in the memory array in a single 70 ns cycle memory array in a single 70 ns cycle memory array in a single 70 ns cycle memory array in a single 70 ns cycle memory array in a single 70 ns cycle add or delete data in the cam in a single cycle add or delete data in the cam in a single cycle add or delete data in the cam in a single cycle add or delete data in the cam in a single cycle add or delete data in the cam in a single cycle match and multiple match signals match and multiple match signals match and multiple match signals match and multiple match signals match and multiple match signals immediate access to associated data translations, immediate access to associated data translations, immediate access to associated data translations, immediate access to associated data translations, immediate access to associated data translations, attributes, or pointers attributes, or pointers attributes, or pointers attributes, or pointers attributes, or pointers flexible patented cam/ram partitioning flexible patented cam/ram partitioning flexible patented cam/ram partitioning flexible patented cam/ram partitioning flexible patented cam/ram partitioning t t t t t wo selectable mask registers with bit by bit wo selectable mask registers with bit by bit wo selectable mask registers with bit by bit wo selectable mask registers with bit by bit wo selectable mask registers with bit by bit capability capability capability capability capability powerful and flexible instruction set powerful and flexible instruction set powerful and flexible instruction set powerful and flexible instruction set powerful and flexible instruction set proximate match capability proximate match capability proximate match capability proximate match capability proximate match capability 16-bit i/o; 32-pin lqfp; 3.3 volt operation 16-bit i/o; 32-pin lqfp; 3.3 volt operation 16-bit i/o; 32-pin lqfp; 3.3 volt operation 16-bit i/o; 32-pin lqfp; 3.3 volt operation 16-bit i/o; 32-pin lqfp; 3.3 volt operation applica applica applica applica applica tion benefits tion benefits tion benefits tion benefits tion benefits accelerate table search and data translation accelerate table search and data translation accelerate table search and data translation accelerate table search and data translation accelerate table search and data translation operations such as those found in: operations such as those found in: operations such as those found in: operations such as those found in: operations such as those found in: lan address processing lan address processing lan address processing lan address processing lan address processing cache tag buffers cache tag buffers cache tag buffers cache tag buffers cache tag buffers hash collision resolution hash collision resolution hash collision resolution hash collision resolution hash collision resolution branch tables branch tables branch tables branch tables branch tables data decoders data decoders data decoders data decoders data decoders other processes or algorithms that require other processes or algorithms that require other processes or algorithms that require other processes or algorithms that require other processes or algorithms that require table searches table searches table searches table searches table searches lancam, the music logo, and the phrase music semiconductors are registered trademarks of music semiconductors. music is a trademark of music semiconductors. certain features of this device are patented under us patent 5,383,146.
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 2 2 2 2 2 skip bit skip bit skip bit skip bit skip bit 0 0 1 1 empty bit empty bit empty bit empty bit empty bit 0 1 0 1 v v v v v alidity t alidity t alidity t alidity t alidity t ype ype ype ype ype valid empty skip ram t t t t t able 1: v able 1: v able 1: v able 1: v able 1: v alidity bits vs. v alidity bits vs. v alidity bits vs. v alidity bits vs. v alidity bits vs. v alidity t alidity t alidity t alidity t alidity t ypes ypes ypes ypes ypes pinout diagram pinout diagram pinout diagram pinout diagram pinout diagram t t t t t able 2: i/o cycles able 2: i/o cycles able 2: i/o cycles able 2: i/o cycles able 2: i/o cycles /w /w /w /w /w low low high high /cm /cm /cm /cm /cm low high low high cycle t cycle t cycle t cycle t cycle t ype ype ype ype ype command write cycle data write cycle command read cycle data read cycle the music list-xl family consists of 256 word and 512 word by 64-bit content- addressable memory (cam), ideal for time critical applications requiring intensive list processing where space and cost are important. content-addressable memories, also known as associative memories, operate in the converse way to random access memories (ram). in a ram, the input to the device is an address and the output is the data stored at that address. in a cam, the input is a data sample and the output is a flag to indicate a match and the address of the matching data. as a result, a cam searches large databases for matching data in a short, constant time period, no matter how many entries are in general description general description general description general description general description the database. the ability to search data words up to 64 bits wide allows large address spaces to be searched rapidly and efficiently. a patented architecture links each cam entry to associated data and makes this data available for use after a successful compare operation. the music list-xl is an inexpensive powerful solution for any application having to retrieve or translate data in a fast, time deterministic manner. it is well suited to handle and speed up functions usually done in software, such as data caches, branch tables, lan address processing, data translations, high speed data filters, and algorithms having to search, recognize, and make decisions on data or a data subset. opera opera opera opera opera tional tional tional tional tional over over over over over view view view view view to use the list-xl, the user loads the data into the comparand register, which is automatically compared to all valid cam locations. the device then indicates whether or not one or more of the valid cam locations contains data that matches the target data. two validity bits at each memory location determines the status of each cam location. the two bits are encoded to render four validity conditions: valid, skip, empty, and random access, as shown in table 1. the memory can be partitioned into cam and associated ram segments on 16-bit boundaries, but by using one of the two available mask registers, the cam/ram partitioning can be set at any arbitrary size between zero and 64 bits. the list-xls internal data path is 64 bits wide for rapid internal comparison and data movement. loading data to the control, comparand, and mask registers automatically triggers a compare. compares may also be initiated by a command to the device. associated ram data is available immediately after a successful compare operation. the status register reports the results of compares including all flags and addresses. two mask registers are available and can be used in two different ways, to mask comparisons or to mask data writes. the random access validity type (see table 1) allows additional masks to be stored in the cam array where they may be retrieved rapidly. a simple three-wire control interface and commands loaded into the instruction decoder control the device. a powerful instruction set increases the control flexibility and minimizes software overhead. these and other features make the list-xl a powerful associative memory that drastically reduces search delays. dq4 dq5 vcc gnd gnd dq6 dq7 nc gnd /r eset vcc /e /ff /c m dq0 dq1 dq2 dq3 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 32-pin 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 /mm /mf vcc gnd vcc /w 24 23 22 21 20 19 18 17 32-pin lqfp 32-pin lqfp 32-pin lqfp 32-pin lqfp 32-pin lqfp (t (t (t (t (t op v op v op v op v op v iew) iew) iew) iew) iew)
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 3 3 3 3 3 /e (chip enable, input, ttl) /e (chip enable, input, ttl) /e (chip enable, input, ttl) /e (chip enable, input, ttl) /e (chip enable, input, ttl) the /e input enables the device while low. the falling edge registers the control signals /w and /cm. the rising edge turns off the dq pins and clocks the destination and source segment counters. the four cycle types enabled by /e are shown in table 2 on page 2. /w (write enable, input, ttl) /w (write enable, input, ttl) /w (write enable, input, ttl) /w (write enable, input, ttl) /w (write enable, input, ttl) the /w input selects the direction of data flow during a device cycle. /w low selects a write cycle and /w high selects a read cycle. /cm (data/command select, input, ttl) /cm (data/command select, input, ttl) /cm (data/command select, input, ttl) /cm (data/command select, input, ttl) /cm (data/command select, input, ttl) the /cm input selects whether the input signals on dq15C0 are data or commands. /cm low selects command cycles and /cm high selects data cycles. dq15C0 (data bus, i/o, ttl) dq15C0 (data bus, i/o, ttl) dq15C0 (data bus, i/o, ttl) dq15C0 (data bus, i/o, ttl) dq15C0 (data bus, i/o, ttl) the dq15C0 lines convey data, commands, and status to and from the list-xl. /w and /cm controls the direction and nature of the information that flows to or from the device. w hen /e is high, dq15C0 go to hi-z. /mf (match flag, output, ttl) /mf (match flag, output, ttl) /mf (match flag, output, ttl) /mf (match flag, output, ttl) /mf (match flag, output, ttl) the /mf output goes low when one or more valid matches occur during the current or most recent compare cycle. /mf is high if there is no match. /mf will be reset when the active configuration register set is changed. /mm (device multiple match flag, output, ttl) /mm (device multiple match flag, output, ttl) /mm (device multiple match flag, output, ttl) /mm (device multiple match flag, output, ttl) /mm (device multiple match flag, output, ttl) the /mm output is low when more than one valid match occurs during the current or the most recent compare cycle. /mm will be reset when the active register set is changed. /ff (full flag, output, ttl) /ff (full flag, output, ttl) /ff (full flag, output, ttl) /ff (full flag, output, ttl) /ff (full flag, output, ttl) the /ff output goes low when no empty memory locations exist within the device. /reset (reset, input, ttl) /reset (reset, input, ttl) /reset (reset, input, ttl) /reset (reset, input, ttl) /reset (reset, input, ttl) /reset must be driven low to place the device in a known state before operation, which will reset the device to the conditions shown in table 4 on page 8. the /reset pin should be driven by ttl levels, not directly by an rc time- out. /e must be kept high during /reset. vcc, gnd (positive power supply vcc, gnd (positive power supply vcc, gnd (positive power supply vcc, gnd (positive power supply vcc, gnd (positive power supply , ground) , ground) , ground) , ground) , ground) these pins are the power supply connections to the list- xl. vcc must meet the voltage supply requirements in the operating conditions section relative to the gnd pins, which are at 0 volts (system reference potential), for correct operation of the device. all the ground and power pins must be connected to their respective planes with adequate bulk and high frequency bypassing capacitors in close proximity to the device. pin descriptions pin descriptions pin descriptions pin descriptions pin descriptions all signals are implemented in cmos technology with ttl levels. signal names that start with a slash (/) are active low. inputs should never be left floating. the cam architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. refer to the electrical characteristics section for more information.
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 4 4 4 4 4 functional description functional description functional description functional description functional description the list-xl is a content-addressable memory (cam) with 16-bit i/o for network address filtering and translation, virtual memory, data compression, caching, and table lookup applications. the memory consists of static cam, organized in 64-bit data fields. each data field can be partitioned into a cam and a ram subfield on 16-bit boundaries. the contents of the memory can be randomly accessed or associatively accessed by the use of a compare. during automatic comparison cycles, data in the comparand register is automatically compared with the valid entries in the memory array. the device id can be read using a tco ps instruction (see table 11 on page 16). the data inputs and outputs of the list-xl are multiplexed for data and instructions over a 16-bit i/o bus. internally, data is handled on a 64-bit basis, since the comparand register, the mask registers, and each memory entry are 64 bits wide. memory entries are globally configurable into cam and ram segments on 16-bit boundaries, as described in us patent 5,383,146 assigned to music semiconductors. seven different cam/ram splits are possible, with the cam width going from one to four segments, and the remaining ram width going from three to zero segments. finer resolution on compare width is possible by invoking a mask register during a compare, which does global masking on a bit basis. the cam subfield contains the associative data, which enters into compares, while the ram subfield contains the associated data, which is not compared. in lan bridges, the ram subfield could hold, for example, port-address and aging information related to the destination or source address information held in the cam subfield of a given location. in a translation application, the cam field could hold the dictionary entries, while the ram field holds the translations, with almost instantaneous response. each entry has two validity bits (known as skip bit and empty bit) associated with it to define its particular type: empty, valid, skip, or ram. when data is written to the active comparand register, and the active segment control register reaches its terminal count, the contents of the comparand register are automatically compared with the cam portion of all the valid entries in the memory array. for added versatility, the comparand register can be barrel-shifted right or left one bit at a time. a compare instruction can then be used to force another compare between the comparand register and the cam portion of memory entries of any one of the four validity types. after a read or move from memory operation, the validity bits of the location read or moved will be copied into the status register, where they can be read from the status register using command read cycles. data can be moved from one of the data registers (cr, mr1, or mr2) to a memory location that is based on the results of the last comparison (highest-priority match or next free), or to an absolute address, or to the location pointed to by the active address register. data also can be written directly to the memory from the dq bus using any of the above addressing modes. the address register may be directly loaded and may be set to increment or decrement, allowing dma-type reading or writing from memory. two sets of configuration registers (control, segment control, address, mask register 1, and persistent source and destination) are provided to permit rapid context switching between foreground and background activities. writes, reads, moves, and compares are controlled by the currently active set of configuration registers. the foreground set would typically be pre- loaded with values useful for comparing input data, often called filtering, while the background set would be pre- loaded with values useful for housekeeping activities such as purging old entries. moving from the foreground task of filtering to the background task of purging can be done by issuing a single instruction to change the current set of configuration registers. the match condition of the device is reset whenever the active register set is changed. the active control register determines the operating conditions within the device. conditions set by this registers contents are reset, cam/ram partitioning, disable or select masking conditions, and disable or select auto-incrementing or -decrementing the address register. the active segment control register contains separate counters to control the writing of 16-bit data segments to the selected persistent destination, and to control the reading of 16-bit data segments from the selected persistent source. there are two active mask registers at any one time, which can be selected to mask comparisons or data writes. mask register 1 has both a foreground and background mode to support rapid context switching. mask register 2 does not have this mode, but can be shifted left or right one bit at a time. for masking comparisons, data stored in the active selected mask register determines which bits of the comparand are
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 5 5 5 5 5 compared against the valid contents of the memory. if a bit is set high in the mask register, the same bit position in the comparand register becomes a dont care for the purpose of the comparison with all the memory locations. during a data write cycle or a mov instruction, data in the specified active mask register can also determine which bits in the destination will be updated. if a bit is high in the mask register, the corresponding bit of the destination is unchanged. the match line associated with each memory address is fed into a priority encoder where multiple responses are resolved, and the address of the highest-priority responder (the lowest numerical match address) is generated. in lan applications, a multiple response might indicate an error. in other applications the existence of multiple responders may be valid. three input control signals and commands loaded into an instruction decoder control the list-xl. two of the three input control signals determine the cycle type. the control signals tell the device whether the data on the i/o bus represents data or a command, and is input or output. commands are decoded by instruction logic and control moves, forced compares, validity bit manipulations, and the data path within the device. registers (control, segment control, address, next free address, etc.) are accessed using temporary command override instructions. the data path from the dq bus to/from data resources (comparand, masks, and memory) within the device are set until changed by select persistent source and destination instructions. after a compare cycle (caused by either a data write to the comparand or mask registers, a write to the control register, or a forced compare), the status register contains the address of the highest-priority matching location, along with flags indicating match, multiple match, and full. the /mf, /mm, and /ff flags also are available directly on output pins. functional description functional description functional description functional description functional description continued continued continued continued continued opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics throughout the following, aaah represents a three-digit hexadecimal number aaa, while bbb represents a two-digit binary number bb. all memory locations are written to or read from in 16-bit segments. segment 0 corresponds to the lowest order bits (bits 15C0) and segment 3 corresponds to the highest order bits (bits 63C48). the control bus the control bus the control bus the control bus the control bus refer to the block diagram on page 1 for the following discussion. the inputs chip enable (/e), write enable (/w), and command enable (/cm) are the primary control mechanism for the list-xl. instructions are the secondary control mechanism. logical combinations of the control bus inputs, coupled with the execution of select persistent source (sps), select persistent destination (spd), and temporary command override (tco) instructions allow the i/o operations to and from the dq15C0 lines to the internal resources, as shown in table 3 on page 7. the comparand register is the default source and destination for data read and write cycles. this default state can be overridden independently by executing a select persistent source or select persistent destination instruction, selecting a different source or destination for data. subsequent data read or data write cycles will access that source or destination until another sps or spd instruction is executed. the currently selected persistent source or destination can be read back through a tco ps or pd instruction. the sources and destinations available for persistent access are those resources on the 64-bit bus: comparand register, mask register 1, mask register 2, and the memory array. the default destination for command write cycles is the instruction decoder, while the default source for command read cycles is the status register. temporary command override (tco) instructions provide access to the control register, the segment control register, the address register, and the next free address register. tco instructions are active only for one command read or write cycle after being loaded into the instruction decoder. the data and control interfaces to the list-xl are synchronous. during a write cycle, the control and data inputs are registered by the falling edge of /e. when writing to the persistently selected data destination, the destination segment counter is clocked by the rising edge of /e. during a read cycle, the control inputs are registered by the falling edge of /e, and the data outputs are enabled while /e is low. when reading from the persistently selected data source, the source segment counter is clocked by the rising edge of /e.
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 6 6 6 6 6 the register set the register set the register set the register set the register set the control, segment control, address, mask register 1, and the persistent source and destination registers are duplicated, with one set termed the foreground set, and the other the background set. the active set is chosen by issuing select foreground registers or select background registers instructions. by default, the foreground set is active after a reset. having two alternate sets of registers that determine the device configuration allows for a rapid return to a foreground network filtering task from a background housekeeping task. writing a value to the control register or writing data to the last segment of the comparand or either mask register will cause an automatic comparison to occur between the contents of the comparand register and the words in the cam segments of the memory marked valid, masked by mr1 or mr2 if selected in the control register. instruction decoder instruction decoder instruction decoder instruction decoder instruction decoder the instruction decoder is the write-only decode logic for instructions and is the default destination for command write cycles. if an instructions address field flag (bit 11) is set to a 1, it is a two-cycle instruction that is not executed immediately. for the next cycle only, the data from a command write cycle is loaded into the address register and the instruction then completes at that address. the address register will then increment, decrement, or stay at the same value depending on the setting of control register bits ct3 and ct2. if the address field flag is not set, the memory access occurs at the address currently contained in the address register. control register (ct) control register (ct) control register (ct) control register (ct) control register (ct) the control register is composed of a number of switches that configure the list-xl, as shown in table 7 on page 15. it is written or read using a tco ct instruction. if bit 15 of the value written during a tco ct is a 0, the device is reset (and all other bits are ignored). see table 4 for the reset states. bit 15 always reads back as a 0. a write to the control register causes an automatic compare to occur (except in the case of a reset). either the foreground or background control register will be active, depending on which register set has been selected, and only the active control register will be written to or read from. control register bits 8C6 control the cam/ram partitioning. the cam portion of each word may be sized from a full 64 bits down to 16 bits in 16-bit increments. the ram portion can be at either end of the 64-bit word. compare masks may be selected by bits 5 and 4. mask register 1, mask register 2, or neither may be selected to mask compare operations. the address register behavior is controlled by bits 3 and 2, and may be set to increment, decrement, or neither after a memory access. segment control register (sc) segment control register (sc) segment control register (sc) segment control register (sc) segment control register (sc) the segment control register, as shown in table 8 on page 16, is accessed using a tco sc instruction. on read cycles, d15, d10, d5, and d2 will always read back as 0s. either the foreground or background segment control register will be active, depending on which register set has been selected, and only the active segment control register will be written to or read from. the segment control register contains dual independent incrementing counters with limits, one for data reads and one for data writes. these counters control which 16-bit segment of the 64-bit internal resource is accessed during a particular data cycle on the 16-bit data bus. the actual destination for data writes and source for data reads (called the persistent destination and source) are set independently with spd and sps instructions, respectively. each of the two counters consists of a start limit, an end limit, and the current count value which points to the segment to be accessed on the next data cycle. the current count value can be set to any segment, even if it is outside the range set by the start and end limits. the counters count up from the current count value to the end limit and then jump back to the start limit. if the current count is greater than the end limit, the current count value will increment to 3, then roll over to 0 and continue incrementing until the end limit is reached; it then jumps back to the start limit. if a sequence of data writes or reads is interrupted, the segment control register can be reset to its initial start limit values by using an rsc instruction. after the list-xl is reset, both source and destination counters are set to count from segment 0 to segment 3 with an initial value of 0. address register (ar) address register (ar) address register (ar) address register (ar) address register (ar) the address register points to the cam memory location to be operated upon when m@[ar] or m@aaah is part of the instruction. it can be loaded directly by using a tco ar instruction or indirectly by using an instruction requiring an absolute address, such as mov aaah, cr,v. after being loaded, the address register value will then be used for the next memory access referencing the address register. a reset sets the address register to zero. opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics continued continued continued continued continued
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 7 7 7 7 7 /cm /cm /cm /cm /cm l l h h x /w /w /w /w /w l h l h x i/o status i/o status i/o status i/o status i/o status in in in in out out out out out out out in in in in in in out out out out out high-z operation operation operation operation operation load instruction decoder load address register load control register load segment control register read next free address register read address register read status register bits 15C0 read status register bits 31C16 read control register read segment control register read current persistent source or destination load comparand register load mask register 1 load mask register 2 write memory array at address write memory array at next free address write memory array at highest-priority match read comparand register read mask register 1 read mask register 2 read memory array at address read memory array at highest-priority match deselected cycle t cycle t cycle t cycle t cycle t ype ype ype ype ype cmd write cmd read data write data read /e /e /e /e /e l l l l h notes notes notes notes notes 1 2,3 3 3 3 3 4 5 3 3 3,10 6,9 7,9 7,9 7,9 7,9 7,9 6, 9 8, 9 8, 9 8, 9 7, 8 sps sps sps sps sps spd spd spd spd spd tco tco tco tco tco notes: notes: notes: notes: notes: 1. default command write cycle destination (does not require a tco instruction). 2. default command write cycle destination (no tco instruction required) if address field flag was set in bit 11 of the instruction loaded in the previous cycle. 3. loaded or read on the command write of read cycle immediately following a tco instruction. active for one command write or read cycle only. nfa register cannot be loaded this way. 4. default command read cycle source (does not require a tco instruction). 5. default command read cycle source (does not require a tco instruction) if the previous cycle was a command read of status register bits 15C0. if next cycle is not a command read cycle, any subsequent command read cycle will access the status register bits 15C0. 6. default persistent source and destination on power-up and after reset. if other resources were sources or destinations, spd cr or sps cr restores the comparand register as the destination or source. 7. selected by executing a select persistent destination instruction. 8. selected by executing a select persistent source instruction. 9. access may require multiple 16-bit read or write cycles. the segment control register is used to control the selection of the desired 16-bit segment(s) by establishing the segment counters start and end limits and count values. 10. a command read cycle after a tco ps or tco pd reads back the instruction decoder bits that were last set to select a persistant source or destination. the tco ps instruction will also read back the device id. t t t t t able 3: input/output operations able 3: input/output operations able 3: input/output operations able 3: input/output operations able 3: input/output operations opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics continued continued continued continued continued control register bits ct3 and ct2 set the address register to automatically increment or decrement (or not change) during sequences of command or data cycles. the address register will change after executing an instruction that includes m@[ar] or m@aaah, or after a data access to the end limit segment (as set in the segment control register) when the persistent source or destination is m@[ar] or m@aaah. either the foreground or background address register will be active, depending on which register set has been selected, and only the active address register will be written to or read from. next free address register (nf) next free address register (nf) next free address register (nf) next free address register (nf) next free address register (nf) the list-xl automatically stores the address of the first empty memory location in the next free address register, which is then used as a memory address pointer for m@nf operations. the next free address register, shown in table 9 on page 16, can be read using a tco nf instruction. after a reset, the next free address register is set to zero.
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 8 8 8 8 8 status register status register status register status register status register the 32-bit status register, as shown in table 10 on page 16, is the default source for command read cycles. bit 31 is the internal full flag, which will go low if there are no empty memory locations. bit 30 is the internal multiple match flag, which will go low if a multiple match was detected. bits 29 and 28 are the skip and empty validity bits, which reflect the validity of the last memory location read. after a reset, the skip and empty bits will read 11 until a read or move from memory has occurred. the rest of the status register down to bit 1 contains the address of the highest-priority match. after a reset or a no- match condition, the match address bits will be all 1s. bit 0 is the internal match flag, which will go low if a match was found. comparand register (cr) comparand register (cr) comparand register (cr) comparand register (cr) comparand register (cr) the 64-bit comparand register is the default destination for data writes and reads, using the segment control register to select which 16-bit segment of the comparand register is to be loaded or read out. the persistent source and destination for data writes and reads can be changed to the mask registers or memory by sps and spd instructions. during an automatic or forced compare, the comparand register is simultaneously compared against the cam portion of all memory locations with the correct validity condition. automatic compares always compare against valid memory locations, while forced compares, using cmp instructions, can compare against memory locations tagged with any specific validity condition. the comparand register may be shifted one bit at a time to the right or left by issuing a shift right or shift left instruction, with the right and left limits for the wrap-around determined by the cam/ram partitioning set in the control register. during shift rights, bits shifted off the lsb of the cam partition will reappear at the msb of the cam partition. likewise, bits shifted off the msb of the cam partition will reappear at the lsb during shift lefts. t t t t t able 4: device control state after reset able 4: device control state after reset able 4: device control state after reset able 4: device control state after reset able 4: device control state after reset cam status cam status cam status cam status cam status validity bits at all memory locations cam/ram partitioning comparison masking address register auto-increment or -decrement source and destination segment counters count ranges address register and next free address register control register after reset (including ct15) persistent destination for command writes persistent source for command reads persistent source and destination for data reads and writes configuration register set /reset condition /reset condition /reset condition /reset condition /reset condition skip = 0, empty = 1 (empty) 64 bits cam, 0 bits ram disabled disabled 00b to 11b; loaded with 00b contains all 0s contains 0008h instruction decoder status register comparand register foreground opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics continued continued continued continued continued mask registers (mr1, mr2) mask registers (mr1, mr2) mask registers (mr1, mr2) mask registers (mr1, mr2) mask registers (mr1, mr2) the mask registers can be used in two different ways, either to mask compares or to mask data writes and moves. either mask register can be selected in the control register to mask every compare, or selected by instructions to participate in data writes or moves to and from memory. if a bit in the selected mask register is set to a 0, the corresponding bit in the comparand register will enter into a masked compare operation. if a mask bit is a 1, the corresponding bit in the comparand register will not enter into a masked compare operation. bits set to 0 in the mask register cause corresponding bits in the destination register or memory location to be updated when masking data writes or moves, while a bit set to 1 will prevent that bit in the destination from being changed. either the foreground or background mr1 can be set active, but after a reset, the foreground mr1 is active by default. mr2 incorporates a sliding mask, where the data can be replicated one bit at a time to the right or left with no wrap-around by issuing a shift right or shift left instruction. the right and left limits are determined by the cam/ram partitioning set in the control register. for a shift right the upper limit bit is replicated to the next lower bit, while for a shift left the lower limit bit is replicated to the next higher bit. the memor the memor the memor the memor the memor y y y y y arra arra arra arra arra y y y y y memory organization memory organization memory organization memory organization memory organization the memory array is organized into 64-bit words with each word having an additional two validity bits (skip and empty). by default, all words are configured to be 64 cam cells. however, bits 8C6 of the control register can divide each word into a cam field and a ram field. the ram field can be assigned to the least-significant or
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 9 9 9 9 9 most- significant portion of each entry. the cam/ram partitioning is allowed on 16-bit boundaries, permitting selection of the configuration shown in table 7 on page 15, bits 8C6 (e.g., 001 sets the 48 msbs to cam and the 16 lsbs to ram). memory array bits designated as ram can be used to store and retrieve data associated with the cam content at the same memory location. memory access memory access memory access memory access memory access there are two general ways to get data into and out of the memory array: directly or by moving the data through the comparand or mask registers. the first way, through direct reads or writes, is set up by issuing a set persistent destination (spd) or set persistent source (sps) command. the addresses for the direct access can be directly supplied; supplied from the address register, supplied from the next free address register, or supplied as the highest-priority match address. additionally, all the direct writes can be masked by either mask register. the second way is to move data via the comparand or mask registers. this is accomplished by issuing data move commands (mov). moves using the comparand register can also be masked by either of the mask registers. i/o cycles i/o cycles i/o cycles i/o cycles i/o cycles the list-xl supports four basic i/o cycles: data read, data write, command read, and command write. the type of cycle is determined by the states of the /w and /cm control inputs. these signals are registered at the beginning of a cycle by the falling edge of /e. table 2 on page 2 shows how the /w and /cm lines select the cycle type. during read cycles, the dq15C0 outputs are enabled after /e goes low. during write cycles, the data or command to be written is captured from dq15C0 at the beginning of the cycle by the falling edge of /e. figures 1 and 2 on page 10 show read and write cycles respectively. figure 3 on page 10 shows typical cycle-to-cycle timing with the match flag valid at the end of the comparand write cycle. data writes and reads to the comparand, mask registers, or memory occur in one to four 16-bit cycles, depending on the settings in the segment control register. the compare operation automatically occurs during data writes to the comparand or mask registers when the destination segment counter reaches the end count set in the segment control register. if there was a match, the second cycle reads status or associated data, depending on the state of /cm. the minimum timings for the /e control signal are given in the switching characteristics section on page 18. note that at minimum timings the /e signal is non-symmetrical, and that different cycle types have different timing requirements, as given in table 6 on page 15. comp comp comp comp comp are opera are opera are opera are opera are opera tions tions tions tions tions during a compare operation, the data in the comparand register is compared to all locations in the memory array simultaneously. any mask register used during compares must be selected beforehand in the control register. there are two ways compares are initiated: automatic and forced compares. automatic compares perform a compare of the contents of the comparand register against memory locations that are tagged as valid, and occur whenever the following happens: the destination segment counter in the segment control register reaches its end limit during writes to the comparand or mask registers. after a command write of a tco ct is executed (except for a software reset), so that a compare is executed with the new settings of the control register. forced compares are initiated by cmp instructions using one of the four validity conditions, v, r, s, and e. the forced compare against empty locations automatically masks all 64 bits of data to find all locations with the validity bits set to empty, while the other forced compares are masked only as selected in the control register. initializing the list-xl initializing the list-xl initializing the list-xl initializing the list-xl initializing the list-xl initialization of the list-xl is required to configure the various registers on the device. since a control register reset establishes the operating conditions shown in table 4 on page 8, restoration of operating conditions better suited for the application may be required after a reset, whether using the control register reset or the /reset pin. when the device powers up, the memory and registers are in an unknown state, so the /reset pin must be asserted to place the device in a known state. opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics continued continued continued continued continued
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 10 10 10 10 10 figure 1: read cycle figure 1: read cycle figure 1: read cycle figure 1: read cycle figure 1: read cycle opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics continued continued continued continued continued figure 2: write cycle figure 2: write cycle figure 2: write cycle figure 2: write cycle figure 2: write cycle figure 3: cycle to cycle timing example figure 3: cycle to cycle timing example figure 3: cycle to cycle timing example figure 3: cycle to cycle timing example figure 3: cycle to cycle timing example /e dq15 ? 0 /w /cm data out /e dq15C0 /w /cm /e dq15C0 /w /cm com par an d w rite cyc l e da ta status read cyc l e associated data rea d c ycl e da ta da ta /mf a nd /m m flags updat ed /m f
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 11 11 11 11 11 opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics continued continued continued continued continued cycle t cycle t cycle t cycle t cycle t ype ype ype ype ype command read command write command write command write command write command write command write command write op-code op-code op-code op-code op-code tco ct 0000h tco ct 8040h tco sc 3808h sps m@hm comments comments comments comments comments clears power-up anomalies target control register for reset causes reset target control register for initial values control register value target segment counter control register set segment counters to write to segment 1, 2, and 3 and read from segment 0. set data reads from segment 0 of the highest-priority match 1 2 control bus control bus control bus control bus control bus /e /cm /w l l l l l l l l notes notes notes notes notes t t t t t able 5: example initialization routine able 5: example initialization routine able 5: example initialization routine able 5: example initialization routine able 5: example initialization routine notes: notes: notes: notes: notes: 1. a software reset using a tco ct followed by 0000h puts the device in a known state. good programming practice dictates a software reset for initialization to account for all possible conditions. 2. a typical list-xl control environment: 48 cam bits, 16 ram bits; disable comparison masking; and enable address increment. see table 7 for control register bit assignments. instruction set descriptions* instruction set descriptions* instruction set descriptions* instruction set descriptions* instruction set descriptions* instruction: select persistent source (sps) instruction: select persistent source (sps) instruction: select persistent source (sps) instruction: select persistent source (sps) instruction: select persistent source (sps) binary op-code: 0000 f000 0000 0sss binary op-code: 0000 f000 0000 0sss binary op-code: 0000 f000 0000 0sss binary op-code: 0000 f000 0000 0sss binary op-code: 0000 f000 0000 0sss f f f f f address field flag? address field flag? address field flag? address field flag? address field flag? sss sss sss sss sss selected source selected source selected source selected source selected source this instruction selects a persistent source for data reads, until another sps instruction changes it or a reset occurs. the default source after reset for data read cycles is the comparand register. setting the persistent source to m@aaah loads the address register with aaah and the first access to that persistent source will be at aaah, after which the ar value increments or decrements as set in the control register. the sps m@[ar] instruction does the same except the current address register value is used. instruction: select persistent destination (spd) instruction: select persistent destination (spd) instruction: select persistent destination (spd) instruction: select persistent destination (spd) instruction: select persistent destination (spd) binary op-code: 0000 f001 mmdd dvvv binary op-code: 0000 f001 mmdd dvvv binary op-code: 0000 f001 mmdd dvvv binary op-code: 0000 f001 mmdd dvvv binary op-code: 0000 f001 mmdd dvvv f f f f f address field flag? address field flag? address field flag? address field flag? address field flag? mm mm mm mm mm mask register select mask register select mask register select mask register select mask register select ddd ddd ddd ddd ddd selected destination selected destination selected destination selected destination selected destination vvv vvv vvv vvv vvv v v v v v alidity setting for memory alidity setting for memory alidity setting for memory alidity setting for memory alidity setting for memory location location location location location destinations destinations destinations destinations destinations this instruction selects a persistent destination for data writes, which remains until another spd instruction changes it or a reset occurs. the default destination for data write cycles is the comparand register after a reset. when the destination is the comparand register or the memory array, the data written may be masked by either mask register 1 or mask register 2, so that only destination bits corresponding to bits in the mask register set to 0 will be modified. an automatic compare will occur after writing the last segment of the comparand or mask registers, but not after writing to memory. setting the persistent destination to m@aaah loads the address register with aaah, and the first access to that persistent destination will be at aaah, after which the ar value increments or decrements as set in the control register. the spd m@[ar] instruction does the same except the current address register value is used. instruction: instruction: instruction: instruction: instruction: t t t t t emporary command override emporary command override emporary command override emporary command override emporary command override (tco) (tco) (tco) (tco) (tco) binary op-code: 0000 0010 00dd d000 binary op-code: 0000 0010 00dd d000 binary op-code: 0000 0010 00dd d000 binary op-code: 0000 0010 00dd d000 binary op-code: 0000 0010 00dd d000 ddd ddd ddd ddd ddd register selected as source or register selected as source or register selected as source or register selected as source or register selected as source or destination for only the next destination for only the next destination for only the next destination for only the next destination for only the next command read or write cycle command read or write cycle command read or write cycle command read or write cycle command read or write cycle the tco instruction selects a register as the source or destination for only the next command read or write cycle, so a value can be loaded or read out of the register. subsequent command read or write cycles revert to reading the status register and writing to the instruction decoder. all registers but the nf, ps, and pd can be written to, and all can be read from. the status register is only available via non-tco command read cycles. reading the ps register also outputs the device id on bits 15C4 as shown in table 11 on page 16. l l l l l l l l h l l l l l l l
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 12 12 12 12 12 instruction: data move (mov) instruction: data move (mov) instruction: data move (mov) instruction: data move (mov) instruction: data move (mov) binary op-code: 0000 f01 binary op-code: 0000 f01 binary op-code: 0000 f01 binary op-code: 0000 f01 binary op-code: 0000 f01 1 mmdd dsss or 1 mmdd dsss or 1 mmdd dsss or 1 mmdd dsss or 1 mmdd dsss or 0000 f01 0000 f01 0000 f01 0000 f01 0000 f01 1 mmdd dvss 1 mmdd dvss 1 mmdd dvss 1 mmdd dvss 1 mmdd dvss f f f f f address field flag? address field flag? address field flag? address field flag? address field flag? mm mm mm mm mm mask register select mask register select mask register select mask register select mask register select ddd ddd ddd ddd ddd destination of data destination of data destination of data destination of data destination of data sss sss sss sss sss source of data source of data source of data source of data source of data v v v v v v v v v v alidity setting if destination is a alidity setting if destination is a alidity setting if destination is a alidity setting if destination is a alidity setting if destination is a memory location memory location memory location memory location memory location the mov instruction performs a 64-bit move of the data in the selected source to the selected destination. if the source or destination is aaah, the address register is set to aaah. for mov instructions to or from aaah or [ar], the address register will increment or decrement from that value after the move completes, as set in the control register. data transfers between the memory array and the comparand register may be masked by either mask register 1 or mask register 2, in which case, only those bits in the destination which correspond to bits in the selected mask register set to 0 will be changed. a memory location used as a destination for a mov instruction may be set to valid or left unchanged. if the source and destination are the same register, no net change occurs (a nop). instruction: v instruction: v instruction: v instruction: v instruction: v alidity bit control (vbc) alidity bit control (vbc) alidity bit control (vbc) alidity bit control (vbc) alidity bit control (vbc) binary op-code: 0000 f100 00dd dvvv binary op-code: 0000 f100 00dd dvvv binary op-code: 0000 f100 00dd dvvv binary op-code: 0000 f100 00dd dvvv binary op-code: 0000 f100 00dd dvvv f f f f f address field flag? address field flag? address field flag? address field flag? address field flag? ddd ddd ddd ddd ddd destination of data destination of data destination of data destination of data destination of data vvv vvv vvv vvv vvv v v v v v alidity setting for memory location alidity setting for memory location alidity setting for memory location alidity setting for memory location alidity setting for memory location the vbc instruction sets the validity bits at the selected memory locations to the selected state. this feature can be used to find all valid entries by using a repetitive sequence of cmp v through a mask of all 1s followed by a vbc hm, s. if the vbc target is aaah, the address register is set to aaah. for vbc instructions to or from aaah or [ar], the address register will increment or decrement from that value after the operation completes, as set in the control register. instruction: compare (cmp) instruction: compare (cmp) instruction: compare (cmp) instruction: compare (cmp) instruction: compare (cmp) binary op-code: 0000 0101 0000 0vvv binary op-code: 0000 0101 0000 0vvv binary op-code: 0000 0101 0000 0vvv binary op-code: 0000 0101 0000 0vvv binary op-code: 0000 0101 0000 0vvv vvv vvv vvv vvv vvv v v v v v alidity condition alidity condition alidity condition alidity condition alidity condition a cmp v, s, or r instruction forces a comparison of valid, skipped, or random entries against the comparand register through a mask register, if one is selected. during a cmp e instruction, the compare is only done on the validity bits and all data bits are automatically masked. instruction: special instructions instruction: special instructions instruction: special instructions instruction: special instructions instruction: special instructions binary op-code: 0000 01 binary op-code: 0000 01 binary op-code: 0000 01 binary op-code: 0000 01 binary op-code: 0000 01 10 00dd drrr 10 00dd drrr 10 00dd drrr 10 00dd drrr 10 00dd drrr ddd ddd ddd ddd ddd t t t t t arget resource arget resource arget resource arget resource arget resource rrr rrr rrr rrr rrr operation operation operation operation operation two alternate sets of configuration registers can be selected by using the select foreground and select background registers instructions. these registers are the control, segment control, address, mask register 1, and the ps and pd registers. an rsc instruction resets the segment control register count values for both the destination and source counters to the original start limits. the shift instructions shift the designated register one bit right or left. the right and left limits for shifting are determined by the cam/ram partitioning set in the control register. the comparand register is a barrel-shifter, and for the example of a device set to 64 bits of cam executing a shift comparand right instruction, bit 0 is moved to bit 63, bit 1 is moved to bit 0, and bit 63 is moved to bit 62. for a shift comparand left instruction, bit 63 is moved to bit 0, bit 0 is moved to bit 1, and bit 62 is moved to bit 63. mr2 acts as a sliding mask, where for a shift right instruction bit 1 is moved to bit 0, while bit 0 falls off the end, and bit 63 is replicated to bit 62. for a shift mask left instruction, bit 0 is replicated to bit 1, bit 62 is moved to bit 63, and bit 63 falls off the end. with shorter width cam fields, the bit limits on the right or left move to match the width of cam field. notes: notes: notes: notes: notes: * instruction cycle lengths given in table 6 on page 15. ? if f=1, the instruction requires an absolute address to be supplied on the following cycle as command write. the value supplied on the second cycle will update the address register. after operations involving m@[ar] or m@aaah, the address register will be incremented or decremented depending on the setting in the control register. instruction set descriptions* instruction set descriptions* instruction set descriptions* instruction set descriptions* instruction set descriptions* continued continued continued continued continued
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 13 13 13 13 13 mnemonic forma mnemonic forma mnemonic forma mnemonic forma mnemonic forma t t t t t ins dst,src[msk],val ins dst,src[msk],val ins dst,src[msk],val ins dst,src[msk],val ins dst,src[msk],val ins: ins: ins: ins: ins: instruction mnemonic dst: dst: dst: dst: dst: destination of the data src: src: src: src: src: source of the data msk: msk: msk: msk: msk: mask register used val: val: val: val: val: validity condition set at the location written instruction: select persistent source instruction: select persistent source instruction: select persistent source instruction: select persistent source instruction: select persistent source operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code comparand register sps cr 0000h mask register 1 sps mr1 0001h mask register 2 sps mr2 0002h memory array at addr. reg. sps m@[ar] 0004h memory array at address sps m@aaah 0804h mem. at highest-prio. match sps m@hm 0005h instruction: select persistent destination instruction: select persistent destination instruction: select persistent destination instruction: select persistent destination instruction: select persistent destination operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code comparand register spd cr 0100h masked by mr1 spd cr[mr1] 0140h masked by mr2 spd cr[mr2] 0180h mask register 1 spd mr1 0108h mask register 2 spd mr2 0110h mem. at addr. reg. set valid spd m@[ar],v 0124h masked by mr1 spd m@[ar][mr1],v 0164h masked by mr2 spd m@[ar][mr2],v 01a4h mem. at addr. reg. set empty spd m@[ar],e 0125h masked by mr1 spd m@[ar][mr1],e 0165h masked by mr2 spd m@[ar][mr2],e 01a5h mem. at addr. reg. set skip spd m@[ar],s 0126h masked by mr1 spd m@[ar][mr1],s 0166h masked by mr2 spd m@[ar][mr2],s 01a6h mem. at addr. reg. set random spd m@[ar],r 0127h masked by mr1 spd m@[ar][mr1],r 0167h masked by mr2 spd m@[ar][mr2],r 01a7h memory at address set valid spd m@aaah,v 0924h masked by mr1 spd m@aaah[mr1],v 0964h masked by mr2 spd m@aaah[mr2],v 09a4h memory at addr. set empty spd m@aaah,e 0925h masked by mr1 spd m@aaah[mr1],e 0965h masked by mr2 spd m@aaah[mr2],e 09a5h memory at address set skip spd m@aaah,s 0926h masked by mr1 spd m@aaah[mr1],s 0966h masked by mr2 spd m@aaah[mr2],s 09a6h mem. at address set random spd m@aaah,r 0927h masked by mr1 spd m@aaah[mr1],r 0967h masked by mr2 spd m@aaah[mr2],r 09a7h mem. at highest-prio. match, valid spd m@hm,v 012ch masked by mr1 spd m@hm[mr1],v 016ch masked by mr2 spd m@hm[mr2],v 01ach instruction: select persistent destination instruction: select persistent destination instruction: select persistent destination instruction: select persistent destination instruction: select persistent destination cont. cont. cont. cont. cont. operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code mem. at highest-prio. match, emp. spd m@hm,e 012dh masked by mr1 spd m@hm[mr1],e 016dh masked by mr2 spd m@hm[mr2],e 01adh mem. at highest-prio. match, skip spd m@hm,s 012eh masked by mr1 spd m@hm[mr1],s 016eh masked by mr2 spd m@hm[mr2],s 01aeh mem. at high.-prio. match, random spd m@hm,r 012fh masked by mr1 spd m@hm[mr1],r 016fh masked by mr2 spd m@hm[mr2],r 01afh mem. at next free addr., valid spd m@nf,v 0134h masked by mr1 spd m@nf[mr1],v 0174h masked by mr2 spd m@nf[mr2],v 01b4h mem. at next free addr., empty spd m@nf,e 0135h masked by mr1 spd m@nf[mr1],e 0175h masked by mr2 spd m@nf[mr2],e 01b5h mem. at next free addr., skip spd m@nf,s 0136h masked by mr1 spd m@nf[mr1],s 0176h masked by mr2 spd m@nf[mr2],s 01b6h mem. at next free addr., random spd m@nf,r 0137h masked by mr1 spd m@nf[mr1],r 0177h masked by mr2 spd m@nf[mr2],r 01b7h instruction: t instruction: t instruction: t instruction: t instruction: t emporary command override emporary command override emporary command override emporary command override emporary command override operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code control register tco ct 0200h segment control register tco sc 0210h read next free address tco nf 0218h address register tco ar 0220h read persistent source tco ps 0230h read persistent destination tco pd 0238h instruction: data move instruction: data move instruction: data move instruction: data move instruction: data move operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code comparand register from: no operation nop 0300h mask register 1 mov cr,mr1 0301h mask register 2 mov cr,mr2 0302h memory at address reg. mov cr,[ar] 0304h masked by mr1 mov cr,[ar][mr1] 0344h masked by mr2 mov cr,[ar][mr2] 0384h memory at address mov cr,aaah 0b04h masked by mr1 mov cr,aaah[mr1] 0b44h masked by mr2 mov cr,aaah[mr2] 0b84h mem. at highest-prio. match mov cr,hm 0305h masked by mr1 mov cr,hm[mr1] 0345h masked by mr2 mov cr,hm[mr2] 0385h instruction set summar instruction set summar instruction set summar instruction set summar instruction set summar y y y y y
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 14 14 14 14 14 instruction set summar instruction set summar instruction set summar instruction set summar instruction set summar y y y y y continued continued continued continued continued instruction: data move instruction: data move instruction: data move instruction: data move instruction: data move continued continued continued continued continued operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code mask register 1 from: comparand register mov mr1,cr 0308h no operation nop 0309h mask register 2 mov mr1,mr2 030ah memory at address reg. mov mr1,[ar] 030ch memory at address mov mr1,aaah 0b0ch mem. at highest-prio. match mov mr1,hm 030dh mask register 2 from: comparand register mov mr2,cr 0310h mask register 1 mov mr2,mr1 0311h no operation nop 0312h memory at address reg. mov mr2,[ar] 0314h memory at address mov mr2,aaah 0b14h mem. at highest-prio. match mov mr2,hm 0315h memory at address register, no change to validity bits, from: comparand register mov [ar],cr 0320h masked by mr1 mov [ar],cr[mr1] 0360h masked by mr2 mov [ar],cr[mr2] 03a0h mask register 1 mov [ar],mr1 0321h mask register 2 mov [ar],mr2 0322h memory at address register, location set valid, from: comparand register mov [ar],cr,v 0324h masked by mr1 mov [ar],cr[mr1],v 0364h masked by mr2 mov [ar],cr[mr2],v 03a4h mask register 1 mov [ar],mr1,v 0325h mask register 2 mov [ar],mr2,v 0326h memory at address, no change to validity bits, from: comparand register mov aaah,cr 0b20h masked by mr1 mov aaah,cr[mr1] 0b60h masked by mr2 mov aaah,cr[mr2] 0ba0h mask register 1 mov aaah,mr1 0b21h mask register 2 mov aaah,mr2 0b22h memory at address, location set valid, from: comparand register mov aaah,cr,v 0b24h masked by mr1 mov aaah,cr[mr1],v 0b64h masked by mr2 mov aaah,cr[mr2],v 0ba4h mask register 1 mov aaah,mr1,v 0b25h mask register 2 mov aaah,mr2,v 0b26h memory at highest-priority match, no change to validity bits,from: comparand register mov hm,cr 0328h masked bymr1 mov hm,cr[mr1] 0368h masked bymr2 mov hm,cr[mr2] 03a8h mask register 1 mov hm,mr1 0329h mask register 2 mov hm,mr2 032ah memory at highest-priority match, location set valid, from: comparand register mov hm,cr,v 032ch masked bymr1 mov hm,cr[mr1],v 036ch masked bymr2 mov hm,cr[mr2],v 03ach mask register 1 mov hm,mr1,v 032dh mask register 2 mov hm,mr2,v 032eh memory at next free address, no change to validity bits, from: comparand register mov nf,cr 0330h masked bymr1 mov nf,cr[mr1] 0370h masked bymr2 mov nf,cr[mr2] 03b0h mask register 1 mov nf,mr1 0331h mask register 2 mov nf,mr2 0332h memory at next free address, location set valid, from: comparand register mov nf,cr,v 0334h masked bymr1 mov nf ,cr[mr1],v 0374h masked bymr2 mov nf ,cr[mr2],v 03b4h mask register 1 mov nf ,mr1,v 0335h mask register 2 mov nf ,mr2,v 0336h instruction: v instruction: v instruction: v instruction: v instruction: v alidity bit control alidity bit control alidity bit control alidity bit control alidity bit control operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code set validity bits at address register set valid vbc [ar],v 0424h set empty vbc [ar],e 0425h set skip vbc [ar],s 0426h set random access vbc [ar],r 0427h set validity bits at address set valid vbc aaah,v 0c24h set empty vbc aaah,e 0c25h set skip vbc aaah,s 0c26h set random access vbc aaah,r 0c27h set validity bits at highest-priority match set valid vbc hm,v 042ch set empty vbc hm,e 042dh set skip vbc hm,s 042eh set random access vbc hm,r 042fh set validity bits at all matching locations set valid vbc alm,v 043ch set empty vbc alm,e 043dh set skip vbc alm,s 043eh set random access vbc alm,r 043fh instruction: compare instruction: compare instruction: compare instruction: compare instruction: compare operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code compare valid locations cmp v 0504h compare empty locations cmp e 0505h compare skipped locations cmp s 0506h comp. random access locations cmp r 0507h instruction: special instructions instruction: special instructions instruction: special instructions instruction: special instructions instruction: special instructions operation operation operation operation operation mnemonic mnemonic mnemonic mnemonic mnemonic op-code op-code op-code op-code op-code shift comparand right sft cr, r 0600h shift comparand left sft cr, l 0601h shift mask register 2 right sft m2, r 0610h shift mask register 2 left sft m2, l 0611h select foreground registers sfr 0618h select background registers sbr 0619h reset seg. cont. reg. to initial val. rsc 061ah
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 15 15 15 15 15 instruction set summar instruction set summar instruction set summar instruction set summar instruction set summar y y y y y continued continued continued continued continued t t t t t able 6: instruction cycle lengths able 6: instruction cycle lengths able 6: instruction cycle lengths able 6: instruction cycle lengths able 6: instruction cycle lengths cycle cycle cycle cycle cycle length length length length length short short short short short medium medium medium medium medium long long long long long command read command read command read command read command read status register or 16-bit register data write data write data write data write data write comparand register (not last segment) mask register (not last segment) memory array (nfa invalid) memory array (nfa valid) comparand register (last segment) mask register (last segment) data read data read data read data read data read comparand register mask register memory array note: the specific timing requirements for short, medium, and long cycles are given in the switching characteristics section under the teleh parameter. for two cycle command writes (tco reg or any instruction with aaah as the source or destination), the first cycle is short, and the second cycle will be the length given. cycle type cycle type cycle type cycle type cycle type command write command write command write command write command write mov reg, reg tco reg (except ct) tco ct (non-reset, hma invalid) sps, spd, sfr sbr, rsc, nop mov reg, mem tco ct (reset) vbc (nfa invalid) mov mem, reg tco ct (non-reset, hma valid) cmp vbc (nfa valid) t t t t t able 7: control register bit able 7: control register bit able 7: control register bit able 7: control register bit able 7: control register bit assignments assignments assignments assignments assignments note: d15 reads back as 0. rst r e s e t = 0 must be set = 000000 cam/ram part. 64 cam/0 ram = 000 48 cam/16 ram = 001 32 cam/32 ram = 010 16 cam/48 ram = 011 48 ram/16 cam = 100 32 ram/32 cam = 101 16 ram/48 cam = 110 no change = 111 comp. mask none = 00 mr1 = 01 mr2 = 10 no change = 11 ar inc/dec increment = 00 decrement = 01 disable = 10 no change = 11 reserved must be set = 00 reserved 1514131211109876543210 register bit assignments register bit assignments register bit assignments register bit assignments register bit assignments
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 16 16 16 16 16 t t t t t able 9: next free able 9: next free able 9: next free able 9: next free able 9: next free address register bit address register bit address register bit address register bit address register bit assignments assignments assignments assignments assignments t t t t t able 10: status register bit able 10: status register bit able 10: status register bit able 10: status register bit able 10: status register bit assignments assignments assignments assignments assignments t t t t t able 1 able 1 able 1 able 1 able 1 1: persistent source register bit 1: persistent source register bit 1: persistent source register bit 1: persistent source register bit 1: persistent source register bit assignments assignments assignments assignments assignments t t t t t able 8: segment control register bit able 8: segment control register bit able 8: segment control register bit able 8: segment control register bit able 8: segment control register bit assignments assignments assignments assignments assignments register bit assignments register bit assignments register bit assignments register bit assignments register bit assignments continued continued continued continued continued set dest. seg. limits = 0 no chng. = 1 set source seg. limits = 0 no chng. = 1 load dest. seg. count = 0 no chng. = 1 load src. seg. count = 0 no chng. = 1 note: d15, d10, d5, and d2 read back as 0s. destination count start limit =00C11 destination count end limit =00C11 source count start limit =00C11 source count end limit =00C11 destination seg. count value =00C11 source seg. count value =00C11 1514131211109876543210 sdl dcsl dcel ssl scsl scel ldc dscv lsc sscv 15 14131211109876543210 next free address, nf7C0 note: the next free address register is read only, and is accessed by performing a command read cycle immediately following a tco nf instruction. 0 0 0 0 0 0 0 0 9 note: the status register is read only, and is accessed by performing command read cycles. on the first cycle, bits 15C0 will be output, and if a second command read cycle is issued immediately after the first command read cycle, bits 31C16 will be output. 151413121110 876543210 match address, am7Cam0 /fl /mm skip empty 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 /mf 000000 0 0 0 0 0 0 0 1514131211109876543210 device id = 341h ps note: the persistent source register is read only, and is accessed by performing a command read cycle immediately following a tco ps instruction. ps device id = 541h 3640l 5640l match address, am8Cam0 0 0 0 0 /mf 00 3640l 5640l next free address, nf8C0 0 0 0 0 0 0 0 3640l 5640l
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 17 17 17 17 17 max max max max max 30 2 0.4 +2 12 10 t t t t t ypical ypical ypical ypical ypical 20 9 absolute maximum ra absolute maximum ra absolute maximum ra absolute maximum ra absolute maximum ra tings tings tings tings tings supply voltage -0.5 to 4.6 volts voltage on all other pins -0.5 to vcc +0.5 volts (-2 volts for 10 ns, measured at the 50% point) temperature under bias -55c to 125c storage temperature -55c to 125c dc output current 20 ma (per output, one at a time, one second duration. stresses exceeding those listed under absolute maximum ratings may include failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied. all voltages referenced to gnd. opera opera opera opera opera tional tional tional tional tional characteristics characteristics characteristics characteristics characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics symbol symbol symbol symbol symbol i cc i cc(sb) v oh v ol i iz i oz parameter parameter parameter parameter parameter average power supply current stand-by power supply current output voltage logic 1 output voltage logic 0 input leakage current output leakage current min min min min min 2.4 -2 6 -10 units units units units units ma ma volts volts a kohms a notes notes notes notes notes t elel = t elel (min); 9 /e = high i oh = -2.0ma i ol = 4.0ma v ss v in v cc v in = 0 v v ss v out v cc; dq n = high impedance opera opera opera opera opera ting conditions (voltages referenced to gnd at the device pin) ting conditions (voltages referenced to gnd at the device pin) ting conditions (voltages referenced to gnd at the device pin) ting conditions (voltages referenced to gnd at the device pin) ting conditions (voltages referenced to gnd at the device pin) symbol symbol symbol symbol symbol v cc v ih v il t a parameter parameter parameter parameter parameter operating supply voltage input voltage logic 1 input voltage logic 0 ambient operating temperature min min min min min 3.0 2.0 -0.5 0 -40 t t t t t ypical ypical ypical ypical ypical 3.3 max max max max max 3.6 v cc + 0.5 0.8 70 85 notes notes notes notes notes 1, 2 still air units units units units units volts volts volts c c cap cap cap cap cap acit acit acit acit acit ance ance ance ance ance symbol symbol symbol symbol symbol c in c out parameter parameter parameter parameter parameter input capacitance output capacitance max max max max max 6 7 notes notes notes notes notes f = 1 mhz, v in = 0 v f = 1 mhz, v out = 0 v units units units units units pf pf input signal transitions 0.0 volts to 3.0 volts input signal rise time < 3 ns input signal fall time < 3 ns input timing reference level 1.5 volts output timing reference level 1.5 volts ac test conditions ac test conditions ac test conditions ac test conditions ac test conditions others /reset commercial industrial
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 18 18 18 18 18 min min min min min 90 25 50 75 15 2 10 3 3 2 10 0 100 symbol symbol symbol symbol symbol t elel t eleh t ehel t cvel t elcx t elqx t elqv t ehqz t dvel t eldx t elffv t ehmfx t ehmfv t rlrh no no no no no 1 2 3 4 5 6 7 8 9 10 11 12 13 14 parameter (all times in nanoseconds) parameter (all times in nanoseconds) parameter (all times in nanoseconds) parameter (all times in nanoseconds) parameter (all times in nanoseconds) chip enable compare cycle time chip enable low pulse width short cycle: medium cycle: long cycle: chip enable high pulse width control input to chip enable low set-up time control input from chip enable low hold time chip enable low to outputs active chip enable low to outputs valid chip enable high to outputs high-z data to chip enable low set-up time data from chip enable low hold time chip enable low to full flag valid chip enable high to /mf, /mm invalid chip enable high to /mf, /mm valid reset low pulse width notes notes notes notes notes 4 4 4 5 5 6 4,6 4,6 7 8 max max max max max 30 52 10 50 18 min min min min min 70 15 35 55 15 2 10 3 3 2 10 0 100 -70 -70 -70 -70 -70 notes: notes: notes: notes: notes: 1. -1.0v for a duration of 10 ns measured at the 50% amplitude points for input-only lines (figure 5). 2. common i/o lines are clamped, so that signal transients cannot fall below -0.5v. 3. at 0 C 70c and vcc(min) to vcc(max). 4. see table 6. 5. control signals are /w and /cm. 6. with load specified in figure 4, test load a. 7. with load specified in figure 4, test load b. 8. /e must be high during this period to ensure accurate default values in the configuration registers. 9. with output and i/o pins unloaded. cycle time cycle time cycle time cycle time cycle time switching characteristics switching characteristics switching characteristics switching characteristics switching characteristics (see note 3) (see note 3) (see note 3) (see note 3) (see note 3) component component component component component v v v v v alue units alue units alue units alue units alue units vcc 3.3 volts r1 635 ohms r2 702 ohms c1 (includes jig) test load a 30 pf test load b 5 pf switching test figures component v switching test figures component v switching test figures component v switching test figures component v switching test figures component v alues alues alues alues alues to device under t est r2 vcc r1 c1 figure 4: figure 4: figure 4: figure 4: figure 4: ac t ac t ac t ac t ac t est load est load est load est load est load figure 5: input signal waveform figure 5: input signal waveform figure 5: input signal waveform figure 5: input signal waveform figure 5: input signal waveform inpu t waveform 0v v il ( min ) 10ns 5 0 % a m pli tude point switching test figures switching test figures switching test figures switching test figures switching test figures max max max max max 50 75 15 75 25 -90 -90 -90 -90 -90
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 19 19 19 19 19 timing diagrams timing diagrams timing diagrams timing diagrams timing diagrams read cycle read cycle read cycle read cycle read cycle write cycle write cycle write cycle write cycle write cycle /e /w /cm dq15C0 23 45 45 78 6 /e /w /c m 23 45 4 5 valid /m f, /m m 1 13 12 /e /w /c m dq15C0 23 4 5 4 5 10 9 /ff 11 comp comp comp comp comp are cycle are cycle are cycle are cycle are cycle
list-xl list-xl list-xl list-xl list-xl rev rev rev rev rev . 2 . 2 . 2 . 2 . 2 20 20 20 20 20 9.00 9.00 9.00 9.00 9.00 ordering informa ordering informa ordering informa ordering informa ordering informa tion tion tion tion tion p p p p p ackage outline ackage outline ackage outline ackage outline ackage outline a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 b b b b b c c c c c d d d d d e e e e e e e e e e hd hd hd hd hd he he he he he l1 l1 l1 l1 l1 1.35 1.35 1.35 1.35 1.35 1.45 1.45 1.45 1.45 1.45 .30 .30 .30 .30 .30 .45 .45 .45 .45 .45 .09 .09 .09 .09 .09 .02 .02 .02 .02 .02 7.00 7.00 7.00 7.00 7.00 7.00 7.00 7.00 7.00 7.00 .80 .80 .80 .80 .80 9.00 9.00 9.00 9.00 9.00 1.00 1.00 1.00 1.00 1.00 .45 .45 .45 .45 .45 dimensions are in mm. part number part number part number part number part number mu9c3640l - 90tzc mu9c3640l - 70tzc mu9c3640l - 90tzi mu9c5640l - 90tzc mu9c5640l - 70tzc mu9c5640l - 90tzi cycle time cycle time cycle time cycle time cycle time 90ns 70ns 90ns 90ns 70ns 90ns package package package package package 32-pin lqfp 32-pin lqfp 32-pin lqfp 32-pin lqfp 32-pin lqfp 32-pin lqfp t t t t t emperature emperature emperature emperature emperature 0-70 c 0-70 c -40C85 c 0-70 c 0-70 c -40C85 c v v v v v oltage oltage oltage oltage oltage 3.3 0.3 3.3 0.3 3.3 0.3 3.3 0.3 3.3 0.3 3.3 0.3 .15 .15 .15 .15 .15 .05 .05 .05 .05 .05 nom nom nom nom nom nom nom nom nom nom organization organization organization organization organization 256x64 256x64 256x64 512x64 512x64 512x64 l l l l l dim dim dim dim dim min min min min min max max max max max .75 .75 .75 .75 .75 d hd e he e b l a2 a1 c l1 european sales office european sales office european sales office european sales office european sales office music semiconductors saville court, saville place clifton, bristol bs8 4ej uk tel: (44) 117-973-4444 fax: (44) 117-923-7598 music semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability, or reliability. information furnished by music is believed to be accurate, but no responsibility is assumed by music semiconductors for the use of said information, nor for any infringement of patents or of other third party rights which may result from said use. no license is granted by implication or otherwise under any patent or patent rights of any music company. ?copyright 2001, music semiconductors music semiconductors agent or distributor: music semiconductors agent or distributor: music semiconductors agent or distributor: music semiconductors agent or distributor: music semiconductors agent or distributor: usa headquarters usa headquarters usa headquarters usa headquarters usa headquarters music semiconductors 1521 california circle milpitas, ca 95035 usa tel: 408 869-4600 fax: 408 942-0837 usa only: 800/933-1550 tech. support 888/226-6874 product info. asian sales office asian sales office asian sales office asian sales office asian sales office music semiconductors special export processing zone carmelray industrial park canlubang, calamba, laguna philippines tel: +63 49 549-1480 fax: +63 49 549-1024 sales tel/fax: +632 723-62 15 http://www.musicsemi.com http://www.musicsemi.com http://www.musicsemi.com http://www.musicsemi.com http://www.musicsemi.com email: info@musicsemi.com email: info@musicsemi.com email: info@musicsemi.com email: info@musicsemi.com email: info@musicsemi.com

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