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| power management 1 www.semtech.com sc2677b dual synchronous voltage mode controller with current sharing circuitry features revision: dec. 04, 2009 the sc2677b is a versatile 2 phase, synchronous, voltage mode pwm controller that can be used in two distinct ways. first, the sc2677b is ideal for applications where point of use output power exceeds any single input power budget. alternatively, the sc2677b can be configured as a dual switcher. the sc2677b features a precise temperature compensated voltage reference, cycle-by-cycle peak cur- rent limit, under voltage lockout over current protection, and internal level-shifted high-side gate drive circuitry. in current sharing configuration, the sc2677b can pro- duce a single output voltage from two separate input volt- age sources (which can be different in voltage levels) while maintaining current sharing between the two channels. current sharing is programmable to allow each input sup- ply to be loaded differently per application requirements. in dual switcher configuration, two feedback paths are pro- vided for independent control of the separate outputs. the device will provide a regulated output from flexibly config- ured inputs, such as 3.3v, 5v, 12v etc. the phasing be- tween the two switchers is adjustable to minimize the in- put and output ripple. ? 300khz to 1mhz externally programmable frequency operation ? soft start and enable function ? power good output provided ? cycle-by-cycle peak current limit ? latch off for over current protection ? phase-shifted switchers minimize ripple ? high efficiency operation, >90% ? programmable output(s) as low as 0.5v ? industrial temperature range ? tssop-24 package ? tssop-24 edp package ? bias voltage as low as 4.5v ? adjustable phase shift between channels two phase, current sharing controller ? flexible, same or separate v in ? programmable current sharing ? thermal distribution via multi-phase output ? graphics cards ? peripheral add-in card ? dual-phase power supply ? power supplies requiring two outputs cs1+ cs2+ c6 m5 c62 d1 cs1+ r20 c39 r49 r5 c63 m7 pwrgd vout2 r48 r21 d3 d2 c4 c25 m3 c38 cs2- cs2- r8 l1 1 2 d4 c36 c23 c19 cs1- l2 1 2 u1 sc2677b 3 4 5 6 7 8 9 10 11 12 13 22 21 20 19 18 17 16 15 14 1 2 23 24 vref freq vcc +i n2 -in2 co mp2 bst2 dh2 dl2 pg nd bstc gnd pwrg d ss/ ena phasi ng -in1 comp1 bst1 dh1 dl1 cs2+ cs2- cs1- cs1+ c26 r18 r19 c57 cs1- r50 vin r10 c28 enable c33 vout1 cs2+ r13 m1 r14 c43 c59 r51 dual independent outputs typical application schematic description applications
power management 2 www.semtech.com sc2677b dual synchronous voltage mode controller with current sharing circuitry vp1 c25 c39 c26 pwrgd r8 r14 d4 c6 r22 c38 vin3 cs1- d m1 c63 c59 cs2+ m5 c43 vin3 d1 r24 r19 vp1 c23 r13 c19 c4 c28 cs2- cs1+ vp2 cs1+ l2 1 2 c36 u1 sc2677b 3 4 5 6 7 8 9 10 11 12 13 22 21 20 19 18 17 16 15 14 1 2 23 24 vref freq vcc +i n2 -in2 comp2 bst2 dh2 dl2 pgnd bstc gnd pwrgd ss/ ena phasi ng -in1 comp1 bst1 dh1 dl1 cs2+ cs2- cs1- cs1+ cs2- r26 cs2+ r50 c37 c35 r10 vin1 r51 m3 r49 c33 vp2 enable vout l1 1 2 vout c62 c57 r21 d3 r5 cs1- vin2 vin3 m7 r48 d2 vout c57 cs2- r48 r8 c4 r21 r26 cs1+ c43 c6 m7 d2 r50 vout vin c63 vout r10 pwrgd r5 c35 c33 vp2 d1 m3 c19 enable c37 r19 vout vp2 l1 1 2 c59 cs1- c38 c26 cs2+ u1 sc2677b 3 4 5 6 7 8 9 10 11 12 13 22 21 20 19 18 17 16 15 14 1 2 23 24 vref freq vcc +i n2 -in2 comp2 bst2 dh2 dl2 pgnd bstc gnd pwrgd ss/ ena phasi ng -in1 comp1 bst1 dh1 dl1 cs2+ cs2- cs1- cs1+ c25 c39 c36 cs1- m5 r24 c23 r22 r51 c28 r49 cs1+ c62 cs2+ d l2 1 2 vp1 r14 m1 d3 vp1 d4 cs2- r13 dual input, single output, current share mode single input/output, current share mode typical application schematic 3 ? 2009 semtech corp. www.semtech.com power management sc2677b r e t e m a r a pr e t e m a r a p r e t e m a r a p r e t e m a r a pr e t e m a r a ps n o i t i d n o cs n o i t i d n o c s n o i t i d n o c s n o i t i d n o cs n o i t i d n o cn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u e g a t l o v t u p t u ov t u o v = b f 5 9 4 . 00 0 5 . 05 0 5 . 0v v t u o v = , b f 5 2 1 o t 0 4 - o c2 9 4 . 00 0 5 . 08 0 5 . 0v e g a t l o v y l p p u sv c c 5 . 45 1v t n e r r u c y l p p u sv c c 0 . 5 =0 1a m o l v uv c c d l o h s e r h t p u p m a r4 8 . 2v s i s e r e t s y h o l v uv c c 0 0 1v m e c n e r e f e r 5 . 0v n o i t a l u g e r d a o l e c n e r e f e rv f e r a u 0 0 1 ~ a u 0 1 e c r u o s2 . 0% n o i t a l u g e r e n i l e c n e r e f e rv 5 5 ? 2009 semtech corp. www.semtech.com power management sc2677b exp exp exp exp exp anded pin description anded pin description anded pin description anded pin description anded pin description pin 1 pin 1 pin 1 pin 1 pin 1 , 2 , 2 , 2 , 2 , 2 4: 4: 4: 4: 4: (cs2+, cs1+) current sense amplifier (for ocp protection) non-inverting inputs. pin 2, 23: pin 2, 23: pin 2, 23: pin 2, 23: pin 2, 23: (cs2-, cs1-) current sense amplifier (for ocp protection) inverting inputs. pin 3: pin 3: pin 3: pin 3: pin 3: (vref) internal 0.5v reference. connected to the + input of the master channel error amplifier. pin 4: pin 4: pin 4: pin 4: pin 4: (freq) external frequency adjustment. connect a resistor to agnd to set the switching frequency. please see more information in application section. pin 5: pin 5: pin 5: pin 5: pin 5: (vcc) bias pin for the controller. connect a ceramic decoupling capacitor from this pin to agnd with minimum trace length. pin 6: pin 6: pin 6: pin 6: pin 6: (+in2) ?+? input of the slave error amplifier. pin 7, 18: pin 7, 18: pin 7, 18: pin 7, 18: pin 7, 18: (-in2, -in1) ?-? inputs of the error amplifiers. pin 8, 1 pin 8, 1 pin 8, 1 pin 8, 1 pin 8, 1 7 7 7 7 7 : : : : : (comp2, comp1) compensation pins of the error amplifiers. pin 9, 1 pin 9, 1 pin 9, 1 pin 9, 1 pin 9, 1 6: 6: 6: 6: 6: (bst2, bst1) supply pins for the high side drivers. usually connected to bootstrap circuit. pin 1 pin 1 pin 1 pin 1 pin 1 0, 1 0, 1 0, 1 0, 1 0, 1 5: 5: 5: 5: 5: (dh2, dh1) gate drive pins for the top mosfets. requires a small series resistor. pin 1 pin 1 pin 1 pin 1 pin 1 1 1 1 1 1 , 1 , 1 , 1 , 1 , 1 4: 4: 4: 4: 4: (dl2, dl1) gate drive pins for the bottom mosfets. requires a small series resistor. pin 12: pin 12: pin 12: pin 12: pin 12: (pgnd) power gnd. return of the high side and low side gate drivers. pin 1 pin 1 pin 1 pin 1 pin 1 3: 3: 3: 3: 3: (bstc) supply pin for bottom mosfet gate drivers. pin 19: pin 19: pin 19: pin 19: pin 19: (phasing) this pin controls the phase shift between master and slave for optimum noise immunity. use a resistive divider from the freq pin (pin 2) to agnd, and connect the tap of the resistive divider to pin 17. please see more information in application section. pin 20: pin 20: pin 20: pin 20: pin 20: (ss/ena) soft start pin. connect a ceramic capacitor from this pin to agnd, and there is an internal current source charg- ing up this capacitor during soft start. the pwm opera- tion can be disabled if this pin is pulled low. pin 2 pin 2 pin 2 pin 2 pin 2 1: 1: 1: 1: 1: (pwrgd) power good signal. this is an open collector output. it is pulled low internally if output voltage is outside the power good window. pin 22: pin 22: pin 22: pin 22: pin 22: (gnd) analog gnd. return of the analog signals and bias of the chip. e c i v e de c i v e d e c i v e d e c i v e de c i v e d ) 1 () 1 ( ) 1 ( ) 1 () 1 ( e g a k c a pe g a k c a p e g a k c a p e g a k c a pe g a k c a p t r t s t i b 7 7 6 2 c s ) 2 () 2 ( ) 2 ( ) 2 () 2 ( 4 2 - p o s s t t r t e t b 7 7 6 2 c s ) 2 () 2 ( ) 2 ( ) 2 () 2 ( p d e 4 2 - p o s s t 1 - b v e b 7 7 6 2 c sd r a o b n o i t a u l a v e e r a h s t n e r r u c 2 - b v e b 7 7 6 2 c sd r a o b n o i t a u l a v e l e n n a h c l a u d notes: notes: notes: notes: notes: (1) only available in tape and reel packaging. a reel con- tains 2500 devices. (2) lead free package. device is fully weee and rohs compliant. top view (tssop-24 pin) pin configuration ordering information pin descriptions 6 ? 2009 semtech corp. www.semtech.com power management sc2677b notes: notes: notes: notes: notes: (1) channel 1 is the master and channel 2 is the slave in current sharing configuration. (2) for dual output operation, tie +in2 to vref and the two pwm channels are independent. 1.25v 50ua block diagram 7 ? 2009 semtech corp. www.semtech.com power management sc2677b main loop(s) main loop(s) main loop(s) main loop(s) main loop(s) the sc2677b is a dual, voltage mode synchronous buck controller. the two separate channels are identical and share only ic supply pins (vcc and gnd), output driver ground (pgnd) and pre-driver supply voltage (bstc). they also share a common oscillator generating a sawtooth waveform for channel 1 and an dephased sawtooth for channel 2. channel 2 has both inputs of the error ampli- fier uncommitted and available externally. this allows the sc2677b to operate in two distinct modes. a) two independent channels with either common or different input voltages and different output voltages. the two channels each have their own volt- age feedback path from their own output. in this mode, positive input of the error amplifier 2 is con- nected externally to vref. if the application uses a common input voltage, the sawtooth phase shift be- tween the channels provides some measure of input ripple current cancellation. b) two channels operating in current sharing mode with common output voltage and either common in- put voltage or different input voltages. in this mode, channel 1 operates as a voltage mode buck controller, as before, but error amplifier 2 monitors and ampli- fies the difference in voltage across the output cur- rent sense resistors of channel 1 and channel 2 (mas- ter and slave) and adjusts the slave duty cycle to match output currents. to controller also works well for using the output choke winding resistance as cur- rent sensing element (please refer the application schematic for details). the amount of the current of the slave channel vs the master channel can be pro- grammed according to the application. this feature is especially useful when two input sources are used and each source has its power budget. the offset of the current sharing error amplifier is trimmed whthin the range of -2mv to 0mv. the po- larity being such that the slave is off if the master has no current. power good power good power good power good power good the controller provides a power good signal. this is an open collector output, which is pulled low if the output voltage is outside of the power good window. sof sof sof sof sof t star t star t star t star t star t/enable t/enable t/enable t/enable t/enable the soft start/enable (ss/ena) pin serves several functions. if held below the enable threshold, both chan- nels are inhibited. dh1 and dh2 will be low, turning off the top fets. between the soft start enable threshold and the soft start end threshold, the duty cycle is allowed to increase. at the soft start end threshold, maximum duty cycle is reached. in practical applications the error amplifier will be controlling the duty cycle before the soft start end threshold is reached. to avoid boost problems during start-up in current share mode, both channels start up in asynchronous mode, and the bottom fet body diode is used for circulating current during the top fet off time. when the ss/ena pin reaches the soft start transition threshold, the channels begin operating in synchronous mode for improved efficiency. the soft start pin sources approximately 50ua and soft start timing can be set by selection of an appropriate soft start capacitor value. f f f f f req req req req req uency se uency se uency se uency se uency se t and phasing t and phasing t and phasing t and phasing t and phasing the switching frequency can be programmed by connect- ing a resistor from the freq pin to agnd. the phasing pin controls the phase shift between the master sawtooth and slave sawtooth which allows the adjustment of the phase shift for maximum noise immunity by controlling the timing between master and slave transition. a resis- tive divider is used from the freq pin to agnd and the divided voltage is fed to the phasing pin as depicted. u1 sc2677b 3 4 5 6 7 8 9 10 11 12 13 22 21 20 19 18 17 16 15 14 1 2 23 24 vref freq vcc +i n2 -in2 comp2 bst2 dh2 dl2 pgnd bstc gnd pwrgd ss/ena phasing -in1 comp1 bst1 dh1 dl1 cs2+ cs2- cs1- cs1+ r13 r19 application information 8 ? 2009 semtech corp. www.semtech.com power management sc2677b over current protection over current protection over current protection over current protection over current protection current sense amplifiers sense the inductor dcr, and com- pare with an internal ocp reference. as over current being detected, the current sense amplifier will trip the peak current limit on cycle-by-cycle basis. if the over current condition sustains, and the output voltage drops below 75% of its nominal voltage level, the pwm will be disabled and the power supply be latched off with short amount of delay. the latch can be reset by power cycling. (r13+r19) vs.oscillator frequency 300 400 500 600 700 800 900 1000 4 6 8 101214161820 (r13+r19) (kohm) oscillator frequency (khz) vphasing vs phase shift 0 20 40 60 80 100 120 140 160 180 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 vphasing (v) phase (deg) controller power dissipation controller power dissipation controller power dissipation controller power dissipation controller power dissipation controller power dissipation is generated by following parameter; switching frequency, total gate charge of all selected mosfets and supply voltage. p = vin * (i cc + q gt * f sw ) q gt = q g * n where vin : supply voltage for controller and driving mosfet. layout guidelines layout guidelines layout guidelines layout guidelines layout guidelines power and signal traces must be kept separated for noise considerations. feedback, current sense traces and ana- log ground should not cross any traces or planes carrying high switching currents, such as in the input loop or the phase node. the input loop, consisting of the input capacitors and both mosfets must be kept as small as possible. since all of the high switching currents occur in the input loop, the enclosed loop area must be kept small to minimize induc- tance and radiated and conducted noise emissions. an example is shown below to demonstrate the procedure introduced above. vin =12v fsw =250khz n =4(number of mosfet) then q gt = 108nc q g = 27nc (per mosfet) it?s recommended that the below figure be performed to ensure sc2677b under safe operation area. i cc : supply current for controller. q gt : total gate charge of all selected mosfets. q g : total gate charge of per selected mosfets. f sw : switching frequency. n : number of mosfet. q gt limitation (with loading) 20 60 100 140 180 220 260 300 340 380 420 460 500 540 580 620 150 200 250 300 350 400 450 500 fsw(khz) q gt (nc ) 5vin 8.5vin 12vin soa soa soa application information(cont.) 9 ? 2009 semtech corp. www.semtech.com power management sc2677b designing for minimum trace length is not the only factor for best design, often a optimum layout can be achieved by keeping the wide trace and using proper layer stacking to minimize the stray inductance. it is important to keep the gate traces short, the ic must be close to the power switches. it is recommended to use at least 25 mil width or wider trace when. a good place- ment can help if the controller is placed in the middle of the two pwm channels. grounding requirements are always important in a buck converter layout, especially at high power. power ground (pgnd) should be returned to the bottom mosfet source to provide the best gate current return path. analog ground (agnd) should be used for the anaglog returns such as chip decoupling, frequency setiing, reference voltage (or soft starting cap), and the compensation. this agnd shape should be single point connected to the pgnd shape near the ground side of the output capacitors. this will provide noise free analog ground for operation stablity, and also provide best possible remote sensing for the feedback voltage. in case two output rails need to be regulated, the agnd shape should single point connected to the geometric cen- ter of the pgnd for the two point of loads. the single ponit tie is a must to prevent the power current from flow- ing on the agnd shape, so that the analog circuitry in the controller has an electrically quiet reference and to pro- vide the greatest noise free operation. keep in mind that the agnd pin is never allowed to have bigger than 1v voltage difference vs the pgnd pin. this usually achiev- able by using a ground plane for pgnd in pcb layout. using ground plane for pgnd can reduce the physical sepa- ration between the two grounds, such that even the fast current transitions in the pgnd plane can not generate voltage spikes exceeding the 1v level, therefore prevent- ing unstable and erratic behavior from happening. the feedback divider must be close to the ic and be re- turned to analog ground. current sense traces must be run parallel and close to each other and to analog ground. application information(cont.) the ic must have a ceramic decoupling capacitor across its supply pins, mounted as close to the device as possible. the small ceramic, noise-filtering capacitors on the cur- rent sense lines should also be placed as close to the ic as possible. 10 ? 2009 semtech corp. www.semtech.com power management sc2677b dual independent outputs q3 2n3906 d5 1n4148 r2 0 1k r10 1.00k c5 7 1800uf c2 3 1uf u1 sc2677b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 cs2+ cs2- vref freq vcc +in2 -in2 comp2 bst2 dh2 dl2 pgnd bstc dl1 dh1 bst1 comp1 -in1 phasing ss/ena pwrgd gnd cs1- cs1+ dcr=8.83mohm c5 9 1uf c9 4.7uf c60 1nf d2 d1n4148 enable/disable circuit(option) l1 8.8uh c40 4.7uf c43 1000uf r35 1.0 pwrgd c39 1uf c24 0.1uf m3 ipd13n03la c1 9 1800uf m7 ipd13n03la cs2+ c4 7 4.7uf r21 4.53k enable d1 d1 n4 148 vout1 vp1 r5 2 2k l2 4.7uh d3 1n4148 r5 5 4.7k c34 47pf c28 1uf r5 0 7.32k c63 220nf dcr=6.35mohm c3 6 0.1uf cs2- r14 12.4k r12 300 r13 4.42k s_enable cs2+ c33 47nf delay output circuit(option) +12v cs2- c6 2 220nf r1 9 6.19k cs1+ d4 1n4148 cs1- r53 8k r9 10.0k r5 7.5k cs1- m5 ipd13n03la r8 9.09k r49 33.2k c6 1uf c26 100nf r1 1.0 3.3v@2a r11 10.0k c1 4.7uf c4 1000uf r51 13k +12v c46 4.7uf q2 2n3904 r31 2.2 c10 4.7uf c50 1uf 5v@2a vp2 r54 3k r1 8 5.6k cs1+ c25 1uf q1 2n3904 c38 1uf c2 1 1nf c27 option m1 ipd13n03la vout2 r36 0r0 r48 4.02k evaluation schematic 11 ? 2009 semtech corp. www.semtech.com power management sc2677b m e t ie c n e r e f e ry t i t n a u qn o i t p i r c s e dt r a p 17 4 c , 6 4 c , 0 4 c , 0 1 c , 9 c , 1 c6r 7 x , p a c c i m a r e c v 6 1f u 7 . 4 23 4 c , 4 c2 . p a c c i t y l o r t c e l e m u n i m u l a v 6 1v 6 1 / f u 0 0 0 1 37 5 c , 9 1 c2 . p a c c i t y l o r t c e l e m u n i m u l a v 6 1v 6 1 / f u 0 0 8 1 40 5 c , 9 5 c , 9 3 c , 8 3 c , 8 2 c , 5 2 c , 3 2 c , 6 c8r 7 x , p a c c i m a r e c v 6 1f u 1 50 6 c , 1 2 c2r 7 x , p a c c i m a r e c v 6 1f n 1 66 3 c , 4 2 c2r 7 x , p a c c i m a r e c v 6 1f u 1 . 0 76 2 c1r 7 x , p a c c i m a r e c v 6 1f n 0 0 1 83 3 c1r 7 x , p a c c i m a r e c v 6 1f n 7 4 94 3 c1r 7 x , p a c c i m a r e c v 6 1f p 7 4 0 13 6 c , 2 6 c2r 7 x , p a c c i m a r e c v 6 1f n 0 2 2 1 11 l1r o t c u d n im h o m 4 / h u 8 . 8 2 12 l1r o t c u d n im h o m 4 / h u 7 . 4 3 17 m , 5 m , 3 m , 1 m4t e f s o m l e n n a h c - n v 0 3a l 3 0 n 3 1 d p i 4 15 d , 4 d , 3 d , 2 d , 1 d5e d o i d l a n g i s l l a m s8 4 1 4 n 1 5 12 q , 1 q2 r e i f i l p m a e s o p r u p l a r e n e g n p n4 0 9 3 n 2 6 13 q1 r e i f i l p m a e s o p r u p l a r e n e g p n p6 0 9 3 n 2 7 15 3 r , 1 r2% 5 m sm h o 1 8 15 r1% 5 m sk 5 . 7 9 18 r1% 5 m sk 9 0 . 9 0 21 1 r , 9 r2% 5 m sk 0 1 1 20 1 r1% 5 m sk 1 2 22 1 r1% 5 m sm h o 0 0 3 3 23 1 r1% 5 m sk 2 4 . 4 4 24 1 r1% 5 m sk 4 . 2 1 5 28 1 r1% 5 m sk 6 . 5 6 29 1 r1% 5 m sk 9 1 . 6 7 20 2 r1% 5 m sk 1 8 21 2 r1% 5 m sk 3 5 . 4 9 21 3 r1% 5 m sm h o 2 . 2 0 36 3 r1% 5 m sm h o 0 1 38 4 r1% 5 m sk 2 0 . 4 2 39 4 r1% 5 m sk 2 . 3 3 3 30 5 r1% 5 m sk 2 3 . 7 4 31 5 r1% 5 m sk 3 1 5 32 5 r1% 5 m sk 2 6 33 5 r1% 5 m sk 8 7 34 5 r1% 5 m sk 3 8 35 5 r1% 5 m sk 7 . 4 9 31 u1r e l l o r t n o c m w pb 7 7 6 2 c s dual independent outputs evaluation board - bill of materials 12 ? 2009 semtech corp. www.semtech.com power management sc2677b test condition:12vin,5vout@0a, 3.3vout@0a vcc 5vout 3.3vout pwrgd vcc 5vout 3.3vout pwrgd test condition:12vin, 5vout@short circuit , 3.3vout@ 0a test condition:12vin,5vout@2a, 3.3vout@2a vcc 5vout 3.3vout pwrgd test condition:12vin,5vout@2a, 3.3vout@short vcc 5vout 3.3vout pwrgd test condition:12vin,5vout@2a, 3.3vout@2a dh1 dl1 dh2 dl2 performance (dual output) 13 ? 2009 semtech corp. www.semtech.com power management sc2677b load current vs. vcs1+ to vout1 0 5 10 15 20 25 30 35 40 01234567 load current (a) vcs1+ to vout1 (mv) 3.3v ocp 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 0123456 load current (a) vout2 (v) load current vs.vcs2+ to vout2 0 5 10 15 20 25 30 35 40 0123456 load current (a) vcs2+ to vout2 (mv) 5v ocp 0.0 1.0 2.0 3.0 4.0 5.0 6.0 01234567 load current (a) vout1 (v) overall system efficiency 80 82 84 86 88 90 92 94 96 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 loading (a) efficiency (% ) io 1 + io 2 performance (dual output) 14 ? 2009 semtech corp. www.semtech.com power management sc2677b c39 1uf c20 1800uf cs1+ c4 1800uf m7 ipd06n03la c10 4.7uf r22 2.32k dcr=4mohm cs1+ pwrgd c56 1800uf r51 5.76k c28 1uf enable/disable circuit (option) c59 1uf r9 10.0k vp1 +12v +3.3v d1 d1n4148 vout1 l2 2uh cs2- c9 4.7uf vp2 (1) r24 4.87k r48 3k r13 4.64k q1 2n3904 cs1- c24 0.1uf c33 33nf cs2+ m1 ipd09n03la r5 7.5k c60 1nf cs2- c25 1uf enable c63 220nf c40 4.7uf c62 220nf (1) c19 1800uf u1 sc2677b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 cs2+ cs2- vref freq vcc +in2 -in2 comp2 bst2 dh2 dl2 pgnd bstc dl1 dh1 bst1 comp1 -in1 phasing ss/ena pwrgd gnd cs1- cs1+ d2 d1n4148 r19 5.9k r35 1.0 r36 0r0 1.4v@20a r12 300 c6 1uf vout cs2+ c57 1800uf c47 4.7uf note (1) : current scale. master channel current weighting factor is around 0.68 * io, slaver is around 0.32 * io q2 2n3904 vp1 d3 1n4148 +5v d5 1n4148 r14 8.06k l1 2uh r21 2.1k dcr=4mohm m5 ipd09n03la c21 1nf cs1- c35 220nf c36 0.1uf c37 220nf r11 10.0k m3 ipd06n03la r31 2.2 d4 1n4148 r8 1.78k r26 4.3k c46 4.7uf r10 1.00k c43 1800uf +12v c1 4.7uf c23 1uf c38 1uf vout r1 1.0 r50 6.34k c26 47nf vp2 single output, current share mode evaluation schematic (cont.) 15 ? 2009 semtech corp. www.semtech.com power management sc2677b m e t ie c n e r e f e ry t i t n a u qn o i t p i r c s e dt r a p 17 4 c , 6 4 c , 0 4 c , 0 1 c , 9 c , 1 c6r 7 x , p a c c i m a r e c v 6 1f u 7 . 4 27 5 c , 6 5 c , 3 4 c , 0 2 c , 9 1 c , 4 c6 . p a c c i t y l o r t c e l e m u n i m u l a v 6 1v 6 1 / f u 0 0 8 1 39 5 c , 9 3 c , 8 3 c , 8 2 c , 5 2 c , 3 2 c , 6 c7r 7 x , p a c c i m a r e c v 6 1f u 1 46 3 c , 4 2 c2r 7 x , p a c c i m a r e c v 6 1f u 1 . 0 56 2 c1r 7 x , p a c c i m a r e c v 6 1f n 7 4 63 3 c1r 7 x , p a c c i m a r e c v 6 1f n 3 3 73 6 c , 2 6 c , 7 3 c , 5 3 c4r 7 x , p a c c i m a r e c v 6 1f n 0 2 2 82 l , 1 l2r o t c u d n im h o m 4 / h u 2 95 m , 1 m2 t e f s o m l e n n a h c - n v 5 2a l 3 0 n 9 0 d p i 0 17 m , 3 m2 t e f s o m l e n n a h c - n v 5 2a l 3 0 n 6 0 d p i 1 15 d , 4 d , 3 d , 2 d , 1 d5e d o i d l a n g i s l l a m s8 4 1 4 n 1 2 12 q , 1 q2 r e i f i l p m a e s o p r u p l a r e n e g n p n4 0 9 3 n 2 3 15 3 r , 1 r2% 5 m sm h o 1 4 15 r1% 5 m sk 5 . 7 5 18 r1% 5 m sk 8 7 . 1 6 11 1 r , 9 r2% 5 m sk 0 1 7 10 1 r1% 5 m sk 1 8 12 1 r1% 5 m sm h o 0 0 3 9 13 1 r1% 5 m sk 4 6 . 4 0 24 1 r1% 5 m sk 6 0 . 8 1 29 1 r1% 5 m sk 9 . 5 2 21 2 r1% 5 m sk 1 . 2 3 22 2 r1% 5 m sk 2 3 . 2 4 24 2 r1% 5 m sk 7 8 . 4 5 26 2 r1% 5 m sk 3 . 4 6 21 3 r1% 5 m sm h o 2 . 2 7 26 3 r1% 5 m sm h o 0 8 28 4 r1% 5 m sk 3 9 20 5 r1% 5 m sk 4 3 . 6 0 31 5 r1% 5 m sk 6 7 . 5 1 31 u1r e l l o r t n o c m w pb 7 7 6 2 c s single output, current share mode evaluation board - bill of materials 16 ? 2009 semtech corp. www.semtech.com power management sc2677b vout dl1 ss/en test condition: 3.3vin/5vin, io=0a dh1 test condition: io=20a vout pwrgd io test condition: 3.3vin/5vin, io=20a test condition: 3.3vin/5vin, short circuit vout pwrgd io test condition: io=0 - 20a, t1=t2=3ms, rt=ft=2.5a/us vout il2 il1 io test condition: 3.3vin/5vin, io= 20a vout pwrgd io test condition:3.3vin/5vin, 1.4vout@20a dh1 dl1 vout performance (single output) 17 ? 2009 semtech corp. www.semtech.com power management sc2677b test condition:3.3vin/5vin, 1.4vout@20a dh2 dl2 vout ocp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 5 10 15 20 25 30 load current (a) vout (v) vo (v) load current vs.vcs+ to vout (m v) 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 load current (a ) vcs1+ to vout1 (mv ) vcs1+ to v out1 vcs2+ to v out2 3.3v and 5v input current 0 1 2 3 4 5 6 7 8 02468101214161820 load current (a) input current (a) iin3.3 a iin5 a regualation characteristic 1.4030 1.4035 1.4040 1.4045 1.4050 1.4055 1.4060 0 5 10 15 20 load current (a) vout (v) vout v overall system efficiency 70 75 80 85 90 0 2 4 6 8 10 12 14 16 18 20 load current (a) efficiency (%) io performance (single output) 18 ? 2009 semtech corp. www.semtech.com power management sc2677b contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 outline drawing - tssop-24 land pattern - tssop-24 l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 24 .004 .169 .303 .173 .307 .007 - 24 0.10 0.65 bsc 6.40 bsc 4.40 7.80 - .177 .311 4.30 7.70 .012 0.19 4.50 7.90 0.30 bxn 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 1 3 2 n reference jedec std mo-153, variation ad. 4. inches b n ccc aaa bbb 01 e1 e l l1 e d c a2 a1 dim a min max millimeters min dimensions nom max nom e a a2 a1 e1 bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view (.039) .004 .008 - .024 - - - - 0 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - (1.0) 0.60 - 0.75 0.20 - - - 1.20 1.05 0.15 a b c d e e/2 h plane d this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters 19 ? 2009 semtech corp. www.semtech.com power management sc2677b contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 outline drawing - tssop-24 edp land pattern - tssop-24 edp l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 24 .004 .169 .303 .173 .307 .007 - 24 0.10 0.65 bsc 6.40 bsc 4.40 7.80 - .177 .311 4.30 7.70 .012 0.19 4.50 7.90 0.30 bxn 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 1 3 2 n a a2 a1 e1 bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- o tes: 1. 2. -a- -h- side view (.039) .004 .008 - .024 - - - - 0 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - (1.0) 0.60 - 0.75 0.20 - - - 1.20 1.05 0.15 a b c d e e/2 h plane d reference jedec std mo-153, variation ad. 4. inches b n ccc aaa bbb 01 e1 e l l1 e d c a2 a1 dim a min max millimeters min dimensions nom max nom e h f view bottom .112 .118 .122 2.85 3.00 3.10 .211 .217 .221 5.37 5.52 5.62 f h (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. inches dimensions z p y x dim c g millimeters f h .225 .126 5.72 3.20 h f |
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