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features n 100ma output current n 1.5ma supply current n 85mhz bandwidth (a v = +2) n -66/-75dbc hd2/hd3 (1mhz) n 25ns settling to 0.05% n 260v/ m s slew rate n stable for capacitive loads up to 1000pf n single 5v to 5v supplies n available in t iny sot23-5 package applications n coaxial cable driver n t wisted pair driver n transformer/coil driver n high capacitive load driver n v ideo line driver n portable/battery-powered applications n a/d driver 451 pinout v ee 1k w 1k w 0.1 m f 6.8 m f v in 5k w 5k w + +5v +5v 1 clc451 7 6 8 5 3 4 2 1k w 1k w 0.1 m f 0.1 m f 451 typ. app. diagram v o 10m of 75 w coaxial cable 75 w 0.1 m f 75 w typical application single supply cable driver pinout dip & soic general description the comlinear clc451 is a low cost, high speed (85mhz) buf fer that features user-programmable gains of +2, +1, and -1v/v . it has a new output stage that delivers high output drive current (100ma), but consumes minimal quiescent supply current (1.5ma) from a single 5v supply . its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a programmable range of gains and wide signal levels, and has a linear-phase response up to one half of the -3db frequency . the clc451 s internal feedback network provides an excellent gain accuracy of 0.3% the clc451 of fers superior dynamic performance with a 85mhz small-signal bandwidth, 260v/ m s slew rate and 6.5ns rise/fall times (2v step ). the combination of the small sot23-5 package, low quiescent power , high output current drive, and high-speed performance make the clc451 well suited for many battery- powered personal communication/computing systems. the ability to drive low-impedance, highly capacitive loads, makes the clc451 ideal for single ended cable applications. it also drives low impedance loads with minimum distortion. the clc451 will drive a 100 w load with only -78/-65dbc second/third harmonic distortion (a v = +2, v out = 2v pp , f = 1mhz). with a 25 w load, and the same conditions, it produces only -55/-60dbc sec - ond/third harmonic distortion. it is also optimized for driving high currents into single-ended transformers and coils. when driving the input of high-resolution a/d converters, the clc451 provides excellent -66/-75dbc second/third harmonic distortion (a v = +2, v out = 2v pp , f = 1mhz, r l = 1k w ) and fast settling time. maximum output voltage vs. r l output voltage (v pp ) r l ( w ) 450 performance plot 1 2 3 4 5 6 7 8 9 10 10 100 1000 v s = +5v v cc = 5v comlinear clc451 single supply , low-power , high output, programmable buffer n december 1996 comlinear clc451 single supply , low-power , high output, programmable buffer response after 10m of cable 100mv/div 20ns/div 450 typ. app. plot v in = 10mhz, 0.5v pp 451 pinout (sot) v inv v cc v ee v o v non-inv 1k w 1k w + - pinout sot23-5 1996 national semiconductor corporation http://www.national.com printed in the u.s.a.
http://www.national.com 2 p arameters conditions typ min/max ra tings units notes ambient t emperature clc451aj +25 c +25 c 0 to 70 c -40 to 85 c frequency domain response -3db bandwidth v o = 0.5v pp 85 70 58 55 mhz b v o = 2.0v pp 70 55 50 45 mhz - 0.1db bandwidth v o = 0.5v pp 20 15 13 13 mhz gain peaking <200mhz, v o = 0.5v pp 0 0.5 0.9 1.0 db b gain rollof f <30mhz, v o = 0.5v pp 0.2 0.5 0.7 0.7 db b linear phase deviation <30mhz, v o = 0.5v pp 0.1 0.4 0.5 0.5 deg time domain response rise and fall time 2v step 6.5 9.0 9.7 10.5 ns settling time to 0.05% 1v step 25 ns overshoot 2v step 13 15 18 18 % slew rate 2v step 260 180 165 150 v/ m s dist ortion and noise response 2 nd harmonic distortion 2v pp , 1mhz -78 -72 -70 -70 dbc 2v pp , 1mhz; r l = 1k w -66 -60 -58 -58 dbc 2v pp , 5mhz -60 -54 -52 -52 dbc b 3 rd harmonic distortion 2v pp , 1mhz -65 -61 -59 -59 dbc 2v pp , 1mhz; r l = 1k w -75 -69 -67 -67 dbc 2v pp , 5mhz -52 -48 -46 -46 dbc b equivalent input noise voltage (e ni ) >1mhz 3.0 3.7 4 4 nv/ ? hz non-inverting current (i bn ) >1mhz 6.9 9 10 10 pa/ ? hz inverting current (i bi ) >1mhz 8.5 11 12 12 pa/ ? hz sta tic dc performance input of fset voltage 8 30 35 35 mv a average drift 80 m v/ ? c input bias current (non-inverting) 3 14 17 18 m a a average drift 25 na/ ? c gain accuracy 0.3 1.5 2.0 2.0 % a internal resistors (r f , r g ) 1000 20% 26% 30% w power supply rejection ratio dc 49 46 44 44 db b common-mode rejection ratio dc 51 48 46 46 db supply current r l = 1.5 1.7 1.8 1.8 ma a miscellaneous performance input resistance (non-inverting) 0.5 0.37 0.33 0.33 m w input capacitance (non-inverting) 1.5 2.3 2.3 2.3 pf input voltage range, high 4.2 4.1 4.0 4.0 v input voltage range, low 0.8 0.9 1.0 1.0 v output voltage range, high r l = 100 w 4.0 3.9 3.8 3.8 v output voltage range, low r l = 100 w 1.0 1.1 1.2 1.2 v output voltage range, high r l = 4.1 4.0 4.0 3.9 v output voltage range, low r l = 0.9 1.0 1.0 1.1 v output current 100 80 65 40 ma c output resistance, closed loop dc 400 600 600 600 m w min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. +5v electrical characteristics (a v = +2, r l = 100 w , v s = +5v 1 , v cm = v ee + (v s /2), r l tied to v cm , unless specified) absolute maximum ratings supply voltage (v cc - v ee ) + 14v output current (see note c) 140ma common-mode input voltage v ee to v cc maximum junction temperature +175? storage temperature range -65 c to +150 ? lead temperature (soldering 10 sec) +300? esd rating (human body model) 500v notes a) j-level: spec is 100% tested at +25 c, sample tested at +85 c. b) j-level: spec is sample tested at +25 ?. c) the short circuit current can exceed the maximum safe output current. 1) v s = v cc - v ee reliability information transistor count 49 mtbf (based on limited test data) 31mhr
3 http://www.national.com p arameters conditions typ guaranteed min/max units notes ambient t emperature clc451aj +25 c +25 c 0 to 70 c -40 to 85 c frequency domain response -3db bandwidth v o = 1.0v pp 100 80 68 65 mhz v o = 4.0v pp 55 45 42 40 mhz - 0.1db bandwidth v o = 1.0v pp 20 15 13 13 mhz gain peaking <200mhz, v o = 1.0v pp 0 0.5 0.9 1.0 db gain rollof f <30mhz, v o = 1.0v pp 0.2 0.7 0.8 0.8 db linear phase deviation <30mhz, v o = 1.0v pp 0.1 0.3 0.4 0.4 deg dif ferential gain ntsc, r l =150 w 0.3 % dif ferential phase ntsc, r l =150 w 0.3 deg time domain response rise and fall time 2v step 5.0 6.5 7.0 7.7 ns settling time to 0.05% 2v step 20 ns overshoot 2v step 10 13 15 15 % slew rate 2v step 350 260 240 220 v/ m s dist ortion and noise response 2 nd harmonic distortion 2v pp , 1mhz -72 -66 -64 -64 dbc 2v pp , 1mhz; r l = 1k w -69 -63 -61 -61 dbc 2v pp , 5mhz -66 -60 -58 -58 dbc 3 rd harmonic distortion 2v pp , 1mhz -65 -61 -59 -59 dbc 2v pp , 1mhz; r l = 1k w -73 -67 -65 -65 dbc 2v pp , 5mhz -52 -48 -46 -46 dbc equivalent input noise voltage (e ni ) >1mhz 3.0 3.7 4 4 nv/ ? hz non-inverting current (i bn ) >1mhz 6.9 9 10 10 pa/ ? hz inverting current (i bi ) >1mhz 8.5 11 12 12 pa/ ? hz sta tic dc performance output of fset voltage 3 30 35 35 mv b average drift 80 m v/ ? c input bias current (non-inverting) 1 12 16 17 m a b average drift 40 na/ ? c gain accuracy 0.3 1.5 2.0 2.0 % internal resistors (r f , r g ) 1000 20% 26% 30% w power supply rejection ratio dc 51 48 46 46 db common-mode rejection ratio dc 53 50 48 48 db supply current r l = 1.6 1.9 2.0 2.0 ma b miscellaneous performance input resistance (non-inverting) 0.7 0.50 0.45 0.45 m w input capacitance (non-inverting) 1.2 1.8 1.8 1.8 pf common-mode input range 4.2 4.1 4.1 4.0 v output voltage range r l = 100 w 3.8 3.6 3.6 3.5 v output voltage range r l = 4.0 3.8 3.8 3.7 v output current 130 100 80 50 ma c output resistance, closed loop dc 400 600 600 600 m w 5v electrical characteristics (a v = +2, r l = 100 w , v cc = 5v, unless specified) notes b) j-level: spec is sample tested at +25 ?. c) the short circuit current can exceed the maximum safe output current. ordering information model temperature range description clc451ajp -40 c to +85 c 8-pin pdip clc451aje -40 c to +85 c 8-pin soic CLC451AJM5 -40 c to +85 c 5-pin sot clc451alc -40 c to +85 c dice package thermal resistance package q jc q ja plastic (ajp) 115 c/w 125 c/w surface mount (aje) 130 c/w 150 c/w surface mount (ajm5) 140 c/w 210 c/w dice (alc) 25 c/w
http://www.national.com 4 +5v typical performance (a v = +2, r l = 100 w , v s = +5v 1 , v cm = v ee + (v s /2), r l tied to v cm , unless specified) frequency response normalized magnitude (1db/div) frequency (hz) 451 plot1 10m v o = 0.5v pp phase (deg) -225 -180 -135 -90 -45 0 100m 1m a v = 1 a v = -1 a v = 2 a v = 1 a v = 2 a v = -1 gain phase frequency response vs. r l magnitude (1db/div) frequency (hz) 451 plot2 10m v o = 0.5v pp phase (deg) -450 -360 -270 -180 -90 0 100m 1m r l = 1k w r l = 100 w r l = 25 w r l = 1k w r l = 100 w r l = 25 w gain phase frequency response vs. v o (a v = 2) magnitude (1db/div) frequency (hz) 451 plot3 10m 100m 1m v o = 1v pp v o = 2v pp v o = 0.1v pp v o = 2.5v pp frequency response vs. v o (a v = +1) magnitude (1db/div) frequency (hz) 451 plot4 10m 100m 1m v o = 1v pp v o = 2v pp v o = 0.1v pp v o = 2.5v pp frequency response vs. v o (a v = -1) magnitude (1db/div) frequency (hz) 451 plot5 10m 100m 1m v o = 1v pp v o = 2v pp v o = 0.1v pp v o = 2.5v pp frequency response vs. c l magnitude (1db/div) frequency (hz) 451 plot6 1m 10m 100m v o = 0.5v pp c l = 10pf r s = 49.9 w c l = 100pf r s = 21 w c l = 1000pf r s = 6.7 w c l 1k r s + - 1k 1k gain flatness magnitude (0.05db/div) frequency (mhz) 451 plot7 10 20 30 v o = 0.5v pp equivalent input noise noise voltage (nv/ ? hz) frequency (hz) 451 plot8 4 3.5 0.1k 1k 10k 100k 1m 10m 3 2.5 non-inverting current 6.9pa/ ? hz inverting current 8.5pa/ ? hz voltage 3.0nv/ ? hz noise current (pa/ ? hz) 10 11 12 9 6 8 7 2nd & 3rd harmonic distortion distortion (dbc) frequency (hz) 451 plot9 1m 10m v o = 2v pp -90 -80 -70 -60 -50 -40 2nd r l = 1k w 2nd r l = 100 w 3rd r l = 100 w 3rd r l = 1k w 2nd harmonic distortion, r l = 25 w distortion (dbc) output amplitude (v pp ) 451 plot10 0 0.5 1 1.5 2 2.5 -25 -30 -35 -40 -45 -50 -55 2mhz 5mhz 10mhz 1mhz 3rd harmonic distortion, r l = 25 w distortion (dbc) output amplitude (v pp ) 451 plot11 0 0.5 1 1.5 2 2.5 -20 -30 -40 -50 -60 2mhz 5mhz 10mhz 1mhz 2nd harmonic distortion, r l = 100 w distortion (dbc) output amplitude (v pp ) 451 plot12 0 0.5 1 1.5 2 2.5 -55 -60 -65 -70 -75 -80 -85 -90 2mhz 5mhz 10mhz 1mhz 3rd harmonic distortion, r l = 100 w distortion (dbc) output amplitude (v pp ) 451 plot13 0 0.5 1 1.5 2 2.5 -30 -35 -40 -45 -50 -55 -60 -65 -70 2mhz 5mhz 10mhz 1mhz 2nd harmonic distortion, r l = 1k w distortion (dbc) output amplitude (v pp ) 451 plot14 0 0.5 1 1.5 2 2.5 -60 -65 -70 -75 -80 -85 2mhz 5mhz 10mhz 1mhz 3rd harmonic distortion, r l = 1k w distortion (dbc) output amplitude (v pp ) 451 plot15 0 0.5 1 1.5 2 2.5 -50 -55 -60 -65 -70 -75 -80 -85 2mhz 5mhz 10mhz 1mhz
5 http://www.national.com +5v typical performance (a v = +2, r l = 100 w , v s = + 5v 1 , v cm = v ee + (v s /2), r l tied to v cm , unless specified) closed loop output resistance output resistance ( w ) frequency (hz) 451 plot16 10k 100k 1m 10m 100m 0.01 0.1 1 10 100 recommended r s vs. c l r s ( w ) c l (pf) 451 plot17 10 100 1000 0 10 20 30 40 50 c l 1k r s + - 1k 1k large & small signal pulse response output voltage (0.5v/div) time (10ns/div) 451 plot18 large signal small signal psrr & cmrr psrr & cmrr (db) frequency (hz) 451 plot19 1k 10k 100m 0 10 20 30 40 50 60 100k 1m 10m psrr cmrr i bn , v os vs. temperature offset voltage v os (mv) temperature ( c) 451 plot20 -100 -50 0 50 100 150 -1.1 i bn ( m a) 1 -1 2 -0.9 3 -0.8 4 -0.7 5 -0.6 6 i bn v os maximum output voltage vs. r l output voltage (v pp ) r l ( w ) 451 plot21 10 100 1000 1 1.5 2 2.5 3 3.5 4 4.5 5 5v typical performance (a v = +2, r l = 100 w , v cc = 5v, unless specified) frequency response normalized magnitude (1db/div) frequency (hz) 451 plot22 1m 10m 100m phase (deg) -45 0 -90 -225 -135 -180 gain phase v o = 1v pp a v = +1 a v = -1 a v = 2 frequency response vs. r l magnitude (1db/div) frequency (hz) 451 plot23 1m 10m 100m phase (deg) -90 0 -180 -450 -270 -360 gain phase v o = 1v pp r l = 1k w r l = 100 w r l = 25 w frequency response vs. v o (a v = 2) magnitude (1db/div) frequency (hz) 451 plot24 1m 10m 100m v o = 5v pp v o = 1v pp v o = 2v pp v o = 0.1v pp frequency response vs. v o (a v = +1) magnitude (1db/div) frequency (hz) 451 plot25 1m 10m 100m v o = 5v pp v o = 1v pp v o = 2v pp v o = 0.1v pp frequency response vs. v o (a v = -1) magnitude (1db/div) frequency (hz) 451 plot26 1m 10m 100m v o = 2v pp v o = 1v pp v o = 0.1v pp frequency response vs. c l magnitude (1db/div) frequency (hz) 451 plot27 1m 10m 100m v o = 1v pp c l = 10pf r s = 49.9 w c l = 100pf r s = 17.4 w c l = 1000pf r s = 6.7 w c l 1k r s + - 1k 1k
http://www.national.com 6 5v typical performance (a v = +2, r l = 100 w , v cc = 5v, unless specified) gain flatness magnitude (0.05db/div) 451 plot28 v o = 1v pp frequency (mhz) 0 5 10 15 20 25 30 large & small signal pulse response output voltage (0.5v/div) time (10ns/div) 451 plot29 large signal small signal 2nd & 3rd harmonic distortion distortion (dbc) frequency (hz) 451 plot30 1m 10m v o = 2v pp -90 -80 -70 -60 -50 -40 2nd r l = 1k w 2nd r l = 100 w 3rd r l = 100 w 3rd r l = 1k w 2nd harmonic distortion, r l = 25 w distortion (dbc) output amplitude (v pp ) 451 plot31 0 1 2 3 4 5 -30 -35 -40 -45 -50 -55 -60 2mhz 5mhz 10mhz 1mhz 3rd harmonic distortion, r l = 25 w distortion (dbc) output amplitude (v pp ) 451 plot32 0 1 2 3 4 5 -25 -30 -35 -40 -45 -50 -55 -60 2mhz 5mhz 10mhz 1mhz 2nd harmonic distortion, r l = 100 w distortion (dbc) output amplitude (v pp ) 451 plot33 0 1 2 3 4 5 -58 -60 -62 -64 -66 -68 -70 -72 -74 2mhz 5mhz 10mhz 1mhz 3rd harmonic distortion, r l = 100 w distortion (dbc) output amplitude (v pp ) 451 plot34 0 1 2 3 4 5 -30 -40 -50 -60 -70 -80 2mhz 5mhz 10mhz 1mhz 2nd harmonic distortion, r l = 1k w distortion (dbc) output amplitude (v pp ) 451 plot35 0 1 2 3 4 5 -60 -65 -70 -75 -80 -85 2mhz 5mhz 10mhz 1mhz 3rd harmonic distortion, r l = 1k w distortion (dbc) output amplitude (v pp ) 451 plot36 0 1 2 3 4 5 -50 -55 -60 -65 -70 -75 -80 -85 2mhz 5mhz 10mhz 1mhz recommended r s vs. c l r s ( w ) c l (pf) 451 plot37 10 100 1000 50 40 30 20 10 0 c l 1k r s + - 1k 1k maximum output voltage vs. r l output voltage (v pp ) r l ( w ) 451 plot38 10 100 1000 2 3 4 5 6 7 8 10 9 differential gain & phase gain (%) number of 150 w loads 451 plot39 1 2 3 4 -0.1 phase (deg) -0.3 -0.2 -0.4 -0.3 -0.5 -0.4 -0.6 -0.5 -0.7 -0.6 -0.8 -0.7 -0.9 f = 3.58mhz gain positive sync phase negative sync phase positive sync gain negative sync i bn , v os vs. temperature offset voltage v os (mv) temperature ( c) 451 plot40 -100 -50 0 50 100 150 -0.5 0 0.5 1 1.5 i bn ( m a) -4 0 4 8 12 i bn v os short term settling time v o (% output step) time (ns) 451 plot41 1 10 100 1000 -0.2 -0.1 0 0.1 0.2 v o = 2vstep long term settling time v o (% output step) time (s) 451 plot42 1 m 10 m 100 m 1m 10m 100m 1 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 v o = 2vstep
7 http://www.national.com clc451 operation the clc451 is a current feedback buf fer built in an advanced complementary bipolar process. the clc451 operates from a single 5v supply or dual 5v supplies. operating from a single 5v supply , the clc451 has the following features: n gains of +1, -1, and 2v/v are achievable without external resistors n provides 100ma of output current while consuming only 7.5mw of power n of fers low -66/-75dbc 2nd and 3rd harmonic distortion n provides bw > 60mhz and 1mhz distortion < -55dbc at v o = 2v pp the clc451 performance is further enhanced in 5v supply applications as indicated in the 5v electrical characteristics table and 5v t ypical performance plots. if gains other than +1, -1, or +2v/v are required, then the clc450 can be used. the clc450 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. current feedback amplifiers some of the key features of current feedback technology are: n independence of ac bandwidth and voltage gain n inherently stable at unity gain n adjustable frequency response with feedback resistor n high slew rate n fast settling current feedback operation can be described using a simple equation. the voltage gain for a non-inverting or inverting current feedback amplifier is approximated by equation 1. equation 1 where: n a v is the closed loop dc voltage gain n r f is the feedback resistor n z(j w ) is the clc451 s open loop transimpedance gain n is the loop gain the denominator of equation 1 is approximately equal to 1 at low frequencies. near the -3db corner frequency , the interaction between r f and z(j w ) dominates the circuit performance. the value of the feedback resistor has a large af fect on the circuits performance. increasing r f has the following af fects: n decreases loop gain n decreases bandwidth n reduces gain peaking n lowers pulse response overshoot n af fects frequency response phase linearity v v a 1 r z(j ) o in v f = + w z j r f w ( ) clc451 design information closed loop gain selection the clc451 is a current feedback op amp with r f = r g = 1k w on chip (in the package). select from three closed loop gains without using any external gain or feedback resistors. implement gains of +2, +1, and -1v/v by connecting pins 2 and 3 as described in the chart below. the gain accuracy of the clc451 is excellent and stable over temperature change. the internal gain setting resistors, r f and r g are dif fused silicon resistors with a process variation of 20% and a temperature coef ficient of ? 2000ppm/ c. although their absolute values change with processing and temperature, their ratio (r f /r g ) remains constant. if an external resistor is used in series with r g , gain accuracy over temperature will suffer. single supply operation (v cc = +5v, v ee = gnd) the specifications given in the +5v electrical character- istics table for single supply operation are measured with a common mode voltage (v cm ) of 2.5v . v cm is the voltage around which the inputs are applied and the output voltages are specified. operating from a single +5v supply , the common mode input range (cmir) of the clc451 is typically +0.8v to +4.2v . the typical output range with r l =100 w is +1.0v to +4.0v. for single supply dc coupled operation, keep input signal levels above 0.8v dc. for input signals that drop below 0.8v dc, ac coupling and level shifting the signal are recommended. the non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. dc coupled single supply operation figures 1, 2, and 3 on the following page, show the recommended configurations for input signals that remain above 0.8v dc. gain input connections a v non-inverting (pin3) inverting (pin2) -1v/v ground input signal +1v/v input signal nc (open) +2v/v input signal ground
http://www.national.com 8 figure 1: dc coupled, a v = -1v/v configuration figure 2: dc coupled, a v = +1v/v configuration figure 3: dc coupled, a v = +2v/v configuration ac coupled single supply operation figures 4, 5, and 6 show possible non-inverting and invert - ing configurations for input signals that go below 0.8v dc. figure 4: ac coupled, a v = -1v/v configuration the input is ac coupled to prevent the need for level shifting the input signal at the source. the resistive voltage divider biases the non-inverting input to v cc 2 = 2.5v (for v cc = +5v). figure 5: ac coupled, a v = +1v/v configuration figure 6: ac coupled, a v = +2v/v configuration dual supply operation the clc451 operates on dual supplies as well as single supplies. the non-inverting and inverting configurations are shown in figures 7, 8 and 9. figure 7: dual supply , a v = -1v/v configuration 451 fig5 0.1 m f 6.8 m f v o v in r r + v cc v cc 1 clc451 7 6 8 5 3 4 2 1k w 1k w c c v v 2.5 low frequency cutoff 1 2 r c where r r 2 r r o in in c in source = + = = >> p , 451 fig1 0.1 m f 6.8 m f v o v in r b r t + v cm v cc r l v cm note: r b provides dc bias for the non-inverting input. r b , r l and r t are tied to v cm for minimum power consumption and maximum output swing. v cm 1 clc451 7 6 8 5 3 4 2 1k w 1k w select r t to yield desired r in = r t ||r g , where r g = 1k w . 451 fig2 0.1 m f 6.8 m f v o v in r t + v cm v cc r l v cm note: r t and r l are tied to v cm for minimum power consumption and maximum output swing. 1 clc451 7 6 8 5 3 4 2 1k w 1k w 451 fig3 0.1 m f 6.8 m f v o v in r t + v cm v cc r l v cm note: r t , r l and r g are tied to v cm for minimum power consumption and maximum output swing. 1 clc451 7 6 8 5 3 4 2 1k w 1k w v cm 451 fig4 0.1 m f 6.8 m f v o v in r r + v cc v cc 1 clc451 7 6 8 5 3 4 2 1k w 1k w c c v v 2.5 low frequency cutoff 1 2 r c o in g c = - + = p where r g = 1k w . , 451 fig6 0.1 m f 6.8 m f v o v in r r + v cc v cc 1 clc451 7 6 8 5 3 4 2 1k w 1k w c c c v 2v 2.5 low frequency cutoff 1 2 r c where r r 2 r r o in in c in source = + = = >> p , 451 fig7 0.1 m f 6.8 m f v o v in r t + v cc note: r b provides dc bias for the non-inverting input. select r t to yield desired r in = r t ||1k w . 1 clc451 7 6 8 5 3 4 2 1k w 1k w r b 0.1 m f 6.8 m f + v ee
9 http://www.national.com figure 8: dual supply, a v = +1v/v configuration figure 9: dual supply, a v = +2v/v configuration bandwidth vs. output amplitude the bandwidth of the clc451 is at a maximum for output voltages near 1v pp . the bandwidth decreases for smaller and larger output amplitudes. refer to the frequency response vs. v o plots. load termination the clc451 can source and sink near equal amounts of current. for optimum performance, the load should be tied to v cm . driving cables and capacitive loads when driving cables, double termination is used to prevent reflections. for capacitive load applications, a small series resistor at the output of the clc451 will improve stability and settling performance. the frequency response vs. c l and recommended r s vs. c l plots, in the typical performance section, give the recommended series resistance value for optimum flatness at various capacitive loads. t ransmission line matching one method for matching the characteristic impedance (z o ) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. figure 10 shows typical inverting and non-inverting circuit configurations for matching transmission lines. non-inverting gain applications: n connect pin 2 as indicated in the table in the closed loop gain selection section. n make r 1 , r 2 , r 6 , and r 7 equal to z o . n use r 3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. inverting gain applications: n connect r 3 directly to ground. n make the resistors r 4 , r 6 , and r 7 equal to z o . n make r 5 ii r g = z o . the input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. use c 6 to match the output transmission line over a greater frequency range. c 6 compensates for the increase of the amplifier s output impedance with frequency . figure 10: t ransmission line matching power dissipation follow these steps to determine the power consumption of the clc451: 1. calculate the quiescent (no-load) power: p amp = i cc (v cc - v ee ) 2. calculate the rms power at the output stage: p o = (v cc - v load ) (i load ), where v load and i load are the rms voltage and current across the external load. 3. calculate the total rms power: p t = p amp + p o the maximum power that the dip , soic, and sot packages can dissipate at a given temperature is illustrated in figure 1 1. the power derating curve for any clc451 package can be derived by utilizing the following equation: where t amb = ambient temperature ( ?) q ja = thermal resistance, from junction to ambient, for a given package ( ?/w) (175 t amb ja - ) q 451 fig8 0.1 m f 6.8 m f v o v in r t + v cc 1 clc451 7 6 8 5 3 4 2 1k w 1k w 0.1 m f 6.8 m f + v ee 451 fig9 0.1 m f 6.8 m f v o v in r t + v cc 1 clc451 7 6 8 5 3 4 2 1k w 1k w 0.1 m f 6.8 m f + v ee 451 fig10 z 0 r 6 v o z 0 r 4 r 5 + - r 3 z 0 r 1 r 2 v 1 v 2 + - c 6 r 7 1 clc451 7 6 8 5 3 4 2 1k w 1k w
http://www.national.com 10 figure 1 1: power derating curve layout considerations a proper printed circuit layout is essential for achieving high frequency performance. comlinear provides evaluation boards for the clc451 (clc730013-dip , clc730027-soic, clc730068-sot) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. general layout and supply bypassing play major roles in high frequency performance. follow the steps below as a basis for high frequency layout: n include 6.8 m f tantalum and 0.1 m f ceramic capacitors on both supplies. n place the 6.8 m f capacitors within 0.75 inches of the power pins. n place the 0.1 m f capacitors less than 0.1 inches from the power pins. n remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. n minimize all trace lengths to reduce series inductances. n use flush-mount printed circuit board pins for prototyping, never use high profile dip sockets. evaluation board information data sheets are available for the clc730013/ clc730027 and c lc730068 evaluation boards. the evaluation board data sheets provide: n evaluation board schematics n evaluation board layouts n general information about the boards the clc730013/clc730027 data sheet also contains tables of recommended components to evaluate several of comlinear s high speed amplifiers. this table for the clc451 is illustrated below . refer to the evaluation board data sheet for schematics and further information. components needed to evaluate the clc451 on the evaluation board: n r in , r out - typically 50 w (refer to the basic operation section of the evaluation board data sheet for details) n r t - optional resistor for inverting gain configura- tions (select r t to yield desired input impedance = r g || r t ) n c 1 , c 2 - 0.1 m f ceramic capacitors n c 3 , c 4 - 6.8 m f tantalum capacitors components not used: n c 5 , c 6 , c 7 , c 8 n r 1 thru r 8 the evaluation boards are designed to accommodate dual supplies. the boards can be modified to provide single supply operation. for best performance; 1) do not connect the unused supply , 2) ground the unused supply pin. special evaluation board considerations for the clc451 t o optimize of f-isolation of the clc451, cut the r f trace on both the clc730013 and the clc730027 evaluation boards. this cut minimizes capacitive feedthrough between the input and the output. figure 12 shows where to cut both evaluation boards for improved of f-isolation. figure 12: evaluation board changes spice models spice models provide a means to evaluate amplifier designs. free spice models are available for comlinear s monolithic amplifiers that: n support berkeley spice 2g and its many derivatives n reproduce typical dc, ac, t ransient, and noise performance n support room temperature simulations the readme file that accompanies the diskette lists released models, and provides a list of modeled parame - ters. the application note oa-18, simulation spice models for comlinear s op amps, contains schematics and a reproduction of the readme file. single supply cable driver the typical application shown on the front page shows the clc451 driving 10m of 75 w coaxial cable. the clc451 is set for a gain of +2v/v to compensate for the divide-by-two voltage drop at v o . application circuits 730013 rev c cut trace here 407 fig4 (left) r6 r3 r1 r7 r8 r5 c3 r2 r4 c4 rout out c6 c2 c1 c5 c8 in rin rg rf c7 -v cc +v cc gnd comlinear a national semiconductor company (303) 226-0500 + + 407 fig 3 (right) cut trace here power (w) ambient temperature ( c) 450 fig8 0 0.2 0.4 0.6 0.8 1.0 -40 -20 0 20 40 60 80 100 120 180 ajp aje sot 140 160
11 http://www.national.com t wisted pair driver the high output current and low distortion, of the clc451, make it well suited for driving transformers. figure 13 illustrates a typical twisted pair driver utilizing the clc451 and a transformer . the transformer provides the signal and its inversion for the twisted pair . figure 13: t wisted pair driver t o match the line s characteristic impedance (z o ) set: n r l = z o n r m = r eq where r eq is the transformed value of the load imped - ance, (r l ), and is approximated by: select the transformer so that it loads the line with a value close to z o , over the desired frequency range. the output impedance, r o , of the clc451 varies with frequency and can also af fect the return loss. the return loss, shown below , takes into account an ideal transformer and the value of r o . the load current (i l ) and voltage (v o ) are related to the clc451 s maximum output voltage and current by: from the above current relationship, it is obvious that an amplifier with high output drive capability is required. r r n eq l 2 = return loss(db) 20log n r z 10 2 o o ? - v n v i i n o max l max 451 fig13 + v o - r m r l z o utp i l r eq 1:n v = a v v in v n 4 a v v in = v -n 4 a v v in = v 1n 2 a v o v in = v in r t 1 clc451 7 6 8 5 3 4 2 1k w 1k w 0.1 m f 6.8 m f + v ee a v = 2
comlinear clc451, single supply , low-power , high output, programmable buffer http://www.national.com 12 lit #150451-001 customer design applications support national semiconductor is committed to design excellence. for sales, literature and technical support, call the national semiconductor customer response group at 1-800-272-9959 or fax 1-800-737-7018 . life support policy national s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, a) are intended for surgical implant into the body , or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user . 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to af fect its safety or ef fectiveness. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: (+49) 0-180-530 85 86 13th floor, straight block tel: 81-043-299-2309 arlington, tx 76017 e-mail: europe.support.nsc.com ocean centre, 5 canton road fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch t el: (+49) 0-180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english t el: (+49) 0-180-532 78 32 hong kong francais t el: (+49) 0-180-532 93 58 tel: (852) 2737-1600 italiano t el: (+49) 0-180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. n

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