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product specification main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 1 of 12 february 27th 2001 12-bit 20msps sampling analog-to-digital converter ip core tsmc 0.35 m 2p3m features 2.8-3.6v power supply sinad typ. 59db for ( f in =5mhz) very low power (70mw@3.0v) sample rate: > 20msps internal sample/hold differential input low input capacitance applications imaging test equipment computer scanners communications set top boxes general description the nad1220 is a compact, high-speed, very low power 12-bit monolithic analog-to- digital converter, implemented in a 0.35 m m cmos process. it has 12-bit resolution with close to 10 effective bits, and more than 10 bit dynamic range for video signals. the converter includes sample and hold. the full-scale range can be set between 0.6v and 1.7v using external references. it operates from a single 2.8-3.6v supply - compatible with modern digital systems. most converters in this performance range demand at least a +5v supply. its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. the conversion rate can be increased to 40mhz while keeping sinad higher than 50db. an evaluation kit is available, see ordering information below. quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 2.8 3.3 3.6 v p d power dissipation ex. references 76 mw dnl differential nonlinearity f in =0.9991mhz 0.4 lsb (10bit) differential nonlinearity f in =0.9991mhz 1 lsb (12bit) inl integral nonlinearity f in =0.9991mhz 1 lsb (10bit) integral nonlinearity f in =0.9991mhz 3 lsb (12it) f s conversion rate 20 mhz n resolution 12 bit table 1. quick reference data ordering information type number name description version nad1220-core core nad1220 hard-core; layout available in 0.35 m mcmos c-1 nad1220-kit kit nad1220 evaluation kit with the nad1220 on board k-1 table 2. ordering information nad1220
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 2 of 12 february 27th 2001 general description (continued) the nad1220 has a pipelined architecture - resulting in low input capacitance. digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching nyquist. the excellent linearity at the color subcarrier frequency makes the converter ideally suited for video. it is also well suited for demanding ultrasonic imaging and flow measurements. the nad1220 is very compact - occupying less than 3.2mm 2 of die area in a standard dual poly 0.35 m m cmos process. the fully differential architecture makes it insensitive to substrate noise. thus it is ideal as a mixed signal asic macro cell. the modular architecture of the converter and the flexible external biasing scheme means that scaling in number of bits and sampling rate is easily achieved. power consumption is roughly proportional to the number of bits and to the maximum sampling rate. thus, nad1220 is an excellent choice as the core of a product family of very low power high speed converters with resolutions ranging from 8 - 12 bits and sampling rates ranging from 1-40mhz. block diagram bgref stage3 stage10 stage_last (2-bit flash) digital delays, error correction and output register clockdr bit<11..0> refp refn inp inn clock biascell cm or refbuff refbuff bias1 bias0 extref stage2 stage1 bgap figure 1. block diagram nad1220
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 3 of 12 february 27th 2001 electrical specifications ( at t a =25 c, v dd = 3.3v, sampling rate = 20mhz, differential input, input frequency = 4.4995mhz with a 50% duty cycle clock unless otherwise noted ) symbol parameter (condition) test level min. typ. max. units dc accuracy dnl differential nonlinearity f in = 0.9991 mhz vi 0.4 lsb (10 bit) 0.6 lsb (12bit) inl integral nonlinearity f in = 0.9991 mhz vi 1.0 lsb (10 bit) 3.0 lsb (12bit) no missing codes vi guaranteed (12 bit) v os midscale offset v 1 % fsr cmrr common mode rejection ratio v 55 db e g gain error v 0.3 % fsr dynamic performance sinad signal to noise and distortion ratio f in =5mhz vi 55 59 db f in =10 mhz v 54 db snr signal to noise ratio (without harmonics) f in =5mhz vi 57 60 db f in =10mhz v 56 db sfdr spurious free dynamic range f in =5mhz vi 60 65 db f in =10mhz v 59 db dp differential phase v 0.2 degrees dg differential gain v 0.5 % psrr power supply rejection ratio v 63 db analog input v fsr input voltage range (differential) iv 0.6 1 1.7 v v cmi common mode input voltage iv 1.2 1.65 1.9 v c ina input capacitance (from each i nput to ground) v1.4pf reference voltages v refno negative input voltage iv 1.15 v v refpo positive input voltage iv 2.15 v v refp -v refn reference input voltage range iv 0.6 1.0 1.7 v v cm common mode output voltage (i o =-1 m a) vi 1.31.651.8 v digital inputs v il logic 0 voltage vi 20% v dd v ih logic 1 voltage vi 80% v dd i il logic 0 current (v i =v ss )vi 1 m a i ih logic 1 current (v i =v dd )vi 1 m a c ind input capacitance v 1.8 pf digital outputs v ol logic 0 voltage (i = + 2 ma) vi 0.1 0.4 v v oh logic 1 voltage (i = - 2 ma) vi 85% v dd 95% v dd v t h output hold time iv 6 ns t d output delay time iv 4 8 12 ns (table continued on next page)
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 4 of 12 february 27th 2001 switching performance f s conversion rate vi 20 tbd msps pipeline delay (see timing diagram) iv 7.5 clocks s ap aperture jitter v 10 ps t ap aperture delay v 5 ns power supply v dd supply voltage iv 2.8 3.3 3.6 v i dd supply current 1) vi 24 30 ma i dd supply current ( sleep mode, extref "0") vi 6.6 ma i dd supply current ( sleep mode, extref "1") vi 1.8 ma v ss supply voltage gnd av dd - dv dd1 analog power - digital power pins v -0.2 +0.2 v dv dd1 - dv dd2 digital power - output driver power v -0.2 +0.2 v p d power dissipation vi 79 100 mw table 3. electrical specifications 1) power down ("zero") power consumption available for ip core. test levels test level i: 100% production tested at +25c test level ii: 100% production tested at +25c and sample tested at specified temperatures test level iii: sample tested only test level iv: parameter is guaranteed by design and characterization testing test level v: parameter is typical value only test level vi: 100% production tested at +25c. guaranteed by design and characterization testing for industrial temterature range absolute maximum ratings supply voltages av dd ...............................- 0.5v to +6v dv dd1 ..................- 0.5v to v dd + 0.5v dv dd2 ..................- 0.5v to v dd + 0.5v input voltages analog in.......... - 0.5v to av dd + 0.5v digital in..............- 0.5v to v dd + 0.5v ref p ................. - 0.5v to av dd + 0.5v ref n ................. - 0.5v to av dd + 0.5v clock ...............- 0.5v to v dd + 0.5v temperatures operating temperature.-55 cto+95 c storage temperature..- 65 c to +125 c note: stress above one or more of the limiting values may cause permanent damage to the device.
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 5 of 12 february 27th 2001 pin functions pin name description in p in n differential input signal pins. common mode voltage: 1.65v ref p ref n reference pins. bypass with 100nf capacitors close to the pins. see application information below. extref digital input: reference select. extref=1: internal reference powered down, use external reference extref=0: internal reference is used bias0, bias1 digital inputs for max. sampling rate programming. bias1=0, bias0=0: sleep mode (power save) bias1=0, bias0=1: max. 5mhz sampling bias1=1, bias0=0: max. 20mhz sampling bias1=1, bias0=1: max. 30mhz sampling clock clock input cm common mode voltage output. bit11 - bit0 digital outputs ( msb to lsb) bgap band gap reference input / output voltage, nominally 2.413v qi, s scan inputs. connect to ground. av dd analog power pins. should be connected to v dd dv dd1 digital power pins. should be connected to v dd dv dd2 power pins for output drivers. should be connected to v dd table 4. pin functions. pin assignment 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 dv dd2 bit0 (lsb) bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 nc extref bgap v ss bias0 bias1 cm v ss in p in n v ss v ss v ss v ss v ss v ss v ss v ss qi s bit11 bit10 ref p ref n av dd av dd av dd dv dd1 dv dd1 dv dd2 v ss clock v ss 11 10 9 8 7654 3 21 23 24 25 26 27 28 29 30 31 32 33 figure 2. pin assignment nad1220 44 pin qfp
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 6 of 12 february 27th 2001 timing diagram data clock analog input s a mn-1 p l e s a mn+1 p l e s a mn p l e data n data n-1 data n+1 t d 8 ns t ap 2 ns s a mn+2 p l e t h 6 ns figure 3. timing diagram package outline figure 5. package outline all dimensions are in inches and paranthetically in millimeters.
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 7 of 12 february 27th 2001 definitions data sheet status objective product specification this datasheet contains target specifications for product development. preliminary product specification this datasheet contains preliminary data; supplementary data may be published from nordic vlsi asa later. product specification this datasheet contains final product specifications. limiting values stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. table 5. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. nordic vlsi asa customers using or selling these products for use in such applications do so at their own risk and agree fully indemnify nordic vlsi asa for any damages resulting from such improper use or sale.
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 8 of 12 february 27th 2001 application information references the nad1220 has a differential analog input. the input range is determined by the voltages v p and v n applied to reference pins ref p and ref n respectively, and is equal to (v p -v n ). externally generated reference voltages connected to ref p and ref n should be symmetric around 1.5v. the input range can be defined between 0.6v and 1.5v. internal reference buffers exists C providing reference voltages at pins ref p and ref n equal to +2.00v (vref p ) and +1.00v (vref n ). these can be connected to ref p and ref n by connecting pin extref to vss. the references should be bypassed as close to the converter pins as possible using 100nf capacitors in parallel with smaller capacitors (e.g. 220pf) (to ground). series resistance from ip reference pins to pad window should be in the range 1 - 5 ohms. analog input the input of the nad1220 can be configured in various ways - dependent upon whether a single ended or differential, ac- or dc-coupled input is wanted. ac-coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. the center tap is connected to the cm-node, as shown in figure 1. in order to obtain low distortion, it is important that the selected transformer does not exhibit core saturation at full-scale. excellent results are obtained with the mini circuits t1-6t or t1-1t. proper termination of the input is important for input signal purity. a small capacitor (typ. 68pf) across the inputs attenuates kickback- noise from the sample and hold. a small capacitor (1nf) between cm and ground has also been proven to be advantageous. 68pf inp inn cm mini circuits t1-6t v in adc 51 w figure 6. ac coupled input using transformer if a dc-coupled single ended input is wanted, a solution based on operational amplifiers - as shown in figure 7, is usually preferred. the ad826 is suggested for low distortion and video bandwidth. lower cost operational amplifiers may be used if the demands are less strict.
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 9 of 12 february 27th 2001 ad826 ad826 51 w 51 w 470 w 470 w 100 w 100 w 470 w 470 w ad826 51 w in p in n 51 w 470 w input offset video in adc 15pf figure 7. dc-coupled single ended to differential conversion (power supplies and bypassing not shown) clock the nad1220 accepts a cmos logic level clock at the clk-node. the duty cycle of the clock should be close to 50%. consecutive pipeline stages in the adc are clocked in antiphase. with a 50% duty cycle, every stage has the same time for settling. if the duty cycle deviates from 50%, every second stage has a shorter time for settling - thus it operates less accurately, potentially causing degradation of snr. in order to preserve accuracy at high input frequency, it is important that the clock has low jitter and steep edges. rise/fall times should be kept shorter than 2ns whenever possible. overshoot should be avoided. low jitter is especially important when converting high frequency input signals. jitter causes the noise floor to rise proportionally to input signal frequency. jitter may be caused by crosstalk on the pcb. it is therefore recommended that the clock trace on the pcb is made as short as possible. digital outputs the digital output data appears in offset binary code at cmos logic levels. full-scale negative input results in output code 000...0. full-scale positive input results in output code 111...1. output data are available 7.5 clock cycles after the data are sampled. the analog input is sampled one aperture delay (t ap ) after the high to low clock transition. output data should be sampled on the low to high clock transition, as shown in the timing diagram. output data are invalid for the first 20 clock cycles after wake-up from power down mode.
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 10 of 12 february 27th 2001 pcb layout and decoupling a well designed pcb is necessary to get good spectral purity from any high performance adc. a multilayer pcb with a solid ground plane is recommended for optimum performance. if the system has a split analog and digital ground plane, it is recommended that all ground pins on the adc are connected to the analog ground plane. it is our experience that this gives the best performance. the power supply pins should be bypassed using 100nf surface mounted capacitors as close to the package pins as possible. analog and digital supply pins should be separately filtered. one should make sure that the analog and digital supply voltages are equal. dynamic testing careful testing using high quality instrumentation is necessary to achieve accurate test results on high speed a/d-converters. it is important that the clock source and signal source has low jitter. a spectrally pure, low noise rf signal generator - such as the hp8662a or hp 8644b is recommended for the test signal. low pass filtering or band pass filtering of the input signal is usually necessary to obtain the required spectral purity (sfdr > 75db). the clock signal can be obtained from either a crystal oscillator or a low-jitter pulse generator. alternatively, a low-jitter rf-generator can be used as a clock source. at nordic vlsi, the marconi instruments 2041a is used. the sinewave clock must then be applied to an ultra high speed comparator (e.g. ad9696) and a ttl to cmos level shifter (e.g. 74lv04) before application to the converter. the most consistent results are obtained if the clock signal is phase locked to the input signal. phase locking allows testing without windowing of output data. a logic analyzer with deep memory - such as the hp16500-series, is recommended for test data acquisition.
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 11 of 12 february 27th 2001 your notes
product specification nad1220 12-bit 20msps sampling adc main office: nordic vlsi asa - vestre rosten 81, n-7075 tiller, norway - phone +4772898900 - fax +4772898989 branch office: nordic vlsi asa - p.o.box 436 sk?yen, n-0212 oslo, norway - phone +4722511050 - fax +4722511099 revision: 3.3 page 12 of 12 february 27th 2001 design center main office: nordic vlsi asa vestre rosten 81 n-7075 tiller norway telephone: +47 72898900 telefax: +47 72898989 branch office: nordic vlsi asa drammensveien 165 p.o.box 436 sk?yen, n-0212 oslo norway telephone: +47 22511050 telefax: +47 22511099 e-mail: for further information regarding datasheets, please send mail to datasheet@nvlsi.no world wide web/internet: visit our site at http://www.nvlsi.no product specification. revision date: february 27 th , 2001 all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. company and product names referred to in this datasheet belong to their respective copyright/trademark holders.

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