preliminary ? 1999 fairchild semiconductor corporation ds012018 www.fairchildsemi.com november 1999 revised november 1999 74lvth652 low voltage octal transceiver/register with 3-state outputs (preliminary) 74lvth652 low voltage octal transceiver/register with 3-state outputs (preliminary) general description the lvth652 consists of bus transceiver circuits with d- type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. data on the a or b bus will be clocked into the registers as the appropriate clock pin goes to high logic level. output enable pins (oeab, oeba ) are pro- vided to control the transceiver function. (see functional description). the lvth652 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. this bus/octal buffer and line driver is designed for low- voltage (3.3v) v cc applications, but with the capability to provide a ttl interface to a 5v environment. the lvth652 is fabricated with an advanced bicmos technology to achieve high speed operation similar to 5v abt while maintaining low power dissipation. features input and output interface capability to systems at 5v v cc bushold data inputs eliminate the need for external pull- up resistors to hold unused inputs live insertion/extraction permitted power up/down high impedance provides glitch-free bus loading outputs source/sink ? 32 ma/ + 64 ma functionally compatible with the 74 series 652 latch-up performance exceeds 500 ma ordering code: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. logic symbols ieee/iec order number package number package description 74lvth652wm m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 ? wide 74lvth652mtc mtc24 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide
preliminary www.fairchildsemi.com 2 74lvth652 pin descriptions connection diagram truth table (note 1) h = high voltage level l = low voltage level x = immaterial n = low to high clock transition note 1: the data output functions may be enabled or disabled by various signals at oeab or oeba inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. pin names description a 0 ? a 7 data register a inputs/ 3-state outputs b 0 ? b 7 data register b inputs/ 3-state outputs cpab, cpba clock pulse inputs sab, sba select inputs oeab, oeba output enable inputs inputs inputs/outputs operating mode oeab oeba cpab cpba sab sba a 0 thru a 7 b 0 thru b 7 l h h or l h or l x x input input isolation l h n n x x store a and b data x h n h or l x x input not specified store a, hold b h h n n x x input output store a in both registers l x h or l n x x not specified input hold a, store b l l n n x x output input store b in both registers l l x x x l output input real-time b data to a bus l l x h or l x h store b data to a bus h h x x l x input output real-time a data to b bus h h h or l x h x stored a data to b bus h l h or l h or l h h output output stored a data to b bus and stored b data to a bus
preliminary 3 www.fairchildsemi.com 74lvth652 functional description in the transceiver mode, data present at the high imped- ance port may be stored in either the a or b register or both. the select (sab, sba) controls can multiplex stored and real-time. the examples below demonstrate the four fundamental bus-management functions that can be performed with the lvth652. data on the a or b data bus, or both can be stored in the internal d-type flip-flop by low-to-high transitions at the appropriate clock inputs (cpab, cpba) regardless of the select or output enable inputs. when sab and sba are in the real time transfer mode, it is also possible to store data without using the internal d-type flip-flops by simulta- neously enabling oeab and oeba . in this configuration each output reinforces its input. thus when all other data sources to the two sets of bus lines are in a high imped- ance state, each set of bus lines will remain at its last state. real-time transfer bus b to bus a storage real-time transfer bus a to bus b transfer storage data to a or b oeab oeba cpab cpba sab sba l lxxxl oeab oeba cpab cpba sab sba xhnxxx lxxnxx lhnnxx oeab oeba cpab cpba sab sba hhxx l x oeab oeba cpab cpba sab sba h l h or l h or l h h
preliminary www.fairchildsemi.com 4 74lvth652 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum rated conditions is not implied. note 3: i o absolute maximum rating must be observed. symbol parameter value conditions units v cc supply voltage ? 0.5 to + 4.6 v v i dc input voltage ? 0.5 to + 7.0 v v o dc output voltage ? 0.5 to + 7.0 output in 3-state v ? 0.5 to + 7.0 output in high or low state (note 3) i ik dc input diode current ? 50 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma i o dc output current 64 v o > v cc output at high state ma 128 v o > v cc output at low state i cc dc supply current per supply pin 64 ma i gnd dc ground current per ground pin 128 ma t stg storage temperature ? 65 to + 150 c symbol parameter min max units v cc supply voltage 2.7 3.6 v v i input voltage 0 5.5 v i oh high level output current ? 32 ma i ol low level output current 64 ma t a free-air operating temperature ? 40 85 c ? t/ ? v input edge rate, v in = 0.8v ? 2.0v, v cc = 3.0v 0 10 ns/v
preliminary 5 www.fairchildsemi.com 74lvth652 dc electrical characteristics note 4: an external driver must source at least the specified current to switch from low-to-high. note 5: an external driver must sink at least the specified current to switch from high-to-low. note 6: this is the increase in supply current for each input that is at the specified voltage level rather than v cc or gnd. dynamic switching characteristics (note 7) note 7: characterized in soic package. guaranteed parameter, but not tested. note 8: max number of outputs defined as (n). n ? 1 data inputs are driven 0v to 3v. output under test held low. symbol parameter v cc t a =? 40 c to + 85 c units conditions (v) min max v ik input clamp diode voltage 2.7 ? 1.2 v i i = ? 18 ma v ih input high voltage 2.7 ? 3.6 2.0 v v o 0.1v or v il input low voltage 2.7 ? 3.6 0.8 v o v cc ? 0.1v v oh output high voltage 2.7 ? 3.6 v cc ? 0.2 v i oh = ? 100 a 2.7 2.4 v i oh = ? 8 ma 3.0 2.0 v i oh = ? 32 ma v ol output low voltage 2.7 0.2 v i ol = 100 a 2.7 0.5 v i ol = 24 ma 3.0 0.4 v i ol = 16 ma 3.0 0.5 v i ol = 32 ma 3.0 0.55 v i ol = 64 ma i i(hold) bushold input minimum drive 3.0 75 av i = 0.8v ? 75 av i = 2.0v i i(od) bushold input over-drive 3.0 500 a (note 4) current to change state ? 500 a (note 5) i i input current 3.6 10 av i = 5.5v control pins 3.6 1 av i = 0v or v cc data pins 3.6 ? 5 av i = 0v 1 av i = v cc i off power off leakage current 0 100 a0v v i or v o 5.5v i pu/pd power up/down 3-state 0 ? 1.5v 100 a v o = 0.5v to 3.0v output current v i = gnd or v cc i ozl 3-state output leakage current 3.6 ? 5 av o = 0.0v i ozh 3-state output leakage current 3.6 5 av o = 3.6v i ozh + 3-state output leakage current 3.6 10 av cc < v o 5.5v i cch power supply current 3.6 0.19 ma outputs high i ccl power supply current 3.6 5 ma outputs low i ccz power supply current 3.6 0.19 ma outputs disabled i ccz + power supply current 3.6 0.19 ma v cc v o 5.5v outputs disabled ? i cc increase in power supply current 3.6 0.2 ma one input at v cc ? 0.6v (note 6) other inputs at v cc or gnd symbol parameter v cc t a = 25 c units conditions (v) min typ max c l = 50 pf, r l = 500 ? v olp quiet output maximum dynamic v ol 3.3 0.8 v (note 8) v olv quiet output minimum dynamic v ol 3.3 ? 0.8 v (note 8)
preliminary www.fairchildsemi.com 6 74lvth652 ac electrical characteristics capacitance (note 9) note 9: capacitance is measured at frequency f = 1 mhz, per mil-std-883b, method 3012. symbol parameter t a = ? 40 c to + 85 c units c l = 50 pf, r l = 500 ? v cc = 3.3v 0.3v v cc = 2.7v min max min max f max maximum clock frequency 150 150 mhz t plh propagation delay data to output 1.8 4.7 1.8 5.6 ns t phl clock to a or b 1.8 4.7 1.8 5.6 t plh propagation delay data to output 1.3 3.5 1.3 4.1 ns t phl data to a or b 1.3 3.5 1.3 4.1 t plh propagation delay data to output 1.5 4.9 1.5 6.0 ns t phl sba or sab to a or b 1.5 4.9 1.5 6.0 t pzh output enable time 1.1 5.2 1.1 6.5 ns t pzl oe to a or b 1.1 5.2 1.1 6.5 t phz output disable time 2.3 5.5 2.3 6.1 ns t plz oe to a or b 2.3 5.5 2.3 5.9 t pzh output enable time 1.3 4.7 1.3 5.7 ns t pzl oe to a or b 1.3 4.7 1.3 5.7 t phz output disable time 1.5 5.6 1.5 6.7 ns t plz oe to a or b 1.5 5.6 1.5 6.3 t w pulse duration clock high or low 3.3 3.3 ns t s setup time data high or low before cp 1.2 1.5 ns clr high before cp 1.6 2.2 t h hold time data high or low after cp 0.8 0.8 ns symbol parameter conditions typical units c in input capacitance v cc = 0v, v i = 0v or v cc 4pf c i/o input/output capacitance v cc = 3.0v, v o = 0v or v cc 8pf
preliminary 7 www.fairchildsemi.com 74lvth652 physical dimensions inches (millimeters) unless otherwise noted 24-lead (0.300? wide) molded small outline package, soic jedec package number m24b
preliminary www.fairchildsemi.com 8 74lvth652 low voltage octal transceiver/register with 3-state outputs (preliminary) physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead molded small outline package, tssop jedec package number mtc24 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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