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lnk454/456-458/460 linkswitch-pl family www.powerint.com november 2010 led driver ic with triac dimming, single-stage pfc and constant current control for non-isolated applications ? output power table product 2 85-265 vac minimum output power maximum output power 1 lnk454d 1.5 w 3 w lnk456d 3 w 6 w lnk457d/k/v 4 w 8 w lnk458k/v 6 w 11.5 w lnk460k/v 8 w 16 w table 1. output power table. notes: 1. maximum practical continuous power in an open frame design with adequate heat sinking, measured at +50 c ambient (see key applications considerations for more information). 2. packages: d: so-8c, k: esop-12, v: edip-12. output current number of serial leds 350 ma 500 ma 700 ma 1000 ma 1 lnk454 lnk454 lnk454 lnk456 2 lnk454 lnk456 lnk456 lnk457 3 lnk456 lnk456 lnk457 lnk458 4 lnk456 lnk457 lnk458 lnk460 5 lnk457 lnk458 lnk460 6 lnk457 lnk458 lnk460 7 lnk458 lnk460 8 lnk458 lnk460 9 lnk458 lnk460 10 lnk460 11 lnk460 12 lnk460 product highlights dramatically simplifes off-line led drivers ? flicker-free phase-controlled triac dimming ? single stage power factor correction and accurate constant current (cc) output ? very low component count with small non-electrolytic bulk capacitor for compact replacement lamp designs ? compact so8, esop, and edip packages ? completely eliminates control loop compensation advanced performance features ? optimized for non-isolated fyback designs ? frequency jitter greatly reduces emi flter size and costs ? low dissipation direct sensing of led current advanced protection and safety features ? cycle skipping regulation for abnormally low output power to clamp peak output current delivered ? 725 v integrated power mosfet allows small bulk capacitance and maximizes power capability ? short-circuit, overload, open feedback and output overvoltage protection ? hysteretic thermal shutdown ? meets high-voltage creepage between drain and all other pins both on pcb and at package ecosmart ? - energy effcient ? high power factor optimizes system lumen per input va ? control algorithm balances switching and conduction losses over line and load to maintain optimum effciency description the linkswitch-pl family enables a very small and low cost single-stage power factor corrected constant current driver for solid state lighting. optimized for direct led current sensing, the linkswitch-pl operates over a wide input voltage range delivering an output power of up to 16 w. the linkswitch-pl control algorithm provides ficker-free triac dimming with minimal external components. each device incorporates a 725 v rated power mosfet, a novel discontinuous mode variable frequency variable on-time controller, frequency jitter, cycle by cycle current limit and hysteretic thermal shutdown in a monolithic 4-pin ic, available in so-8c, esop-12, and edip-12 packages. figure 1. basic application schematic. figure 2. device selection based on length of output led series string and current. a typical voltage drop of 3.5 v per led is assumed. d s bp control fb pi-5835-060710 linkswitch-pl ac in
rev. a 11/01/10 2 lnk454/456-458/460 www.powerint.com figure 3. pin confguration (top view). figure 2. functional block diagram. pin functional description drain (d) pin: high-voltage power mosfet drain connection. the internal start-up bias current is drawn from this pin through a switched high-voltage current source. drain current sensing and associated controller functions are also performed using this pin. source (s) pin: power mosfet source connection. ground reference for bypass and feedback pins. bypass (bp) pin: connection point for the external bypass capacitor for the internally generated 5.85 v supply. feedback (fb) pin: led current sensing pin. during normal operation the 290 mv threshold determines the average value of the current fowing through the load sense resistor. a second threshold clamps excessive output current ripple. a third higher threshold is used to protect against output short-circuit and overvoltage conditions (see figure 5). pi-5893-091010 drain (d) source (s) bypass (bp) feedback (fb) v fb(lo) v fb(sk) zero crossing v_i lim i fb v_z lim 4.9 v i lim i lim uv soa uv update clk s q r q s q r q on-time extension auto-restart frequency/ duty cycle controller digital integrator inc/dec filter phase measurement regulator 5.85 v v ref dac set clr set clr + + + + + current limit soa state machine 1 a pi-5836a-092710 exposed pad internally connected to source pin 1 nc 2 fb 3 bp 4 nc 5 nc 6 d s 12 s 11 s 10 s 9 s 8 s 7 v package (edip-12) d package (so-8c) fb bp d 1 2 4 8 7 6 5 s s s s 12 s 11 s 10 s 9 s 8 s 7 s nc 1 fb 2 bp 3 nc 4 nc 5 d 6 k package (esop-12) exposed pad (on bottom) internally connected to source pin
rev. a 11/01/10 3 lnk454/456-458/460 www.powerint.com functional description the linkswitch-pl combines a high-voltage power mosfet switch with a power supply controller in one device. the ic provides a single stage power factor correction plus led current control. the linkswitch-pl controller consists of an oscillator, feedback (sense and logic) circuit, 5.85 v regulator, hysteretic over-temperature protection, frequency jittering, cycle-by-cycle current limit, loop compensation circuitry, auto- restart, switching on-time extension, power factor and constant current control. in a direct led current sensing confguration, the average feedback pin voltage is a replica of the led current, scaled by the sense resistor (r sense in figure 4). a small low-pass flter (r f and c f in figure 4) reduces high frequency noise at the feedback pin. figure 5 illustrates the operating regions of the feedback pin voltage. the linkswitch-pl sets its operating point such that the average feedback pin voltage in steady-state operation is 290 mv. this threshold is set low to minimize the sensing resistor dissipation. the internal mosfet switching frequency and on-time are updated once every input ac half-cycle to regulate the output current and maintain high power factor. if the feedback pin peak voltage exceeds 520 mv, cycle skipping mode is triggered and the power processed by the integrated power mosfet is clamped on a cycle-by-cycle basis. switching frequency may vary during an input voltage half-cycle to reduce thermal stress on the output leds. figure 4. typical application schematic. figure 5. feedback pin operational voltage thresholds. auto-restart protection is triggered by a feedback pin voltage in excess of 2 v. this feature can be used to provide output overvoltage protection (via dz ov and r ov , in figure 4), which triggers the ic to enter auto-restart. pi-5838-091010 auto-restart 2 v 520 mv cycle skipping mode normal operation 290 mv d s bp control fb pi-5837-060710 linkswitch-pl ac in c f r sense r f r ov dz ov r es d es
rev. a 11/01/10 4 lnk454/456-458/460 www.powerint.com triac (phase-controlled) dimming the linkswitch-pl integrates several features to improve dimming range and reduce external circuit complexity when using a phase-controlled triac dimmer. the output led current is controlled by the feedback pin voltage which changes proportionally to the triac dimmer conduction angle. when the conduction angle decreases, the voltage at the feedback pin decreases causing the average led current to decrease. the feedback pin reference voltage adjustment is initiated at approxi-mately 25% of the ac line half-cycle duration. when this ( j os) threshold is exceeded, v fb and the output led current are reduced until a second phase angle threshold is reached. at this point, with the triac conduction angle being very limited, the ic runs open loop at constant frequency and duty cycle ( j ol region) and the integrated power mosfet processes as much power as the heavily chopped input voltage will allow creating a light output that is deeply dimmed. the 520 mv clamping feedback threshold is also linearly reduced during dimming to control led current ripple. figure 6. feedback voltage vs. phase angle dimming characteristics. v fb( ? ) v fb( ? ) v fb ? ol ? ? 180 0 v line phase angle phase angle conduction angle conduction angle leading edge triac dimmers trailing edge dimmers v triac 180 0 0 0 pi-5894a-091010 ? os ? ol ? os phase angle phase angle phase angle phase angle
rev. a 11/01/10 5 lnk454/456-458/460 www.powerint.com ic supply and bypass pin the internal 5.85 v regulator charges the bypass capacitor connected to the bypass pin to 5.85 v by drawing current from the voltage on the drain pin whenever the power mosfet is off. the bypass pin is the internal supply voltage node. when the power mosfet is on, the device operates from the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows linkswitch-pl to operate continuously from current it takes from the drain pin. a bypass capacitor value of 1 f is suffcient for both high frequency decoupling and energy storage. dimming applications may require a higher bypass capacitor value. during phase angle dimming when the conduction angle is small the ac input voltage is present for only short periods of time. in that case the ic should not rely on the integrated high voltage current source, but instead external bias circuitry should be used to supply the ic from the output (d es and r es in figure 4). if the output voltage is less than 7 v, external bias circuitry should be implemented. this is accomplished by adding an auxiliary winding on the transformer, which is then rectifed and fltered via a diode (ultrafast) and capacitor. the winding voltage (turns) should be selected such that the maximum ic consumption can be supported at the lowest operating output current. start-up, switching frequency and on-time range at start-up the controller uses an initial switching frequency f min and minimum on-time t on(min) . the charging of the output capacitor together with the energy delivery to the output leds determines a step-by-step increase of the power mosfet switching frequency and on-time updated every half-cycle of the ac input voltage. the steady state switching frequency and on-time are determined by the line voltage, voltage drop across the leds and converter effciency. at light load when the device reaches the minimum frequency f min and on-time t on(min) , the controller regulates by skipping cycles. in this mode of operation the input current is not power factor corrected and the average output current is not guaranteed to fall within the normal range. the feedback pin cycle skipping threshold is reduced from approximately twice the normal regulation level down to just above the level required to limit output power delivery under these conditions. a properly designed supply will not operate in this mode under normal load conditions. a power supply designed correctly will operate within the switching frequency range [f min f max ], with an on-time falling between t on(min) and t on(max) when connected to a normal load. overload protection in case of overload, the system will increase the operating frequency and on-time each ac half-cycle until the maximum frequency and maximum on-time are reached. when this state is reached, the controller enters auto-restart protection, thus inhibiting the gate of the power mosfet for approximately 1.28 s if the main line frequency is 50 hz, 1.02 s if it is 60 hz. after this auto-restart off-time expires, the power mosfet is re-enabled and a normal start-up is initiated, i.e. at f min and t on(min) , stepping up until regulation is achieved again. in case of a persistent overload condition, the auto-restart duty cycle dc ar is ~33%. overload protection is inhibited during phase dimming when the triac conduction duty cycle is less than 60%. output overvoltage protection if a no-load condition is present on the output of the supply, the output overvoltage zener (dz ov in figure 4) will conduct once its threshold is reached. a voltage v ov in excess of v fb(ar) = 2 v will appear across the feedback pin and the ic will enter auto- restart. output short-circuit if the output of the supply (i.e. the led load) is short-circuited, then a large amount of energy will be delivered to the sense resistor, generating a high voltage at the feedback pin. if this condition develops more than 2 v on the feedback pin, then the ic will interpret this event as an output short-circuit and will enter auto-restart. safe operating area (soa) protection if 3 consecutive cycles of the power mosfet are prematurely terminated due to the power mosfet current exceeding the current limit after the leading edge blanking time, soa protection mode is triggered and the ic will enter auto-restart. hysteretic thermal shutdown the thermal shutdown circuitry senses the die junction temperature. the thermal shutdown threshold is set to 142 c typical with a 75 c hysteresis. when the die temperature rises above this threshold (142 c) the power mosfet is disabled and remains disabled until the die temperature falls by 75 c, at which point the power mosfet is re-enabled.
rev. a 11/01/10 6 lnk454/456-458/460 www.powerint.com linkswitch-pl application example the circuit shown in figure 7 provides a single constant current output of 350 ma with an led string voltage of 15 v. the output current can be reduced using a standard ac mains triac dimmer down to 1% (3 ma) without instability and fickering of the led load. the board is compatible with both low cost leading edge and more sophisticated trailing edge dimmers. the board was optimized to operate over the universal ac input voltage range (85 vac to 265 vac, 47 hz to 63 hz) but suffers no damage over an input range of 0 vac to 300 vac. this increases feld reliability and lifetime during line sags and swells. linkswitch-pl based designs provide high power factor (>0.9 at 115 vac / 230 vac) and low thd (<15% at 230 vac, <10% at 115 vac) enabling compliance to all current international requirements and enabling a single design to be used worldwide. the form factor of the board was chosen to meet the requirements for standard pear shaped (a19) led replacement lamps. the output is non-isolated and requires the mechanical design of the enclosure to isolate both the supply and the led load from the user. pi part selection one device size larger than required was selected to increase effciency and reduce device thermal rise. this typically gives the highest effciency. further increasing the device size often results in the same or lower effciency due to the larger switching losses associated with a larger power mosfet. ac line triac dimmer interface circuits the requirement to provide output dimming with low cost, triac based, leading edge phase dimmers introduces a number of trade-offs in the design. due to the much lower power consumed by led lighting compared to incandescent lighting, the current drawn by the lamp is below the holding current of the triac dimmer. this causes undesirable behavior such as limited dimming range and/or fickering. inrush current that fows to charge the input capacitance when the triac turns on causes current ringing. this too can cause similar undesirable behavior as the ringing may cause the triac current to fall to zero and turn off for the remainder of the ac cycle or rapidly turn on and off. to overcome these issues the design includes three circuit blocks, a passive damper, an active damper and a bleeder. the drawback of these blocks is increased power dissipation and therefore reduced effciency of the supply. in this design, the values selected allow ficker-free operation with a single lamp connected to a single dimmer at high line. for ficker-free operation with multiple lamps in parallel or at low line voltages only (100/115 vac) then the values may be optimized to reduce dissipation and increase effciency. as these blocks are only required for dimming applications, for non-dimming designs these components can simply be omitted with jumpers used to replace r7, r8 and r20. active and passive damper circuits resistor r20 forms a passive damper that together with the active damper limits the peak inrush current when the triac fres on each half cycle. it should be a fameproof type to safely fail during a single point fault (e.g. failure of a bridge diode). the active damper circuit connects a series resistance (r7 and r8) with the input rectifer for a period of each ac half-cycle, it is then bypassed for the remainder of the ac cycle by a parallel scr (q3). resistor r3, r4 and c3 determines the delay before the turn-on of q3 which then shorts out the damper resistors r7 and r8. r3 750 k r4 750 k r9 4.7 k l2 2.2 mh pi-6171a-102910 d s bp control 7 t1 ee16 1 2 3 6 r10 510 f1 3.15 a rv1 275 vac r20 47 r2 4.7 k r11 510 r13 4.7 r12 100 k r16 10 k 15 v, 350 ma 90 - 265 vac rtn l n r18 0.82 1% r17 27 r15 3.3 k r14 1 k r21 1 k d2 us1j d4 bav19ws passive damper active damper bleeder vr2 mazs2000ml 20 v d5 ss110-tp d6 dl4006 br1 mb6s 600 v c10 1 nf 100 v c11 680 f 25 v c8 10 nf 50 v c9 1 f 25 v linkswitch-pl u1 lnk457dg c6 68 nf 400 v c7 1000 pf 630 v c5 68 nf 400 v c4 22 nf 630 v l1 2.2 mh fb r7 240 c3 22 nf 50 v r8 240 q3 figure 7. schematic of a 5 w, 15 v led driver for a19 incandescent lamp replacement.
rev. a 11/01/10 7 lnk454/456-458/460 www.powerint.com bleeder circuit resistor r10, r11 and c6 form a bleeder network which ensures the initial input current is high enough meet the triac holding current requirement, especially during small conduction angles. for non-dimming application r10, r11 and c6 may be omitted. input rectifer and emi filter emi fltering is provided by l1 and a pi () flter formed by c4, l2 and c5. resistors r2 and r9 dampen the self resonances of the flter stages and reduce the resultant peaks in the conducted emi spectrum. as shown the design meets en55015 conducted limits with >20 db margin. the incoming ac is rectifed by br1 and fltered by c4 and c5. the total effective input capacitance, the sum of c4 and c5, was selected to ensure correct zero crossing detection of the ac input by the linkswitch-pl device, necessary for correct dimming operation. primary components the lnk457dg device (u1) incorporates the power switching device, oscillator, cc control engine, startup, and protection functions. the integrated 725 v power mosfet provides extended design margin, improving robustness during line surge events even in high line applications. the device is powered from the bypass pin via the decoupling capacitor c9. at start-up, c9 is charged by u1 from an internal current source via the drain pin and then during normal operation it is supplied by the output via r15 and d4. for non-dimming designs d4 and r15 may be omitted. the rectifed and fltered input voltage is applied to one end of the primary winding of t1. the other side of the transformers primary winding is driven by the integrated power mosfet in u1. the leakage inductance drain voltage spike is limited by an rcd-r clamp consisting of d2, r13, r12, and c7. diode d6 is used to protect the ic from negative ringing (drain voltage below source voltage) when the power mosfet is off and the input voltage is below the refected output voltage (v or ). output rectifcation the secondary of the transformer is rectifed by d5, a schottky barrier type for higher effciency, and fltered by c11. resistor r17 and c10 damp high frequency ringing and improve conducted and radiated emi. output feedback the cc mode set-point is determined by the voltage drop that appears across r18 which is then fed to the feedback pin of u1. output overvoltage protection is provided by vr2 and r21. application considerations input capacitor selection for correct operation during dimming, the linkswitch-pl device must detect line voltage zero crossing. this is sensed internally via the drain node at the point the dc bus falls to <19 v. the requirement for the dc bus to reach this level on each half-cycle limits the maximum capacitance on the dc side of the input bridge rectifer. typically the maximum capacitance value needed for high power factor also results in meeting the 19 v limit however during development, this should be verifed on an oscilloscope. if a reduction in capacitance is required and this results in increased conducted emi then capacitance may be added before the input rectifer which effectively isolates it from the bus capacitance. for applications intended for use with leading edge triac dimmers, flm capacitors are recommended as ceramic capacitors typically create audible noise. output capacitor selection output capacitance has a direct effect on the output load (led) ripple current. the larger the capacitance, the lower the ripple current. excessive capacitance can prevent the output reaching regulation within the auto-restart time and either cause failure to start or require several start-up attempts (hiccups). too little capacitance can cause the voltage of the feedback pin to exceed the cycle skipping mode threshold, degrading pf and causing output ficker while dimming. therefore the output capacitance value should be selected such that the ripple voltage across the output current sense resistor (r18 in figure 7) and fed into the feedback pin is within the range of 100 mvp-p v feedback 400 mvp-p with a target value of 290 mvp-p. the output capacitor type is not critical. non-electrolytic capacitors are attractive in terms of lifetime (ceramics and solid dielectric types do not have an electrolyte that evaporates over time) however electrolytic types offer the best volumetric effciency vs. cost. if multi-layer ceramics are selected, verify the data sheet curves of capacitance vs. applied voltage and temperature coeffcient. the typical capacitance value may be 50% lower across temperature and/or close to rated voltage. for all capacitor types verify the capacitor(s) selected are rated for the output ripple current. for electrolytic types, this requires selecting a low esr type. a temperature rating of 105 c or higher is recommended for long lifetime. for typical designs there is minimal self heating of the output capacitor and therefore lifetime is determined by the internal ambient temperature and broadly follows the arrhenius equation, i.e. lifetime doubles for every 10 c drop in operating temperature. for example the selection of a capacitor with a rated life of 5,000 hours at 105 c would have an expected lifetime of 40,000 hours at 75 c. end of life is typically defned for an electrolytic capacitor as a doubling of the esr and the capacitance reducing by 20%. this often has little impact to the performance seen by the end user and extends the ft for purpose lifetime. feedback pin signal during normal non-dimming (full power) operation, the feedback pin threshold voltage (the voltage developed across the current sense resistor) is 290 mv. for best output current regulation, between 100 mvp-p to 400 mvp-p of voltage ripple is recommended.
rev. a 11/01/10 8 lnk454/456-458/460 www.powerint.com this can be achieved through selecting the appropriate value of output capacitance and the value of the current sense resistor. if the peak of the ripple voltage exceeds 520 mv, the device will enter cycle skipping mode which will reduce pfc performance (lower pf and increase thd). transformer considerations for use with leading edge triac dimmers audible noise can be created in the transformer due to the abrupt change in fux when the triac turns on. this can be minimized by selecting cores with higher mechanical resonant frequencies. cores with long narrow legs should be avoided (e.g. eel types). rm and other pot core types are good choices and produce less audible noise than ee cores for the same fux density. reducing the core fux density (bm) also reduces audible noise generation. a value below 1500 gauss usually eliminates any noise generation but reduces the power capability of a given core size. working with triac dimmers the requirement to provide output dimming with low cost, triac based, leading edge phase dimmers introduces a number of trade-offs in the design. for correct operation incandescent phase angle dimmers typically have a specifed minimum load, typically ~40 w for a 230 vac rated unit. this is to ensure that the current through the internal triac stays above its specifed holding current threshold. due to the much lower power consumed by led lighting the input current drawn by the lamp is below the holding current of the triac within the dimmer. the input capacitance of the driver allows large inrush currents to fow when the triac fres. this then generates input current ringing with the input stage and line inductance which may cause the current to fall below the triac holding current. both of these mechanisms cause undesirable behavior such as limited dimming range and/or fickering. to overcome these issues two circuit blocks, damper and bleeder, are incorporated in dimming applications. the drawback of these circuits is increased dissipation and therefore reduced effciency of the supply. figure 8 shows the line voltage and current at the input of a leading edge triac dimmer. in this example, the triac conducts at 90 degrees. figure 9 shows the desired rectifed bus voltage and current. figure 10 shows undesired rectifed bus voltage and current with the triac turning off prematurely and restarting. on the frst half cycle this is due to the input current ringing below the holding current of the triac, excited by the initial inrush current. the second half cycle also shows the triac turning off due to the current falling below the holding current towards the end of the conduction angle. this difference in behavior on alternate half cycles is often seen due to a difference in the holding current of the triac between the two operating quadrants. if the triac is turning off before the end of the half cycle or rapidly turning on and off then a bleeder and damper circuit are required. in general as power dissipated in the bleeder and damper circuits increases, so does dimmer compatibility. initially install a bleeder network across the rectifed power bus (r10, r11 and c6 in figure 7) with initial values of 0.1 f and a total resistance of 1 k w and power rating of 2 w. figure 8. ideal input voltage and current waveforms for a leading edge triac dimmer at 90 conduction angle. 50 100 150 200 250 300 350 400 conduction angle () line voltage (at dimmer input) (v) line current (through dimmer) (a) 350 250 150 50 -50 -150 -250 -350 0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 pi-5983-060810 voltage current 0.5 0 50 100 150 200 250 400 350 300 conduction angle () rectified input voltage (v) rectified input current (a) 350 300 250 200 150 100 50 0 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 pi-5984-060810 voltage current figure 9. resultant waveforms following rectifcation of ideal triac dimmer output. 0 50 100 150 200 250 400 350 300 conduction angle () rectified input voltage (v) rectified input current (a) 350 300 250 200 150 100 50 0 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 pi-5985-102810 voltage current figure 10. example of phase angle dimmer showing erratic firing.
rev. a 11/01/10 9 lnk454/456-458/460 www.powerint.com reduce the capacitance value to fnd the minimum acceptable value. reducing the capacitance value reduces power dissipation and therefore increases effciency. if the bleeder circuit does not maintain conduction in the triac, then add a damper. the purpose of the damper is to limit the inrush current (as the input capacitance charges) and associated ringing that occurs when the triac turns on. initially add a passive damper which is a simple resistor in series with the ac input (r20 in figure 7). values in the range of 10 w C 100 w are typical with the upper range being limited by the allowed dissipation / temperature rise and reduction in effciency. values below 10 w may also be used but are less effective especially in high ac line input designs. if a passive damper is insuffcient to prevent incorrect triac operation then an active damper can be added. this is typical in high line applications due to the much larger inrush current that fows when the triac turns on. a low cost active damper circuit is formed by r3, r4, c3, q3, r7 and r8 in figure 7. resistor r7 and r8 limit the inrush current and can be a much higher value than the passive case as they are in circuit for only a fraction of the line cycle. silicon controlled rectifer (scr) q3 shorts r7 and r8 after a delay defned by r3, r4 and c3. the delay is adjusted to give the shortest time that provides acceptable dimmer performance to minimize the dissipation in the resistors. the scr is a low current, low cost device available in to-92 packages with very low gate current requirements. the gate drive requirement of the selected scr together with the minimum specifed line voltage defnes the maximum value of r7 and r8. its common for different dimmers to behave differently across manufacturers and power ratings. for example a 300 w dimmer requires less dampening and requires less power loss in the bleeder than a 600 w or 1000 w dimmer due to the use of a lower current rating triac which typically have lower holding currents. line impedance differences can also cause variation in behavior so during development the use of an ac source is recommended for consistency however testing using ac mains power should also be performed. electronic trailing edge dimmers figure 11 shows the line voltage and current at the input of the power supply with a trailing edge electronic dimmer. in this example, the dimmer conducts at 90 degrees. this type of dimmer typically uses a power mosfet or igbt to provide the switching function and therefore no holding current is necessary. also since the conduction begins at the zero crossing, high current surges and line ringing are not an issue. use of these types of dimmers typically does not require damper and bleeder circuits. thermal considerations lighting applications present unique thermal challenges for the power supply designer. in many cases the led load and associated heatsink determine the power supply ambient temperature. therefore it is important to properly heatsink and verify the operating temperatures of all devices. for the linkswitch-pl device a source pin (d package) or exposed pad (k or v package) temperature of <115 c is recommended to allow margin for unit to unit variation. worst case conditions are typically maximum output power, maximum external ambient and either minimum or maximum input voltage. layout considerations primary side connections the bypass pin capacitor should be located as close to the bypass pin and connected as close to the source pin as possible. the source pin trace should not be shared with the main power mosfet switching currents. all feedback pin components that connect to the source pin should follow the same guideline as for the bypass pin capacitor. it is critical that the main power mosfet switching currents return to the bulk capacitor with the shortest path possible. long high current paths create excessive conducted and radiated noise. 50 100 150 200 250 300 350 conduction angle () dimmer output voltage (v) dimmer output current (a) 350 250 150 50 -50 -150 -250 -350 0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 pi-5986-060810 voltage current 0 figure 11. ideal dimmer output voltage and current waveforms for a trailing edge dimmer at 90 conduction angle.
rev. a 11/01/10 10 lnk454/456-458/460 www.powerint.com secondary side connections the output rectifer and output flter capacitor should be as close as possible. the transformer output return pin should have a short trace to the return side of the output flter capacitor. these currents should not fow through the primary side source pin currents. the primary side source pin and secondary side return should be connected with a short trace. quick design checklist maximum drain voltage verify that the peak v ds does not exceed 700 v under all operating conditions including start-up and fault conditions. maximum drain current measure the peak drain current under all operation conditions including start-up and fault conditions. look for signs of transformer saturation (usually occurs at high ambient temperatures). verify that the peak current is less than stated in the absolute maximum ratings section. thermal check at maximum output power, both minimum and maximum line voltage and ambient temperature; verify that temperature specifcations are not exceeded for the linkswitch-pl, transformer, output diodes, output capacitors and drain clamp components. figure 12. rd-251 pcb top view. figure 13. rd-251 pcb bottom view. transformer u1 bulk capacitor copper heat sink area output filter capacitor switching current loop (primary) pi-6212-102810 transformer u1 bulk capacitor connection between primary and secondary switching current loop (secondary) pi-6213-102810
rev. a 11/01/10 11 lnk454/456-458/460 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to +125 c (unless otherwise specifed) min typ max units control functions maximum output frequency f max t j = 25 c average 110 122 134 khz peak-peak jitter 6 % minimum output frequency f min t j = 25 c average 25.8 28.7 31.6 khz peak-peak jitter 6 % maximum switch on-time t on(max) t j = 25 c 5.74 s minimum switch on-time t on(min) t j = 25 c 1.2 s maximum duty cycle dc max 70 % feedback pin voltage v fb t j = 25 c non-dimming (full power) operation 280 290 300 mv feedback pin voltage triggering cycle skipping mode v fb(sk) non-dimming (full power) operation 520 mv feedback pin voltage for ic auto-restart v fb(ar) 2 v feedback pull-up current i fb -1.3 -1.0 -0.7 a absolute maximum ratings (1,4) drain pin peak current (5) : lnk454 ............... 400 ma (750 ma) lnk456 .............. 850 ma (1450 ma) lnk457 ........... 1350 ma (2000 ma) lnk458 ............ 1750 ma (2650 ma) lnk460 ............ 2700 ma (5100 ma) drain pin voltage ............. -0.3 v to 725 v feedback pin voltage ............ -0.3 to 9 v bypass pin voltage ................. -0.3 to 9 v lead temperature (3) ....................................................... ......... 260 c storage temperature . .................. -65 to 150 c operating junction temperature (2) ......................... -40 to 150 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. the absolute maximum ratings specifed may be applied, one at a time without causing permanent damage to the product. exposure to absolute maximum ratings for extended periods of time may affect product reliability. 5. the higher peak drain current (in parentheses) is allowed while the drain voltage is simultaneously less than 400 v. thermal resistance thermal resistance: d (so-8c) package: ( q ja ) .......................... ........ 100 c/w (1) , 80 c/w (2) ( q jc ) ................................................. ....... 30 c/w (3) k (esop) package: ( q ja ) .......................... .......... 69 c/w (1) , 49 c/w (2) ( q jc ) ................................................. .......... 2 c/w (4) v (edip) package: ( q ja ) .......................... .......... 76 c/w (1) , 64 c/w (2) ( q jc ) ................................................. .......... 2 c/w (4) notes: 1. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610g/m 2 ) copper clad, with no external heat sink attached. 2. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610g/m 2 ) copper clad, with no external heat sink attached. 3. measured on the source pin close to plastic interface. 4. measured at the surface of exposed pad.
rev. a 11/01/10 12 lnk454/456-458/460 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to +125 c (unless otherwise specifed) min typ max units control function (cont.) drain supply current i s1 v fb > v fb(sk) (mosfet not switching) 450 a i s2 v fb = 0 v (mosfet switching at f max ) lnk454 530 a lnk456 585 lnk457 650 lnk458 730 lnk460 1050 bypass pin charge current i ch1 v bp = 0 v, t j = 25 c lnk454 -5.9 -4.2 -2.5 ma lnk456/457/458 -8.3 -5.9 -3.5 lnk460 -11.9 -8.5 -5.1 i ch2 v bp = 4 v, t j = 25 c lnk454 -3.4 -2.4 -1.4 ma lnk456/457/458 -5.2 -3.7 -2.2 lnk460 -8.0 -5.7 -3.4 bypass pin voltage v bp 5.60 5.85 6.15 v bypass pin shunt voltage v shunt i bp = 2 ma 5.9 6.2 6.6 v circuit protection current limit i limit di/dt = 160 ma/ s t j = 25 c lnk454 255 290 325 ma di/dt = 325 ma/ s t j = 25 c lnk456 510 580 650 di/dt = 490 ma/ s t j = 25 c lnk457 800 910 1020 di/dt = 650 ma/ s t j = 25 c lnk458 1012 1150 1288 di/dt = 980 ma/ s t j = 25 c lnk460 1637 1860 2083 leading edge blanking time t leb t j = 25 c 160 200 ns current limit delay t ild t j = 25 c 150 ns thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t sd(h) 75 c bypass pin power-up reset threshold voltage v bp(reset) 4.9 v
rev. a 11/01/10 13 lnk454/456-458/460 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to +125 c (unless otherwise specifed) min typ max units output on-state resistance r ds(on) lnk454 i d = 26 ma t j = 25 c 23.1 26.6 w t j = 100 c 34.4 39.8 lnk456 i d = 53 ma t j = 25 c 11.7 13.5 t j = 100 c 17.5 20.2 lnk457 i d = 85 ma t j = 25 c 6.9 7.9 t j = 100 c 10.4 11.9 lnk458 i d = 110 ma t j = 25 c 4.4 5.1 t j = 100 c 6.7 7.6 lnk460 i d = 170 ma t j = 25 c 2.2 2.6 t j = 100 c 3.3 3.9 off-state leakage i dss1 v bp = 6.2 v, v fb > v fb(sk) , v ds = 580 v, t j = 125 c 50 a breakdown voltage bv dss v bp = 6.2 v, v fb > v fb(sk) , t j = 25 c 725 v drain supply voltage 50 v auto-restart off-time t ar(off) f main = 50 hz 1.28 s f main = 60 hz 1.02 auto-restart duty cycle dc ar 33 %
rev. a 11/01/10 14 lnk454/456-458/460 www.powerint.com typical performance characteristics 0 100 200 300 400 500 600 0 10 100 1000 pi-6005-060210 drain voltage (v) drain capacitance (pf) lnk454 0.3 lnk456 0.6 lnk457 1.0 lnk458 1.55 lnk460 3.1 scaling factors: 1.2 0 0 2 4 6 8 10 12 14 16 18 20 drain voltage (v) drain current (a) pi-6006-060210 0.6 0.4 0.2 lnk457 t case = 25 c lnk457 t case = 100 c 1 0.8 lnk454 0.3 lnk456 0.6 lnk457 1.0 lnk458 1.55 lnk460 3.1 scaling factors: figure 7. drain capacitance vs. drain voltage. figure 9. breakdown vs. temperatue. figure 10. standard current limit vs. temperature. figure 8. drain current vs. drain voltage. 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction t emperature ( c) b rea kd own v o l tage (normalized to 25 c) pi-2213-012301 1 0.8 0.6 0.4 0.2 0 -50 0 50 100 150 temperature ( c) pi-6209-102910 1.2 current limit (normalized to 25 c)
rev. a 11/01/10 15 lnk454/456-458/460 www.powerint.com pi-4526-0401 10 d07c 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal bur r. 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc sea ting plane 0.25 (0.010) 0.17 (0.007) det ail a det ail a c sea ting plane pin 1 id b 4 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions so-8c (d package)
rev. a 11/01/10 16 lnk454/456-458/460 www.powerint.com side view end view 12 2 pi-5748-082510 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches [mm]. 6. datums a & b to be determined at datum h. esop-12 (k package) b c c h top view bottom view pin #1 i.d. (laser marked) 0.023 [0.58] 0.018 [0.46] 0.006 [0.15] 0.000 [0.00] 0.098 [2.49] 0.086 [2.18] 0.092 [2.34] 0.086 [2.18] 0.032 [0.80] 0.029 [0.72] seating plane detail a seating plane to package bottom standoff 0.034 [0.85] 0.026 [0.65] 0.049 [1.23] 0.046 [1.16] 3 4 0.460 [11.68] 0.400 [10.16] 0.070 [1.78] 0.306 [7.77] ref. 2 0.350 [8.89] 0.010 [0.25] ref. gauge plane seating plane 0.055 [1.40] ref. 0.010 [0.25] 0.059 [1.50] ref, typ 0.213 [5.41] ref. 0.019 [0.48] ref. 0.022 [0.56] ref. 0.020 [0.51] ref. 0.028 [0.71] ref. 0.316 [8.03] ref. 0.356 [9.04] ref. 0.059 [1.50] ref, typ 0.010 (0.25) m c a b 12 0.016 [0.41] 0.011 [0.28] 3 detail a (not drawn to scale) 0.008 [0.20] c 2x, 6 lead tips 0.004 [0.10] c 0.004 [0.10] c a 2x 0.004 [0.10] c b 0 - 8 1 2 3 4 5 6 6 1 7 12 2x 0.217 [5.51] 0.321 [8.15] 0.429 [10.90] 0.028 [0.71] 0.067 [1.70] land pattern dimensions 11 12 10 9 8 7 2 1 3 4 5 6
rev. a 11/01/10 17 lnk454/456-458/460 www.powerint.com side view c a end view 12 12 detail a 0.059 [1.50] ref, typ. 2 8 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches [mm]. 6. datums a & b to be determined at datum h. 7. measured with the leads constrained to be perpendicular to datum c. 8. measured with the leads unconstrained. 9. lead numbering per jedec spp-012. edip-12 (v package) b h top view 0.316 [8.03] ref. pin #1 i.d. (laser marked) pin #1 i.d. (laser marked) 0.350 [8.89] 0.070 [1.78] 1 2 3 4 5 6 12 11 10 9 8 7 7 12 6 0.059 [1.50] ref, typ. 1 0.213 [5.41] ref. 0.192 [4.87] ref. 0.436 [11.08] 0.406 [10.32] 0.023 [0.58] 0.018 [0.46] 0.092 [2.34] 0.086 [2.18] 0.049 [1.23] 0.046 [1.16] 0.022 [0.56] ref. 0.031 [0.80] 0.028 [0.72] 0.016 [0.41] 0.011 [0.28] 0.400 [10.16] 7 2 3 4 0.400 [10.16] 0.010 [0.25] ref. seating plane 0.412 [10.46] ref. 0.306 [7.77] ref. 0.104 [2.65] ref. 0.356 [9.04] ref. 0.019 [0.48] ref. 0.028 [0.71] ref. 0.020 [0.51] ref. bottom view 0.010 [0.25] m c a b 2x 0.004 [0.10] c b detail a (not drawn to scale) 0.004 [0.10] c a 5 4 pi-5556-110210 0.07 [1.78] 0.03 [0.76] 0.400 [10.16] mounting hole pattern dimensions drill hole 0.03 [0.76] round pad 0.05 [1.27] solder mask 0.056 [1.42]
rev. a 11/01/10 18 lnk454/456-458/460 www.powerint.com part ordering information ? linkswitch product family ? pl series number ? package identifer d so-8c k esop-12 v edip-12 ? package material g green: halogen free and rohs compliant ? tape & reel and other options blank standard confgurations tl tape & reel, 2.5 k pcs minimum for d package, 1 k pcs minimum for k package. lnk 454 d g - tl
rev. a 11/01/10 19 lnk454/456-458/460 www.powerint.com
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, capzero, senzero, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2010, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #19-01/05 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a initial release 11/01/10

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