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1 ds05-10188-1e fujitsu semiconductor data sheet memory cmos 1m 16 bit hyper page mode dynamic ram mb8118165a-60/-70 cmos 1,048,576 16 bit hyper page mode dynamic ram n description the fujitsu mb8118165a is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 16-bit increments. the mb8118165a features a ?yper page mode of operation whereby high-speed random access of up to 1,024-bits of data within the same row can be selected. the mb8118165a dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb8118165a is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb8118165a is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb8118165a are not critical and all inputs are ttl compatible. n absolute maximum ratings (see note) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7.0 v voltage of v cc supply relative to v ss v cc ?.5 to +7.0 v power dissipation pd 1.0 w short circuit output current i out ?0 to +50 ma operating temperature t ope 0 to 70 c storage temperature t stg ?5 to +125 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb8118165a-60/mb8118165a-70 n product line & features n package parameter mb8118165a-60 mb8118165a-70 ras access time 60 ns max. 70 ns max. random cycle time 104 ns min. 124 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. hyper page mode cycle time 25 ns min. 30 ns min. low power dissipation operating current 880 mw max. 825 mw max. standby current 11 mw max. (ttl level)/5.5 mw max. (cmos level) 1,048,576 words 16 bit organization silicon gate, cmos, advanced stacked capacitor cell all input and output are ttl compatible 1,024 refresh cycles every 16.4 ms self refresh function early write or oe controlled write capability ras only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance package and ordering information ?42-pin plastic (400 mil) soj, order as mb8118165a- pj ?50-pin plastic (400 mil) tsop-ii with normal bend leads, order as mb8118165a- pftn plastic soj package (lcc-42p-m01) plastic tsop packages (fpt-50p-m06) (normal bend)
3 mb8118165a-60/mb8118165a-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol max. unit input capacitance, a 0 to a 9 c in1 5pf input capacitance, ras , lcas , ucas , we , oe c in2 5pf input/output capacitance, dq 1 to dq 16 c dq 7pf fig. 1 ? mb8118165a dynamic ram - block diagram mode control write clock gen a 2 a 1 a 4 a 3 a 6 a 5 a 8 a 7 a 9 a 0 ras lcas ucas clock gen #2 data in buffer we dq 1 to dq 16 oe data out buffer column decoder clock gen #1 sense amp & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder refresh address counter substrate bias gen v cc v ss row decoder
4 mb8118165a-60/mb8118165a-70 n pin assignments and descriptions designator we oe function a 0 to a 9 address inputs row : a 0 to a 9 column : a 0 to a 9 refresh : a 0 to a 9 ras row address strobe lcas lower column address strobe write enable output enable dq 1 to dq 16 data input/output v cc +5.0 volt power supply v ss circuit ground ucas upper column address strobe n.c no connection 1 pin index v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 dq 1 dq 2 dq 3 dq 4 v cc v ss v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss 21 22 n.c. n.c. n.c. n.c. a 0 a 1 a 2 a 3 v cc dq 12 dq 11 dq 10 dq 9 n.c. a 9 a 8 a 7 a 6 a 5 a 4 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 21 30 v cc dq 1 dq 2 dq 3 dq 4 v cc v ss dq 5 dq 6 dq 7 dq 8 dq 16 dq 15 dq 14 dq 13 v ss n.c. dq 12 dq 11 dq 10 dq 9 n.c. 22 29 23 28 24 27 25 26 n.c. a 0 a 1 a 2 a 3 v cc n.c. v ss n.c. a 9 a 8 a 7 a 6 a 5 a 4 1 pin index 42-pin soj (top view) 50-pin tsop (top view) we ras lcas ucas oe we ras lcas ucas oe n.c. n.c.
5 mb8118165a-60/mb8118165a-70 n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. since only ten address bits (a 0 to a 9 ) are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 1. first, ten row address bits are input on pins a 0 -through-a 9 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min.) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways: an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or lcas / ucas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data of dq 1 -dq 8 is strobed by lcas and dq 9 -dq 16 is strobed by ucas and the setup/hold times are referenced to each lcas and ucas because we goes low before lcas / ucas . in a delayed write or a read-modify-write cycle, we goes low after lcas / ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max.) is satis?d. t cac : from the falling edge of lcas (for dq 1 -dq 8 ) ucas (for dq 9 -dq 16 ) when t rcd is greater than t rcd (max.). t aa : from column address input when t rad is greater than t rad (max.), and t rcd (max.) is satis?d. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . t oez : from oe inactive. t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and lcas (and/or ucas ) are inactive, or cas is reactived. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs v ih 2.4 6.5 v input high voltage, all inputs/ outputs* v il ?.3 0.8 v 1 1 1
6 mb8118165a-60/mb8118165a-70 hyper page mode operation the hyper page mode operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (within column address locations), any of 1,024 16-bits can be accessed and, when multiple mb8118165as are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated.
7 mb8118165a-60/mb8118165a-70 n dc characteristics (recommended operating conditions unless otherwise noted) notes 3 parameter notes symbol conditions value unit min. typ. max. output high voltage v oh i oh = ?.0 ma 2.4 v output low voltage v ol i ol = +4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in v cc ; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i do(l) 0 v v out v cc ; data out disabled ?0 10 operating current (average power supply current) mb8118165a-60 i cc1 ras & lcas , ucas cycling; t rc = min. 160 ma mb8118165a-70 150 standby current (power supply current) ttl level i cc2 ras = lcas = ucas = v ih 2.0 ma cmos level ras = lcas = ucas 3 v cc ?.2 v 1.0 refresh current #1 (average power supply current) mb8118165a-60 i cc3 lcas = ucas = v ih , ras cycling; t rc = min. 160 ma mb8118165a-70 150 hyper page mode current mb8118165a-60 i cc4 ras = v il , lcas = ucas cycling; t hpc = min. 100 ma mb8118165a-70 90 refresh current #2 (average power supply current) mb8118165a-60 i cc5 ras cycling; cas -before-ras ; t rc = min. 160 ma mb8118165a-70 150 refresh current #3 (average power supply current) mb8118165a-60 i cc9 ras = v il , cas = v il self refresh; t rass = min. 1000 m a mb8118165a-70 1 1 2 2 2 2
8 mb8118165a-60/mb8118165a-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb8118165a-60 mb8118165a-70 unit min. max. min. max. 1 time between refresh t ref 16.4 16.4 ms 2 random read/write cycle time t rc 104 124 ns 3 read-modify-write cycle time t rwc 138 162 ns 4 access time from ras t rac ?0?0ns 5 access time from cas t cac ?5?7ns 6 column address access time t aa ?0?5ns 7 output hold time t oh 3?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time t off ?5?7ns 11 output buffer turn off delay time from ras t ofr ?5?7ns 12 output buffer turn off delay time from we t wez ?5?7ns 13 transition time t t 150150ns 14 ras precharge time t rp 40?0ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 15?7ns 17 cas to ras precharge time t crp 5?ns 18 ras to cas delay time t rcd 14 45 14 53 ns 19 cas pulse width t cas 10?3ns 20 cas hold time t csh 40?0ns 21 cas precharge time (normal) t cpn 10?0ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 10?0ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 10?0ns 26 column address hold time from ras t ar 24?4ns 27 ras to column address delay time t rad 12 30 12 35 ns 28 column address to ras lead time t ral 30?5ns 29 column address to cas lead time t cal 23?8ns 30 read command set up time t rcs 0?ns 31 read command hold time referenced to ras t rrh 0?ns 6, 9 7, 9 8, 9 10 10 10 21 11, 12, 22 19 13 14
9 mb8118165a-60/mb8118165a-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb8118165a-60 mb8118165a-70 unit min. max. min. max. 32 read command hold time referenced to cas t rch 0?ns 33 write command set up time t wcs 0?ns 34 write command hold time t wch 10?0ns 35 write hold time from ras t wcr 24?4ns 36 we pulse width t wp 10?0ns 37 write command to ras lead time t rwl 15?7ns 38 write command to cas lead time t cwl 10?3ns 39 din set up time t ds 0?ns 40 din hold time t dh 10?0ns 41 data hold time from ras t dhr 24?4ns 42 ras to we delay time t rwd 77?9ns 43 cas to we delay time t cwd 32?6ns 44 column address to we delay time t awd 47?4ns 45 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 46 cas set up time for cas -before-ras refresh t csr 0?ns 47 cas hold time for cas -before-ras refresh t chr 10?2ns 48 access time from oe t oea ?5?7ns 49 output buffer turn off delay from oe t oez ?5?7ns 50 oe to ras lead time for valid data t oel 10?0ns 51 oe to cas lead time t col 5?ns 52 oe hold time referenced to we t oeh 5?ns 53 oe to data in delay time t oed 15?7ns 54 ras to data in delay time t rdd 15?7ns 55 cas to data in delay time t cdd 15?7ns 56 din to cas delay time t dzc 0?ns 57 din to oe delay time t dzo 0?ns 58 oe precharge time t oep 8?ns 59 oe hold time referenced to cas t oech 10?0ns 60 we precharge time t wpz 8?ns 14 15, 20 20 20 20 9 10 16 17 17
10 mb8118165a-60/mb8118165a-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb8118165a-60 mb8118165a-70 unit min. max. min. max. 61 we to data in delay time t wed 15?7ns 62 hyper page mode ras pulse width t rasp 100000 100000 ns 63 hyper page mode read/write cycle time t hpc 25?0ns 64 hyper page mode read-modify-write cycle time t hprwc 69?9ns 65 access time from cas precharge t cpa ?5?0ns 66 hyper page mode cas precharge time t cp 10?0ns 67 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 68 hyper page mode cas precharge to we delay time t cpwd 52?9ns 9, 18 20
11 mb8118165a-60/mb8118165a-70 notes: 1. referenced to v ss . 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il , ucas = v ih , lcas = v ih and v il > ?.3 v. i cc1 , i cc3 i cc4 and i cc5 are speci?d at one time of address change during ras = v il and ucas = v ih , lcas = v ih . i cc2 is speci?d during ras = v ih and v il > ?.3 v. 3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. 4. ac characteristics assume t t = 2 ns. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min.) and v il (max.). 6. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig.2 and 3. 7. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 8. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 50 pf. 10. t off , t ofr , t wez and t oez are speci?d that output buffer change to high mpedance state. 11. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min.) = t rah (min.) + 2t t + t asc (min.). 13. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access tome is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 16. assumes that t wcs < t wcs (min.). 17. either t dzc or t dzo must be satis?d. 18. t cpa is access time from the selection of a new column address (that is caused by changing both ucas and lcas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max.). 19. assumes that cas -before-ras refresh. 20. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and d out pin will maintain high impedance state through out the entire cycle. if t cwd 3 t cwd (min.), t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations. 21. the last cas rising edge. 22. the ?st cas falling edge.
12 mb8118165a-60/mb8118165a-70 n functional truth table note: x ; ? or ? * ; it is impossible in hyper page mode. operation mode clock input address input/output data refresh note ras lcas ucas we oe row column dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l h l valid valid valid high-z valid high-z valid valid yes* t rcs 3 t rcs (min.) write cycle (early write) l l h l h l l l x valid valid valid valid high-z valid valid high-z yes* t wcs 3 t wcs (min.) read-modify- write cycle l l h l h l l h ? ll ? h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle l h h x x valid high-z high-z yes cas -before- ras refresh cycle l l l x x high-z high-z yes t csr 3 t csr (min.) hidden refresh cycle h ? l l h l h l l h ? xl valid high-z valid high-z valid valid yes previous data is kept fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad fig. 4 ? t cpa vs. t cp 60 40 100 80 120 20 060 40 100 80 70ns version 60ns version t rac (ns) t rcd (ns) 60 50 80 70 90 20 040 30 60 50 70ns version t rac (ns) t rad (ns) 40 30 60 50 70 10 030 20 50 40 t cpa (ns) t cp (ns) 60ns version 60ns version 10 70ns version
13 mb8118165a-60/mb8118165a-70 t dzc t cah t cdd t asr t asc fig. 5 ? read cycle description to implement a read operation, a valid address is latched by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. dq 8 -dq 16 pins is valid when ras and cas are high or until oe goes high. the access time is determined by ras(t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max.), access time = t cac . if t rad > t rad (max.), access time = t aa if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either lcas /ucas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. ras v ih v il v ih v il v ih v il v ih v il v oh v ol lcas or ucas we dq (output) a 0 to a 9 v ih v il dq (input) v ih v il oe t rc t ras t ar t rp t rcd t crp t rah t oel t rch t rcs t oea t dzo t on t oed t oh t off t rad ? or ? row add column add t ral t cal t aa t cac t rac high-z high-z t oh t csh t rsh t cas t on t rdd t wpz t wed t wez valid data t oez t col t rrh
14 mb8118165a-60/mb8118165a-70 t wcs t asc t cah t rah t asr t crp fig. 6 ? early write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) description a write cycle is similar to a read cycle except we is set to a low state and oe is an ? or ? signal. a write cycle can be implemented in either of three ways?arly write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. t rc t ras t rp t csh t rcd t cas high-z ? or ? row add column add t wcr t wch t dh t ds valid data in t rsh t ar t dhr
15 mb8118165a-60/mb8118165a-70 t asr t oed t rp t cah t asc fig. 7 ? delayed write cycle (oe controlled) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description in the delayed write cycle, t wcs is not satis?d; thus, the data on the dq pins are latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). t rc t ras t cas t rcd t crp t rcs t dzc ? or ? invalid data t csh t rah t cwl t wp t ds t dh t dzo t oeh t oez row col valid t rsh t wch t rwl high-z high-z high-z t on t on t ar
16 mb8118165a-60/mb8118165a-70 t oed t oeh t rp t cah t asc t rah fig. 8 ? read-modify-write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. t rwc t ras t rcd t crp t asr t rwl t rcs ? or ? t cwl t ds t dh t dzo row col t rad t cwd t wp valid t oez t oh t rwd t awd t dzc t cac t rac t aa t on t on high-z high-z valid t oea t ar high-z
17 mb8118165a-60/mb8118165a-70 t rrh t rp t on t dzo t rcd fig. 9 ? hyper page mode read cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. t rasp t crp t asr t asc t rcs t rhcp ? or ? row add col t cas t rsh t hpc t cas t cas t cp t rch t rch t rcs t dzc t cpa t cah t cah t rah t asc t cah t asc t rch valid data t on t on col t csh t ral high-z t aa high-z t rac t rdd t oh t ofr t off t oh t cpa t oh t ohc t cac t ohc during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t off t cdd t oed t oez t rad t ar col t rcs t cac t aa
18 mb8118165a-60/mb8118165a-70 t oea t cas t cas t rad t rcd t rasp t crp t asr t asc t rcs t rhcp t rp row add col t rsh t hpc t cas t cp t dzc t cah t cah t rah t asc t rrh t cah t asc t rch t cac t aa col t csh t ral high-z high-z t ofr high-z t off t oh t oez t oed t rdd t oh t oh t aa t cpa t cac t aa t on t oea t oep t oh t oech t oez t oh t oez t dzo t on t rac t cp t cal t cdd t col t oea t cac t cpa t ohc t ar col fig. 10 ? hyper page mode read cycle (oe = ? or ?? ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. ? or ? valid data during one cycle is achieved, the input/output timing apply the same manner as the former cycle.
19 mb8118165a-60/mb8118165a-70 t rcd t rp t wez t wez t cas t cas t cas t rasp t crp t asr t asc t rcs t rhcp ? or ? row add col t rsh t hpc t dzc t csh t cah t rah t asc t csh t asc t rch valid data t cac t aa col t csh t ral high-z high-z t off t oh t oez t oed during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t rdd t oh t oh t aa t cac t aa t oea t dzo t on t rac t ofr t rcs t rch t wpz t rcs t rch t cal t cac t on t wpz high-z t on t wpz t cdd t wed t wez t on t rad fig. 11 ? hyper page mode read cycle (we = ? or ?? ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. col
20 mb8118165a-60/mb8118165a-70 t rp t dh fig. 12 ? hyper page mode early write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we dq (input) a 0 to a 9 v oh v ol dq (output) description the hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of we and oe are reversed. data appearing on the dq 1 to dq 8 is latched on the falling edge of lcas and one appearing on the dq 9 to dq 16 is latched on the falling edge of ucas and the data is written into the memory. during the hyper page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. t rasp t crp ? or ? row add t rsh t hpc t rcd t csh t cas t asc t cah t asr col col high-z t cas t cas t cp col t cah t asc t cah valid valid valid t wcs t wch t wcs t wch t wcs t wch t ds t dh t asc t rah t ds t dh t ds t ar t wcr t dhr t rhcp t ral during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t cwl t rwl t cwl t cwl
21 mb8118165a-60/mb8118165a-70 t oeh t oeh t rah fig. 13 ? hyper page mode delayed write cycle description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 9 v oh v ol v ih v il oe valid valid col add col add row add high-z data i n data i n t rasp t crp t csh t rcd t cas t cp t hpc t rsh t cas t asr t asc t cah t asc t cah t cwl t ar t rp t rcs t wch t cwl t wp t wch t wp t rwl t ds t dzc t ds t dh t dh t dzo t oed t on t on t oez t on t oez t oed t on ? or ? invalid data
22 mb8118165a-60/mb8118165a-70 t cas fig. 14 ? hyper page mode read/write mixed cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 9 v oh v ol v ih v il oe description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min.) is invalid. ? or ? valid data valid col add col add high-z row add col add high-z high-z data i n t rasp t hpc t crp t cp t rcd t cas t csh t rhcp t rsh t cah t asc t ral t cah t cas t asr t rad t asc t rah t cal t asc t cah t rp t rch t wcs t rcs t wch t dzc t dh t wed t ds t dzo t on t aa t rac t oea t cpa t wez t oed t aa t cac t on t ohc t oez t cac
23 mb8118165a-60/mb8118165a-70 fig. 15 ? hyper page mode read-modify-write cycle description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. ? or ? valid data dq (input) dq (output) valid valid col add high-z row add col add v ih v oh ras v ih v il v ih v il v ih v il v ih v il v il lcas or ucas we a 0 to a 9 v ol v ih v il oe t crp t rasp t rcd t rad t asr t rah t asc t cwd t cah t cp t asc t hprwc t cwd t rwl t cah t rp t rcs t awd t cwl t cpwd t rcs t wp t cwl t rwd t dzc t ds t dh t ds t wp t dh t oed t aa t on t on t rac t dzo t cac t oeh t oez t aa t oed t on t on t oez t oeh t cac t oea t oea t cpa
24 mb8118165a-60/mb8118165a-70 t off t crp fig. 16 ? ras -only refresh (we = oe = ? or ?? dq (output) ras v ih v il v ih v il v ih v il lcas or ucas a 0 to a 9 v oh v ol description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1,024 row addresses every 16.4-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and ucas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras. during ras -only refresh, dq pins are kept in a high-impedance state. t rc ? or ? t rp t asr t rpc high-z t rah t crp t oh t ras row address t off fig. 17 ? cas -before-ras refresh (addresses = we = oe = ? or ?? dq (output) ras v ih v il v ih v il lcas or ucas v oh v ol description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. t rc ? or ? high-z t ras t rpc t cpn t csr t chr t rp t oh t csr t cpn
25 mb8118165a-60/mb8118165a-70 t cdd t crp t rah fig. 18 ? hidden refresh cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 9 v oh v ol v ih v il oe description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. t rc ? or ? t rp t chr t rc t ras t ras t rp t oel t rsh t rad t asc t cah t rcs t rrh t cac t dzc t dzo t oea t oed t oez t asr t oh t off t on row column valid data out t rcd t ral t ar t aa t rac high-z high-z t ofr t oh
26 mb8118165a-60/mb8118165a-70 t cdd t crp t rah fig. 18 ? hidden refresh cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il lcas or ucas we a 0 to a 9 v oh v ol v ih v il oe description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. t rc ? or ? t rp t chr t rc t ras t ras t rp t oel t rsh t rad t asc t cah t rcs t rrh t cac t dzc t dzo t oea t oed t oez t asr t oh t off t on row column valid data out t rcd t ral t ar t aa t rac high-z high-z t ofr t oh
27 mb8118165a-60/mb8118165a-70 dq (output) lcas or ucas fig. 19 ? self refresh cycle (a 0 - a 11 = we = oe = ? or ?? (at recommended operating conditions unless otherwise noted.) note: assumes self refresh cycle only. parameter unit min. max. no. min. max. 74 100 100 symbol 75 124 104 76 ?0 ?0 m s ns ns ras pulse width ras precharge time cas hold time mb8118165a-60 mb8118165a-70 t rass t rps t chs ? or ? v ih v il ras v ih v il v oh v ol a 0 to a 9 , we, oe = ? or ? high-z t rass t rps t rpc t chs t csr t cpn t off t oh description the self refresh cycle provides a refresh operation without external clock and external address. self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator. if cas goes to ? before ras goes to ? (cbr) and the condition of cas ? and ras ? is kept for term of trass (more than 100 m s), the device can enter the self refresh cycle. following that, refresh operation is automatically executed at ?ed intervals using internal refresh address counter during ?as = l and ?as =l? exit from self refresh cycle is performed by toggling /ras and /cas to ? with speci?d tchs min.. in this time, ras must be kept ? with speci?d trps min.. using self refresh mode, data can be retained without external cas signal during system is in standby. restriction for self refresh operation; for self refresh operation, the notice below must be considered. 1) in the case that distributed cbr refresh are operated between read/write cycles self refresh cycles can be executed without special rule if 4,096 cycles of distributed cbr refresh are executed within tref max.. 2) in the case that burst cbr refresh or distributed/burst /ras only refresh are operated between read/write cycles 1,024 times of burst cbr refresh or 1,024 times of burst /ras only refresh must be executed before and after self refresh cycles. * read/write operation can be performed non refresh time within t ns or t sn 1,024 burst refresh cycle 1,024 burst refresh cycle read/write operation self refresh operation read/write operation v ih v il ras t ns < 1 ms t rass t sn < 1 ms
28 mb8118165a-60/mb8118165a-70 n package dimensions (suf?: -pj) r.032(0.81)typ. .134 +.014 (3.40 ) +0.35 42-lead plastic leaded chip carrier (case no.: lcc-42p-m01) ? 1994 fujitsu limited c42001s-2c(w) *: this dimension exclude resin protrusion. (each side:.006(0.15)max.) dimensions in inches (millimeters) .004(0.10) 1.075 .005 (27.30 0.13) .050 .005 (1.27 0.13) .098(2.50) nom 1.000(25.40)ref. * index .400(10.16) nom. .108(2.75)nom. .025(0.64)min. .370 .020 (9.40 0.51) .432 .005 (10.97 0.13) details of ? part .032(0.81) max .017 .004 (0.43 0.10) .008 +.002 (0.20 ) +0.05 ? 1 lead no. 21 22 42
29 mb8118165a-60/mb8118165a-70 n package dimensions (continued) (suf?: -pftn) .005(0.13) m ? 1994 fujitsu limited f50006s-1c(w) 50-lead plastic flat package (case no.: fpt-50p-m06) dimensions in inches (millimeters) *: this dimension exclude resin protrusion.(each side : .006(0.15) max) .012 .004 (0.30 0.10) 1 lead no. 11 15 25 50 40 36 26 index ? *.825 .004 (20.95 0.10) .004(0.10) .756(19.20)ref details of ? part .463 .008 (11.76 0.20) .400 .004 (10.16 0.10) .424 .008 (10.76 0.20) .005 .002 (0.125 0.05) .006(0.15) .010(0.25) .006(0.15)max .016(0.40)max .031(0.80) typ .020 .004 (0.50 0.10) 0(0) min (stand off .043 (1.10 ) (mounting height) +.004 +0.10
30 mb8118165a-60/mb8118165a-70 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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