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UCD9112 digital dual phase synch ronous buck controller ver. 0.5 september 2006 1 co py ri g ht ? 2001, texas instruments incor p orated product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. www.ti.com ? features ? digital dual phase synchronous buck pwm controller with 175ps pwm resolution ? digital control with programmable pid compensation ? dual-phase with current balancing capability ? vin from 4.5v to 14.5v (ucd7230) ? vout from 1% to 99% of vin ? programmable switching frequency, capable of up to 2mhz/phase ? programmable soft start and soft stop ? supports pre-biased start-up ? internally trimmed 0.5% 800mv reference ? remote sensing differential amplifier ? power supply monitoring via pmbus ? single bias supply (3.3v vdd) ? graphical user interface configuration ? internal thermal sensor ? pmbus support query voltage, current, faults, etc voltage setting and calibration protection threshold adjustment ? 32-pin qfn package ? applications ? ? networking equipment ? servers ? storage systems ? telecommunications equipment ? dc power distributed systems ? industrial / ate ? description the UCD9112 is dual-phase synchronous buck digital pwm controller that supports point of load (pol) applications. the device is configured thru the use of a graphical user interface (gui). the loop compensator is configurable with the gui to meet dynamic converter performance allowing a single hardware design to cover a broad range of pol applications. in addition to digital control loop, the UCD9112 is able to monitor and manage power supply operating conditions and report the status to the host system through pmbus. the management parameters are configurable through gui. the gui also allows the power supply designer to easily configure the digital control loop characteristics and generate the gain and phase information for analysis using bode plots. to ensure balanced outputs on each phase, the UCD9112 incorporates a current balancing scheme. the pwm output of the dual phase controller is capable of operating at a switching frequency of up to 2mhz with a relative phase adjustment of 180 o . the ucd7230 synchronous buck driver has been designed to work with the UCD9112 controller to provide a highly integrated digital power solution. in addition to 4a output drive capability, the driver integrates current limit, short circuit protection as well as under-voltage lockout protection. the ucd7230 also has a 3.3v, 10ma linear regulator that provides the supply current for the controller . ordering information package tape and reel qty part number qfn 250 UCD9112rhb
UCD9112 digital dual phase synch ronous buck controller ver. 0.5 september 2006 2 co py ri g ht ? 2001, texas instruments incor p orated product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. www.ti.com table of contents features 1 device information 3 1.1 system block diagram 4 1.2 example dual phase implementation 5 1.3 pin assignment 5 1.4 pin functions 5 2 device ratings 7 2.1 absolute maximum ratings 7 2.2 recommended operating conditions 7 2.3 electronic discharge (esd) protection 7 3 electrical characteristics 8 4 typical characteristics 11 5 function overview 11 5.1 reset 11 5.1.1 power-on reset 11 5.1.2 brown-out reset 11 5.1.3 watchdog 11 5.1.4 external reset 11 5.2 analog inputs 12 5.2.1 resolution 12 5.2.2 input impedance 12 5.3 pmbus address 13 5.4 pid compensator 14 5.5 output voltage sensing 15 6 pmbus interface 16 6.1 pmbus timing 16 6.2 output configuration commands 16 6.2.1 remote on/off 16 6.2.2 output voltage set point 16 6.2.3 output voltage calibration 17 6.2.4 margin up/down 17 6.2.5 output current measurement 17 6.2.6 start up into pre-bias 18 6.2.7 output voltage sequencing 18 6.2.8 output voltage soft start 19 6.2.9 output voltage soft stop 19 6.2.10 power good (pgood) 20 6.3 protection commands 20 6.3.1 input under voltage protection 20 6.3.2 input over voltage protection 21 6.3.3 output over voltage protection 21 6.3.4 output under voltage protection 22 6.3.5 output over current protection 23 6.3.6 over temperat ure protection 23 6.4 status & fault reporting commands 24 6.5 non-volatile storage commands 24 6.6 host data storage commands 25 7 dual phase current balancing 25 8 gui 26 9 package information 29 list of figures figure 1-1 UCD9112 block diagram 3 figure 1-2. UCD9112 with the ucd7230 4 figure 1-3. UCD9112 pin assignment 5 figure 3-1 pmbus timing diagram 10 figure 5-1 v addr to pmbus address translation 13 figure 5-2 output voltage sensing circuitry 15 figure 6-1 current gain and offset 18 figure 8-1 gui interface for pol configuration 27 figure 9-1 32-pin powerpad tm qfn package 29 list of tables table 1-1 UCD9112 pin descriptions 5 table 5-1device reset voltage threshold 11 table 5-2 analog input assignments 12 table 5-4 configuration of pmbus addresses 14 table 7-1 current balancing of two phases 26
UCD9112 digital dual phase synch ronous buck controller ver. 0.5 september 2006 3 co py ri g ht ? 2001, texas instruments incor p orated product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. www.ti.com 1 device information 1.1 block diagram figure 1-1. UCD9112 block diagram
UCD9112 september 2006 4 www.ti.com 1.2 example dual phase implementation with the ucd7230 driver out2 neg bst pos pgnd agnd sre clf ilim ucd7230 iout0 pmbus commun in cs+ 3v3 vout UCD9112 addr1 addr0 iout_0 vin vout iout_1 dvss dv25 rst eap ilim dpwm1a dpwm0b dpwm0a dpwm1b clk data clf1 ean clf0 vd33 avss ao vdd cs bias pvdd out1 io out2 neg bst pos pgnd agnd sre clf ilim in cs+ 3v3 ao vdd cs bias pvdd out1 io sw sw ucd7230 vin vin vin vout 3.3v iout1 vd33 iout0 vd33 iout1 rs- rs+ r1 r2 r3 r4 r10 r8 r7 r6 r5 c11 r11 r9 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 c1 c2 c3 c4 c10 c9 c8 c7 c6 c5 c12 c13 c14 c15 c16 c17 c18 c19 c20 r22 r23 r24 r25 c21 c22 c23 c24 c25 c26 r26 q1 q2 d1 q3 d2 q4 l1 l2 rs+ rs- r27 r28 dly dly figure 1-2. UCD9112 in a dual phase configuration
UCD9112 sepember 2006 5 www.ti.com 1.2 pin assignments figure 1-3. UCD9112 qfn package pin assignments 1.3 pin functions table 1.1 UCD9112 pin descriptions terminal pin name no. i/o a/d description addr1 1 i a addr0 2 i a addr1 and addr0 signals are analog voltage that are sampled when UCD9112 is released from reset. the voltage levels set the addresses. see the below section, pmbus address. iout_0 3 i a phase 0 inductor current, the value is amplified in ucd7230 vin 4 i a input dc voltage sensing through resistors. vout 5 i a output dc voltage sensing through resistors. iout_1 6 i a phase 1 inductor curren sensi ng, the value is amplified in ucd7230. nc 7 - - open connection. nc 8 - - open connection. dvss 9 - dp digital ground of ic. this ground should be separate from power ground. vd25 10 o p internal 2.5v bypass pin for UCD9112. a 1 f ceramic cap must be connected from vd25 to dvss. rst 11 i - pulling high resets the chip. need a pull-down resistor and a 0.1 f decoupling capacitor. dum 12 - - connected to analog ground avss. nc 13 - - no connection.
UCD9112 september 2006 6 www.ti.com clf0 14 i d phase 0 over current limit flag from ucd7230. ilim 15 o d a pwm ouptut that is used to generate an analog input to the ucd7230 current limit. the ilim requires an rc filter consisting of 15k and 0.1uf nc 16 - - open connection dpwmb1 17 o d phase 1 dpwm output to the drive ucd7230. dpwma1 18 o d phase 1 dpwm output to the drive ucd7230. dpwmb0 19 o d phase 0 dpwm output to the drive ucd7230. dpwma0 20 o d phase 0 dpwm output to the drive ucd7230. pgood 21 o d power good signal indi cating power conversion status. alert 22 o d alert signal indiating pmbus status. ctrl 23 i d on/off command to turn on/off power supply output. clf1 24 i d phase 1 over current flag from ucd7230. nc 25 i d open connection. nc 26 o d open connection. clk 27 i d pmbus/smbus/i 2 c clock input. data 28 i/o d pmbus/smbus/i 2 c data (bi-directional). ean 29 i a output voltage remote sense to error amplifier negative input. eap 30 i a output voltage remote sense to error amplifier positivve input. vd33 31 i p 3.3v vdd bias supply and analog reference. avss 32 - p analog ground. pad gnd 33 - pad pad analog ground.
UCD9112 sepember 2006 7 www.ti.com 2 device ratings 2.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) range unit vd33 relative to vss -0.3 to 3.6 v io pin relative to vss -0.3 to 3.6 v operating junction temperature, t j -40 to 125 oc storage temperature, t sj -65 to 150 oc lead temperature(soldering for 10 sec) 300 oc (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other c onditions beyond those specified is not implied. 2.2 recommended operating conditions over operating free-air temperatur e range (unless otherwise noted) min typ max unit vd33 relative to vss -0.2 3.3 3.5 v veap relative to vean 0 2.45 v operating free-air temperature -40 85 oc 2.3 electrostatic discharge (esd) protection parameter min typ max unit hbm (human body model) 2000 v cdm (charged device model) 500 v
UCD9112 september 2006 8 www.ti.com 3 electrical characteristics vd33 = 3.3v, ta=-40 oc to 85 oc (unless otherwise noted) parameter conditions min typ max unit vdd input supply vd33 supply voltage 3.14 3.3 3.46 v icc supply current norma l operation 4 7 10 ma vd25 output voltage range 1uf ceramic connected, without source current 2.4 2.45 2.5 v source current 1 5% maximum voltage drop -10 ma eap & ean input differential range -0.2 2.5 v input bias current to eap veap-vean = 2.5v -10 50 a output source current from ean -10 a bandwidth 2 mhz pwm output duty cycle 1 99 % rise time (t r ) 1000pf cap load 15 ns fall time (t f ) 1000pf cap load 15 ns dead band (t db ) fs = 500khz 20 512 ns fault shutdown delay (t dl ) the count of clf is set at zero 20 ns pwm frequency (f sw ) 30 500 2000 khz frequency set point accuracy t a = 25 oc 5 % ilim pwm frequency (f il ) 50 khz duty cycle range 0 100 % fall time(t f_il ) 1000pf cap load 15 ns rise time (t f_il ) 1000pf cap load 15 ns power good pgood assertion delay tbd s pgood deassertion delay tbd s low level output voltage (v ol ) i pgood = 5 ma 0.4 v high level output voltage (v oh ) i pgood = -5 ma 2.8 v
UCD9112 sepember 2006 9 www.ti.com pmbus aert pmbus alert assertion delay tbd s pmbus alert deassertion delay tbd s low level output voltage (v ol ) i alert = 5 ma 0.4 v high level output voltage (v oh ) i alert = -5 ma 2.8 v thermal shutdown shutdown temperature junction temperature tbd oc hysteresis tbd oc i/o characteristics high input voltage, v ih vd33=3.3v 2 3.45 v low input voltage, v il vd33=3.3v 0.8 v input hysteresis voltage. vd33=3.3v 0.3 v output voltage high (v oh ) vd33=3.3v, ioh = -5ma 2.8 output voltage low (v ol ) vd33 = 3.3v, iol = 5ma 0.4 pmbus/smbus/i2c fsmb pmbus/smbus operating frequency slave mode, smbc 50% duty cycle 100 khz fi2c i 2 c operating frequency slave mode, scl 50% duty cycle 400 khz t (buf) bus free time between start and stop 4.7 us t (hd:sta) hold time after (repeated) start 4.0 us t (su:sta) repeated start setup time 4.7 us t (su:sto) stop setup time 4.0 us t (hd:dat) data hold time receive mode 0 ns transmit mode 300 ns t (su:dat) data setup time 250 ns t (timeout) error signal/detect (1) 25 35 ms t (low) clock low period 4.7 us t (high) clock high period (2) 4.0 50 us t (low:sext) cumulative clock low slave extend time (3) 25 ms
UCD9112 september 2006 10 www.ti.com t (low:mext) cumulative clock low master extend time (4) 10 ms t f clock/data fall time (5) 300 ns t r clock/data rise time (6) 1000 ns (1) the UCD9112 times out when any clock low exceeds t (timeout) . (2) t (high) , max, is the minimum bus idle time. smbc = smbd = 1 for t > 50 ms causes reset of any transaction involving ucd9110 that is in progress. this specif ication is valid when the nc_smb control bit remains in the default cleared state (clk[0]=0). (3) t (low:sext) is the cumulative time a slave devi ce is allowed to extend the clock cycl es in one message from initial start to the stop. (4) t (low:mext) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. (5) fall time t f = 0.9vdd to (vilmax ? 0.15) (6) rise time t r = vilmax ? 0.15) to (vihmin + 0.15) figure 3-1. pmbus/smbus/i2c timing diagram
UCD9112 sepember 2006 11 www.ti.com 4 typical characteristics to be included in later revision of the data sheet 5 function overview 5.1 reset 5.1.1 power-on reset the UCD9112 has an integrated reset block which m onitors the supply voltage. at power-up, the por detects the vd33 rise. when vd33 is greater than a predetermined reference point, vrst, a reset pulse is generated and a startup delay sequence is initiated. at the end of the delay sequence, the system reset signal is deasserted and the device begins normal operation. (see table 5-1) in applications with long vd33 rise times, the external reset (rst) should be used to ensure startup occurs when the supply voltage is greater than the minimu m operating voltage. at the normal operating condition, this rst pin must be connected to a parallel combination of a 10k ? resistor and 0.1 f capacitor to avss. 5.1.2 brown-out reset the UCD9112 also has an integrated brown-out reset circuit that is used to generate a reset when the supply voltage falls below a fixed trip reference volt age. the device is held in reset until the supply voltage rises above the minimum voltage threshold, at which time a new reset pulse is generated and the por circuit restarts the device. (see table 5-1) 5.1.3 watchdog timer built-in watchdog provide protection from unpredicted operation. 5.1.4 external reset the device can be forced into the rese t state by an external circuit conn ected to the pin rst. a logic high voltage on this pin generates a reset signal. to avoid an erroneous trigger caused by the noise, a pull down resistor and a decoupling cap is necessary. table 5-1 device reset voltage threshold vd33= 3.3v, ta= -40oc to 85oc (unless otherwise noted) parameter test conditions min typ max unit power-on reset, vrst 2.4 2.5 2.8 v brown-out threshold 2.2 v rst delay tbd ms hysteresis 0.2 v
UCD9112 september 2006 12 www.ti.com 5.2 analog monitoring the UCD9112 monitors 7 analog signals to determine su pply operation. table 5-2 below shows the analog input pin assignments. table 5-2. analog input assignment pin. no pin name function description 1 addr1 address 1 voltage conversion 2 addr0 address 0 voltage conversion 3 iout_0 phase 0 output current conversion 4 vin pol input voltage conversion 5 vout pol output voltage conversion 6 iout_1 phase 1 output current conversion internal - temperature sensing voltage conversion the UCD9112 takes the proper action based on the in formation acquired from these analog inputs, for example turning on the dc output or sending alarm signal to the host system if t he output is under voltage. the device temperature is monitored using an internal temperature sensor. the data can be reported to the host after the UCD9112 receives the commands via pmbus. the pmbu s commands will be addressed in the section titled pmbus interface. 5.2.1 resolution the external analog inputs have 3.22mv resolution bas ed on a 3.3v vd33 input. the maximum input voltate at the analog input should not exceed 3.0v for proper measurement. in some applications, a voltage divider is used to reduce the voltage level applied to the analog input. the division ratio changes the conversion resolution. . 5.2.2 input impedance the input impedance is typically a 250 ? series input and a 30pf capacitor to ground. the inputs are sampled and require 60ns of settling time. it is desirable to have a 0.1uf input capacitor at each analog input pin.
UCD9112 sepember 2006 13 www.ti.com 5.3 pmbus address the digital pol system has the ability to be configur ed with different pmbus addresses. to configure different addresses, a voltage will be applied to the pins addr1 and addr0 on the UCD9112. the following table shows what pmbus addre sses are indicated by the applied voltage. figure 5-1. v addr to pmbus address translation note that the nominal value for each voltage step (and each pmbus address) is in the center of each band. the address can be represented by the formula: pmbus_addr = addr0 * 12 + addr1 table 5-4 lists the examples of the pmbus addres s for given the voltage level on the pin1 and pin2. addresses 0 1 2 3 4 5 6 7 8 9 10 11 v addr 3.00 3.30 address not valid 3.0< v addr < 3.3 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
UCD9112 september 2006 14 www.ti.com table 5-4. the configuration of pmbus addresses pmb_addr0 pmb_addr1 pbm address pmb_addr0 pmb_addr 1 pbm address <0.25 0x00 <0.25 0x0c 0.25-0.5 0x01 0.25-0.5 0x0d 0.5-0.75 0x02 0.5-0.75 0x0e 0.75-1.0 0x03 0.75-1.0 0x0f 1.0-1.25 0x04 1.0-1.25 0x10 1.25-1.50 0x05 1.25-1.50 0x11 1.50-1.75 0x06 1.50-1.75 0x12 1.75-2.0 0x07 1.75-2.0 0x13 2.0-2.25 0x08 2.0-2.25 0x14 2.25-2.50 0x09 2.25-2.50 0x15 2.50-2.75 0x0a 2.50-2.75 0x16 <0.25 2.75-3.0 0x0b 0.25-0.50 2.75-3.0 0x17 the other address can be figured out by using the abov e formula. if the voltage pl aced on the address pins is over 3.0v or below zero, the value is not valid. 5.4 pid compensator the pid compensator allows the output voltage to be r egulated at the set point reference level with zero steady state error and at the same time, maintain good dynamic performance. the high dc gain of the control loop maintains the zero steady state error. this is realized by an integrator in the pid compensator. however, the dynamic response may not be ideal if only an integrator exists in the control loop for different applications. to further improve step response and st ability, the pid compensator should be designed with properly placed pole and zeros in order to achieve desired bandwidth and optimum phase margin, and gain margin. the synchronous buck topology is commonly used for non-isolated dc/dc converters. the placement of the pole and zeros is determined by the out put filter inductor, capacitor and th e esr parasitic. in the traditional power supply design, an operational error amplifier and external compensation components are used to implement the pole and zeros. using the UCD9112, the output voltage is properly scaled and fed to the UCD9112 error converter. the adc output is then fed to the UCD9112? s on chip pid compensator. the compensator is configured using the graphical user in terface (during development) and the configuration is stored into the UCD9112?s flash memory. 5.5 output voltage sensing
UCD9112 sepember 2006 15 www.ti.com figure 5-2. output voltage sensing circuitry figure 5-2 shows the voltage sensi ng circuitry in UCD9112. it is part of feedback loop. two dedicated pins, eap and ean, are employed to sense the output volt age differentially. the di fferential sensing can effectively reduce the noise induced by the switching devices. the maximum voltage for veap-vean should be less than 2.45v. if output voltage is higher than 2.45v, a voltage divider should be used to decrease the input voltage level below 2.45v.
UCD9112 september 2006 16 www.ti.com 6 pmbus interface pmbus is an industry st andard specification for power management.. the uc d9112 supports all of the pmbus data commands that are relevant to this applicati on. most of the functionality in the dpol application for the UCD9112 uses pmbus commands to support each of the functions. for each pmbus command supported in this specification, all smbus transa ction types associated with that command are also supported. this enables the user to write and read the support parameters through the pmbus commands, and smbus transactions. the UCD9112 is pmbus compliant, in accordance with t he ?compliance? section of the pmbus specification. the firmware is also compliant with the smbus 1.1 specification, including support for the smbus alert function. 6.1 pmbus timing the timing characteristics and timing diagram fo r the communications interface that supports i 2 c, smbus and pmbus is shown at figure 3 in the se ction electrical characteristics. 6.2 output configuration commands 6.2.1 remote on/off remote on/off is supported by the software in the uc d9112 controller. this behav ior is configurable and is supported by a combination of the pmbus commands bel ow and the pmb_ctl signal which is connected to pin 23. the pmbus commands that support this functionality are: on_off_config operation the on_off_config command is used to configure the policy by which th e unit is turned on and off, and the operation command is used to turn the unit on and off according to this policy. power supply is turned on when pmb_ctl pin is pulled high; it is turned off when the pin is pulled down. 6.2.1 output voltage set point the pmbus commands that support this functionality are: vout_mode vout_command vout_max voltage_scale_loop voltage_scale_monitor
UCD9112 sepember 2006 17 www.ti.com vout_mode and vout_command set the new output voltage mode and the vout_max command sets the maximum output voltage. vout_mode is used fo r commanding and reading output voltage, and it consists of a three-bit mode and a five-bit parame ter representing the exponent used in output voltage read/write. the voltage set by vout_command is more than vout_max, the command is ignored. the voltage_scale_loop and voltage_scale_monitor commands are used to scaling the output voltage. 6.2.3 output voltage calibration the UCD9112 supports v out output calibration. output calibration is supported dynamically and can be changed with the supply is operational. the pmbu s command that supports this functionality is: vout_cal the vout_cal command supports output voltage calibra tion by providing a fixed offset voltage to the output voltage command values. 6.2.4 margin up/down the UCD9112 supports margin up/down linearly through a programmable rate. the pmbus commands to support this functionality are: vout_margin_high vout_margin_low vout_transition_rate the vout_margin_high command is used to provide th e unit with the voltage to which the output is to be changed when the operation is set to ?margin high?. the vout_margin_low command is used to provide the unit with the voltage to which the output is to be changed when the operation is set to ?margin low?. when margining up or down, the rate at which the voltage margining increases or decreases will be specified by the vout_transition_rate command. 6.2.5 output current measurement there are two commands in UCD9112 to measure output current. the output current is measured by sensing the voltage drop across the dcr of each output inductor . the current of each phase is added to provide the iout value. the pmbus commands that support this functionality are: iout_scale iout_cal_offset the UCD9112 has two manufacturer specific commands to report the current on each of the two phases. the iout_cal_offset command support output current ca libration by nullifying any offsets in the current sensing circuits. the iout_scale command is used to set the ratio of the voltage at the current sense pins to the sensed current of each phase. the output current can be calculated as:
UCD9112 september 2006 18 www.ti.com offset cal iout scale iout v i sense o ? ? ? ? = this can be graphically depicted as shown below. figure 6-1. current gain and offset 6.2.6 start up into pre-bias the UCD9112 supports starting the power supply when there is an existing output voltage when the system starts. the system will start up with an output voltage higher than the output voltage set point. the duty cycle is calculated by dividing v out by v in (duty cycle = v out / v in ). the time constant for this operation is 50 ms and regulation will be achieved by this time. when the pmbus control line is asserted, the ucd911 2 looks at the output voltage to determine if a prebias is present. the algorithm for this is as follows: if v out < 300 mv, then the startup is done assuming no pr e-bias. start up proceeds normally through delay and soft start states. if v out > 3.65v, then the device does not attempt startup if v out > output voltage set point, then disable overvolt age protection (ovp), calculate the duty cycle (v out / v in ), bypass the soft start state and commence switching. when v out < v out_ high limit, re-enabled ovp. the response time from this action will be less than 10 ms. if v out < output voltage set point, then turn off v out low protection, calculate the duty cycle, bypass the soft start state and commence switching. when v out > v out low, then re-enable v out low protection. there are no pmbus commands associated with this functionality. 6.2.7 output voltage sequencing the UCD9112 supports output voltage sequencing. out put voltage sequencing is started based on receiving an indication from the pmb control (pmb_ctl) signal from the system host. the pmbus commands that support this functionality are: i out v sense offset gain measured value adjusted value
UCD9112 sepember 2006 19 www.ti.com ton_delay toff_delay ton_delay is used to specify the delay from when the pmbus control line is asserted to when the output voltage starts to rise. toff_delay is used to specify the delay from when the pmbus control line is deasserted to when the output voltage starts to fall. 6.2.8 output voltage soft start soft start timing starts when the pmb_ctl line is asse rted (voltage rise). the system configures the delay from the assertion of the pmb_ctl signal to when the output voltage entered the regulation band. the system also configures the maximum time this pr ocess can take, without causing an undervoltage fault, and what action to take for an error. the pmbus commands that support this functionality are: ton_rise ton_max_fault_limit ton_max_fault_response when the voltage is rising, the ton_rise command sp ecifies the time from when output voltage tracking starts, to when the output voltage enters the re gulation band. the ton_max_fault_limit command specifies the maximum amount of time that this proces s can take, before an undervoltage fault will occur. the ton_max_fault_response command specifies the action to be taken if the po wer supply does not reach the regulation band before the maximum time specified by ton_rise has elapsed. 6.2.9 output voltage soft stop soft stop timing starts when the pmb_ctl line is deasserted (voltage fall). toff_fall toff_max_fault_limit toff_max_fault_response the toff_fall command specifies the time from when the voltage starts to fall to when it is off. the toff_max_fault_limit command specifies the maximum amount of time that this process can take, before an overvoltage fault will oc cur. the toff_max_fault_response command specifies the action to be taken if the power supply does not reach 0v by the maximum time specifies in toff fall has elapsed. in the event that the voltage fails to rise or fall ac cording to the criteria above, the status_vout command will reflect the failure to meet the configured output voltage tracking.
UCD9112 september 2006 20 www.ti.com 6.2.10 power good (pgood) the UCD9112 supports an indication of power good to the host. the UCD9112 will monitor output voltage and will either assert or de-assert the power good si gnal based on this voltage. the UCD9112 uses the pgood (pin 21) as the power good signal and the polarity of this signal can be configured as active high or active low through pmbus. this signal drives an open collector gpio pin on the host system. power good is asserted when the syst em is operational and is deliver ing the configured output voltage. power good will be de-asserted when any condition (fault or otherwise) causes the system to ramp down output voltage. the system w ill assert (or de-asser t) this signal within 1ms of the event that causes the transition. the pmbus commands that support this functionality are: power_good_on power_good_off mfr_specific_00 the power_good_on command is used to specify the voltage at which the power good signal should be asserted. the power_good_off command is used to specify the voltage at which the power good signal should be de-asserted. the mf r_specific_00 command configures the polarity of the power good signal. a value of 0 in the least significant byte in this command means that the power good signal should be configured to be active low. a value of 1 in the least significant byte in this command means that the power good signal should be configured to be active high. 6.3 protection commands UCD9112 provides many features to monitor input vo ltage, output voltage, output current, and temperature. the thresholds can be programmable through pmbus, and the status and the faults are sent to the host computer if requested. 6.3.1 input under voltage protection(vin_uvp) input voltage is sensed on vin (p in4) of UCD9112, and the data is processed based on the threshold programmed through pmbus. the pmbus commands that will support this functionality are: vin_uv_warn_limit vin_uv_fault_limit vin_uv_fault_response vin_on vin_off when the input voltage starts to rise towards the re gulation band, the vin_on command sets the voltage at which power conversion starts. when the voltage is in the regulation band, the system then observes the
UCD9112 sepember 2006 21 www.ti.com input voltage for both input under and over voltage warnings and faults. if the voltage falls below the value set by the vin_off command, t hen power conversion will stop. if the voltage falls below the value set through t he vin_uv_warn_limit command, then an under voltage warning occurs. if the voltage continues to fall and falls below the value set through the vin_uv_fault_limit command, then an under voltage fault occurs. the action taken in this event is specified by the vin_uv_fault_respo nse command. when an under-voltage fault occurs, the vin_uv_fault _response register instructs the system how to react. there are two response bits that instruct the sy stem what to do in the even t of these failures. input under-voltage fault response actions 6.3.2 input over voltage protection (vin_ovp) the UCD9112 supports warnings and faults for input over voltage protection. the latency from when the voltage goes out of range to when power is ramped down is 20ms. the pmbus commands that support this functionality are: vin_ov_warn_limit vin_ov_fault_limit vin_ov_fault_response for input over voltage warnings , the vin_ov_warn_limit command is used to set the input voltage at which an over voltage warning occurs. 6.3.3 output over voltage protection (vo_ovp) UCD9112 monitors output voltage by the vout (pin5). in order to compensate for possible transient cases, when the first over-voltage reading happens, the firmware will monitor the output voltage more closely. if a second over-voltage reading happens within 100 s, the firmware will flag this as an over-voltage event and not just as a transient condition. when an over-voltage fault event oc curs, the firmware will send out a short pwm pulse and toggle the sre signal to latch the sync fet on. this will make sure that the driver w ill try to pull down the over voltage actively through the sync fet. the UCD9112 offers programmable output over voltage protection. the firmware can be configured to monitor (and act upon) ovp faults and warnings in dependently. if this condition occurs, the UCD9112 will take the action configured through the pmbus response commands shown below. the pmbus commands that support this functionality are: vout_ov_warn_limit vout_ov_fault_limit vout_ov_fault_response
UCD9112 september 2006 22 www.ti.com for output under voltage warnings , the vout_ov_warn_limit command sets the voltage at which an output under voltage warning will occur. for output under voltage faults , the vout_uv_fault_limit command sets the voltage at which an output under voltage fault will occur. in this event, t he vout_uv_fault_response command spec ifies the action to be taken. when an ovp fault occurs, the vout_ov_fault_respon se register instructs the system how to react. there are two response bits that instruct the system what to do in the event of these failures. 6.3.4 output under voltage protection (vo_uvp) when a fault condition is detected, the pmbus alert signal is asserted to the host controller to announce this event. the latency between the under voltage faul t event and the pmbus alert to the host is 1 ms. after this event has occurred, the system reacts acco rding to the configuration according to the response commands below. the latency between the under voltage fault event happening and the UCD9112 taking the configured action is 10 ms. the output under voltage warning does not raise the pmbus alert signal. the latency between when output under voltage warning threshold being crossed and the UCD9112 taking the configured action is 10 ms. the pmbus commands that support this functionality are: vout_uv_warn_limit vout_uv_fault_limit vout_uv_fault_response for output under voltage warnings , the vout_uv_warn_limit command specifies the value of the output voltage that will cause an under voltage warning. for output under voltage faults , the vout_uv_fault_limit command specifies the value of the output voltage that will cause an under voltage fault. the vout_uv_fault_response command will specify the action to be taken should this event occur. when an output under voltage fault occurs, the vout_u v_fault_response register instructs the system how to react. there are two response bits that instruct the system what to do in t he event of these failures. 6.3.5 output over current protection (io_ocp) the UCD9112 cooperated with the ucd7230 drive monito rs the output current and provides output current protection. current is sensed either by the top fet? s rdson or by dcr of the output inductor. there are two different sensing methods and two different protections. first, by sensing the current of top mosfet, the cycl e-by-cycle current is obtained on ucd7230. the peak current is compared to the peak current threshold set by external resistors. if the pe ak current of top fet is higher than the set point, the gate drive pulse is cut o ff, and the top fet is immediately turned off. in the event the output is short and the current increases ex tremely fast, this pulse-by-pulse protection can take actions immediately to avoid the damage of the power converter. when over current happens, the output of clf is set and kept high until the next switching cy cle. the UCD9112 counts the number of clf low to high transitions. if over current continues for multiple switch ing cycles greater than the limit set in the UCD9112,
UCD9112 sepember 2006 23 www.ti.com the decision will be made by UCD9112 to s hut off the dpwm outputs. the converter is going to enter hiccup mode or latched-off mode. second, the output current is also obtained by me asuring the voltage across the dcr of each output inductor. by properly selecting rc network that is conne cted in parallel with the output inductor, the output inductor current is sensed and fed to the uc d7230. the UCD9112 prov ides current limit (i lim ) threshold to the ucd7230 through a filtered pwm output. the sensed voltage across the dcr of each output inductor is compared to i lim using a high speed comparator in the ucd7230. if the ics > i lim , the clf is set. the UCD9112 counts the number of clf high to low transitions. the converter enters hiccup or latched-off mode after the number of clf pulses is more than the limit set in the UCD9112. the current limit threshold i lim and the number of clf pulses are programmable through pmbus. the pmbus commands that support this functionality are: iout_oc_warn_limit iout_oc_fault_limit iout_oc_fault_response mfr_specific_01 for over current warnings, the iout_oc_warn_limit command specifies the current at which the over current warning occurs. for over current faults, the iout_oc_fault_limit command specifies the current at which the over current fault occurs. when this event occurs, the iout_oc_fault_respon se command specifies the action to be taken by the system. the number of current limit flags to accept befor e taking action can be configured by using the mfr_specific_01 command. the 16b data value from this command will represent the number of clf events. the inductor current of phase0 and phase1 are amplif ied in the ucd7230. then, the current of each phase is input to UCD9112 on the iout_0 and iout_1. the software will monitor the output current and send warning signal if the current is over limit. 6.3.6 over temperature protection (otp) the UCD9112 supports over temperature protection warn ings and faults. there is a temperature sensor in the UCD9112 that is used for sensing over temperat ure events. the temperature sensor is calibrated according to a calculation based on current output and the power scale using a manufacturer specific command. the latency between over temperatur e events and system reaction time is 20ms. the pmbus commands to support this functionality are: ot_warn_limit ot_fault_limit ot_fault_response mfr_specific_02
UCD9112 september 2006 24 www.ti.com for over temperature warnings, the ot_warn_limit command specifies the temperature at which the power supply will indicate an over temperature warning alarm. for over temperature faults, the ot_fault_limit comma nd specifies the temperature at which the power supply will indicate a fault. t he ot_fault_response command specifies the action to be taken in the event of a temperature fault c ondition in the power supply. the mfr_specific_02 command will be used to calibra te the temperature repo rted by the temperature sensor on the UCD9112. when an over-temperature fault occurs, the ot_fau lt_response register instructs the system how to react. there are two response bits that instruct the system what to do in the event of these failures. 6.4 status & fault reporting commands the UCD9112 controller supports stat us and fault reporting, for maintenance of an operating supply. the pmbus commands are listed below: status_byte status_word status_vout status_iout status_input status_temperature status_cml clear_faults status_byte command returns one byte of informati on with a summary of the most critical faults. status_word command returns two bytes of informat ion with a summary of the unit fault condition. status_vout command returns one byte information of output voltage status_iout command returns one by te information of output current status_input command returns one byte information of input voltage status_temperarue command returns one byte information of temperature clear_fault command clears any set faults 6.5 non-volatile storage commands the UCD9112 supports storing configuration valued to it?s non-volatile memory. the latency for this operation is 1 second. the pmbus commands that support this functionality are: store_default_all restore_default_all
UCD9112 sepember 2006 25 www.ti.com store_default_code restore_default_code store_user_all restore_user_all store_user_code restore_user_code the store_default_all command stores all default va lues in the system to non-volatile memory. the restore_default_all command will set all operational values to the values stored in non-volatile memory. the store_default_code command w ill store the given value for the given command to non-volatile memory. the restore_default_code restore the gi ven value for the given command to operational memory from non-volatile memory. the store_user_all command stores all user valu es in the system to non-volatile memory. the restore_user_all command will restore all user va lues from non-volatile memory to operational memory. the store_user_code command will store the given value for the given user command to non-volatile memory. the restore_ user_code will restore the gi ven value for the given command from non-volatile memory to operational memory. 6.5 host data storage commands the pmbus commands to support this functionality are: mfr_id mfr_model mfr_revision mfr_date mfr_serial the mfr_id, mfr_model, mfr_revision, mfr_da te and mfr_serial commands will be used by the firmware to store that appropriate data from the release of the UCD9112 and driver, as well as firmware for the application. 7 dual phase current balancing UCD9112 uses two pins, pin iout_0 a nd iout_1, to sense the output cu rrent of each phase. the current accuracy is important because the curr ent values are used for current balan ce. dcr of output inductor varies with temperature and is compensated for temperature changes by the UCD9112. an assumption that is
UCD9112 september 2006 26 www.ti.com made is that the internal temperature of the device is equivalent to the temperature of each inductor. the current balancing is implemented through the software. the current balancing condition is reported to the host. the below requirement of current balancing can be met for UCD9112 dual phase application. table 7-1. current balancing of two phases test condition at 25c. output total current two phase current difference 0% to 30%, 0a to 12a tbd 30% to 50%, 12a to 20a tbd 50% to 100%, 20a to 40a tbd 8 gui UCD9112 provides gui (graphic user interface) for t he user to configure pol operating condition. the functionality of gui supporting UCD9112 is based on the pmbus specifications compliance. the key functions of gui are listed below: - pid coefficients programming - pol on/off - vout set point - converter switching frequency set - output voltage soft start and soft stop - read output voltage - read output current - read input voltage - read temperature - fault threshold configuration - manufacturing information storage more information is provided on the gui user?s manual. figure 6 is the front picture of gui shown before users.
UCD9112 sepember 2006 27 www.ti.com figure 8-1. example gui interface for pol configuration
UCD9112 september 2006 28 www.ti.com figure 8-2. example gui design tool 9 package information the UCD9112 is available in texas instruments? 32-pin powerpad tm plastic quad flatpack package. figure 9-1. 32-pin powerpad tm qfn package
UCD9112 sepember 2006 29 www.ti.com

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