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document no. s15677ej1v0ds00 (1st edition) date published may 2002 ns cp(k) printed in japan source driver for 240-output tft-lcd (navigation, automobile lcd-tv) data sheet mos integrated circuit pd16449 the mark shows major revised points. 2001 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description pd16449 is a source driver for tft liquid crystal panels. this ic consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. in addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the lcd panel. it is ideal for a wide range of applications, including navigation systems and automobile lcd-tvs. features ? can be driven on 5 v (dynamic range: 4.3 v, v dd2 = 5.0 v) ? 240-output ? f clk = 15 mhz max. (v dd1 = 3.0 v) ? simultaneous/successive sampling selectable according to pixel array simultaneous sampling: vertical stripe successive sampling: delta array, mosaic array ? two sample and hold circuits ? low output deviation between pins ( 20 mv max.) ? stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit ? left and right shift selected by r,/l pin ? tcp/cog mounting possible remark /xxx indicates active low si gnal. ordering information part number package pd16449n-xxx tcp pd16449p chip remark purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
data sheet s15677ej1v0ds 2 pd16449 1. block diagram 240-bit bidirectional shift register level shifter sample and hold sthr h 1 sthl r,/l cli1 to cli3 v dd1 v ss1 c 1 c 2 c 3 mp/th v dd2 v ss2 h 2 h 3 h 240 inh multiplexer c1 c2 c3 mp/1.5 reset c 239 c 240 2. sample and hold circuit and output circuit swb1 swa1 c h1 swb2 swa2 c h2 h n video line + +
data sheet s15677ej1v0ds 3 pd16449 3. pin configuration h 240 h 239 v ss1 cli3 test sthr reset inh cli1 cli2 sthl mp/th mp/1.5 r,/l v dd2 v ss1 v dd1 c1 c2 c3 0 y(+) x(+) v ss2 dummy h 2 h 1 dummy dummy dummy dummy dummy dummy dummy dummy dummy v ss2 v ss2 v ss2 v ss2 v ss2 c1 c1 c2 c2 c3 c3 v dd2 v dd2 v dd1 v dd1 sthl sthl mp/th mp/th mp/1.5 mp/1.5 r,/l r,/l v ss1 dummy reset reset inh inh cli1 cli1 cli2 cli2 cli3 cli3 test test sthr
data sheet s15677ej1v0ds 4 pd16449 table 3 ? ? ? ? 1. pad layout (1/3) no. pad name x [
data sheet s15677ej1v0ds 5 pd16449 table 3 ? ? ? ? 1. pad layout (2/3) no. pad name x [
data sheet s15677ej1v0ds 6 pd16449 table 3 ? ? ? ? 1. pad layout (3/3) no. pad name x [
data sheet s15677ej1v0ds 7 pd16449 4. pin functions symbol pin name pad no. i/o description c1 to c3 video signal input 1 to 3, 4 to 6, 7 to 9 input input r, g, and b video signals. h 1 to h 300 video signal output 65 to 304 output video signal output pins. output sampled and held video signals during horizontal period. sthr, sthl cascade i/o 46, 47 16 to 18 i/o start pulse i/o pins of sample hold timing. sthr serves as an input pin and sthl, as an output pin, in the case of right shift. in the case of left shift, sthl serves as an input pin, and sthr, as an output pin. cli1 to cli3 shift clock input 34 to 38, 37 to 39, 40 to 42 input a start pulse is read at the rising edge of cli1. sampling pulse shpn is generated at the rising edge of cli1 through cli3 during successive sampling, and at the rising edge of cli1 during simultaneous sampling (for details, refer to the timing charts in 5. functional description ). inh inhibit input 31 to 33 input selects a multiplexer and one of the two sample and hold circuits at the falling edge. reset reset input 28 to 30 input resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. after reset, the multiplexer is turned off, so sure to input one pulse of the inh signal before inputting the video signal. if the video signal is input without the inh signal, sampling is not executed. four types of color filter arrays can be supported by combination of mp/th and mp/1.5. mode mp/th mp/1.5 mp/th multiplexer circuit select input (1) 19 to 21 input vertical stripe array l l single-side delta array l h mosaic array h l double-side delta array h h mp/1.5 multiplexer circuit select input (2) 22 to 24 input r,/l shift direction select input 25 to 27 input r,/l = h: right shift: sthr h 1 h 240 sthl r,/l = l: left shift: sthl h 240 h 1 sthr v dd1 logic power supply 13 to 15 ? 3.0 to 5.5 v v dd2 driver power supply 10 to 12 ? 5.0 v 0.5 v v ss1 logic ground 49 to 51 ? connect this pin to ground of system. v ss2 driver ground 52 to 57 ? connect this pin to ground of system. test test 43 to 45 ? fix this pin to low level. dummy dummy 48, 58 to 64, 305 to 311 ? no dummy pins are connected with other pins inside ic.
data sheet s15677ej1v0ds 8 pd16449 5. functional discription 5.1 multiplexer circuit this circuit selects rgb video signals input to the c1 to c3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the h 1 through h 240 pins. vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the mp/th and mp/1.5 pins. 5.1.1 vertical stripe array mode (mp/th = l, mp/1.5 = l) in this mode, the relation between video signals c1 to c3, and output pins is as shown below. this mode is used to drive a panel of vertical stripe array. in this mode, the multiplexer circuit is in the through status. table 5 ? ? ? ? 1. relation between video signals c1 to c3, and output pins (during right shift) line no. (number of inhn) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )...h 239 (h 2 )h 240 (h 1 ) 0hl sampling c1 (c3) sampling c2 (c2) sampling c3 (c1) sampling c1 (c3) ... sampling c2 (c2) sampling c3 (c1) 1l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 2l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 3l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 ? ? ? ? 1. pixel arrangement of vertical stripe array and multiplexer operation r r r r r b b b b b g g g g g r r r r r b b b b b g g g g g r r r r r h 7 h 6 h 5 h 4 h 3 h 2 h 1 c1 c2 c3 r b g pd16449 right shift (r,/l = "h"), mp/th = "l", mp/1.5 = "l"
data sheet s15677ej1v0ds 9 pd16449 figure 5 ? ? ? ? 2. timing chart of vertical stripe array undifined undifined c1 (c3) reset inh h 1 (h 240 ) sampling input data output ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h 2 (h 239 ) sampling input data h 3 (h 238 ) sampling inputdata h 239 (h 2 ) sampling input data h 240 (h 1 ) sampling input data output output output output c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15677ej1v0ds 10 pd16449 5.1.2 single-side delta array mode (mp/th = l, mp/1.5 = h) table 5 ? ? ? ? 2. relation between video signals c1 to c3, and output pins line no. (number of inhn) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )...h 239 (h 2 )h 240 (h 1 ) 0 h l undefined undefined undefined undefined ... undefined undefined 1l sampling c1 (c3) sampling c2 (c2) sampling c3 (c1) sampling c1 (c3) ... sampling c2 (c2) sampling c3 (c1) 2l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 3l output c2 (c1) output c3 (c3) output c1 (c2) output c2 (c1) ... output c3 (c3) output c1 (c2) 4l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 5l output c2 (c1) output c3 (c3) output c1 (c2) output c2 (c1) output c3 (c3) output c1 (c2) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 ? ? ? ? 3. pixel arrangement of single-side delta array and multiplexer operation r r r b b b g g g r r r b b b g g g r r r r b g r b g r h 7 h 6 h 5 h 4 h 3 h 2 h 1 c1 c2 c3 r b g pd16449 right shift (r,/l = "h"), mp/th = "l", mp/1.5 = "h" bgrbg bg r bgrbg bg r bgrbg bg r
data sheet s15677ej1v0ds 11 pd16449 figure 5 ? ? ? ? 4. timing chart of single-side delta array reset inh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h 1 (h 240 ) sampling input data output h 2 (h 239 ) sampling input data h 3 (h 238 ) sampling inputdata h 239 (h 2 ) sampling input data h 240 (h 1 ) sampling input data output output output output c1 (c3) c1 (c3) c2 (c1) c2 (c1) undifined undifined undifined undifined c1 (c3) c1 (c3) c2 (c1) c2 (c1) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c3 (c1) c3 (c1) c1 (c2) c1 (c2) c3 (c1) c3 (c1) c1 (c2) c1 (c2) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c3 (c1) c3 (c1) c1 (c2) c1 (c2) c3 (c1) c3 (c1) c1 (c2) c1 (c2) undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15677ej1v0ds 12 pd16449 5.1.3 double-side delta array mode (mp/th = h, mp/1.5 = h) because the pad pitch of the pd16449 is designed so that the ic is mounted on one side, the output pitch must be expanded on the tcp if the ic is mounted on both sides. table 5 ? ? ? ? 3. relation between video signals c1 to c3 and output pins line no. (number of inhn) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )...h 239 (h 2 )h 240 (h 1 ) 0 h l undefined undefined undefined undefined ... undefined undefined 1l sampling c2 (c3) sampling c3 (c2) sampling c1 (c1) sampling c2 (c3) ... sampling c3 (c2) sampling c1 (c1) 2l output c2 (c3) output c3 (c2) output c1 (c1) output c2 (c3) ... output c3 (c2) output c1 (c1) 3l output c1 (c1) output c2 (c3) output c3 (c2) output c1 (c1) ... output c2 (c3) output c3 (c2) 4l output c2 (c3) output c3 (c2) output c1 (c1) output c2 (c3) ... output c3 (c2) output c1 (c1) 5l output c1 (c1) output c2 (c3) output c3 (c2) output c1 (c1) ... output c2 (c3) output c3 (c2) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 ? ? ? ? 5. pixel arrangement of double-side delta array and multiplexer operation r r r b b b g g g r r r b b b g g g r r r h 4 h 3 h 2 h 1 c1 c2 c3 r b g pd16449 right shift (r,/l = "h"), mp/th = "h", mp/1.5 = "h" h 237 h 238 h 239 h 240 c1 c2 c3 g r b pd16449 left shift (r,/l = "l"), mp/th = "h", mp/1.5 = "h" bgrbg bg r bgrbg bg r
data sheet s15677ej1v0ds 13 pd16449 figure 5 ? ? ? ? 6. timing chart of both-sides delta array reset inh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h 1 (h 240 ) sampling input data output h 2 (h 239 ) sampling input data h 3 (h 238 ) sampling inputdata h 239 (h 2 ) sampling input data h 240 (h 1 ) sampling input data output output output output c2 (c3) c2 (c3) c1 (c1) c1 (c1) undifined undifined undifined undifined c2 (c3) c2 (c3) c1 (c1) c1 (c1) c3 (c2) c3 (c2) c2 (c3) c2 (c3) c3(c2) c3 (c2) c2 (c3) c2 (c3) c1 (c1) c1(c1) c3 (c2) c3 (c2) c1 (c1) c1 (c1) c3 (c2) c3 (c2) c3 (c2) c3 (c2) c2 (c3) c2 (c3) c3 (c2) c3 (c2) c2 (c3) c2 (c3) c1 (c1) c1 (c1) c3 (c2) c3 (c2) c1 (c1) c1 (c1) c3 (c2) c3 (c2) undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15677ej1v0ds 14 pd16449 5.1.4 mosaic array mode (mp/th = h, mp/1.5 = l) table 5 ? ? ? ? 4. relation between video signals c1 to c3, and output pins line no. (number of inhn) reset inh h 1 (h 240 )h 2 (h 239 )h 3 (h 238 )h 4 (h 237 )...h 239 (h 2 )h 240 (h 1 ) 0 h l undefined undefined undefined undefined ... undefined undefined 1l sampling c1 (c3) sampling c2 (c2) sampling c3 (c1) sampling c1 (c3) ... sampling c2 (c2) sampling c3 (c1) 2l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 3l output c3 (c2) output c1 (c1) output c2 (c3) output c3 (c2) ... output c1 (c1) output c2 (c3) 4l output c2 (c1) output c3 (c3) output c1 (c2) output c2 (c1) ... output c3 (c3) output c1 (c2) 5l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 ? ? ? ? 7. pixel arrangement of mosaic array and multiplexer operation r b g r b g r b g r b g r b g r b g r b g r b g r b g r b g r b g r b h 7 h 6 h 5 h 4 h 3 h 2 h 1 c1 c2 c3 r g b pd16449 right shift (r,/l = "h"), mp/th = "h", mp/1.5 = "l"
data sheet s15677ej1v0ds 15 pd16449 figure 5 ? ? ? ? 8. timing chart of mosaic array reset inh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h 1 (h 240 ) sampling input data output h 2 (h 239 ) sampling input data h 3 (h 238 ) sampling inputdata h 239 (h 2 ) sampling input data h 240 (h 1 ) sampling input data output output output output c1 (c3) c1 (c3) c3 (c2) c3 (c2) undifined undifined undifined undifined c2 (c1) c2 (c1) c1 (c3) c1 (c3) c2 (c2) c2 (c2) c1 (c1) c1 (c1) c3(c3) c3 (c3) c2 (c2) c2 (c2) c3 (c1) c3(c1) c2 (c3) c2 (c3) c1 (c2) c1 (c2) c3 (c1) c3 (c1) c2 (c2) c2 (c2) c1 (c1) c1 (c1) c3 (c3) c3 (c3) c2 (c2) c2 (c2) c3 (c1) c3 (c1) c2 (c3) c2 (c3) c1 (c2) c1 (c2) c3 (c1) c3 (c1) undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15677ej1v0ds 16 pd16449 5.1.5 relation between shift clock clin and internal sampling pulse shpn (1) simultaneous sampling ( ( ) indicates the case of left shift.) c1 sampling c2 sampling c3 sampling shp 1 (shp 240 ) sthr (sthl) cli1 shp 2 (shp 239 ) shp 3 (shp 238 ) shp 4 (shp 237 ) shp 5 (shp 236 ) shp 6 (shp 235 ) c1 sampling c2 sampling c3 sampling remark c1 through c3 are sampled while shpn is high level. (2) successive sampling ( ( ) indicates the case of left shift.) c1 sampling 3-phase clock c2 samling c3 sampling c1 sampling c2 sampling c3 sampling shp 1 (shp 240 ) sthr (sthl) cli3 cli2 cli1 shp 2 (shp 239 ) shp 3 (shp 238 ) shp 4 (shp 237 ) shp 5 (shp 236 ) shp 6 (shp 235 ) ? ? ? ? ? ? ? ? ? remarks 1. input a three-phase clock to shift clock pins cli1 through cli3. 2. the video signals (c1 to c3) are sampled while shpn is high level.
data sheet s15677ej1v0ds 17 pd16449 5.2 sample and hold circuit the sample and hold circuit samples and holds the video input signals c1 through c3 selected by the multiplexer circuit in the timing shown below. swa1 through swb2 are reset by the reset signal and change at the rising and falling edges of the inh signal (refer to 1. block diagram .). reset data swa1 swa2 swb1 swb2 inh undifined on on undifined 5.3 write operation timing the sampled video signals are written to the lcd panel by output currents i vol and i voh via output buffer. the dynamic range is 4.3 v min. (v dd2 = 5.0 v). while inh = h, do not stop shift clocks cli1 through cli3. the output operation of this ic is controlled by inh signals. inh = hi-z inh = connected with internal circuit (switch sample and hold circuit at the falling edge.) therefore, performing v com inversion while inh = l causes current flow to these ic output pins, which may result in malfunction. perform v com in version during inh = h (hi-z) and start output operation of the next line after the v com signal is stable enough to operate. make sure to evaluate this output operation sufficiently.
data sheet s15677ej1v0ds 18 pd16449 cautions 1. turn on power to v dd1 , logic input, v dd2 , and video signal input in that order to prevent destruction due to latch-up, and turn off power in the reverse sequence. observe this power sequence even during the transition period. 2. the pd16449 is designed to input successive signals such as chrome signals. the input band of the video signals is designed to be 9 mhz max. if video signals faster than that are input, display is not performed correctly. 3. insert a bypass capacitor of 0.1 f between v dd1 and v ss1 and between v dd2 and v ss2 . if the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. 4. display may not be correctly performed if noise is superimposed on the start pulse pin. therefore, be sure to input a reset signal during the vertical blanking period. 5. even if the start pulse width is extended by half a clock or more, sampling start timing shp 1 is not affected, and the sampling operation is performed normally. 6. when the multiplexer circuit is used in the vertical stripe mode, c1 to c3 are simultaneously sampled at the rising edge of shpn. internally, however, only cli1 is valid. therefore, input a shift clock to cli1 only. at this time, keep the cli2 and cli3 pins to "l". when using the multiplexer circuit in the delta array mode or mosaic array mode, c1 to c3 are sequentially sampled. input a three-phase clock to cli1 through cli3 (for the sampling timing, refer to 5. functional description.). 7. the recommended timing of t r-1 and pw res on starting is shown below (the following timing chart shows simultaneous sampling.). an inh pulse width of at least 5 clocks is required to reset the internal logic. unless the inh pulse is input after reset, sampling is not performed in the correct sequence. cli1 reset inh sthr (sthl) shp 1 to shp 3 shp 4 to shp 6 shp 7 to shp 9 12345 123 pw res t isetup t ihold t r?i pw inh : 5 clocks min. 3 clocks min.
data sheet s15677ej1v0ds 19 pd16449 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = 0 v) parameter symbol condition ratings unit logic supply voltage v dd1 ? 0.5 to +6.0 v driver supply voltage v dd2 ? 0.5 to +6.0 v logic input voltage v i ? 0.5 to v dd1 +0.5 v video input voltage v vi c1 to c3 ? 0.5 to v dd2 +0.5 v logic output voltage v 01 ? 0.5 to v dd1 +0.5 v driver output voltage v 02 ? 0.5 to v dd2 +0.5 v driver output current i o2 10 ma operating temperature range t a ? 30 to +85 c storage temperature range t stg ? 65 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = ?40 to +85 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic supply voltage v dd1 3.0 3.3 5.5 v driver supply voltage v dd2 4.5 5.0 5.5 v video input voltage v vi v ss2 + 0.35 v dd2 ? 0.35 v driver output voltage v 02 v ss2 + 0.35 v dd2 ? 0.35 v high level input voltage v ih 0.7 v dd1 v dd1 v low level input voltage v il 00.3 v dd1 v
data sheet s15677ej1v0ds 20 pd16449 electrical characteristics (t a = ? ? ? ? 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit maximum video signal output voltage v voh v dd 2 ? 0.35 v minimum video signal output voltage v vol 0.35 v logic high level output voltage v loh sthl, sthr pins, i oh = ? 1.0 ma 0.9 v dd1 v logic low level output voltage v lol sthl, sthr pins i ol = 1.0 ma 0.1 v dd1 v video signal high level output current v voh i nh = l, v of = v dd2 ? 1.0 v v o = v dd2 ? 0.5 v ? 0.20 ? 0.08 ma video signal low level output current v vol i nh = l, v of = 1.0 v, v o = 0.5 v 0.08 0.20 ma reference voltage 1 v ref1 v dd2 = 5.0 v, t a = 25 c, v vi = 0.5 v 0.49 v reference voltage 2 v ref2 v dd2 = 5.0 v, t a = 25 c, v vi = 2.0 v 1.99 v reference voltage 3 v ref3 v dd2 = 5.0 v, t a = 25 c, v vi = 3.5 v 3.49 v output voltage deviation 1 ? v vo1 v dd2 = 5.0 v, t a = 25 c, v vi = 0.5 v 20 mv output voltage deviation 2 ? v vo2 v dd2 = 5.0 v, t a = 25 c, v vi = 2.0 v 20 mv output voltage deviation 3 ? v vo3 v dd2 = 5.0 v, t a = 25 c, v vi = 3.5 v 20 mv logic input leakage current i ll 1.0 a video input leakage current i vl 10 a v dd1 = 3.3 v 0.3 v 2.5 ma logic dynamic current consumption i dd1 f cli = 14 mhz v vi = 2.0 v, no load, f inh = 15.4 khz, pw inh = 5.0 s v dd1 = 5.0 v 0.5 v 4.0 ma driver dynamic current consumption i dd2 f cli = 14 mhz v vi = 2.0 v, no load, f inh = 15.4 khz, pw inh = 5.0 s 10.0 ma remarks 1. v of : output applied voltage, v o : output voltage without load 2. the reference values are typical values only. the output deviation is only guaranteed within the chip.
data sheet s15677ej1v0ds 21 pd16449 switching characteristics (t a = ? ? ? ? 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit t phl c l = 20 pf 10 54 ns start pulse propagation delay time t plh c l = 20 pf 10 54 ns clock frequency 1 f clk 1 15 mhz clock frequency 2 f clk 2 with 3-phase clock input 8 mhz logic input capacitance c i1 other than sthl, sthr 15 pf sthl, sthr input capacitance c i2 sthl, sthr 20 pf video input capacitance c 3 c1 to c3, v vi = 2.0 v 50 pf timing requirements (t a = ? ? ? ? 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pw cli duty = 50% 33 ns start pulse setup time t setup 8ns start pulse hold time t hold 8ns reset pulse width pw res 66 ns inh setup time t isetup 33 ns inh hold time t ihold 33 ns reset-inh time t r-i 81 ns inh pulse width pw inh 5clk remark keep the rise and fall times of the logic input signals to within t r = t f = 5 ns (10 to 90%). as an example, the switching characteristic wave of cli1 is defined on the next page.
data sheet s15677ej1v0ds 22 pd16449 switching characteristic waveform (simultaneous/successive sampling) start pulse input timing 1/f cli 1 pw cli 1pw cli 1 50% 50% 50% 50% t setup t hold cli1 sthr (sthl) shp 1 (shp 240 ) v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 start pulse output timing 50% 50% t plh 50% 50% t phl cli1 sthl (sthr) v dd1 v ss1 v oh v ol remark the input/output timing of the start pulse is the same for simultaneous/successive sampling.
data sheet s15677ej1v0ds 23 pd16449 reset inh pulse timing cli1 reset inh pw res t isetup t iihold pw inh t r-i 50% 50% 50% 50% 50%
data sheet s15677ej1v0ds 24 pd16449 [memo]
data sheet s15677ej1v0ds 25 pd16449 [memo]
data sheet s15677ej1v0ds 26 pd16449 [memo]
data sheet s15677ej1v0ds 27 pd16449 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16449 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of may, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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