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preliminary technical data preliminary technical data rev. prf 09/2003 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5380 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2003 14 dac reg 0 vout 0 ldac clr wr/(dcen/ad1) fifo en busy interface control logic avdd (x5) dvdd (x3) dgnd (x3) + 14 input reg 0 14 m reg0 c reg0 14 14 14 agnd (x5) + input reg 6 14 m reg6 14 14 14 x + - c reg6 14 14 dac 6 dac reg 6 vout 5 + input reg 7 14 m reg7 c reg7 14 vout 1 vout 4 14 dac reg 7 14 vout 7 vout 8 vout 38 vout 2 vout 3 ad5380 x5 x x vout 6 14 14 dac 0 dac 7 + input reg 1 14 m reg1 14 14 14 x c reg1 14 14 dac 1 dac reg 1 . . . . . . . . . . . . . . . . . . + - + - + - . . . power-on reset fifo + state machine + control logic reset db10 db0 . db13 /(din/sda) a0 a5 cs/( sync/ad0) reg0 reg1 ser/par 2.5v reference refout/ refin db12 /(sclk/scl) pd r r r r r r r r signal gnd (x5) refgnd dac gnd (x5) sdo(a/b) db11 /(spi/i2c) 39 -to-1 mux vout 0 .......... vout 38 vout 39 / mon_out 40-channel, 3v/5v single supply, 14-bit, voltage-output dac features guaranteed monotonic inl error: 4lsb max on-chip 1.25/2.5v, 10ppm/c reference temperature range: -40c to +85c rail to rail output amplifier package type: 100-lead lqfp (14mm x 14mm) user interfaces: parallel, serial (spi, qspi, microwire and dsp compatible featuring data readback) i2c compatible interface integrated functions channel monitor simultaneous output update via ldac ldac ldac ldac ldac clear function to user programmable code amplifier boost mode to optimize slew rate user programmable offset and gain adjust toggle mode: enables squarewave generation applications variable optical attenuators (voa) level setting optical microelectromechanical systems (mems) control systems general description the ad5380 is a complete single supply, 40-channel, 14- bit dac available in 100-lead lqfp package. all 40-channels have an on-chip output amplifier with rail-to- rail operation. the ad5380 includes an internal 1.25/ 2.5v, 10ppm/c reference, an on-chip channel monitor function that multiplexes the analog outputs to a common mon_out pin for external monitoring and an output amplifier boost mode that allows the amplifier settling time to be optimized. the ad5380 contains a double buffered parallel interface featuring a wr pulse width of 20ns, a serial interface compatible with spi tm , qspi tm , microwire tm and dsp interface standards with interface speeds in excess of 30mhz and an i2c compatible interface supporting 400khz data transfer rate. an input register followed by a dac register provides double buffering allowing the dac outputs to be updated independantly or simultaneously using the ldac input. each channel has a programmable gain and offset adjust register allowing the user to fully calibrate any dac channel. power consumption is typically 0.3ma/channel. *protected by u.s. patent nos. 5,969,657; other patents pending. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. functional block diagram
preliminary technical data rev. prf 09/2003 ?2? parameter ad5380-5 1 units test conditions/comments accuracy resolution 14 bits relative accuracy 3 4 lsb max differential nonlinearity -1/+2 lsb max gu aranteed monotonic over temp zero-scale error 10 mv max offset error 10 mv max measured at code 32 in the linear region offset error tc 5 uv/c typ gain error 0.02 % fsr max gain temperature coefficient 2 20 ppm fsr/c typ dc crosstalk 2 0.5 lsbmax referenceinput/output reference input 2 reference input voltage 2.5 v 1% for specified performance dc input impedance 1 m ? min typically 100 m ? input current 1 0 a max typically 30 na reference range 1/v dd /2 v min/max reference output 4 output voltage 2.495/2.505 v min/max at ambient 1.248/1.252 v min/max reference tc 1 0 ppm /c typ output characteristics 2 output voltage range 3 0/av dd v min/max short circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l =5k ? t b d pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ tristate leakage current 100 na typ logic inputs (except sda/scl) 2 dv dd = 2.7 v to 5.5 v v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 10 a max total for all pins. t a =t min to t max pin capacitance 10 pf max logic inputs (scl, sda only) v ih , input high voltage 0.7 dv dd v min smbus-compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus-compatible at dv dd < 3.6 v i in , input leakage current 1 a v hyst , input hysteresis 0.05 dv dd v c in , input capacitance 8 pf glitch rejection 50 ns i nput filtering suppresses noise spikes of less than 50 ns. logic outputs ( busy , sdo) 2 v ol, output low voltage 0.4 v max dv dd = 5v 10%, sinking 200a v oh, output high voltage dv dd -1 v min dv dd = 5v 10%, sourcing 200a v ol, output low voltage 0.4 v max dv dd = 2.7v to 3.6v, sinking 200a v oh, output high voltage dv dd -0.5 v min dv dd = 2.7v to 3.6v, sourcing 200a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a three-state output capacitance 8 pf ad5380-5?specifications (av dd = 4.5v to 5.5v ; dv dd =2.7v to 5.5v, agnd=dgnd = 0 v; c l = 200 pf to agnd; r l = 5k ? ? ? ? ? ; external refin=2.5v; all specifications t min to t max unless otherwise noted.)
preliminary technical data rev. prf 09/2003 ?3? ad5380 power requirements av dd 4.5/5.5 v min/max dv dd 2.7/5.5 v min/max power supply sensitivity 2 ? mid scale/ ? v dd -85 db typ ai dd 0.5 ma/channelmax outputs unloaded. boost off. xxma typ ai dd 0.57 m a/channelmax outputs unloaded. boost on. xxma typ di dd 5 ma max v ih = dv dd , v il = dgnd. xxma typ ai dd (power down) 5 ua max di dd (power down) 5 ua max power dissipation 125 mw max outputs unloaded. notes 1 ad5380-5 is calibrated using an external 2.5v reference. temperature range for all versions: -40c to +85c 2 guaranteed by characterization. not production tested. 3 accuracy guaranteed from vout = 10mv to av dd -50mv 4 default on the ad5380-5 is 2.5v.programmable to 1.25v via cr12 in the ad5380 control register but operating the ad5380-5 with a 1.25v reference will lead to degraded accuracy specifications. specifications subject to change without notice. ad5380-5 ?specifications (av dd = 4.5v to 5.5v ; dv dd =2.7v to 5.5v, agnd=dgnd = 0 v; c l = 200 pf to agnd; r l = 5k ? ? ? ? ? ; external refin=2.5v; all specifications t min to t max unless otherwise noted.) parameter all units test conditions/comments dynamic performance output voltage settling time 2 boost mode off, cr11=0 ad5380 8 s typ 1/4 scale to 3/4 scale change settling to 1lsb. 10 s max output voltage settling time 2 boost mode on, cr11=1 ad5380 3 s typ 1/4 scale to 3/4 scale change settling to 1lsb. 5 s max slew rate 2 0.7 v/s typ boost mode off, cr11=0 1.5 v/s typ b oost mode on, cr11=1 digital-to-analog glitch energy 12 nv-s typ glitch impulse peak amplitude 5 mv max channel-to-channel isolation 100 db typ see terminology dac-to-dac crosstalk 10 nv-s typ see terminology digital crosstalk 10 nv-s typ digital feedthrough 1 nv-s typ effect of input bus activity on dac output under test output noise 0.1 to 10hz 8 uv p-p typ output noise spectral density @ 1 khz 150 nv/(hz) 1/2 typ @ 10 khz 100 nv/(hz) 1/2 typ 1 guaranteed by design and characterization, not production tested. 2 the settling time and slew rate can be programmed via the current boost control bit (cr11 ) in the ad5380 control register. specifications subject to change without notice. ac characteristics 1 (av dd = 4.5v to 5.5v ; dv dd =2.7v to 5.5v; agnd = dgnd= 0 v; c l = 5k ? ? ? ? ? and 200 pf to agnd)
preliminary technical data rev. prf 09/2003 ?4? parameter ad5380-3 1 units test conditions/comments accuracy resolution 14 bits relative accuracy 3 4 lsb max differential nonlinearity -1/+2 lsb max gu aranteed monotonic over temp zero-scale error 10 mv max offset error 10 mv max measured at code 64 in the linear region offset error tc 5 uv/c typ gain error 0.02 % fsr max gain temperature coefficient 2 20 ppm fsr/c typ dc crosstalk 2 0.5 lsbmax referenceinput/output reference input 2 reference input voltage 1.25 v 1% for specified performance dc input impedance 1 m ? min typically 100 m ? input current 1 0 a max typically 30 na reference range 1 to av dd /2 v min/max reference output 4 output voltage 1.248/1.252 v min/max at ambient 2.495/2.505 v min/max reference tc 1 0 ppm /c typ output characteristics 2 output voltage range 3 0/av dd v min/max short circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l =5k ? t b d pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ tristate leakage current 100 na typ logic inputs (except sda/scl) 2 dv dd = 2.7 v to 3.6v v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 10 a max total for all pins. t a =t min to t max pin capacitance 10 pf max logic inputs (scl, sda only) v ih , input high voltage 0.7 dv dd v min smbus-compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus-compatible at dv dd < 3.6 v i in , input leakage current 1 a v hyst , input hysteresis 0.05 dv dd v c in , input capacitance 8 pf glitch rejection 50 ns i nput filtering suppresses noise spikes of less than 50 ns. logic outputs ( busy , sdo) 2 v ol, output low voltage 0.4 v max sinking 200a v oh, output high voltage dv dd -0.5 v min sourcing 200a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a three-state output capacitance 8 pf ad5380-3?specifications (av dd = 2.7v to 3.6v ; dv dd =2.7v to 5.5v, agnd=dgnd = 0 v; c l = 200 pf to agnd; r l = 5k ? ? ? ? ? ; external refin=1.25v; all specifications t min to t max unless otherwise noted.)
preliminary technical data rev. prf 09/2003 ?5? ad5380 power requirements av dd 2.7/3.6 v min/max dv dd 2.7/3.6 v min/max power supply sensitivity 2 ? mid scale/ ? v dd -85 db typ ai dd 0.5 ma/channelmax outputs unloaded. boost off. xxma typ ai dd 0.57 m a/channelmax outputs unloaded. boost on. xxma typ di dd 5 ma max v ih = dv dd , v il = dgnd. xxma typ ai dd (power down) 5 ua max di dd (power down) 5 ua max power dissipation 125 mw max outputs unloaded. notes 1 ad5380-3 is calibrated using an external 1.25v reference. temperature range is -40c to +85c. 2 guaranteed by characterization. not production tested. 3 accuracy guaranteed from vout = 10mv to av dd -50mv 4 default on the ad5380-3 is 1.25v. programmable to 2.5v via cr12 in the ad5380 control register but operating the ad5380-3 with a 2.5v reference will lead to degraded accuracy specifications and limited input code range. specifications subject to change without notice. ad5380-3?specifications (av dd = 2.7v to 3.6v ; dv dd =2.7v to 5.5v, agnd=dgnd = 0 v; c l = 200 pf to agnd; r l = 5k ? ? ? ? ? ; external refin=1.25v; all specifications t min to t max unless otherwise noted.) parameter all units test conditions/comments dynamic performance output voltage settling time 2 boost mode off, cr11=0 ad5380 8 s typ 1/4 scale to 3/4 scale change settling to 1lsb. 10 s max output voltage settling time 2 boost mode on, cr11=1 ad5380 3 s typ 1/4 scale to 3/4 scale change settling to 1lsb. 5 s max slew rate 2 0.7 v/s typ boost mode off, cr11=0 1.5 v/s typ b oost mode on, cr11=1 digital-to-analog glitch energy 12 nv-s typ glitch impulse peak amplitude 5 mv max channel-to-channel isolation 100 db typ see terminology dac-to-dac crosstalk 10 nv-s typ see terminology digital crosstalk 10 nv-s typ digital feedthrough 1 nv-s typ effect of input bus activity on dac output under test output noise 0.1 to 10hz 8 uv p-p output noise spectral density @ 1 khz 150 nv/(hz) 1/2 typ @ 10 khz 100 nv/(hz) 1/2 typ 1 guaranteed by design and characterization, not production tested. 2 the settling time and slew rate can be programmed via the current boost control bit (cr11 ) in the ad5380 control register. specifications subject to change without notice. ac characteristics 1 (av dd = 2.7v to 3.6v ; dv dd =2.7v to 5.5v; agnd = dgnd= 0 v; c l = 5k ? ? ? ? ? and 200 pf to agnd)
preliminary technical data rev. prf 09/2003 ?6? serial interface parameter 1,2,3 limit at t min, t max units description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 4 13 ns min 24th sclk falling edge to sync falling edge t 6 4 33 ns min minimum sync low time t 7 10 ns min minimum sync high time t 7a 50 ns min minimum sync high time in readback mode t 8 5 ns min data setup time t 9 4.5 ns min data hold time t 10 4,5 30 ns max 24th sclk falling edge to busy falling edge t 11 900 ns typ busy pulse width low (single channel update) t 12 4 20 ns min 24th sclk falling edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 100 ns max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 100 ns min ldac falling edge to dac output response time t 17 8 s typ dac output settling time, boost mode off. t 18 20 ns min clr pulse width low t 19 12 s max clr pulse activation time t 20 6,7 20 ns max sclk rising edge to sdo valid t 21 7 5 ns min sclk falling edge to sync rising edge t 22 7 8 ns min sync rising edge to sclk rising edge t 23 7 20 ns min sync rising edge to ldac falling edge notes 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and timed from a voltage level of 1.2 v. 3 see figures 3 and 4 4 stand-alone mode only. 5 this is measured with the load circuit of figure 1a. 6 this is measured with the load circuit of figure 1b. 7 daisy-chain mode only. specifications subject to change without notice. (dv dd = 2.7v to 5.5v ; av dd =+4.5v to +5.5v or +2.7v to +3.6v; agnd= dgnd = 0 v; ) all specifications t min to t max unless otherwise noted.) timing characteristics i ol 200ua i oh 200ua c l 50pf to output pin v oh (min) or v ol (max) c l 50pf r l 2.2k to output pin v ol v cc figure 1a load circuit for busy timing diagram figure 1b. load circuit for sdo timing diagram (serial interface, daisy-chain mode)
preliminary technical data rev. prf 09/2003 ad5380 ?7? figure 4. serial interface timing diagram (daisy-chain mode) input word for dac n db23 undefined db0 sdo t20 sclk sync din db23 t1 t4 db23' t21 t22 db0' db0 input word for dac n+1 input word for dac n 24 48 t13 t3 t2 t1 t7 t8 t9 ldac t23 figure 3. serial interface timing diagram (stand-alone mode) sclk sync din db23 db0 t4 t7 t6 1 2 24 clr v out t 19 t 18 24 t9 t8 t3 t2 t1 1 ldac active during busy 2 ldac active after busy ldac 1 t 10 ldac 2 v out 1 t 16 v out 2 busy t 11 t 12 t 13 t 13 t 15 t 14 t 17 t 17 t5 selected register data clocked out. db23 db0 db23' db0' 48 nop condition undefined sdo sclk sync din db23 db0 input word specifies register to be read 24 t 7a figure 3a. serial interface timing in data readback mode
preliminary technical data rev. prf 09/2003 ?8? ad5380 f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos-com patible) t 11 300 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos-compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line timing characteristics (dv dd = 2.7v to 5.5v ; av dd =+4.5v to +5.5v or +2.7v to +3.6v; agnd= dgnd = 0 v; ) all specifications t min to t max unless otherwise noted.) i2c serial interface parameter 1,2 limit at t min, t max units description notes 1 guaranteed by design and characterization, not production tested. 2 see figure 5 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of scl?s falling edge. 4 cb is the total capacitance of one bus line in pf. t r and t f measured between 0.3 vdd and 0.7 vdd. scl sda start condition t 9 t 3 t 4 t 6 t 2 t 5 t 7 t 8 t 1 t 4 t 11 t 10 repeated start condition stop condition figure 5. i2c compatible serial interface timing diagram
preliminary technical data rev. prf 09/2003 ad5380 ?9? parallel interface parameter 1,2,3 limit at t min, t max units description t 0 4.5 ns min reg0,reg1,address to wr rising edge setup time t 1 4.5 ns min reg0,reg1, address to wr rising edge hold time t 2 20 ns min cs pulse width low t 3 20 ns min wr pulse width low t 4 0 ns min cs to wr falling edge setup time t 5 0 ns min wr to cs rising edge hold time t 6 4.5 ns min data to wr rising edge setup time t 7 4.5 ns min data to wr rising edge hold time t 8 20 ns min wr pulse width high t 9 4 430 ns min minimum wr cycle time (single channel write) t 10 4 30 ns max wr rising edge to busy falling edge t 11 4,5 400 ns max busy pulse width low (single channel update) t 12 4 30 ns min wr rising edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 4 100 ns max busy rising edge to dac output response time t 15 20 ns min ldac rising edge to wr rising edge t 16 0 ns min busy rising edge to ldac falling edge t 17 4 100 ns min ldac falling edge to dac output response time t 18 8 s typ dac output settling time, boost mode off. t 19 20 ns min clr pulse width low t 20 12 s max clr pulse activation time (dv dd = 2.7 v to +5.5v; av dd =+4.5v to +5.5v or +2.7v to +3.6v; agnd = dgnd = 0 v; all specifications t min to t max unless otherwise noted.) notes 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and timed from a voltage level of 1.2 v. 3 see timing diagram in figure 6. 4 see table xxx. 5 this is measured with the load circuit of figure 1a. specifications subject to change without notice. timing characteristics figure 6. parallel interface timing diagram t 4 t 7 t 6 db13..db0 t 5 reg0, reg1, a5..a0 cs ldac 1 t 2 clr t 20 t 19 t 3 wr t 10 ldac 2 1 ldac active during busy 2 ldac active after busy v out 1 t 17 v out 2 t 8 busy t 11 t 12 t 13 t 13 t 16 t 14 t 18 t 18 v out t 9 t 1 t 0 t 15
preliminary technical data rev. prf 09/2003 ?10? ad5380 absolute maximum ratings 1,2 (t a = +25c unless otherwise noted) av dd to agnd...............................................-0.3 v to +7 v dv dd to dgnd..............................................-0.3 v to +7 v digital inputs to dgnd............-0.3 v to dv dd + 0.3 v sda/scl to dgnd..............................-0.3 v to + 7 v digital outputs to dgnd..........-0.3 v to dv dd + 0.3 v refin/refout to agnd......-0.3 v to av dd + 0.3 v agnd to dgnd................................-0.3 v to +0.3 v vout0-39 to agnd............... - 0.3 v to av dd + 0.3 v analog inputs to agnd............ - 0.3 v to av dd + 0.3 v operating temperature range commercial (b version).......................-40c to +85c storage temperature range...................-65c to +150c junctiontemperature (t j max).............................+150c 100-lead lqfp package, ja thermalimpedance.....................................44c/w reflow soldering peak temperature......................................................230c notes: 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100ma will not cause scr latch-up caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5380 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide linearity package package model resolution av dd output error (lsbs) description option range channels ad5380bst-5 14-bits +4.5v to +5.5v 40 4 100-lead lqfp st-100 AD5380BST-3 14-bits +2.7v to +3.6v 40 4 100-lead lqfp st-100 eval-ad5380eb ad5380 evaluation kit
preliminary technical data rev. prf 09/2003 ad5380 ?11? ad5380 (40-channel, 14-bit) pin configurations ad5380 pin function descriptions mnemonic function voutx buffered analog outputs for channel x. each analog output is driven by a rail to rail output amplifier operating at a gain of 2. each output is capable of driving an output load of 5k to ground. typical output impedance is 0.5 ohms. signal_gnd(1-5) analog ground reference points for each group of 8 output channels. all signal_gnd pins are tied together internally and should be connected to agnd plane as close as possible to the ad5380. dac-gnd (1-5) each group of 8 channels contains a dac_gnd pin. this is the ground reference point for the internal 14-bit dacs.these pins shound be connected to the agnd plane. agnd (1-5) analog ground reference point. each group of 8 channels contains an agnd pin. all agnd pins should be connected externally to the agnd plane. avdd (1-5) analog supply pins. each group of 8 channels has a separate avdd pin. these pins should be decoupled with 0.1uf ceramic capacitors and 10uf tantalum capacitors. operating range for the asd5380-5 is 4.5v to 5.5v and for the ad5380-3 is 2.7v to 3.6v dgnd ground for all digital circuitry. dvdd logic power supply; guaranteed operating range is 2.7 v to 5.5 v. recommended that these pins be decoupled with 0.1uf ceramic and 10uf tantalum capacitors to dgnd. ref-gnd ground reference point for the internal reference. refout/refin the ad5380 contains a common refout/ref in pin. when the internal reference is selected this pin is the reference output. if the application necessitates the use of an external reference, it can be applied to this pin and the internal reference disabled vis the control register. the default for this pin is a reference input. 94 93 92 91 90 89 88 87 86 85 84 83 82 81 db8 sdout(a/b) dgnd dgnd dgnd a5 a4 a3 a2 a1 a0 dvdd dvdd dvdd 97 96 95 c s /( s y n c / ad0) db13/(din/sda) db12/(sclk/scl ) db11/( spi / i 2 c ) db10 db9 100 99 98 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 fifo en clr vout 24 vout 25 vout 26 vout 27 signal_gnd4 dac_gnd4 agnd4 avdd4 vout 28 vout 29 vout 30 vout 31 ref gnd refout/refin signal_gnd1 dac_gnd1 avdd1 vout 0 vout 1 vout 2 vout 3 vout 4 agnd1 26 28 27 30 29 signal_gnd5 dac_gnd5 agnd5 avdd5 vout5 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 vout 6 vout 7 vout 32 vout 33 vout 34 vout 35 vout 36 vout 37 vout 38 vout 39/mon_ out vout 8 vout 9 vout 10 vout 11 vout 12 dac_gnd2 signal_gnd2 vout 13 vout 14 vout 15 76 77 78 79 80 ser/ p a r pd w r (dcen/ad1 ) l d a c b u s y 74 75 72 73 70 71 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 r e s e t db7 db6 db5 db4 db3 db2 db1 db0 reg0 reg1 vout 23 vout 22 vout 21 vout 20 avdd3 agnd3 dac_gnd3 signal_gnd3 vout 19 vout 18 vout 17 vout 16 avdd2 agnd2 pin 1 identifier top view (not to scale) ad5380
preliminary technical data rev. prf 09/2003 ?12? ad5380 vout39/mon_out this pin has a dual fun ction, it acts a a buffered output for channel 39 in default mode but when the monitor function is enabled this output acts as the output of a 39-to-1 channel multiplexer which can be programmed to multiplex one of channels 0 to 38 to the mon_out pin. the mon_out pins output impedance is typically 500 ohms and is intended to drive a high input impedance like that exhibited by sar adc inputs. ser/ par . interface select input. this pin allows the user to select whether the serial or parallel interface will be used. if it is tied high the serial interface mode is selected and pin 97 ( spi / i2c) is used to determine if the interface mode is spi or i2c. parallel interface mode is selected when ser/ par is low. cs /( sync /ad0) in parallel interface mode this pin acts as chip select input (level sensitive, active low). when low the ad5380 device is selected. serial interface mode: this is the frame synchronisation input signal for the serial interface. when taken low the internal counter is enabled to count the required number of clocks before the addressed register is updated. i2c mode: this pin acts as a hardware address pin used in conjunction with ad1 to determine the software address for the device on the i2c bus. wr /( dcen / ad1) multi function pin. in parallel interface mode acts as write enable and in serial interface mode acts as a daisy chain enable in spi mode and as a hardware address pin in i2c mode. parallel interface write input (edge sensitive). the rising edge of wr is used in conjunction with cs low and the address bus inputs to write to the selected device registers. serial interface: daisy-chain select input (level sensitive, active high). when high this signal is used in conjunction with ser/ par high to enable spi serial interface daisy-chain mode. i2c mode: this pin acts as a hardware address pin used in conjunction with ad0 to determine the software address for this device on the i2c bus. db13-db0 parallel data bus. db13 is the msb and db0 is the lsb of the input data word on the ad5380 a5-a0 parallel address inputs. a5 to a0 are decoded to address one of the 40 input channels on the ad5380. used in conjunction with the reg1 and reg0 pins to determine the destination register for the input data. reg1,reg0 reg1 and reg0 are used in decoding the destination registers for the input data. reg1 and reg0 are decoded to address the input data register, offset register or gain register for the selected channel and also are used to decide the special function registers. sdout/( a /b) serial data output in serial interface mode. tristatable cmos output. sdo can be used for daisy-chaining a number of devices together. data is clocked out on sdo on the rising edge of sclk and is valid on the falling edge of sclk. when operating in parallel interface mode this pin acts as the a or b data register select when writing data to the ad5380 data registers when toggle mode is selected (see toggle mode function). in toggle mode the ldac is used to switch the output between the data contained in the a and b data registers. all dac channels contain two data registers. in normal mode data register a is the default for data transfers. busy digital cmos output. busy goes low during internal calculations of the data (x2) loaded to the dac data register. during this time the user can continue writing new data to further x1, c and m registers (these are stored in a fifo) but no further updates to the dac registers and dac outputs can take place. if ldac is taken low while busy is low this event is stored. busy also goes low during power-on-reset and when the reset pin is low. during this time the interface is disabled and any events on ldac are ignored. a clr operation also brings busy low. ldac load dac logic input (active low) . if ldac is taken low while busy is inactive (high) the contents of the input registers are transferred to the dac registers and the dac outputs are updated. if ldac is taken low while busy is active and internal calculations are taking place, the ldac event is stored and the dac registers are updated when busy goes inactive. however any events on ldac during power-on-reset or reset are ignored. clr asynchronous clear input (level sensitive, active low) . while clr is low all lda c pulses are ignored. when clr is activated all channels are updated with the data contained in the clr code register. busy is low for a duration of 12us while all channels are being updated with the clr code. reset asynchronous digital reset input (falling edge sensitive). the function of this pin is equivalent to that of the power-on-reset generator. when this pin is taken low, the state- machine initiates a reset sequence to digitally reset x1, m, c, and x2 registers to their default
preliminary technical data rev. prf 09/2003 ad5380 ?13? power-on values. this sequence takes 300us (typ). the falling edge of reset initiates the reset process and busy goes low for the duration returning high when reset is complete. while busy is low all interfaces are disabled and all ldac pulses are ignored. when busy returns high the part resumes normal operation and the status of the reset pin is ignored till the next falling edge is detected. p d power down (level sensitive active high). used to place the device in low power mode where the device consumes less than 5ua. in power pown mode all internal analog circuitry is placed in low power mode, the analog output will be configured as high impedance outputs or will provide a 100k load to ground depending on how the power down mode is configured. the serial interface remains active during power down. fifo_en fifo enable (level sensitive active high). when connected to dvcc the internal fifo is enabled allowing the user to write to the device at full speed. fifo is only available in parallel interface mode. the status of the fifo_en pin is sampled on power-up, and also following a clear or reset to determine if the fifo is enabled. in either serial or i2c interface modes the fifo_en pin shpould be tied low. db11 (spi/ i2c ) multi-function input pin. in parallel interface mode this pin acts as db11 of the parallel input data word. in serial interface mode this pin acts as serial interface mode select. when serial interface mode is selected (ser/ par =1) and this input is low i2c mode is selected. in this mode db12 is the serial clock (sclk) input and db13 is the serial data (din) input. when serial interface mode is selected (ser/ par =1) and this input is high spi mode is selected. in this mode db12 is the serial clock (scl) input and db13 is the serial data (sda) input. db12 (sclk/scl) m ulti-function input pin. in parallel interface mode this pin acts as db12 of the parallel input data word. in serial interface mode this pin acts as a serial clock input. serial interface mode: in serial interface mode data is clocked into the shift register on the falling edge of sclk. this operates at clock speeds up to 50 mhz. i2c mode: in i2c mode this pin performs the scl function, clocking data into the device. data transfer rate in i2c mode is compatible with both 100khz and 400khz operating modes. db13/(din/sda) multi-function data input pin. in parallel interface mode this pin acts as db13 of the parallel input data word. serial interface mode: in serial interface mode this pin acts as the serial data input. data must be valid on the falling edge of sclk. i2c mode: in i2c mode this pin is the serial data pin (sda) operating as an open drain input/output.
preliminary technical data rev. prf 09/2003 ?14? ad5380 terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. ideally, with all 0s loaded to the dac and m = all 1s, c = 2 n-1 : vout (zero-scale) = 0v zero-scale error is a measure of the difference between vout (actual) and vout (ideal) expressed in mv. it is mainly due to offsets in the output amplifier. offset-error offset error is a measure of the difference between vout (actual) and vout (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5380-5 with code 32 loaded into the dac register and with code 64 on the ad5380-3. gain error gain error is specified in the linear region of the ouput range between vout =10mv and vout =avdd-50mv. it is the deviation in slope of the dac transfer characteristic from ideal and is expressed in % fsr with the dac output unloaded. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a fullscale code (all 0?s to all 1?s and vice versa) and output change of all other dacs. it is expressed in lsbs. dc output impedance this is the effective output source resistance. it is dominated by package lead resistance. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a 1/4 to 3/4 full-scale input change and measured from busy rising edge. digital-to-analog glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 1fff hex and 2000hex. dac-to-dac crosstalk dac-to-dac crosstalk is defined as the glitch impulse that appears at the output of one dac output due to both the digital change and subsequent analog o/p change at another dac. the victim channel is loaded with mid- scale and dac-to-dac crosstalk is specified in nv-s. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the device?s digital inputs can be capacitively coupled both across and through the device to show up as noise on the v out pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per root hertz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/( hz ) 1/2 in a 1 hz bandwidth at 10khz.
preliminary technical data rev. prf 09/2003 ad5380 ?15? ad5380 typical inl plot ad5380 typical dnl plot ad5380 power-up transient ad5380 slew rate with boost off ad5380 slew rate with boost on ad5380 glitch energy ad5380-5 typical performance characteristics
preliminary technical data rev. prf 09/2003 ?16? ad5380 2* idd histograms inl/dnl vs vref inl /dnl distributions offset error distribution fullscale error distribution output spectral density vs frequency source and sink capability dac-dac crosstalk 0.1 to 10hz noise plot typical performance characteristics
preliminary technical data rev. prf 09/2003 ad5380 ?17? functional description dac architecture ? general the ad5380 is a complete single supply, 40-channel, voltage output dac offering 14-bit resolution, available in a 100 lead lqfp package and features both a parallel and serial interfaces. this family includes an internal 1.25/2.5v, 10ppm/c reference that can be used to drive the buffered reference inputs, alternatively an external reference can be used to drive these inputs. reference selection is via a bit in the control register. all channels have an on-chip output amplifier with rail-to-rail output capable of driving a 5k ? ohm in parallel with a 200pf load. the architecture of a single dac channel consists of a 14-bit resistor-string dac followed by an output buffer amplifier operating at a gain of two. this resistor-string architecture guarantees dac monotonicity. the 14-bit binary digital code loaded to the dac register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. each channel on these devices contains independant offset and gain control registers allowing the user to digitally trim offset and gain. the inclusion of these registers allows the user the ability to calibrate out errors in the complete signal chain including the dac using the internal m and c registers which hold the correction factors. all channels are double buffered allowing synchronous updating of all channels using the ldac pin. figure 7 shows a block diagram of a single channel on the ad5380. the digital input transfer function for each dac can be represented as: x2 = [(m + 1 )/8192 x1] + (c-2 n-1 ) x2 is the dataword loaded to the resistor string dac x1 is the 14-bit dataword written to the dac input register. m is the13-bit gain coefficient (default is all 1fff hex on the ad5380. the gain coefficient is written to the 13 most significant bits. if a 14 bit data word is provided to the m register the lsb of the data word will be a zero. n=dac resolution (n=14 for ad5380) c is the14-bit offset coefficient (default is 2000hex on the ad5380) the complete transfer function for these devices can be represented as: vout = 2 v ref x2/2 n x2 is the dataword loaded to the resistor string dac v ref is the reference voltage applied to the dac, 2.5v for specified performance. data decoding the ad5380 contains a 14-bit data bus, db13-db0. depending on the value of reg1 and reg0 outlined in table 1, this data is loaded into the addressed dac input register(s), offset (c) register(s), or gain (m) register(s). the format data, offset (c) and gain (m) register contents are outlined in tables ii to iv. x1 input reg m reg c reg x2 dac reg 14-bit dac input data r r + - avdd vout vref figure 7. single channel architecture db13 to db0 dac output 11 1111 1111 1111 2 v ref (16383/16384) v 11 1111 1111 1110 2 v ref (16382/16384)v 10 0000 0000 0001 2 v ref (8193/16384) v 10 0000 0000 0000 2 v ref (8192/16384) v 01 1111 1111 1111 2 v ref (8191/16384) v 00 0000 0000 0001 2 v ref (1/16384) v 00 0000 0000 0000 0 v table ii. dac data format (reg1 = 1, reg0 = 1) reg1 reg0 register selected 1 1 input data register (x1) 1 0 offset register (c) 0 1 gain register (m) 0 0 special function registers (sfrs) table i. register selection db13 to db1 gain factor 1 1111 1111 1111 1 1 0111 1111 1111 0.75 0 1111 1111 1111 0.5 0 0111 1111 1111 0.25 0 0000 0000 0000 0 table iv. gain data format (reg1 = 0, reg0 = 1) db13 to db0 offset 11 1111 1111 1111 + 8191lsb 11 1111 1111 1110 + 8190lsb 10 0000 0000 0001 +1 lsb 10 0000 0000 0000 +0 lsb 01 1111 1111 1111 -1 lsb 00 0000 0000 0001 -8191 lsb 00 0000 0000 0000 -8192 lsb table iii. offset data format (reg1 = 1, reg0 = 0)
preliminary technical data rev. prf 09/2003 ?18? ad5380 ad5380 on-chip special function registers (sfr) the ad5380 contains a number of special function registers (sfrs)as outlined in table v. sfrs are addressed with reg1=reg0= 0 and are decoded using the address bits a5 to a0. table v. sfr register functions (reg1 =0, reg0 = 0) r/ w w w w w a5 a4 a3 a2 a1 a0 function x 00000 0 nop (no operation) 0 00000 1 write clr code 0 00001 0 soft clr 0 00100 0 soft power down 0 00100 1 soft power up 0 00110 0 control register write 1 00110 0 control register read 0 00101 0 m onitor channel 0 00111 1 soft reset sfr commands nop (no operation) reg1=reg0=0, a5-a0=000000 performs no operation but is useful in readback mode to clock out data on dout for diagnostic purposes. busy pulses low during a nop operation. write clr code reg1=reg0=0, a5-a0=000001 db13-db0= contain the clr data. bringing the clr line low or exercising the soft clear function will load the contents of the dac registers with the data contained in the user configurable clr register and sets vout0-vout39 accordingly. this can be very useful not only for setting up a specific output voltage in a clear condition but can also be used for calibration purposes where the user can load fullscale or zeroscale to the the clear code register and then issue a hardware or software clear to load this code to all dac removing the need for individual writes to all dacs. default on power up is all zeroes. soft clr reg1=reg0=0, a5-a0=000010 db13-db0= dont care. executing this instruction performs the clr which is functionally the same as that provided by the external clr pin. the dac outputs are loaded with the data in the clr code register. the time taken to fully execute the soft clr is 80*400ns and is indicated by the busy low time. soft power down reg1=reg0=0, a5-a0=001000 db13-db0= dont care. executing this instruction performs a global power-down feature that puts all channels into a low power mode reducing both analog and digital power consumption to 5ua. in power down mode the output amplifier can be configured as a high impedance output or provide a 100k load to ground. the contents of all internal registers are retained in power- down mode. cannot write to any register while in power down. soft power up reg1=reg0=0, a5-a0=001001 db13-db0= dont care. this instruction is used to power up the output amplifiers and internal reference. the time to exit power down is xxus. the hardware power down and software function are internally combined in a digital or function. soft reset reg1=reg0=0, a5-a0=001111 db13-db0= dont care. this instruction is used to implement a software reset. all internal registers are reset to their default values which corre- sponds to m at fullscale and c at zero. the contents of the dac registers are cleared setting all analog outputs to zero volts. the soft reset activation time is 150us (typ).
preliminary technical data rev. prf 09/2003 ad5380 ?19? control register write/read reg1=reg0=0, a5-a0=001100, r/ w status determines if the operation is a write (r/ w =0) or a read (r/ w =1). db13-db0 contains the control register data. ad5380 control register contents msb lsb cr13 cr12 cr11 cr10 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 table vi: ad5380 control register contents cr13: power down status. this bit is used to configure the output amplifier state in power down. cr13=1 amplifier output is high impedance . cr13=0 amplifier output is 100k to ground (default on power up). cr12: ref select. this bit selects the operating internal reference for the ad5380. cr12 is programmed as follows: cr12=1: internal reference is 2.5v (ad5380-5 default). recommended operating reference for ad5380-5. cr12=0: internal reference is 1.25v (ad5380-3 default). recommended operating reference for ad5380-3. cr11: current boost control. this bit is used to boost the current in the output amplifier therby altering its slew rate. this bit is configured as follows: cr11=1: boost mode on. this maximizes the bias current in the output amplifier optimizing its slew rate but increasing the power dissipation. cr11=0: boost mode off (default on power up). this reduces the bias current in the output amplifier and reduces the overall power consumption. cr10: internal/external reference. this bits determines if the dac uses its internal reference or an externally applied reference. cr10=1: internal reference enabled. reference output depends on data loaded to cr12. cr10=0: external reference selected (default on power up) cr9: channel monitor enable (see channel monitor function ) cr9=1: monitor enabled. this enables the channel monitor function. following a write to the monitor channel in the sfr register the selected channel output is routed to the mon_out pin. vout 39 operates as the mon-out pin on the ad5380. cr9=0: monitor disabled (default on power-up). when monitor is disabled the mon_out pin assumes its normal dac output function on the ad5380. cr8: thermal monitor function. this function is used to monitor the internal die temperature of the ad5380 when enabled. the thermal monitor powers down the output amplifiers when the temperature exceeds 130 degree c. this function can be used to protect the device in cases where the power dissipation of the device may be exceeded if a number of output channels are simultaneously short circuited. a soft power-up will re-enable the output amplifiers id the die temperature has dropped below 130c. cr8=1: thermal monitor enabled. cr8=0 thermal monitor disabled (default on power-up). cr7: dont care cr6 to cr2: toggle function enable. this function allows the user to toggle the output between two codes loaded to the a and b register for each dac. control register bits cr6 to cr2 are used to enable individual groups of 8-chan- nels for operation in toggle mode. a logic 1 written to any bit enables a group of channels and a logic zero disables a group. ldac is used to toggle between the two registers. logic 1 enables a group of channels and a logic zero disables a group. cr bit cr6 cr5 cr4 cr3 cr2 group 4 3210 channels 32-39 24-31 16-23 8-15 0-7 cr1 and cr0 are dont cares.
preliminary technical data rev. prf 09/2003 ?20? ad5380 channel monitor function reg1=reg0=0, a5-a0=001010 db13-db8= contain data to address the channel to be monitored. a monitor function is provided on all devices. this feature consisting of a multiplexer addressed via the interface allows any channel output to be routed to this pin for monitoring using an external adc. in channel monitor mode vout 39 becomes the mon_out pin, the pin to which all monitored pins are routed. the channel monitor function must be enabled in the control register before any channels are routed to the mon_out pin. on the ad5380, db13 to db8 contain the channel address for the monitored channel. selecting channel address 63 tristates the mon_out pin. the channel address decoding for the ad5380 is as follows: reg1 reg0 a5 a4 a3 a2 a1 a0 db13 db12 db11 db10 db9 db8 db7 ->db0 ad5380 mon_out 0 0 001010 000000x vout 0 0 0 001010 000001x vout 1 0 0 001010 000010x vout 2 0 0 001010 000011x vout 3 0 0 001010 000100x vout 4 0 0 001010 000101x vout 5 0 0 001010 000110x vout 6 0 0 001010 000111x vout 7 0 0 001010 001000x vout 8 0 0 001010 001001x vout 9 0 0 001010 001010x vout 10 0 0 001010 001011x vout 11 0 0 001010 001100x vout 12 0 0 001010 001101x vout 13 0 0 001010 001110x vout 14 0 0 001010 001111x vout 15 0 0 001010 010000x vout 16 0 0 001010 010001x vout 17 0 0 001010 010010x vout 18 0 0 001010 010011x vout 19 0 0 001010 010100x vout 20 0 0 001010 010101x vout 21 0 0 001010 010110x vout 22 0 0 001010 010111x vout 23 0 0 001010 011000x vout 24 0 0 001010 011001x vout 25 0 0 001010 011010x vout 26 0 0 001010 011011x vout 27 0 0 001010 011100x vout 28 0 0 001010 011101x vout 29 0 0 001010 011110x vout 30 0 0 001010 011111x vout 31 0 0 001010 100000x vout 32 0 0 001010 100001x vout 33 0 0 001010 100010x vout 34 0 0 001010 100011x vout 35 0 0 001010 100100x vout 36 0 0 001010 100101x vout 37 0 0 001010 100110x vout 38 0 0 001010 100111x undefined . . ...... ....... . . . ...... ....... . 0 0 001010 111110x undefined 0 0 001010 111111x tristate table x. ad5380 channel monitor decoding
preliminary technical data rev. prf 09/2003 ad5380 ?21? db13-db8 vout 39/mon_out 0 0 00 1 01 0 a0 a1 a2 a3 a4 a5 reg0 reg1 channel address vout 0 vout 1 vout 37 vout 38 . . . . . ad5380 channel monitor decoding figure 8. ad5380 channel monitor decoding
preliminary technical data rev. prf 09/2003 ?22? ad5380 hardware functions reset function bringing the reset line low resets the contents of all internal registers to their power-on-reset state. reset is a negative edge sensitive input. the default corresponds to m at fullscale and c at zero. the contents of the dac registers are cleared setting vout0-vout39 to zero volts. this sequence takes 300us (typ). the falling edge of reset initiates the reset process and busy goes low for the duration returning high when reset is complete. while busy is low all interfaces are disabled and all ldac pulses are ignored. when busy returns high the part resumes normal operation and the status of the reset pin is ignored till the next falling edge is detected. asynchronous clear function bringing the clr line low clears the contents of the dac registers to the data contained in the user configurable clr register and sets vout0-vout39 accordingly. this function can be used in system calibration to load zeroscale and fullscale to all channels together.the execution time for a clr is 32us. busy busy busy busy busy and ldac ldac ldac ldac ldac functions busy is a digital cmos output indicating the status of the ad5380 device. the value of x2 (x2 is the internal data loaded to the dac data register) is calculated each time the user writes new data to the corresponding x1, c or m regis- ters. during the calculation of x2 the busy output goes low. while busy is low the user can continue writing new data to the x1, m or c registers but no dac output updates can take place. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update im- mediately after busy goes high. the user may hold the ldac input permanently low and in this case the dac outputs update immediately after busy goes high. busy also goes low during power-on-reset and when a falling edge is de- tected on the reset pin . during this time all interfaces are disabled and any events on ldac are ignored. the ad5380 contains an extra feature whereby a dac register is not updated unless it?s x2 register has been written to sincethe last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2 registers. however the ad5380 will only update the dac register if the x2 data has changed, thereby removing unnecessary digital crosstalk. fifo operation in parallel mode the ad5380 contains a fifo to optimize operation when operating in parallel interface mode. the fifo enable (level sensitive active high)is uesed to enable the internal fifo. when connected to dvcc the internal fifo is en- abled allowing the user to write to the device at full speed. fifo is only available in parallel interface mode. the status of the fifo_en pin is sampled on power-up, and also following a clear or reset to determine if the fifo is enabled. in either serial or i2c interface modes the fifo_en pin shpould be tied low. up to 128 successive intructions can be written to the fifo at maximum speed in parallel mode. when the fifo is full any further writes to the device are ignored. figure 9 shows a comparisson between fifo mode and non-fifo mode in terms of channel update time, diguial loading time is also outlined in this graph. 0.00e+00 5.00e-06 1.00e-05 1.50e-05 2.00e-05 2.50e-05 1 4 7 10 13 16 19 22 25 28 31 34 37 40 number of writes time without fifo (channel update time) with fifo (channel update time) with fifo (digital loading time) figure 8. channel update rate (fifo vs non-fifo)
preliminary technical data rev. prf 09/2003 ad5380 ?23? power-on-reset the ad5380 contains a power-on-reset generator and state-machine. the power-on-reset resets all registers to a predefined state and the analog outputs are configured with a 100k impedance to ground. the busy pin goes low during the power-on-reset sequencing preventing data writes to the device. power-down the ad5380 contains a global power-down feature that puts all channels into a low power mode reducing both analog and digital power consumption to 5ua. in power down mode the output amplifier can be configured as a high impedance output or provide a 100k load to ground. the contents of all internal registers are retained in power-down mode. when exiting power down the settling time of the amplifier will elapse before the outputs settle to their correct value. ad5380 interfaces the ad5380 contains both a parallel and serial interfaces. furthermore, the serial interface can be programmed to be either dsp,spi,microwire or i2c compatible. the ser/ par pin selects parallel and serial interface modes. in serial mode spi/ i2c pin is used to select dsp,spi,microwire or i2c interface mode. the devices use an internal fifo memory to allow high speed successive writes in parallel interface mode. the user can continue writing new data to the device while write instructions are being executed. the busy signal indicates the current status of the device, going low while instructions in the fifo are being executed. up to 128 successive intructions can be written to the fifo at maximum speed in parallel mode. when the fifo is full any further writes to the device are ignored. to minimize both the power consumption of the device and on-chip digital noise, the active interface only powers up fully when the device is being written to, i.e. on the falling edge of wr or on the falling edge of sync . dsp, spi, microwire compatible serial interfaces the serial interface can be operated with a minimum of 3-wires in stand alone mode or 4-wires in daisy chain mode. daisy chaining allows many devices to be cascaded together to increase system channel count.the ser/ par pin must be tied high and the spi/ i2c (pin 97) should be tied high to enable the dsp,spi,microwire compatible serial interface. in serial interface mode the user does not need to drive the parallel input data pins. the serial interface is control pins are as follows: sync sync sync sync sync , din, sclk - standard 3-wire interface pins. dcen - selects stand-alone mode or daisy-chain mode. sdo - data out pin for daisy-chain mode. figures 3 and 4 show the timing diagram for a serial write to the ad5380 in both stand-alone and daisy-chain mode. the 24-bit data word format for the serial interface in shown in figure 9 below. msb lsb a a a a a /b r/ w w w w w a5 a4 a3 a2 a1 a0 reg1 reg0 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 figure 9 . ad5380, 40-channel, 14-bit dac serial input register configuration a /b when toggle mode is enabled this selects whether the data write is to the a or b register, with toggle disabled this bit should be set to zero to select the a data register. r/ w is the read or write control bit. a5-a0 are used to address the input channels . reg1 & reg0 select the register to which data is written as outlined in table 1. db13-db0 contain the input data word. x is a dont care condition. stand-alone mode by connecting dcen (daisy-chain enable) pin low, stand-alone mode is enabled. the serial interface works with both a continuous and a noncontinuous serial clock. the first falling edge of sync starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. any further edges on sync except for a falling edge are ignored until 24 bits are clocked in. once 24 bits have been shifted in, the sclk is ignored. in order for another serial transfer to take place the counter must be reset by the falling edge of sync . daisy-chain mode for systems which contain several devices the sdo pin may be used to daisy-chain several devices together. this daisy- chain mode can be useful in system diagnostics and reducing the number of serial interface lines. by connecting dcen (daisy-chain enable) pin high, the daisy-chain mode is enabled. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24
preliminary technical data rev. prf 09/2003 ?24? ad5380 figure 10 . ad5380, serial readback operation selected register data clocked out. db23 db0 db23' db0' 48 nop condition undefined sdo sclk sync din db23 db0 input word specifies register to be read 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the din input on the next device in the chain, a multi-device interface is constructed. 24 clock pulses are required for each device in the system. therefore, the total number of clock cycles must equal 24n where n is the total number of ad538x devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy-chain and prevents any further data being clocked into the input shift register. if the sync is taken high before 24 clocks are clocked into the part this is considered as a bad frame and the data is discarded. the serial clock may be either a continuous or a gated clock. a continuous sclk source can only be used if it can be arranged that sync is held low for the correct number of clock cycles. in gated clock mode a burst clock containing the exact number of clock cycles must be used and sync taken high after the final clock to latch the data. readback mode readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. with r/ w =1, the bits a5-a0 in association with bits reg1 and reg0 selects the register to be read. the remaining data bits in the write sequence are dont cares. during the next spi write the data appearing on the sdo output will contain the data from the previously addressed register. for a read of a single register the nop command can be used in clocking out the data from the selected register on sdo. the readback diagram in figure 10 shows the readback sequence. for example, to readback the m register of channel 0 on the ad5380 the following sequence should be implemented. firstly write 404xxx hex to the ad5380 input register. this configures the ad5380 for read mode with m register of channel zero selected. note all the data bits db13 to db0 are dont cares. follow this with a second write, a nop condition, 000000 hex, during this write the data from the m register is clocked out on the dout line, ie data clocked out will contain the data from the m register in bits db13 to db0, and the top 10 bits contain the address information as previously written. in readback mode the sync signal must frame the data. data is clocked out on the rising edge of sclk and is valid on the falling edge of the sclk signal. is the sclk idles high between the write and read operations of a readback operation then the first bit of data is clocked out on the falling edge of sync.
preliminary technical data rev. prf 09/2003 ad5380 ?25? i2c serial interface the ad5380 features an i2c compatible 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the ad5380 and the master at rates up to 400khz. figure 5,6 and shows the 2-wire interface timing diagrams that incorporate three different modes of operation. in selecting the i2c operating mode firstly configure serial operating mode (ser/ par =1) and then select i2c mode by configuring the spi/ i2c pin to a logic 0. the device is connected to this bus as slave devices (i.e., no clock is generated by the ad5380/81/82/83). the ad5380 has a 7-bit slave address 1010 1ad1ad0. the 5 msbs are hard coded and the two lsbs are determined by the state of the ad1 ad0 pins.the facility to hardware configure ad1 and ad0 allows four of these devices to be configured on the bus. i2c data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals that configure start and stop condi- tions. both sda and scl are pulled high by the external pull-up resistors when the i 2 c bus is not busy. start and stop conditions a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda, while scl is high. a start condition from the master signals the beginning of a transmission to the ad5380. the stop condition frees the bus. if a repeated start condition (s r ) is generated instead of a stop condition, the bus remains active. repeated start conditions a repeated start (s r ) condition may indicate a change of data direction on the bus. s r may be used when the bus mas- ter is writing to several i 2 c devices and does not want to relinquish control of the bus. acknowledge bit (ack) the acknowledge bit (ack) is the ninth bit attached to any 8-bit data word. ack is always generated by the receiving device. the ad5380 devices generate an ack when receiving an address or data by pulling sda low during the ninth clock period. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication. ad5380 slave addresses a bus master initiates communication with a slavedevice by issuing a start condition followed by the 7- bit slave address. when idle, the ad5380 waits for a start condition followed by its slave address. the lsb of the address word is the read/write (r/ w ) bit. the ad538x devices are receive devices only and when communicating with these r/ w = 0. after receiving the proper address 1010 1ad1ad0 , the ad5380 issues an ack by pulling sda low for one clock cycle. the ad5380 has four different user programmable addresses determined by the ad1 and ad0 bits. write operation there are three specific modes in which data can be written to the ad5380 family of dacs. 4-byte mode. when writing to the ad5380 dacs, the user must begin with an address byte (r/ w = 0) after which the dac w ill ac- knowledge that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte, this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. two bytes of data are then written to the dac as shown in figure 11. a stop condition follows. this allows the user to update a single channel within the ad5380 at any time and requires 4 bytes of data to be transferred from the master. figure 11 . 4-byte ad5380, i2c write operation 0 0 most significant data byte least significant data byte 1 0 10 1 ad0 r/ w a0 ack by ad538x ack by ad538x msb address byte start cond by master scl sda scl sda reg1 lsb msb lsb ack by ad538x ack by ad538x stop cond by master pointer byte ad1 a5 a4 a3 a2 a1 reg0 msb
preliminary technical data rev. prf 09/2003 ?26? ad5380 3-byte mode three byte mode allows the user update more than one channel in a write sequence without having to write the device address byte each time. the device address byte is only required once and subsequent channel updates require the pointer byte and the data bytes. in three byte mode the user begins with an address byte (r/ w = 0) after which the dac will acknowledge that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte, this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. this is then followed by the two data bytes. reg1 and reg0 determine the register to be updated. if a stop condition is not sent following the data bytes another channel can be updated by sending a new pointer byte followed by the data bytes. this mode only requires 3-bytes to be sent to update any channel once the device has been initially addressed and reduces the software overhead in updating the ad5380 channels. a stop condition at any time exits this mode. figure 12 shows a typical configuration. figure 12 . 3-byte ad5380, i2c write operation 0 a0 ack by ad538x msb pointer byte for channel ?n? a5 a4 a3 a2 a1 0 most significant data byte least significant data byte scl sda reg1 lsb msb lsb ack by ad538x ack by ad538x reg0 msb 1 0 10 1 ad0 r/ w ack by ad538x address byte start cond by master scl sda ad1 0 a0 ack by ad538x msb a5 a4 a3 a2 a1 0 most significant data byte least significant data byte scl sda reg1 lsb msb lsb ack by ad538x ack by ad538x stop cond by master reg0 msb scl sda data for channel ?n? pointer byte for channel ?next channel? data for channe l ?next channel?
preliminary technical data rev. prf 09/2003 ad5380 ?27? figure 13 . 2-byte ad5380, i2c write operation 2-byte mode two byte mode allows the user update channels sequentially following initialization of this mode. the device address byte is only required once and the pointer address pointer is configured for auto increment or burst mode. the user must begin with an address byte (r/ w = 0) after which the dac w ill acknowledge that it is prepared to receive data by pulling sda low. the address byte is followed by a specific pointer byte (ff hex) which initiates the burst mode of operation. the address pointer initializes to channel zero and the data following the pointer is loaded to channel 0, the address pointer automatically increments to the next address. the reg0 and reg 1 bits in the data byte determine the register to be updated. in this mode, following the initial- ization only the 2-data bytes are required to update a channel, the channel address automatically increments from address 0 to channel 39 and then returns to the normal 3-byte mode of operation. this mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. a stop condition at any time exits this mode. toggle mode of operation is not supported in 2-byte mode. figure 13 shows a typical configura- tion. a7=1 most significant data byte least significant data byte scl sda reg1 lsb msb lsb ack by ad538x ack by ad538x reg0 msb channel 0 data 1 0 10 1 ad0 r/ w a0=1 ack by converter ack by converter msb address byte start cond by master scl sda pointer byte ad1 a5=1 a4=1 a3=1 a2=1 a1=1 most significant data byte least significant data byte scl sda reg1 lsb msb lsb ack by converter ack by converter stop cond by master reg0 msb most significant data byte least significant data byte scl sda reg1 lsb msb lsb ack by converter ack by converter reg0 msb channel 1 data channel n data followed by stop a6=1
preliminary technical data rev. prf 09/2003 ?28? ad5380 ad538x controller/ dsp processor* address decode d15 d0 data bus upper bits of address bus a2 a1 a0 r/w *additional pins omitted for clarity d13 d0 cs ldac a2 a1 a0 wr a3 a4 a5 reg1 reg0 a3 a4 a5 ad5380 parallel interface the ser/ par pin must be tied low to enable the parallel interface and disable the serial interfaces. figure 5 shows the timing diagram for a parallel write. the parallel interface is controlled by the following pins: cs cs cs cs cs pin active low device select pin. wr wr wr wr wr pin on the rising edge of wr , with cs low, the address on pins a5-a0 are latched and data present on the data bus is loaded into the selected input registers. reg0, reg1 pins the reg0 and reg1 pins determine the destination register of the data being written to the ad5380. see table i. a5-a0 pins each of the 40 dac channels can be addressed individually. db13-db0 pins the ad5380 accepts a straight 14-bit parallel word on db13-db0 where db13 is the msb and db0 is the lsb. microprocessor interfacing parallel interface figure 14 . ad5380 -parallel interface
preliminary technical data rev. prf 09/2003 ad5380 ?29? the ad5380 can be interfaced to a variety of 16-bit microcontrollersor dsp processors. figure 14 shows the ad5380 family interfaced to a generic 16-bit microcontroller/dsp processor. the lower address lines from the processor are connected to a0 to a5 on the ad5380 as shown. the upper address lines are decoded to provide a cs, ldac signals for the ad5380. the fast interface timing of the ad5380 allows direct interface to a wide variety of microcontrollers and dsps as shown in figure 14. ad5380 to mc68hc11 the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock po- larity bit (cpol) = 0 and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)?see 68hc11 user manual . sck of the 68hc11 drives the sclk of the ad5380, the mosi output drives the serial data line (d in ) of the ad5380 and the miso input is driven from d out . the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5380, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8 -bit bytes with only eight falling clock edges occurring in the transmit cycle. ad5380 to pic16c6x/7x the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit = 0. this is done by writing to the synchronous serial port control register(sspcon). see user pic16/17 mi- crocontroller user manual . in this example i/o port ra1 is being used to pulse sync and enable the serial port of the ad5380. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write opera- tions are needed depending on the mode. figure 16 shows the connection diagram. miso sck mc68hc11 reset sclk sdo din sync ad538x dv dd spi/i2c pc7 ser/par mosi figure 15 . ad5380 -mc68hc11 interface sck/rc3 pic16c6x/7x reset sclk sdo din sync ad538x dv dd spi/i2c ra1 ser/par sdo/rc5 sdi/rc4 figure 16 . ad5380 -pic16c6x/7x interface rxd txd 8xc51 reset sclk sdo din sync ad538x dv dd dv dd spi/i2c p1.1 ser/par figure 17 . ad5380 - 8051 interface
preliminary technical data rev. prf 09/2003 ?30? ad5380 ad5380 to 8051 the ad5380 requires a clock synchronized to the serial data. the 8051 serial interface must therefore be oper ated in mode 0. in this mode serial data enters and exits through rxd and a shift clock is output on txd. figure 17 shows how the 8051 is connected to the ad5380. be- cause the ad5380 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. the ad5380 re quires its data with the msb first. since the 8051 outputs the lsb first, the transmit routine must take this into account. ad5380 to adsp2101/2103 figure 18 shows a serial interface between the ad5380 and the adsp-2101/adsp-2103. the adsp-2101/ adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/ adsp-2103 sport is programmed through the sport control register and should be configured as follows: inter- nal clock operation, active low framing, 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. power supply decoupling in any circuit where accuracy is important, careful consid- eration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5380 is mounted should be de- signed so that the analog and digital sections are separated, and confined to certain areas of the board. if the ad5380 is in a system where mu ltiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (av dd , av cc ) it is recom- mended to tie those pins together. the ad5380 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply l ocated as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and ef- fective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at h igh frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5380 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and s hould never be run near the reference inputs. a ground line routed between the d in and sclk lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). it is essential to minimize noise on v in and refin lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-s ided board. in this tech- nique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. dr sck adsp2101/ adsp2103 reset sclk sdo din sync ad538x dv dd spi/i2c rfs ser/par dt tfs figure 18 . ad5380 -adsp2101/adsp3103 interface
preliminary technical data rev. prf 09/2003 ad5380 ?31? applications information ad5380 monitor function the ad5380 contains a channel monitor function consisting of a multiplexer addressed via the interface allowing any channel output to be routed to this pin for monitoring using an external adc. in channel monitor mode vout 39 be- comes the mon_out pin, the pin to which all monitored signals are routed. the channel monitor function must be enabled in the control register before any channels are routed to the mon_out pin. table x contains the decoding information required to route any channel to the mon_out pin. selecting channel address 63 tristates the mon_out pin. figure 19 shows a typical monitoring circuit implemented using a 12-bit sar adc in a 6-lead sot package. the controller output port selects the channel to be monitored and the input port reads the converted data from the adc. ad5380 vout 39/mon_out sclk s data cs ad7476 . . . . . . vout 0 vout 38 avcc vin avcc dac_gnd signal gnd agnd din sync sclk controller input port output port gnd figure 19. typical channel monitoring circuit toggle mode function the toggle mode function allows an output signal to be generated using the ldac control signal that switches between two dac data registers. this function is configured using the sfr control register as follows. a write with reg1=reg0=0, a5-a0=001100 specifies a control register write. the toggle mode function is enabled in groups of 8- channels using bits cr6 to cr2 in the control register. see ad5380 control register description. figure 20 shows a block diagram of the toggle mode implementation. each of the 40 dac channels on the ad5380 contain an a and a b data register. note, the ?b? registers can only be loaded when toggle mode is enabled. the sequence of events when configuring the ad5380 for toggle mode of operation is as follows: i) enable toggle mode for the required channels via the control register ii) load data to a registers iii) load data to b registers. iv) apply ldac . the ldac is used to switch between the ?a? and ?b? registers in determining the analog output. the first ldac configures the output to reflect the data in the ?a? registers. this mode offers significant advantages if the user wants to generate a square wave at the output of all 40 channels as might be required to drive a liquid crystal based variable opti- cal attenuators. in this case the user writes to the control register and enables the toggle function by setting cr6 to cr2=1 enabling the five groups of 8 for toggle mode operation. the user must then load data to all 40 ?a? registers and ?b? registers. toggling the ldac will set the output values to reflect the data in the a and b registers and the frequency of the ldac will determine the frequency of the squarewave output. toggle mode is disabled via the control register, the first ldac following the disabling of the toggle mode will update the outputs with the data contained in the ?a? registers.
preliminary technical data rev. prf 09/2003 ?32? ad5380 thermal monitor function the ad5380 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. the short circuit current of each output amplifier is typically 40ma. operating the ad5380 at 5v leads to a power dissipa- tion of 200mw / shorted amplifier. with 5 channels shorted this leads to an extra watt of power dissipation. for the 100-lead lqfp the qja is typically 44 c /w. the thermal monitor is enabled by the user via cr8 in the control register. the output amplifiers on the ad5380 are automatically powered down if the die temperature exceeds 130 c approx. after a thermal shutdown has occured the user can re-enable the part by executing a soft power up if the temperature has dropped below 130 c or by turning off the thermal monitor function via the control register. input register data register a dac register 14-bit dac ldac control input data register b vout input data a/b figure 20. toggle mode function ad5380 in a mems based optical optical switch mems based optical switches have a requirement for high resolution dacs in their feedforward control path that offer high channel density with 14-bit monotonic behaviour. the ad5380, 40-channel, 14-bit dac in a 100lead lqfp pack- age satisifies these requirements. in the circuit shown in figure 19, the 0v?5v outputs of the ad5380 are amplified to achieve an output range of 0v?200v used to control actuators that determine the position of mems mirrors in an optical switch. the exact position of each mirror is measured using sensors. the sensor outputs are multiplexed into a high reso- lution adc in determining the mirror position. the control loop is closed and driven by an adsp-21065l, a 32-bit sharc ? dsp with an spi-compatible sport interface. it writes data to the dac, controls the multiplexer, and reads data from the adc via the serial interface. 14- bi t dac vo 1 act uat ors for mems mi rro r a rra y sensor + mul t i pl exer 8- c hannel adc ( a d 7856) a d 5380 14- bi t dac vo 40 . . . . . . . . a d s p 21065l refi n out put r ange 0- 200v or si ngl e c hannel adc ( a d 7671) +5v av dd refout . . . . g=50 g=50 0. 01uf figure 19 . ad5380 in a mems based optical switch
preliminary technical data rev. prf 09/2003 ad5380 ?33? fi bre a d 5380, 40- c hannel , 14- bi t dac dw dm i n dw dm out fi bre add po rts drop po rts fi bre at t enuat or at t enuat or at t enuat or at t enuat or aw g aw g . . . . . . . . . n: 1 mul t i pl exer ti a/ log am p ( a d 8304/ 5) 16- bi t adc phot o- di odes controller l l l l 1 2 n- 1 n . . . . . . . . . . . opt i cal sw i t ch a d g 731 ( 40: 1 mux) a d 7671 ( 0- 5v, 1m sps) figure 20 . oadm using the ad5380 as part of an optical attenuator optical attenuators the ad5380 based on its high channel count, high resolution, monotonic behaviour and high level of integration is ide- ally targetted at optical attenuation applications used in dynamc gain equilizers, variable optical attenuators (voa) and optical add-drop mutliplexers (oadm). in these applications each wavelength is individually extracted using an ar- rayed wavequide and its power monitored using a photo-diode, transimpedance amplifier and adc in a close loop control system. the ad5380 controls the optical attenuator for each wavelength ensuring that the power is equilized in all wavelengths before being multiplexed onto the fibre. this prevents information loss and saturation from occurring at amplification stages further along the fibre. utilizing the ad5380 fifo the ad5380 fifo mode optimizes total system update rate in applications where a large number of channels need to be updated. fifo mode is only available when the parallel interface mode is selected. the fifoen pin is used to enable the fifo. the status of the fifoen pin is sampled during the initialisation sequence, therefore the fifo status can only be changed by resetting the device. an example of where a large number of channels need to be updated in a short period of time would be in a telescope that provides for the cancellation of atmospheric distortion. in these systems as many as 400channels need to be updated in a window of 40us. 400 channels necessitates the use of 10* ad5380 devices. with fifo mode enabled the data write cycle time is 40ns, therefore each group consisting of 40 channels can be fully loaded 1.6us. in fifo mode a complete group of 40 channels will update in 14.4us. therefore the time taken to update all 400channels will equate to 14.4us +9*1.6us = 28.8us. figure 21 shows a graphical view of the fifo operation scheme. group a chnls 0-39 group b chnls 40-79 group c chnls 80-119 group d chnls 120-159 group e chnls 160-199 group f chnls 200-239 group h chnls 280-319 group g chnls 240-279 group i chnls 320-359 time to update 400 channels = 28.8us group j chnls 360-399 1.6us 14.4us fifo data load group b 1.6us fifo data load group a output update time for group a output update time for group b 14.4us fifo data load group j 1.6us output update time for group j 14.4us figure 21. using fifo mode 400 channels updated in under 30us.
preliminary technical data rev. prf 09/2003 ?34? ad5380 seating plane 0.026 (0.65) 0.014 (0.35) 0.061 (1.55) 0.049 (1.25) 12? typ 0.007 (0.177) 0.003 (0.077) 6? 4? 0? e 10? 0.004 (0.102) max lead coplanarity top view (pins dow n) 1 25 26 51 50 75 100 76 0.012 (0.20) 0.004 (0.10) 0.640 (16.25) 0.620 (15.75) sq 0.555 (14.10) 0.547 (13.90) sq 0.020 (0.50) bsc outline dimensions st100 (100 lead lqfp) package dimensions

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