View LH28F800BGHB-TTL90_3321621.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? integrated circuits group LH28F800BGHB-TTL90 flash memory 8m (512k 16) (model no.: lhf80bza) spec no.: el10z134b issue date: sept. 19, 2001 p roduc t s pecific a tions
lhf80bza rev. 1.1 handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. please direct all queries regarding the products covered herein to a sales representative of the company. sharp sharp sharp sharp sharp
lhf80bza 1 rev. 1.1 contents page 1 introduction.............................................................. 3 1.1 features ........................................................................ 3 1.2 product overview......................................................... 3 2 principles of operation........................................ 6 2.1 data protection............................................................. 7 3 bus operation ............................................................ 7 3.1 read.............................................................................. 7 3.2 output disable.............................................................. 7 3.3 standby......................................................................... 7 3.4 deep power-down ....................................................... 7 3.5 read identifier codes operation .................................. 8 3.6 write............................................................................. 8 4 command definitions............................................. 8 4.1 read array command................................................ 11 4.2 read identifier codes command ............................... 11 4.3 read status register command ................................. 11 4.4 clear status register command................................. 11 4.5 block erase command............................................... 11 4.6 word write command ............................................... 12 4.7 block erase suspend command ................................ 12 4.8 word write suspend command................................. 13 4.9 considerations of suspend ......................................... 13 4.10 block locking .......................................................... 13 4.10.1 v pp =v il for complete protection ...................... 13 4.10.2 wp#=v il for block locking.............................. 13 4.10.3 wp#=v ih for block unlocking.......................... 13 page 5 design considerations ...................................... 19 5.1 three-line output control ....................................... 19 5.2 power supply decoupling ........................................ 19 5.3 v pp trace on printed circuit boards ........................ 19 5.4 v cc , v pp , rp# transitions ....................................... 19 5.5 power-up/down protection...................................... 20 5.6 power dissipation ..................................................... 20 6 electrical specifications ............................... 21 6.1 absolute maximum ratings ..................................... 21 6.2 operating conditions ................................................ 21 6.2.1 capacitance......................................................... 21 6.2.2 ac input/output test conditions ....................... 22 6.2.3 dc characteristics .............................................. 23 6.2.4 ac characteristics - read-only operations ....... 25 6.2.5 ac characteristics - write operations ............... 27 6.2.6 alternative ce#-controlled writes..................... 29 6.2.7 reset operations ................................................. 31 6.2.8 block erase and word write performance ......... 32 7 package and packing specifications......... 33 sharp
lhf80bza 2 rev. 1.1 LH28F800BGHB-TTL90 8m-bit (512kbit 16) smart3 flash memory smart3 technology 2.7v-3.6v v cc 2.7v-3.6v or 11.4v-12.6v v pp 16bit i/o interface high-performance access time 90ns(2.7v-3.6v) operating temperature -40c to +85c optimized array blocking architecture two 4k-word boot blocks six 4k-word parameter blocks fifteen 32k-word main blocks top boot location extended cycling capability 100,000 block erase cycles enhanced automated suspend options word write suspend to read block erase suspend to word write block erase suspend to read enhanced data protection features absolute protection with v pp =gnd block erase and word write lockout during power transitions boot blocks protection with wp#=v il automated word write and block erase command user interface status register low power management deep power-down mode automatic power savings mode decreases i cc in static mode sram-compatible write interface chip size packaging 0.75mm pitch 48-ball csp etox tm* nonvolatile flash technology cmos process (p-type silicon substrate) not designed or rated as radiation hardened sharp?s LH28F800BGHB-TTL90 flash memory with smart3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F800BGHB-TTL90 can operate at v cc =2.7v-3.6v and v pp =2.7v-3.6v. its low voltage operation capability realize battery life and suits for cellular phone application. its boot, parameter and main-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the LH28F800BGHB-TTL90 offers two levels of protection: absolute protection with v pp at gnd, selective hardware boot block locking. these alternatives give designers ultimate control of their code security needs. the LH28F800BGHB-TTL90 is manufactured on sharp?s 0.35m etox tm* process technology. it come in chip size package: the 0.75mm pitch 48-ball csp ideal for board constrained applications. *etox is a trademark of intel corporation. sharp
lhf80bza 3 rev. 1.1 1 introduction this datasheet contains LH28F800BGHB-TTL90 specifications. section 1 provides a flash memory overview. sections 2, 3, 4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 features key enhancements of LH28F800BGHB-TTL90 smart3 flash memory are: ? smart3 technology ? enhanced suspend capabilities ? boot block architecture please note following important differences: ? v pplk has been lowered to 1.5v to support 2.7v-3.6v block erase and word write operations. the v pp voltage transitions to gnd is recommended for designs that switch v pp off during read operation. ? to take advantage of smart3 technology, allow v cc and v pp connection to 2.7v-3.6v. 1.2 product overview the LH28F800BGHB-TTL90 is a high-performance 8m- bit smart3 flash memory organized as 512k-word of 16 bits. the 512k-word of data is arranged in two 4k-word boot blocks, six 4k-word parameter blocks and fifteen 32k-word main blocks which are individually erasable in- system. the memory map is shown in figure 3. smart3 technology provides a choice of v cc and v pp combinations, as shown in table 1, to meet system performance and power expectations. v pp at 2.7v-3.6v eliminates the need for a separate 12v converter, while v pp =12v maximizes block erase and word write performance. in addition to flexible erase and program voltages, the dedicated v pp pin gives complete data protection when v pp v pplk . table 1. v cc and v pp voltage combinations offered by smart3 technology v cc voltage v pp voltage 2.7v-3.6v 2.7v-3.6v, 11.4v-12.6v internal v cc and v pp detection circuitry automatically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and word write operations. a block erase operation erases one of the device?s 32k- word blocks typically within 0.51s (2.7v-3.6v v cc , 11.4v-12.6v v pp ), 4k-word blocks typically within 0.31s (2.7v-3.6v v cc , 11.4v-12.6v v pp ) independent of other blocks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in word increments of the device?s 32k-word blocks typically within 12.6s (2.7v-3.6v v cc , 11.4v-12.6v v pp ), 4k-word blocks typically within 24.5s (2.7v-3.6v v cc , 11.4v-12.6v v pp ). word write suspend mode enables the system to read data or execute code from any other flash memory array location. the boot blocks can be locked for the wp# pin. block erase or word write for boot block must not be carried out by wp# to low and rp# to v ih . the status register indicates when the wsm?s block erase or word write operation is finished. the access time is 90ns (t avqv ) over the extended temperature range (-40c to +85c) and v cc supply voltage range of 2.7v-3.6v. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 3ma at 2.7v v cc . when ce# and rp# pins are at v cc , the i cc cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 0.75mm pitch 48-ball csp (chip size package). pinout is shown in figure 2. sharp
input buffer buffer output multiplexer i/o command user v cc ce# rp# oe# identifier register status register data register data comparator y-gating y decoder decoder x address latch address counter write machine program/erase voltage v pp v cc gnd a 0 -a 18 dq 0 -dq 15 input buffer logic state boot block 0 boot block 1 parameter block 0 parameter block 5 parameter block 4 parameter block 3 parameter block 2 parameter block 1 main block 0 main block 1 main block 13 main block 14 15 32k-word wp# we# output interface switch main blocks 0.75mm pitch 48-ball csp pinout 8mm x 8mm top view 8 7 6 5 4 3 2 1 f e d c b a a 5 a 8 a 11 v pp a 12 a 15 a 18 a 6 a 9 rp# nc ce# a 14 a 17 a 4 a 7 a 10 nc a 13 a 16 a 3 a 0 dq 2 dq 6 a 1 dq 1 gnd nc dq 4 dq 7 oe# a 2 dq 0 dq 3 gnd v cc dq 5 we# wp# dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 nc lhf80bza 4 rev. 1.1 figure 1. block diagram figure 2. 0.75mm pitch csp 48-ball pinout note: nc balls at c4 and c5 are internally connected. sharp
lhf80bza 5 rev. 1.1 table 1. pin descriptions symbol type name and function a 0 -a 18 input address inputs: addresses are internally latched during a write cycle. a 0 -a 10 : row address. selects 1 of 2048 word lines. a 11 -a 14 : column address. selects 1 of 16 bit lines. a 15 -a 18 : main block address. (boot and parameter block addresses are a 12 -a 18 .) dq 0 -dq 15 input/ output data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high- impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. rp# input reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. with rp#=v hh , block erase or word write can operate to all blocks without wp# state. block erase or word write with v ih 7ffff 7f000 7efff 7e000 7dfff 7d000 7cfff 7c000 7bfff 7b000 7afff 7a000 79fff 79000 78fff 78000 77fff 70000 6ffff 68000 67fff 60000 5ffff 58000 57fff 50000 4ffff 48000 47fff 40000 4k-word parameter block 3 4k-word parameter block 2 4k-word parameter block 1 4k-word parameter block 0 32k-word main block 0 32k-word main block 1 32k-word main block 2 32k-word main block 3 32k-word main block 5 32k-word main block 6 4k-word parameter block 5 4k-word parameter block 4 top boot 4k-word boot block 0 4k-word boot block 1 32k-word main block 4 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 00000 32k-word main block 8 32k-word main block 9 32k-word main block 10 32k-word main block 11 32k-word main block 13 32k-word main block 14 32k-word main block 12 3ffff 38000 32k-word main block 7 [ a 18 -a 0 ] lhf80bza 6 rev. 1.1 2 principles of operation the LH28F800BGHB-TTL90 smart3 flash memory includes an on-chip wsm to manage block erase and word write functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erasure and word write, and minimal processor overhead with ram- like interface timings. after initial device power-up or return from deep power- down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erasure and word writing. all functions associated with altering memory contents?block erase, word write, status and identifier codes?are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase and word write. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. interface software that initiates and polls progress of block erase and word write can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. word write suspend allows system software to suspend a word write to read data from any other flash memory array location. figure 3. memory map sharp
lhf80bza 7 rev. 1.1 2.1 data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when memory block erases or word writes are required) or hardwired to v pph1/2 . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. the cui, with two-step block erase or word write command sequences, provides protection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v cc is below the write lockout voltage v lko or when rp# is at v il . the device?s boot blocks locking capability for wp# provides additional protection from inadvertent code or data alteration by block erase and word write operations. refer to table 6 for write protection alternatives. 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes or status register independent of the v pp voltage. rp# can be at either v ih or v hh . the first task is to write the appropriate read mode command (read array, read identifier codes or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. five control pins dictate the data flow in and out of the component: ce#, oe#, we#, rp# and wp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 -dq 15 ) control and when active drives the selected memory data onto the i/o bus. we# must be at v ih and rp# must be at v ih or v hh . figure 11 illustrates read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins (dq 0 -dq 15 ) are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 -dq 15 outputs are placed in a high- impedance state independent of oe#. if deselected during block erase or word write, the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of 100ns. time t phqv is required after return from power- down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase or word write modes, rp#-low will abort the operation. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase or word write modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. sharp
device code manufacturer code 7ffff 00001 00000 reserved for future implementation 00002 [a 18 -a 0 ] lhf80bza 8 rev. 1.1 3.5 read identifier codes operation the read identifier codes operation outputs the manufacturer code and device code (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. figure 4. device identifier code memory map 3.6 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v cc =2.7v-3.6v and v pp =v pph1/2 , the cui additionally controls block erasure and word write. the block erase command requires appropriate command data and an address within the block to be erased. the word write command requires the command and address of the location to be written. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 12 and 13 illustrate we# and ce# controlled write operations. 4 command definitions when the v pp voltage v pplk , read operations from the status register, identifier codes, or blocks are enabled. placing v pph1/2 on v pp enables successful block erase and word write operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. sharp
lhf80bza 9 rev. 1.1 table 2. bus operations (1,2) mode notes rp# ce# oe# we# address v pp dq 0-15 read 7 v ih or v hh v il v il v ih x x d out output disable v ih or v hh v il v ih v ih x x high z standby 8 v ih or v hh v ih x x x x high z deep power-down 3,8 v il x x x x x high z read identifier codes 7 v ih or v hh v il v il v ih see figure 4 x note 4 write 5,6,7 v ih or v hh v il v ih v il x x d in notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. rp# at gnd0.2v ensures the lowest deep power-down current. 4. see section 4.2 for read identifier code data. 5. command writes involving block erase or word write are reliably executed when v pp =v pph1/2 and v cc =2.7v-3.6v. block erase or word write with v ih lhf80bza 10 rev. 1.1 table 3. command definitions (7) bus cycles first bus cycle second bus cycle command req?d. notes oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array/reset 1 write x ffh read identifier codes 2 4 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write ba 20h write ba d0h word write 2 5,6 write wa 40h or 10h write wa wd block erase and word write suspend 1 5 write x b0h block erase and word write resume 1 5 write x d0h notes: 1. bus operations are defined in table 3 2. x=any valid address within the device. ia=identifier code address: see figure 4. ba=address within the block being erased. the each block can select by the address pin a 18 through a 12 combination. wa=address of memory location to be written. 3. srd=data read from status register. see table 7 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer and device codes. see section 4.2 for read identifier code data. 5. if the block is boot block, wp# must be at v ih or rp# must be at v hh to enable block erase or word write operations. attempts to issue a block erase or word write to a boot block while wp# is v ih or rp# is v ih . 6. either 40h or 10h are recognized by the wsm as the word write setup. 7. commands other than those shown above are reserved by sharp for future device implementations and should not be used. sharp
lhf80bza 11 rev. 1.1 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or word write, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or word write suspend command. the read array command functions independently of the v pp voltage and rp# can be v ih or v hh . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer and device codes (see table 5 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage and rp# can be v ih or v hh . following the read identifier codes command, the following information can be read: table 4. identifier codes code address [a 18 -a 0 ] data [dq 15 -dq 0 ] manufacture code 00000h 00b0h device code 00001h 0060h 4.3 read status register command the status register may be read to determine when a block erase or word write is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage. rp# can be v ih or v hh . 4.4 clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 7). by allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pp voltage. rp# can be v ih or v hh . this command is not functional during block erase or word write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v cc =2.7v-3.6v and v pp =v pph1/2 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". successful block erase for boot blocks requires that the corresponding if set, that wp#=v ih or rp#=v hh . if block erase is attempted to boot block when the corresponding wp#=v il or rp#=v ih , sr.1 and sr.5 will be set to "1". block erase operations with v ih lhf80bza 12 rev. 1.1 4.6 word write command word write is executed by a two-cycle command sequence. word write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word write and write verify algorithms internally. after the word write sequence is written, the device automatically outputs status register data when read (see figure 6). the cpu can detect the completion of the word write event by analyzing the status register bit sr.7. when word write is complete, status register bit sr.4 should be checked. if word write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the cui remains in read status register mode until it receives another command. reliable word writes can only occur when v cc =2.7v-3.6v and v pp =v pph1/2 . in the absence of this high voltage, memory contents are protected against word writes. if word write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful word write for boot blocks requires that the corresponding if set, that wp#=v ih or rp#=v hh . if word write is attempted to boot block when the corresponding wp#=v il or rp#=v ih , sr.1 and sr.4 will be set to "1". word write operations with v ih lhf80bza 13 rev. 1.1 4.8 word write suspend command the word write suspend command allows word write interruption to read data in other flash memory locations. once the word write process starts, writing the word write suspend command requests that the wsm suspend the word write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the word write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the word write operation has been suspended (both will be set to "1"). specification section 6.2.8 defines the word write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while word write is suspended are read status register and word write resume. after word write resume command is written to the flash memory, the wsm will continue the word write process. status register bits sr.2 and sr.7 will automatically clear. after the word write resume command is written, the device automatically outputs status register data when read (see figure 8). v pp must remain at v pph1/2 (the same v pp level used for word write) while in word write suspend mode. rp# must also remain at v ih or v hh (the same rp# level used for word write). wp# must also remain at v il or v ih (the same wp# level used for word write). 4.9 considerations of suspend after the suspend command write to the cui, read status register command has to write to cui, then status register bit sr.6 or sr.2 should be checked for places the device in suspend mode. 4.10 block locking this boot block flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. 4.10.1 v pp =v il for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. 4.10.2 wp#=v il for block locking the lockable blocks are locked when wp#=v il ; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two boot blocks are lockable. for the bottom configuration, the bottom two boot blocks are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). 4.10.3 wp#=v ih for block unlocking wp#=v ih unlocks all lockable blocks. these blocks can now be programmed or erased. wp# controls 2 boot blocks locking and v pp provides protection against spurious writes. table 6 defines the write protection methods. table 5. write protection alternatives operation v pp rp# wp# effect v il x x all blocks locked. block erase v il x all blocks locked. or >v pplk v hh x all blocks unlocked. word write v ih v il 2 boot blocks locked. v ih all blocks unlocked. sharp
lhf80bza 14 rev. 1.1 table 6. status register definition wsms ess es wws vpps wwss dps r 76543210 sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase sr.4 = word write status (wws) 1 = error in word write 0 = successful word write sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = word write suspend status (wwss) 1 = word write suspended 0 = word write in progress/completed sr.1 = device protect status (dps) 1 = wp# or rp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes: check sr.7 to determine block erase or word write completion. sr.6-0 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase or word write command sequences. sr.3 is not guaranteed to reports accurate feedback only when v pp v pph1/2 . the wsm interrogates the wp# and rp# only after block erase or word write command sequences. it informs the system, depending on the attempted operation, if the wp# is not v ih, rp# is not v hh . sr.0 is reserved for future use and should be masked out when polling the status register. sharp
bus operation command comments write write read standby erase setup erase confirm data=20h addr=within block to be erased data=d0h addr=within block to be erased status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. bus operation command comments standby 1=v pp error detect 1=device protect detect check sr.4,5 sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=block erase error standby standby standby check sr.3 check sr.1 both 1=command sequence error start write 20h, block address write d0h, block address read status register sr.7= 0 1 suspend block erase no yes suspend block erase loop full status check if desired block erase complete full status check procedure read status register data(see above) sr.3= 1 0 v pp range error device protect error command sequence error block erase error sr.1= 1 0 sr.4,5= sr.5= 1 1 0 0 block erase successful lhf80bza 15 rev. 1.1 figure 5. automated block erase flowchart sharp
bus operation command comments write write read standby setup word write word write data=40h or 10h addr=location to be written data=data to be written addr=location to be written status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent word writes. sr full status check can be done after each word write, or after a sequence of word writes. write ffh after the last word write operation to place device in read array mode. bus operation command comments 1=v pp error detect 1=device protect detect sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=data write error standby standby standby check sr.3 check sr.1 start write 40h or 10h, address write word data and address read status register sr.7= 0 1 suspend word write no yes suspend word write loop full status check if desired word write complete full status check procedure read status register data(see above) sr.3= 1 0 v pp range error device protect error word write error sr.1= 1 0 sr.4= 1 0 word write successful lhf80bza 16 rev. 1.1 figure 6. automated word write flowchart sharp
start write b0h word write loop read status register sr.7= 0 1 no bus operation command comments write read standby data=b0h addr=x data=d0h status register data check sr.7 1=wsm ready 0=wsm busy yes sr.6= 0 1 read array data done? block erase resumed read array data block erase completed write ffh write d0h standby write erase suspend erase resume addr=x addr=x check sr.6 1=block erase suspended 0=block erase completed read word write read or word write? lhf80bza 17 rev. 1.1 figure 7. block erase suspend/resume flowchart sharp
start write b0h write ffh read status register sr.7= 0 1 no bus operation command comments write read standby data=b0h addr=x data=d0h status register data check sr.7 1=wsm ready 0=wsm busy yes sr.2= 0 1 read array data done reading word write resumed read array data write ffh write d0h standby write write read word write suspend read array word write resume addr=x addr=x data=ffh addr=x check sr.2 1=word write suspended 0=word write completed read array locations other than that being written. word write completed lhf80bza 18 rev. 1.1 figure 8. word write suspend/resume flowchart sharp
lhf80bza 19 rev. 1.1 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7f electrolytic capacitor should be placed at the array?s power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.3 v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for word writing and block erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 5.4 v cc , v pp , rp# transitions block erase and word write are not guaranteed if v pp falls outside of a valid v pph1/2 range, v cc falls outside of a valid 2.7v-3.6v range, or rp# v ih or v hh . if v pp error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase or word write, the reset operation will execute. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v il clear the status register. the cui latches commands issued by system software and is not altered by v pp or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power-down or after v cc transitions below v lko . after block erase or word write, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. sharp
lhf80bza 20 rev. 1.1 5.5 power-up/down protection the device is designed to offer protection against accidental block erasure or word writing during power transitions. upon power-up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the cui?s two-step command sequence architecture provides added level of protection against data alteration. wp# provide additional protection from inadvertent code or data alteration. the device is disabled while rp#=v il regardless of its control inputs state. 5.6 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering rp# to v il standby or sleep modes. if access is again needed, the devices can be read following the t phqv and t phwl wake-up cycles required after rp# is first raised to v ih . see ac characteristics? read only and write operations and figures 11, 12 and 13 for more information. sharp
lhf80bza 21 rev. 1.1 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, block erase and word write ......................................-40c to +85c (1) temperature under bias ...................... -40c to +85c storage temperature ................................ -65c to +125c voltage on any pin (except v cc , v pp , and rp#) ............ -0.5v to +7.0v (2) v cc supply voltage................................ -0.2v to +7.0v (2) v pp update voltage during block erase and word write.................. -0.2v to +14.0v (2,3) rp# voltage ........................................ -0.5v to +14.0v (2,3) output short circuit current................................100ma (4) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc and v pp pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins and v cc is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. maximum dc voltage on v pp and rp# may overshoot to +14.0v for periods <20ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature and v cc operating conditions symbol parameter min. max. unit test condition t a operating temperature -40 +85 c ambient temperature v cc v cc supply voltage (2.7v-3.6v) 2.7 3.6 v 6.2.1 capacitance (1) t a =+25c, f=1mhz symbol parameter typ. max. unit condition c in input capacitance 7 10 pf v in =0.0v c out output capacitance 9 12 pf v out =0.0v note: 1. sampled, not 100% tested. sharp
ac test inputs are driven at 2.7v for a logic "1" and 0.0v for a logic "0." input timing begins, and output timing ends, at 1.3 5v. input rise and fall times (10% to 90%) <10 ns. 2.7 0.0 input test points output 1.35 1.35 1.3v 1n914 device under test c l out c l includes jig r l =3.3k ? capacitance lhf80bza 22 rev. 1.1 6.2.2 ac input/output test conditions figure 9. transient input/output reference waveform for v cc =2.7v-3.6v test configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.6v 30 figure 10. transient equivalent testing load circuit sharp
lhf80bza 23 rev. 1.1 6.2.3 dc characteristics dc characteristics v cc =2.7v-3.6v test sym. parameter notes typ. max. unit conditions i li input load current 1 0.5 a v cc =v cc max. v in =v cc or gnd i lo output leakage current 1 0.5 a v cc =v cc max. v out =v cc or gnd i ccs v cc standby current 1,5,9 25 50 a cmos inputs v cc =v cc max. ce#=rp#=v cc 0.2v 1,5 0.2 2 ma ttl inputs v cc =v cc max. ce#=rp#=v ih i ccd v cc deep power-down current 1,9 5 20 a rp#=gnd0.2v i ccr v cc read current 1,4,5 15 25 ma cmos inputs v cc =v cc max., ce#=gnd f=5mhz, i out =0ma 30 ma ttl inputs v cc =v cc max., ce#=gnd f=5mhz, i out =0ma i ccw v cc word write current 1,6 5 17 ma v pp =2.7v-3.6v 5 12 ma v pp =11.4v-12.6v i cce v cc block erase current 1,6 4 17 ma v pp =2.7v-3.6v 4 12 ma v pp =11.4v-12.6v i ccws i cces v cc word write or block erase suspend current 1,2 1 6 ma ce#=v ih i pps v pp standby or read current 1 2 15 a v pp v cc i ppr 10 200 a v pp >v cc i ppd v pp deep power-down current 1 0.1 5 a rp#=gnd0.2v i ppw v pp word write current 1,6 12 40 ma v pp =2.7v-3.6v 30 ma v pp =11.4v-12.6v i ppe v pp block erase current 1,6 8 25 ma v pp =2.7v-3.6v 20 ma v pp =11.4v-12.6v i ppws i ppes v pp word write or block erase suspend current 1 10 200 a v pp =v pph1/2 sharp
lhf80bza 24 rev. 1.1 dc characteristics (continued) v cc =2.7v-3.6v sym. parameter notes min. max. unit test conditions v il input low voltage 6 -0.5 0.8 v v ih input high voltage 6 2.0 v cc +0.5 v v ol output low voltage 6 0.4 v v cc =v cc min. i ol =2.0ma v oh1 output high voltage (ttl) 6 2.4 v v cc =v cc min. i oh =-1.5ma v oh2 output high voltage (cmos) 6 0.85 v cc v v cc =v cc min. i oh =-2.0ma v cc -0.4 v v cc =v cc min. i oh =-100a v pplk v pp lockout voltage during normal operations 3,6 1.5 v v pph1 v pp voltage during word write or block erase operations 2.7 3.6 v v pph2 v pp voltage during word write or block erase operations 11.4 12.6 v v lko v cc lockout voltage 2.0 v v hh rp# unlock voltage 7,8 11.4 12.6 v unavailable wp# notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a =+25c. 2. i ccws and i cces are specified with the device de-selected. if read or word written while in erase suspend mode, the device?s current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. block erases and word writes are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.) and above v pph2 (max.). 4. automatic power savings (aps) reduces typical i ccr to 3ma at 2.7v v cc in static operation. 5. cmos inputs are either v cc 0.2v or gnd0.2v. ttl inputs are either v il or v ih . 6. sampled, not 100% tested. 7. boot block erases and word writes are inhibited when the corresponding rp#=v ih and wp#=v il . block erase and word write operations are not guaranteed with v ih lhf80bza 25 rev. 1.1 6.2.4 ac characteristics - read-only operations (1) v cc =2.7v-3.6v, t a =-40c to +85c sym. parameter notes min. max. unit t avav read cycle time 90 ns t avqv address to output delay 90 ns t elqv ce# to output delay 2 90 ns t phqv rp# high to output delay 600 ns t glqv oe# to output delay 2 50 ns t elqx ce# to output in low z 3 0 ns t ehqz ce# high to output in high z 3 55 ns t glqx oe# to output in low z 3 0 ns t ghqz oe# high to output in high z 3 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3 0 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. sharp
addresses(a) ce#(e) oe#(g) we#(w) data(d/q) rp#(p) v cc standby device address selection data valid address stable t avav t ehqz t ghqz high z valid output t glqv t elqv t glqx t elqx t avqv t phqv high z t oh v il v oh v ol v ih v ih v ih v ih v ih v il v il v il v il (dq 0 -dq 15 ) lhf80bza 26 rev. 1.1 figure 11. ac waveform for read operations sharp
lhf80bza 27 rev. 1.1 6.2.5 ac characteristics - write operations (1) v cc =2.7v-3.6v, t a =-40c to +85c sym. parameter notes min. max. unit t avav write cycle time 90 ns t phwl rp# high recovery to we# going low 2 1 s t elwl ce# setup to we# going low 10 ns t wlwh we# pulse width 50 ns t phhwh rp# v hh setup to we# going high 2 100 ns t shwh wp# v ih setup to we# going high 2 100 ns t vpwh v pp setup to we# going high 2 100 ns t avwh address setup to we# going high 3 50 ns t dvwh data setup to we# going high 3 50 ns t whdx data hold from we# high 0 ns t whax address hold from we# high 0 ns t wheh ce# hold from we# high 0 ns t whwl we# pulse width high 20 ns t whgl write recovery before read 0 ns t qvvl v pp hold from valid srd 2,4 0 ns t qvph rp# v hh hold from valid srd 2,4 0 ns t qvsl wp# v ih hold from valid srd 2,4 0 ns notes: 1. read timing characteristics during block erase and word write operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a in and d in for block erase or word write. 4. v pp should be held at v pph1/2 (and if necessary rp# should be held at v hh ) until determination of block erase or word write success (sr.1/3/4/5=0). sharp
v il v ih v ih v ih v ih v il v il v il v il v ih v hh v il v pplk v pph2,1 v ih v il notes: 1. v cc power-up and standby. 2. write block erase or word write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. addresses(a) ce#(e) oe#(g) we#(w) data(d/q) rp#(p) v pp (v) } } } } } } 1 2 3 4 5 6 a in a in t avav t avwh t whax t elwl t wheh t whgl t whwl t whqv1,2 t wlwh t dvwh t whdx valid srd t phwl t vpwh t qvvl d in d in high z d in wp#(s) v ih v il t phhwh t qvph t shwh t qvsl lhf80bza 28 rev. 1.1 figure 12. ac waveform for we#-controlled write operations sharp
lhf80bza 29 rev. 1.1 6.2.6 alternative ce#-controlled writes (1) v cc =2.7v-3.6v, t a =-40c to +85c sym. parameter notes min. max. unit t avav write cycle time 90 ns t phel rp# high recovery to ce# going low 2 1 s t wlel we# setup to ce# going low 0 ns t eleh ce# pulse width 50 ns t phheh rp# v hh setup to ce# going high 2 100 ns t sheh wp# v ih setup to ce# going high 2 100 ns t vpeh v pp setup to ce# going high 2 100 ns t aveh address setup to ce# going high 3 50 ns t dveh data setup to ce# going high 3 50 ns t ehdx data hold from ce# high 0 ns t ehax address hold from ce# high 0 ns t ehwh we# hold from ce# high 0 ns t ehel ce# pulse width high 20 ns t ehgl write recovery before read 0 ns t qvvl v pp hold from valid srd 2,4 0 ns t qvph rp# v hh hold from valid srd 2,4 0 ns t qvsl wp# v ih hold from valid srd 2,4 0 ns notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a in and d in for block erase or word write. 4. v pp should be held at v pph1/2 (and if necessary rp# should be held at v hh ) until determination of block erase or word write success (sr.1/3/4/5=0). sharp
v il v ih v ih v il v il v ih v hh v il v pplk v pph2,1 v ih v il notes: 1. v cc power-up and standby. 2. write block erase or word write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. addresses(a) oe#(g) data(d/q) rp#(p) v pp (v) a in a in t avav t aveh t ehax t ehgl t ehdx valid srd t phel t vpeh t qvvl d in d in high z d in } } } } } } 1 2 3 4 5 6 v ih v il wp#(s) t phheh t qvph t sheh t qvsl v ih v il we#(w) t wlel t ehwh t ehqv1,2 t dveh v ih v il ce#(e) t ehel t eleh lhf80bza 30 rev. 1.1 figure 13. ac waveform for ce#-controlled write operations sharp
v il t plph v ih rp#(p) v il t 2vph (b)rp# rising timing v ih 2.7v v il rp#(p) v cc (a)reset timing device state device busy (reset operation) device busy device ready reset operating time lhf80bza 31 rev. 1.1 6.2.7 reset operations figure 14. ac waveform for reset operation reset ac specifications v cc =2.7v-3.6v sym. parameter notes min. max. unit t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) 100 ns reset operating time (during block erase or word write operation is executing) 1,2 22 s t 2vph v cc 2.7v to rp# high 3 100 ns notes: 1. if rp# is asserted while a block erase or word write operation is not executing, the reset will complete within 100ns. 2. a reset time, t phqv , is required from the later of reset operation is finished or rp# going high until outputs are valid. 3. when the device power-up, holding rp# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. sharp
lhf80bza 32 rev. 1.1 6.2.8 block erase and word write performance (3) v cc =2.7v-3.6v, t a =-40c to +85c v pp =2.7v-3.6v v pp =11.4v-12.6v sym. parameter notes typ. (1) max. typ. (1) max. unit t whqv1 word write time 32k word block 2 44.6 12.6 s t ehqv1 4k word block 2 45.9 24.5 s block write time 32k word block 2 1.46 0.42 s 4k word block 2 0.19 0.11 s t whqv2 block erase time 32k word block 2 1.14 0.51 s t ehqv2 4k word block 2 0.38 0.31 s word write suspend latency time to read 7 8 6 7 s erase suspend latency time to read 18 22 11 14 s notes: 1. typical values measured at t a =+25c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. sharp

rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph *1 v cc gnd v cc (min) rp# v il v ih (p) t phqv v ccw *2 gnd v ccwh1/2 (v) ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) wp# v il v ih (s) v oh v ol (d/q) data high z valid output t vr t f t r t elqv t f t glqv (a) address valid (rst#) (v pp ) t r or t f address v il v ih t avqv *1 t 5vph for the device in 5v operations. t r or t f t r t r *2 to prevent the unwanted writes, system designers should consider the v ccw (v pp ) switch, which connects v ccw (v pp ) to gnd during read operations and v ccwh1/2 (v pph1/2 ) during write or erase operations. (v pph1/2 ) see the application note ap-007-sw-e for details. sharp
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. t r (max.) and t f (max.) for rp# (rst#) are 100 s/v. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v sharp
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ?dc characteristics? describ ed in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises sharp
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit sharp
specifications are subject to change without notice. suggested applications (if any) are for standard use; see important restrictions for limitations on special applications. see limited warranty for sharp?s product warranty. the limited warranty is in lieu, and exclusive of, all other warranties, express or implied. all express and implied warranties, including the warranties of merchantability, fitness for use and fitness for a particular purpose, are specifically excluded. in no event will sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. north america europe japan sharp microelectronics of the americas 5700 nw pacific rim blvd. camas, wa 98607, u.s.a. phone: (1) 360-834-2500 fax: (1) 360-834-8903 fast info: (1) 800-833-9437 www.sharpsma.com sharp microelectronics europe division of sharp electronics (europe) gmbh sonninstrasse 3 20097 hamburg, germany phone: (49) 40-2376-2286 fax: (49) 40-2376-2232 www.sharpsme.com sharp corporation electronic components & devices 22-22 nagaike-cho, abeno-ku osaka 545-8522, japan phone: (81) 6-6621-1221 fax: (81) 6117-725300/6117-725301 www.sharp-world.com taiwan singapore korea sharp electronic components (taiwan) corporation 8f-a, no. 16, sec. 4, nanking e. rd. taipei, taiwan, republic of china phone: (886) 2-2577-7341 fax: (886) 2-2577-7326/2-2577-7328 sharp electronics (singapore) pte., ltd. 438a, alexandra road, #05-01/02 alexandra technopark, singapore 119967 phone: (65) 271-3566 fax: (65) 271-3855 sharp electronic components (korea) corporation rm 501 geosung b/d, 541 dohwa-dong, mapo-ku seoul 121-701, korea phone: (82) 2-711-5813 ~ 8 fax: (82) 2-711-5819 china hong kong sharp microelectronics of china (shanghai) co., ltd. 28 xin jin qiao road king tower 16f pudong shanghai, 201206 p.r. china phone: (86) 21-5854-7710/21-5834-6056 fax: (86) 21-5854-4340/21-5834-6057 head office: no. 360, bashen road, xin development bldg. 22 waigaoqiao free trade zone shanghai 200131 p.r. china email: smc@china.global.sharp.co.jp sharp-roxy (hong kong) ltd. 3rd business division, 17/f, admiralty centre, tower 1 18 harcourt road, hong kong phone: (852) 28229311 fax: (852) 28660779 www.sharp.com.hk shenzhen representative office: room 13b1, tower c, electronics science & technology building shen nan zhong road shenzhen, p.r. china phone: (86) 755-3273731 fax: (86) 755-3273735

▲Up To Search▲

Price & Availability of LH28F800BGHB-TTL90

	To Download LH28F800BGHB-TTL90 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .