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rev.0.02 2003.10.24 page 1 of 16 rej03c0100 - 0002z rev.0.02 2003.10.24 r1la1616r series 16mb supersram (1m wordx16bit) preliminary this product is under development and its specification might be changed without any notice. the r1la1616r series is a family of low voltage 16 - mbit static rams organized as 1048576 - words by 16 - bit, fabricated by renesas's high - performance 0.15um cmos and tft technologies. the r1la1616r series is suitable for memory applications wher e a simple interfacing , battery operating and battery backup are the important design objectives. the r1la1616r series is packaged in a 52pin micro thin small outline mount device[ tsop / 10.79mm x 10.49mm with the pin - pitch of 0.4mm] or a 48balls fine pitch ball grid array [ f - bga / 7.5mmx8.5mm with the ball - pitch of 0.75mm and 6x8 array] . it gives the best solution for a comp action of mounting area as well as flexibility of wiring pattern of printed circuit boards. ? single 1.65 - 2.3v power supply ? small stand - by current:3 a (1.8v, typ .) ? smaller stand - by current by "data retention mode"( ? cs2"='l') : 1 a (1.8v, typ .) ? data retention supply voltage =1.5v ? no clocks, no refresh ? easy memory expansion by cs1#, cs2, lb# and ub# ? common data i/o ? three - state outputs: or - tie capability ? oe# prevents data contention on the i/o bus ? process technology: 0.15um cmos description features
r1la1616r series rev. 0.02 2003. 10 . 24 page 2 of 16 preliminary this product is under development and its specification might be changed without any notice. type no. r1la1616rsd - 7si r1la1616rsd - 8si r1la1616rbg - 7si r1la1616rbg - 8si access time 70 ns 85 ns 70 ns 85 ns package 350 - mil 52 - pin plastic - tsop(ii) (normal - bend type) (52ptg) 7.5 mmx8.5mm f - bga 0.75mm pitch 48ball ordering information
r1la1616r series rev. 0.02 2003. 10 . 24 page 3 of 16 preliminary this product is under development and its specification might be changed without any notice. a0 to a19 dq 0 to dq15 cs1# &cs2 we# oe# lb# ub# vcc vss byte# nc pin name function address input data input/output chip select write enable output enable lower byte select upper byte select power supply ground byte control mode enable input non connection 52 - pin tsop 48 - pin fbga 1 2 3 4 5 6 a b c d e f g dq2 a7 dq0 cs2 vcc vss dq5 a2 cs1# dq1 dq3 dq4 dq6 a1 a4 a6 a5 a17 a16 a15 a0 a3 a14 oe# ub# dq14 dq12 dq11 dq9 lb# dq15 dq13 vss vcc dq10 dq7 we# a13 a12 a19 dq8 n.c. a11 a10 a9 a8 h a18 byte# 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 52 51 50 49 a16 dq0 a0 vss oe# dq8 dq1 dq9 dq2 nc vss dq10 dq3 dq11 dq4 dq12 dq5 dq13 dq6 dq14 dq7 dq15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a17 a11 a10 a15 17 18 19 20 21 22 23 24 a13 a12 a14 a9 a8 a7 a6 a5 a4 a1 a2 a3 we# a19 vcc cs1# 28 27 25 26 lb# cs2 nc nc nc nc ub# nc nc or vss pin arrangement pin description
r1la1616r series rev. 0.02 2003. 10 . 24 page 4 of 16 preliminary this product is under development and its specification might be changed without any notice. note, byte# pin supported by only tsop type. block diagram address buffer decoder cs2 we# oe# a 0 a 19 memory array 1048576 words x 16 bits or 2097152 words x 8 bits clock generator sense amplifier dq7 dq0 dq15 / a - 1 dq8 vcc vss data input buffer cs1# ub# lb# data selector data selector output buffer output buffer x8/x16 switching circuit byte# internal voltage supply circuit ( supplying voltage to internal circuits) sense amplifier data input buffer *
r1la1616r series rev. 0.02 2003. 10 . 24 page 5 of 16 preliminary this product is under development and its specification might be changed without any notice. note 1,h:vih l:vil x: vih or vil 2, byte# pin supported by only tsop type. when apply by te# = ? l ? ,please assign lb#=ub#= ? l ? . note 1: - 1.0v in case of ac (pulse width 30ns) 2:maximum voltage is +2.7v power supply voltage relative to vss terminal voltage on any pin relation tovss power dissipation storage temperature range parameter symbol value unit vcc - 0.5 to +2.7 v v t - 0.5* to vcc +0.3* v 1 2 p t 0.7 w tstg storage temperature range under bias tbias - 40 to + 85 - 65 to + 150 operation temperature topr - 40 to + 85 o c o c o c *3 notification about a new function of cs2 signal r1la1616r series use cs2 signal to control the internal voltage for as 'data retention mode'. in case of conventional sram products, both cs1# and cs2 signals are used a s control signals for device operation of active and stand - by modes. in terms of r1la1616r series, cs1# is an ordinary func tion that controls device operation, but cs2 function is to make a switch device status between 'stan d - by mode' and 'data retention mode', based on the input level of cs2 signal. in the concrete, when setting cs2 at a high level, a device status is changed from 'data retention mode' to 'stand - by mode'. and when setting cs2 at a low level, it's changed from 'stand - by mode' to 'data retention mode'. the latter is a new function. during ' data retention mode' with cs2='l', the reduction of current consumption is achieved by turning off the internal volt age supply except memory cell array. therefore in case of using with cs2 signal as for 'back up control with batte ry' , it will be realized the most suitable system. with regard to the detailed specifications for cs2 signal, ple ase refer to the item of "timing diagram" in p.11~p.14 and that of "data retention characteristics" in p.15. operating table absolute maximum ratings 3 2 we# high - z oe# dq0~7 x x dq8~14 high - z x l din h dout l high - z h high - z h h high - z high - z l din x h l dout ub# lb# high - z h high - z l write din x h read l dout high - z x x high - z high - z x x high - z operation stand - by l l l h h h l l l h x h h h l l l l l l h high - z high - z high - z high - z din dout x write in lower byte data retention stand - by cs2* h h h h h h cs1# l h l l l l l h h h l l l l x h x x byte#* h h h h h h x l l l h h h high - z h high - z l din x h l dout l l l l l l h h h l l l dq15 high - z high - z high - z din dout high - z high - z high - z high - z high - z din dout a - 1 a - 1 a - 1 high - z high - z h h h h x x x output disable read from lower byte write in upper byte read from upper byte write read output disable output disable output disable
r1la1616r series rev. 0.02 2003. 10 . 24 page 6 of 16 preliminary this product is under development and its specification might be changed without any notice. dc operating conditions note 1: typical parameter indicates the value for the center of distribution at 1.8v (ta=25 o c ) , and not 100% tested. 2: byte# pin supported by only tsop type. byte# 3 vcc - 0.2v or byte# 0.2v note 1 ? 1.0v in case of ac (pulse width 30ns) supply voltage input high voltage ambient temperature range parameter symbol note vcc v vss v ih ta input low voltage v il o c min 1.65 0 0.7 x vcc - 40 - 0.2 typ 1.80 0 max 2.30 0 vcc +0.2 85 0.4 unit v v v 1 parameter symbol test conditions* min typ * max unit input leakage current | i li | | i l0 | 1 output leakage current vin = vss to vcc operating current icc icc 1 icc 2 average operating current standby current standby current i sb i sb1 output hige voltage output low voltage v oh v ol i oh = - 0.1ma i ol = 0.1ma 1 1 3 ma 20 40 ma 1.5 8 ma 1.5 0.3 0.1 ma 5 3 a 1.3 0.2 v v ~+25 o c ~+40 o c ~+70 o c ~+85 o c 10 5 20 40 2 cs1# =v ih or cs2=v il or oe# = v ih or we# =v il or lb# =ub# =v ih, v i/o = vss to vcc cs1#=v il , cs2=v ih others = v ih / v il i i/o = 0 ma min. cycle, duty =100% i i/o = 0 ma ,cs1# =v il , cs2=v ih others = v ih / v il cycle time = 1 s,duty=100% i i/o = 0 ma ,cs1# =v il , cs2=v ih others = v ih / v il cs1#=cs2=v ih 0 v vin cs2 3 v cc - 0.2v (1)cs1# 3 vcc - 0.2v or (2) lb# = ub# 3 vcc - 0.2v cs1# 0.2v a a a a a dc characteristics
r1la1616r series rev. 0.02 2003. 10 . 24 page 7 of 16 preliminary this product is under development and its specification might be changed without any notice. ac characteristics test conditions ( vcc =1.65v~2.3v , ta = - 40~+85 o c) ? input pulse levels : vil= 0.2v, vih= vcc - 0.2v ? input rise and fall time : 5ns ? input and output timing reference levels : 0.9v ? output load : see figures (including scope and jig) cl=30pf cl=5fpf (for t clz , t blz , t olz , t chz , t clz , t bhz , t ohz , t owz , t ohz , t whz ) capacitance note 1: this parameter is sampled and not 100% tested. parameter symbol test conditions min typ max unit input capacitance v in =0v 10 pf note c in input / output capacitance c i/o v i/o =0v 10 pf 1 1 ( ta=+25 o c, f=1mhz) cl dq 1008 w 1210 w vcc
r1la1616r series rev. 0.02 2003. 10 . 24 page 8 of 16 preliminary this product is under development and its specification might be changed without any notice. read cycle r1la1616r** - 7si r1la1616r** - 8si parameter symbol min max min max unit notes t rc t aa t acs t oe t oh t ba t clz t blz t olz t chz t bhz t ohz 70 85 70 85 70 85 35 45 10 10 70 85 10 10 5 5 5 5 25 25 25 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 0 0 0 0 0 0 read cycle time address access time chip select access time output enable to output valid output hold from address change lb#,ub# access time chip select to output in low - z lb#,ub# enable to low - z output enable to output in low - z chip deselect to output in high - z lb#,ub# disable to high - z output disable to output in high - z
r1la1616r series rev. 0.02 2003. 10 . 24 page 9 of 16 preliminary this product is under development and its specification might be changed without any notice. write cycle r1la1616r** - 7si r1la1616r** - 8si parameter symbol min max min max unit notes t wc t aw t cw t wp t bw t as t wr t dw t dh t ow t ohz t whz 70 85 65 70 35 40 0 0 25 25 30 30 ns ns ns ns ns ns ns ns ns ns ns ns 6 7 2 1,2 1,2 5 0 0 5 0 0 65 70 55 60 65 70 0 0 0 0 5 4 write cycle time address valid to end of write chip selection to end of write write pulse width lb#,ub# valid to end of write address setup time write recovery time data to write time overlap data hold from write time output active from end of write output disable to output in high - z write to output in high - z note 1 . t chz , t ohz , t whz and t bhz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2.this parameter is sampled and not 100% tested. 3.at any given temperature and voltage condition, t hz max is less than t hz min both for a given device and form device to device. 4. a write occurs during the overlap of a low cs1#, a high cs2, a low we# and a low lb# or a low ub#. a write begins at the latest transition among cs1# go ing low, we# going low and lb# going low or ub# going low . a write ends at the earliest transitio n among cs1# going high, we# going high and lb# going high or ub# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1# going low to end of write. 6. t as is measured the address valid to the beginning of write. 7. t wr is measured from the earliest of cs1# or we# going high to the end of write cycle.
r1la1616r series rev. 0.02 2003. 10 . 24 page 10 of 16 preliminary this product is under development and its specification might be changed without any notice. byte control byte# timing waveform r1la1616r** - 7si r1la1616r** - 8si parameter symbol min max min max unit notes byte setup time t bs t br 5 5 5 5 ms ms byte recovery time t bs byte# cs1# t br
r1la1616r series rev. 0.02 2003. 10 . 24 page 11 of 16 preliminary this product is under development and its specification might be changed without any notice. timing waveform read cycle lb#,ub# a 0~19 ( word mode) a - 1~19 ( byte mode) dq 0~15 ( word mode) dq 0~7 ( byte mode) t aa we# = "h" level oe# v alid data cs1# t rc cs2 t pr * t acs t ba t clz t blz t oe t olz t ohz t chz t bhz t oh valid address note , about t pr , see data retention characteristics p.15
r1la1616r series rev. 0.02 2003. 10 . 24 page 12 of 16 preliminary this product is under development and its specification might be changed without any notice. write cycle (1) (we# clock) note , about t pr , see data retention characteristics p.15 a 0~19 ( word mode) a - 1~19 ( byte mode) dq 0~15 ( word mode) dq 0~7 ( byte mode) lb#,ub# we# cs1# cs2 t pr * t cw t bw t as t aw t wp t whz t ow t dw t dh t wr t wc valid data valid address
r1la1616r series rev. 0.02 2003. 10 . 24 page 13 of 16 preliminary this product is under development and its specification might be changed without any notice. write cycle (2) (cs1# ,cs2 clock, oe#=v ih ) t wc a 0~19 ( word mode) a - 1~19 ( byte mode) valid data dq 0~15 ( word mode) dq 0~7 ( byte mode) we# cs1# cs2 t as t bw t wr lb#,ub# t cw t pr * t wp t dw t dh valid address note , about t pr , see data retention characteristics p.15
r1la1616r series rev. 0.02 2003. 10 . 24 page 14 of 16 preliminary this product is under development and its specification might be changed without any notice. write cycle (3) ( lb#,ub# clock, oe#=v ih ) t wc a 0~19 ( word mode) a - 1~19 ( byte mode) dq 0~15 ( word mode) dq 0~7 ( byte mode) we# cs1# cs2 lb#,ub# valid data t as t bw t wr t cw t pr * t wp t dw t dh valid address note , about t pr , see data retention characteristics p.15
r1la1616r series rev. 0.02 2003. 10 . 24 page 15 of 16 preliminary this product is under development and its specification might be changed without any notice. data retention characteristics *1 note 5 . on the ub#,lb# control mode or the cs1# control mode ,when rec overing from the data retention mode , the level of ub# and lb# or cs1# during t pr period must be fixed 0.7v x vcc ~ vcc . data retention timing waveform (1) (lb#,ub# controlled) data retention timing waveform (2) (cs1# controlled) parameter symbol test conditions min typ max unit vcc for data retention v in 3 0v v dr 1.5 v 2.3 v v 0 v cs2 0.2v data retention current icc dr 1.0 37 a vcc =1.8v v in 3 0v cs2 0.2v chip deselect to data retention time operation recovery time t r t cdr 0 5 ns ms see retention waveform *2 *3,4 power off setup time power supply recovery time t pr t ps 0 200 ns s see retention waveform 3.0 17 8.0 3.0 a a a ~+25 o c ~+40 o c ~+70 o c ~+85 o c 0 v cs2 0.2v lb# ub# cs2 vcc t cdr t r t pr t ps *5 0.7 x vcc 0.7 x vcc 1.65 v cs1# cs2 vcc t cdr t r t pr t ps *5 0.7 x vcc 0.7 x vcc 1.65 v 0 v cs2 0.2v ( ta= - 40~+85 o c) note 1. different from conventional sram products, this is the redu ction mode of data retention current when cs2 is low. during cs2 low , internal voltage supply cir cuit is turned off except memory cell array. 2.typical parameter of i cc dr indicates the value for the center of distribution at vcc =1.8v and not 100% tested. 3. byte# pin supported by tsop type. byte# 3 vcc - 0.2v or byte# 0.2v 4. also cs2 controls address buffer, we# buffer ,cs1# buffer ,oe# buffer ,lb# ,ub# buffer and din buffer . in the data retention mode (0v cs2 0.2v) , vin levels (address, we# ,oe#,cs1#,lb#,ub#,i/o) can be in the high impedance state.
r1la1616r series rev. 0.02 2003. 10 . 24 page 16 of 16 preliminary this product is under development and its specification might be changed without any notice. sales strategic planning div. nippon bldg., 2 - 6 - 2, ohte - machi , chiyoda - ku , tokyo 100 - 0004, japan copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. http://www. renesas .com keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semi conductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, f ire or property damage. remember to give due consideration to safety when making your ci rcuit designs, with appropriate measures such as (i) placement o f substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunctio n or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our cus tomers in the selection of the renesas technology corporation product best suited to the customer ? s application; they do not convey any license under any intellectual property rights , or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage , or infringement of any third - party ? s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including produ ct data, diagrams, charts, programs and algorithms represents in formation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvemen ts or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracie s or typographical errors. renesas technology corporation assumes no responsibility for any damage , liability, or other loss rising from these inaccuracies or err ors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www. renesas .com). 4. when using any or all of the information contained in these m aterials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicab ility of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manuf actured for use in a device or system that is used under circums tances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems f or transportation, vehicular, medical, aerospace, nuclear, or un dersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan an d/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
(1/1) rev. date description page summary 0.01 jul. 04, 2003 first edition issued revision history r1la1616r series data sheet 0.02 oct. 24, 2003 revise a write occurs during the overlap of a low cs1#, a high cs2, a l ow we# and a low lb# or a low ub#.a write begins at the latest transition among c s1# going low, cs2 going high , we# going low and lb# going low or ub# going low . a write e nds at the earliest transition among cs1# going high , cs2 going low , we# going high and lb# going high or ub# going high. twp is measured from the beginning of write to the end of write. 9 note 4. former removed ? cs2 signal operation ? from note 4,5 & 7 as follows. a write occurs during the overlap of a low cs1#, a high cs2, a l ow we# and a low lb# or a low ub#.a write begins at the latest transition among c s1# going low, we# going low and lb# going low or ub# going low . a write ends at the earliest transition among cs1# going high , we# going high and lb# going high or ub# going high. twp is measured from the beginning of write to the end of write. note 4. revision twr is measured from the earliest of cs1# or we# going high or cs2 going low to the end of write cycle. note 7. former twr is measured from the earliest of cs1# or we# going high to the end of write cycle. note 7. revision tcw is measured from the later of cs1# going low or cs2 going high to end of write note 5. former tcw is measured from the later of cs1# going low to end of write. note 5. revision 5 in ? note 2 ? , add instructions ? when apply byte# = ? l ? ,please assign lb#=ub#= ? l ? . ? 3 change pin name ? i/o 0 to i/o15 ? to ? dq 0 to dq15 ? in ? pin description ? .

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