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stpc ? elite x86 core general purpose pc compatible system - on - chip issue 0.1 - october 17, 2000 1/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. logic diagram n powerful x86 processor n 64-bit sdram controller n pci master / slave controller n isa master/slave n 16-bit local bus interface n eide controller n integrated peripheral controller - dma controller - interrupt controller - timer / counters n power management unit n i c interface n 16 general purpose i/o. n jtag ieee1149.1 n programmable output clock description the stpc elite integrates a fully static x86 proc- essor, fully compatible with standard x86 proces- sors, and combines it with powerful chipset to pro- vide a general purpose pc compatible subsystem on a single device. the device is packaged in a 388 ball grid array (pbga). n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back and write through capability. n parallel processing integral floating point unit, with automatic power down. n clock core speeds up to of 100 mhz in x1 clock mode and 133mhz in x2 mode. n fully static design for dynamic clock control. n low power and system management modes. pbga388 s t p c e l i t e x86 core host i/f sdram control pci pci isa i/f eide ctrl pci isa bus eide l.b. i/f local bus ipc jtag pmu
2/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. n sdram controller n 64-bit data bus. n up to 100mhz sdram clock speed. n supports 8mb up to 128 mb system memory. n supports 16-, 64- and 128-mbit memories. n supports up to 4 memory banks. n supports buffered, non buffered, registered dimms n 4-line write buffers for cpu to dram and pci to dram cycles. n 4-line read prefetch buffers for pci masters. n programmable latency n programmable timing for dram parameters. n supports -8, -10, -12, -13, -15 memory parts n supports memory hole between 1mb and 8mb for pci/isa busses. n pci controller n compliant with pci 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external logic allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n 0.25x, 0.33x and 0.5x host clock pci clock. n isa master/slave n generates the isa clock from either 14.318mhz oscillator clock or pci clock n supports programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n 16-bit i/o decoding. n local bus interface n multiplexed with isa/dma/timer functions. n high speed, low latency bus. n supports 32-bit flash burst. n 16-bit data bus with word steering capability. n separate memory and i/o address spaces. n programmable timing (host clock granularity) n supports 2 cashable banks of 16mb flash devices with boot block shadowed to 0x000f0000. n 2 programmable flash/eprom chip select. n 4 programmable i/o chip select. n 2-level hardware key protection for flash boot block protection. n 22 bit address bus. n eide controller n compatible with eide (ata-2). n backward compatibility with ide (ata-1). n supports up to 4 ide devices n supports pio and bus master ide n concurrent channel operation (pio & dma modes) - 4 x 32-bit buffer fifo per channel n support for 11.1/16.6 mb/s, i/o channel ready pio data transfers. n bus master with scatter/gather capability. n multi-word dma support for fast ide drives. n individual drive timing for all four ide devices. n supports both legacy & native ide modes. n supports hard drives larger than 528mb. n support for cd-rom and tape peripherals. n integrated peripheral controller n 2x8237/at compatible 7-channel dma controller. n 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n supports external rtc.
issue 0.1 - october 17, 2000 3/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports smm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n supports rtc, interrupts and dmas wake-up n gpios n 16 general purpose io. n jtag function n programmable gp-clock n this clock is programmable to frequencies up to 135 mhz.
4/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.
general description issue 0.1 - october 17, 2000 5/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 1 general description at the heart of the stpc elite is an advanced processor block that includes a powerful x86 proc- essor core along with a 64-bit sdram controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt control- ler, dma controller, interval timer and isa bus) and eide controller. the processor bus runs at the speed of the proc- essor (x1 mode) or half the speed (x2 mode). the stmicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. the core has all the functionality of the st standard x86 processor products, including the low power sys- tem management mode (smm). system management mode (smm) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. while run- ning in isolated smm address space, the smm in- terrupt routine can execute without interfering with the operating system or application programs. further power management facilities include a suspend mode that can be initiated from either hardware or software. because of the static nature of the core, no internal data is lost. the `standard' pc chipset functions (dma, inter- rupt controller, timers, power management logic) are integrated with the x86 processor core. the pci bus is the main data communication link to the stpc elite chip. the stpc elite translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports generation of config- uration cycles on the pci bus. the stpc elite, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also imple- ments the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three external pci de- vices. the stpc elite integrates an isa bus controller. peripheral modules such as parallel and serial communications ports, keyboard controllers and additional isa devices can be accessed by the stpc elite chip set through this bus. an industry standard eide (ata 2) controller is built in to the stpc elite and connected internally via the pci bus. the stpc elite core is compliant with the ad- vanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal comput- ers. the power management unit module (pmu) controls the power consumption providing a com- prehensive set of features that control the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu provides fol- lowing hardware structures to assist the software in managing the power consumption by the sys- tem. - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system perform- ance in various power down states of the system including full power on state. - power control outputs to disable power from dif- ferent planes of the board. lack of system activity for progressively longer period of times is detected by the three power down timers. these timers can generate smi in- terrupts to cpu so that the smm software can put the system in decreasing states of power con- sumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states: doze state, stand-by state and sus- pend mode. these correspond to decreasing lev- els of power savings. power down puts the stpc elite into suspend mode. the processor completes execution of the current instruction, any pending decoded instruc- tions and associated bus cycles. during the sus- pend mode, internal clocks are stopped. remov- ing power down, the processor resumes instruc- tion fetching and begins execution in the instruc- tion stream at the point it had stopped.
general description 6/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. memory controller the stpc handles the memory data (data) bus directly, controlling from 2 to 128 mbytes. the sdram controller supports accesses to the mem- ory banks to/from the cpu (via the host) , from the vmi, to/from the crtc, to the video & to/from the ge. (banks 0 to 3) which can be populated with either single or double sided 72-bit (4 bit par- ity) dimms. parity is not supported. the sdram controller only supports 64 bit wide memory banks. four memory banks (if dimms are used; single sided or two double-sided dimms) are supported in the following configurations (seetable 1-1) table 1-1. memory configurations memory bank size number organisa tion device size 1mx64 4 1mx16 16mbits 2mx64 8 2mx8 4mx64 16 4mx4 4mx64 4 2mx16x2 64mbits 8mx64 8 4mx8x2 16mx64 16 8mx4x2 4mx64 4 1mx16x4 8mx64 8 2mx8x4 32mx64 16 4mx4x4 16mx64 8 2mx16x2 128mbits 32mx64 16 4mx8x4
general description issue 0.1 - october 17, 2000 7/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 1-1. functional description. host i/f x86 core sdram pci m/s isa m/s eide pci m/s isa bus ipc 82c206 eide gpio x16 general purpose chip select local bus i/f jtag local bus
general description 8/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 1-2. typical application stpc elite isa pci 4x 16-bit sdrams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy irq dma.req dma.ack dmux dmux mux mux rtc gpios
pin description issue 0.1 - october 17, 2000 9/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2 pin description 2.1 introduction the stpc elite integrates most of the functionali- ties of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devices are totally internal to the stpc elite. this offers im- proved performance due to the tight coupling of the processor core and these peripherals. as a re- sult many of the external pin connections are made directly to the on-chip peripheral functions. figure 2-1 shows the stpc elite external interfac- es. it defines the main busses and their function. table 2-1 describes the physical implementation listing signals type and their functionality.table 2- 2 provides a full pin listing and description of pins. table 2-5 provides a full listing of pin locations of the stpc elite package by physical connection. note: several interface pins are multiplexed with other functions, refer to table 2-3 and table 2-4 for further details table 2-1. signal description group name qty basic clocks reset & xtal 6 memory interface 96 pci interface 56 isa 79 90 ide 34 local bus 50 grounds 69 v dd 24 miscellaneous 8 gpio 16 unconnected 23 total pin count 388 figure 2-1. stpc elite external interfaces south north pci x86 sdram i/f sys isa/ide/lb 96 56 6 90 stpc elite
pin description 10/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 2-2. definition of signal pins signal name dir description qty basic clocks and resets sysrseti# 2 i system power good input 1 sysrsto# 2 o system reset output 1 xtali i 14.3mhz crystal input 1 xtalo i/o 14.3mhz crystal output - external oscillator input 1 hclk i/o host clock (test) 1 gp_clk o general purpose clock 1 v dd _xxx_pll 1 power supply for pll clocks memory interface mclki i memory clock input 1 mclko o memory clock output 1 cs#[1:0] o dimm chip select 2 cs#[3]/ma[12]/ba[1] o dimm chip select/ memory address/ bank address 1 cs#[2]/ma[11] o dimm chip select/ bank address 1 ba[0] o bank address ma[10:0] o memory row & column address 12 md[63:0] 3 i/o memory data 64 ras#[1:0] o row address strobe 2 cas#[1:0] o column address strobe 2 mwe# o write enable 1 dqm[7:0] o data input/output mask 8 pci interface pci_clki i 33mhz pci input clock 1 pci_clko o 33mhz pci output clock (from internal pll) 1 ad[31:0] 2 i/o pci address / data 32 cbe[3:0] 2 i/o bus commands / byte enables 4 frame# 2 i/o cycle frame 1 irdy# 2 i/o initiator ready 1 trdy# 2 i/o target ready 1 lock# 2 i pci lock 1 devsel# 2 i/o device select 1 stop# 2 i/o stop transaction 1 par 2 i/o parity signal transactions 1 serr# 2 o system error 1 pci_req#[2:0] 2 i pci request 3 pci_gnt#[2:0] 2 o pci grant 3 pci_int[3:0] 2 i pci interrupt request 4 isa control isa_clk o isa clock output - multiplexer select line for ipc 1 isa_clk2x o isa clock x2 output - multiplexer select line for ipc 1 osc14m 2 o isa bus synchronisation clock 1 note 1 ; these pins must be connected to the 2.5vpower supply. they must not be connected to the 3.3v supply. note 2 ; denotes that the pin is v 5t (see section 4 ) note 3 ; see table 2-5 for v 5t signals
pin description issue 0.1 - october 17, 2000 11/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. la[23:17] 2 o unlatched address 7 sa[19:0] 2 i/o latched address 20 sd[15:0] 2 i/o data bus 16 ale 2 o address latch enable 1 memr# 2 , memw# 2 i/o memory read and memory write 2 smemr# 2 , smemw# 2 o system memory read and memory write 2 ior# 2 , iow# 2 i/o i/o read and write 2 mcs16# 2 , iocs16# 2 i memory/io chip select16 2 bhe# 2 o system bus high enable 1 zws# 2 i zero wait state 1 ref# 2 o refresh cycle. 1 master# 2 i add on card owns bus 1 aen 2 o address enable 1 iochck# 2 i i/o channel check. 1 iochrdy 2 i/o i/o channel ready (isa) - busy/ready (ide) 1 isaoe# 2 o isa/ide selection 1 gpiocs# 2 i/o general purpose chip select 1 irq_mux[3:0] 2 i time-multiplexed interrupt request 4 dreq_mux[1:0] 2 i time-multiplexed dma request 2 dack_enc[2:0] 2 o encoded dma acknowledge 3 tc 2 o isa terminal count 1 rtcas 2 o real time clock address strobe 1 rmrtccs# 2 i/o rom/rtc chip select 1 kbcs# 2 i/o keyboard chip select 1 rtcrw# 2 i/o rtc read/write 1 rtcds 2 i/o rtc data strobe 1 local bus pa[23:0] 2 o address bus 24 pd[15:0] i/o data bus 16 prd1#,prd0# o peripheral read control 2 pwr1#,pwr0# o peripheral write control 2 prdy# i data ready 1 fcs1#, fcs0# o flash chip select 2 iocs#[3:0] o i/o chip select 4 ide control da[2:0] o address bus 3 dd[15:0] i/o data bus 16 pcs3#,pcs1#,scs3#,scs1# o primary & secondary chip selects 4 diordy o data i/o ready 1 pirq 2 , sirq 2 i primary & secondary interrupt request 2 pdrq 2 , sdrq 2 i primary & secondary dma request 2 pdack# 2 , sdack# 2 o primary & secondary dma acknowledge 2 pdior# 2 , sdior# 2 o primary & secondary i/o channel read 2 table 2-2. definition of signal pins signal name dir description qty note 1 ; these pins must be connected to the 2.5vpower supply. they must not be connected to the 3.3v supply. note 2 ; denotes that the pin is v 5t (see section 4 ) note 3 ; see table 2-5 for v 5t signals
pin description 12/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. pdiow# 2 , sdiow# 2 o primary & secondary i/o channel write 2 miscellaneous gpio[15:0] 2 i/o general purpose i/os 16 spkrd 2 o speaker device output 1 scl 2 i/o i c interface - clock / can be used for vga ddc[1] signal 1 sda 2 i/o i c interface - data / can be used for vga ddc[0] signal 1 scan_enable 2 i reserved (test pin) 1 tclk 2 i test clock 1 tdi 2 i test data input 1 tms 2 i test mode input 1 tdo 2 o test data output 1 table 2-2. definition of signal pins signal name dir description qty note 1 ; these pins must be connected to the 2.5vpower supply. they must not be connected to the 3.3v supply. note 2 ; denotes that the pin is v 5t (see section 4 ) note 3 ; see table 2-5 for v 5t signals
pin description issue 0.1 - october 17, 2000 13/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2 signal descriptions 2.2.1 basic clocks and resets sysrsti# system reset/power good. this input is low when the reset switch is depressed. other- wise, it reflects the power supply's power good signal. this input is asynchronous to all clocks, and acts as a negative active reset. the reset cir- cuit initiates a hard reset on the rising edge of this signal. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3mhz crystal input xtalo 14.3mhz crystal output. these pins are connected to the 14.318 mhz crystal to provide the reference clock for the internal frequency syn- thesizer to generate all the other clocks. a 14.318 mhz series cut quartz crystal should be connected between these two pins. balance capacitors of 15 pf should also be added. in the event of an external oscillator providing the master clock signal to the stpc elite device, the ttl sig- nal should be provided on xtalo. hclk host clock. this clock supplies the cpu and the host related blocks. this clock can e dou- bled inside the cpu and is intended to operate in the range of 25 to 100 mhz. this clock in generat- ed internally from a pll but can be driven directly from the external system. gp_clk general purpose clock. this clock is programmable and its frequency can be as high as 135 mhz. 2.2.2 memory interface mclki memory clock input. this clock is driving the sdram controller, the graphics engine and display controller. this input should be a buffered version of the mclko signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the dimms. mclko memory clock output. this clock is driv- ing the dimms on board and is generated from an internal pll. the default value is 66mhz. cs#[2]/ma[11] chip select/ bank address this pin is cs#[2] in the case when 16mbit devices are used. for all other densities, it becomes ma[11]. cs#[3]/ma[12]/ba[1] chip select/ memory ad- dress/ bank address this pin is cs#[3] in the case when 16mbit devices are used. for all other den- sities, it becomes ma[12] when 2 internal banks devices are used and ba[1] when 4 internal bank devices are used. ma[10:0] memory address. multiplexed row and column address lines. ba[0] memory bank address. cs#[1:0] chip select these signals are used to disable or enable device operation by masking or enabling all sdram inputs except mclk, cke, and dqm. md[63:0] memory data. this is the 64-bit memory data bus. md[40-0] are read by the device strap option registers during rising edge of sysrsti#. ras#[1:0] row address strobe. these signals enable row access and precharge. row address is latched on rising edge of mclk when ras# is low. cas#[1:0] column address strobe. these sig- nals enable column access. column address is latched on rising edge of mclk when cas# is low. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). dqm#[7:0] data mask. makes data output hi-z after the clock and masks the sdram outputs. blocks sdram data input when dqm active. 2.2.3 pci interface pci_clki 33mhz pci input clock. this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33mhz pci output clock. this is the master pci bus clock output. ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. cbe#[3:0] bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data
pin description 14/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc elite owns the bus and outputs when the stpc elite owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc elite owns the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc elite initiates a bus cycle on the pci bus. it is used as an input during the pci cycles targeted to the stpc elite to determine when the current pci master is ready to complete the cur- rent transaction. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc elite is the target of the current bus transaction. it is used as an input when stpc elite initiates a cycle on the pci bus. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. devsel# i/o device select. this signal is used as an input when the stpc elite initiates a bus cy- cle on the pci bus to determine if a pci slave de- vice has decoded itself to be the target of the cur- rent transaction. it is asserted as an output either when the stpc elite is the target of the current pci transaction or when no other device asserts devsel# prior to the subtractive decode phase of the current pci transaction. stop# stop transaction. stop is used to imple- ment the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc elite and is used as an output when a pci master cycle is targeted to the stpc elite. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc elite initiated pci transaction. its assertion by ei- ther the stpc elite or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. pci_req#[2:0] pci request. this pin are the three external pci master request pins. they indi- cates to the pci arbiter that the external agents desire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it on its pcireq#. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. vdd5 5v power supply. these power pins are necessary for 5v esd protection. in case the pci bus is used in 3.3v only, these pins can be con- nected to 3.3v. 2.2.4 isa interface isa_clk, isa_clkx2 isa clock x1, x2. these pins generate the clock signal for the isa bus and a doubled clock signal. they are also used as the multiplexor control lines for the interrupt controller interrupt input lines. isa_clk is generated from either pciclk/4 or osc14m/ 2. osc14m isa bus synchronisation clock output. this is the buffered 14.318 mhz clock for the isa bus. la[23:17] unlatched address. when the isa bus is active, these pins are isa bus unlatched ad- dress for 16-bit devices. when isa bus is ac- cessed by any cycle initiated from pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are in input mode. sa[19:0] isa address bus. system address bus of isa on 8-bit slot. these pins are used as an in- put when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus. these pins are the exter- nal databus to the isa bus. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc elite to indicate that la23-17, sa19- 0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc elite. ale is driven low after reset. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in-
pin description issue 0.1 - october 17, 2000 15/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc elite generates smemr# signal of the isa bus only when the address is below one megabyte or the cycle is a refresh cycle. smemw# system memory write. the stpc elite generates smemw# signal of the isa bus only when the address is below one megabyte. ior# i/o read. this is the io read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the io write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. mcs16# memory chip select16. this is the de- code of la23-17 address pins of the isa address bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc elite ignores this signal during io and refresh cy- cles. iocs16# io chip select16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc elite does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc elite is execut- ed as an extended 8-bit io cycle. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. zws# zero wait state. this signal, when assert- ed by addressed device, indicates that current cy- cle can be shortened. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc elite performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a re- fresh cycle. the stpc elite performs a pseudo hidden re- fresh. it requests the host bus for two host clocks to drive the refresh address and capture it in exter- nal buffers. the host bus is then relinquished while the refresh cycle continues on the isa bus. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. iochrdy channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc elite. the stpc elite monitors this sig- nal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc elite since the access to the system memory can be consid- erably delayed due uma architecture. isaoe# bidirectional oe control. this signal con- trols the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. gpiocs# i/o general purpose chip select. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the external pe- ripheral devices or any other desired function. irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they have to be encoded before connection to the stpc elite using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq pin of the rtc. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc elite using isaclk and isaclkx2 as the input selection strobes.
pin description 16/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc elite before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.5 x-bus interface pins rtcas# real time clock address strobe. this sig- nal is asserted for any i/o write to port 70h. rmrtccs# rom/real time clock chip select. this signal is asserted if a rom access is decod- ed during a memory cycle. it should be combined with memr# or memw# signals to properly ac- cess the rom. during a io cycle, this signal is as- serted if access to the real time clock (rtc) is decoded. it should be combined with ior or iow# signals to properly access the real time clock. kbcs# keyboard chip select. this signal is as- serted if a keyboard access is decoded during a i/ o cycle. rtcrw# real time clock rw. this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcrw#. this signal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is a multi- function pin. when isaoe# is active, this signal is used as rtcds. this signal is asserted for any i/ o read to port 71h. note: rmrtccs#, kbcs#, rtcrw# and rtcds# signals must be ored externally with isaoe# and then connected to the external de- vice. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor as shown in figure 2-2. 2.2.6 local bus pa[23:0] address bus output. pd[15:0] data bus. this is the 16-bit data bus. d[7:0] is the lsb and pd[15:8] is the msb. prd#[1:0] read control output. prd0# is used to read the lsb and prd1# to read the msb. pwr#[1:0] write control output. pwr0# is used to write the lsb and pwr1# to write the msb. prdy# data ready input. this signal is used to create wait states on the bus. when low, it com- pletes the current cycle. fcs#[1:0] flash chip select output. these are the programmable chip select signals for up to 2 banks of flash memory. iocs#[3:0] i/o chip select output. these are the programmable chip select signals for up to 4 ex- ternal i/o devices. 2.2.7 ide interface da[2:0] address. these signals are connected to da[2:0] of ide devices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored with isaoe# before being connected to the ide devic- es. dd[15:0] databus. when the ide bus is active, they serve as ide signals dd[11:0]. ide devices are connected to sa[19:8] directly and isa bus is connected to these pins through two ls245 trans- ceivers as described infigure 2-2. pcs1#, pcs3# primary chip select. these sig- nals are used as the active high primary master & slave ide chip select signals. these signals must be externally anded with the isaoe # signal be- fore driving the ide devices to guarantee it is ac- tive only when isa bus is idle. scs1#, scs3# secondary chip select. these signals are used as the active high secondary master & slave ide chip select signals. these sig- nals must be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. diordy busy/ready. this pin serves as ide sig- nal diordy. pirq primary interrupt request. sirq secondary interrupt request. interrupt request from ide channels. pdrq primary dma request. sdrq secondary dma request. dma request from ide channels. pdack# primary dma acknowledge. sdack# secondary dma acknowledge. dma acknoledge to ide channels. pdior#, pdiow# primary i/o read & write. sdior#, sdiow# secondary i/o read & write . primary & secondary channel read & write.
pin description issue 0.1 - october 17, 2000 17/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 2.2.8 miscellaneous gpio[15:0] general purpose i/os spkrd speaker drive. this the output to the speaker and is and of the counter 2 output with bit 1 of port 61, and drives an external speaker driver. this output should be connected to 7407 type high voltage driver. scl, sda i c interface . these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open-collector output drivers which are internally connected to v dd through pull-up resistors. they can be used for the ddc1 (scl) and ddc0 (sda) lines of the vga interface. scan_enable reserved . the pin is reserved for test and miscellaneous functions. vdd_core 2.5v core power supply. these power pins are necessary to supply the core with 2.5v. tclk test clock tdi test data input tms test mode input tdo test data output
pin description 18/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. .. table 2-3. isa / ide dynamic multiplexing isa bus (isaoe# = 0) ide (isaoe# = 1) rmrtccs# dd[15] kbcs# dd[14] rtcrw# dd[13] rtcds dd[12] sa[19:8] dd[11:0] la[23] scs3# la[22] scs1# sa[21] pcs3# sa[20] pcs1# la[19:17] da[2:0] iochrdy diordy table 2-4. isa / local bus pin sharing isa / ipc local bus sd[15:0] pd[15:0] dreq_mux[1:0] pa[21:20] smemr# pa[19] memw# pa[18] bhe# pa[17] aen pa[16] ale pa[15] memr# pa[14] ior# pa[13] iow# pa[12] ref# pa[11] iochck# pa[10] gpiocs# pa[9] zws# pa[8] sa[7:4] pa[7:4] tc, dack_enc[2:0] pa[3:0] sa[3] prdy# isaoe#,sa[2:0] iocs#[3:0] dev_clk, rtcas# fcs#[1:0] iocs16#, master# prd#[1:0] smemw#, mcs16# pwr#[1:0] isaclk, isa_clk2x figure 2-2. typical isa/ide demultiplexing master# 74ls245 rmrtccs# ab dir oe isaoe# kbcs# rtcrw# rtcds sa[19:8] stpc bus / dd[15:0] la[22] la[23] sa[20] sa[21] scs1# scs3# pcs1# pcs3#
pin description issue 0.1 - october 17, 2000 19/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 2-5. pinout. pin # pin name af3 sysrseti# ae4 sysrseto# a3 xtali c4 xtalo g23 hclk 2 h24 gp_clk af15 mclki ab23 mclko ae16 ma[0] ad15 ma[1] af16 ma[2] ae17 ma[3] ad16 ma[4] af17 ma[5] ae18 ma[6] ad17 ma[7] af18 ma[8] ae19 ma[9] ae20 ma[10] ac19 ba[0] af22 cs#[0] ad21 cs#[1] ae24 cs#[2]/ma[11] ad23 cs#[3]/ma[12]/ba[1] af23 ras#[0] ad22 ras#[1] ae21 cas#[0] ac20 cas#[1] af20 dqm#[0] ad19 dqm#[1] af21 dqm#[2] ad20 dqm#[3] ae22 dqm#[4] ae23 dqm#[5] af19 dqm#[6] ad18 dqm#[7] ac22 mwe# r1 md[0] 3 t2 md[1] 3 r3 md[2] t1 md[3] r4 md[4] u2 md[5] t3 md[6] u1 md[7] for note definition see table 2-2 definition of signal pins u4 md[8] 3 v2 md[9] 3 u3 md[10] v1 md[11] w2 md[12] v3 md[13] y2 md[14] w4 md[15] y1 md[16] w3 md[17] aa2 md[18] y4 md[19] aa1 md[20] y3 md[21] ab2 md[22] ab1 md[23] aa3 md[24] ab4 md[25] ac1 md[26] ab3 md[27] ad2 md[28] ac3 md[29] ad1 md[30] af2 md[31] af24 md[32] ae26 md[33] ad25 md[34] ad26 md[35] ac25 md[36] ac24 md[37] ac26 md[38] ab25 md[39] ab24 md[40] ab26 md[41] aa25 md[42] y23 md[43] aa24 md[44] aa26 md[45] y25 md[46] y26 md[47] y24 md[48] w25 md[49] 3 v23 md[50] 3 w26 md[51] 3 w24 md[52] 3 v25 md[53] 3 v26 md[54] 3 pin # pin name for note definition see table 2-2 definition of signal pins u25 md[55] 3 v24 md[56] 3 u26 md[57] 3 u23 md[58] 3 t25 md[59] 3 u24 md[60] 3 t26 md[61] 3 r25 md[62] 3 r26 md[63] 3 f24 pci_clki 2 d25 pci_clko b20 ad[0] c20 ad[1] b19 ad[2] a19 ad[3] c19 ad[4] b18 ad[5] a18 ad[6] b17 ad[7] c18 ad[8] a17 ad[9] d17 ad[10] b16 ad[11] c17 ad[12] b15 ad[13] a15 ad[14] c16 ad[15] b14 ad[16] d15 ad[17] a14 ad[18] b13 ad[19] d13 ad[20] a13 ad[21] c14 ad[22] b12 ad[23] c13 ad[24] a12 ad[25] c12 ad[26] a11 ad[27] d12 ad[28] b10 ad[29] c11 ad[30] a10 ad[31] d10 cbe[0] c10 cbe[1] a9 cbe[2] pin # pin name for note definition see table 2-2 definition of signal pins
pin description 20/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. b8 cbe[3] a8 frame# b7 trdy# d8 irdy# a7 stop# c8 devsel# b6 par d7 serr# a6 lock# d20 pci_req#[0] c21 pci_req#[1] a21 pci_req#[2] c22 pci_gnt#[0] a22 pci_gnt#[1] b21 pci_gnt#[2] a5 pci_int[0] c6 pci_int[1] b4 pci_int[2] d5 pci_int[3] f2 la[17]/da[0] g4 la[18]/da[1] f3 la[19]/da[2] f1 la[20]/pcs1# g2 la[21]/pcs3# g1 la[22]/scs1# h2 la[23]/scs3# j4 sa[0] h1 sa[1] h3 sa[2] j2 sa[3] j1 sa[4] k2 sa[5] j3 sa[6] k1 sa[7] k4 sa[8] l2 sa[9] k3 sa[10] l1 sa[11] m2 sa[12] m1 sa[13] l3 sa[14] n2 sa[15] m4 sa[16] m3 sa[17] p2 sa[18] p4 sa[19] pin # pin name for note definition see table 2-2 definition of signal pins k25 sd[0] l24 sd[1] k26 sd[2] k23 sd[3] j25 sd[4] k24 sd[5] j26 sd[6] h25 sd[7] h26 sd[8] j24 sd[9] g25 sd[10] h23 sd[11] d24 sd[12] c26 sd[13] a25 sd[14] b24 sd[15] ad4 isa_clk af4 isa_clk2x c9 osc14m p25 ale ae8 zws# r23 bhe# p26 memr# r24 memw# n25 smemr# n23 smemw# n26 ior# p24 iow# n24 mcs16# m26 iocs16# m25 master# l25 ref# m24 aen l26 iochck# t24 iochrdy m23 isaoe# a4 rtcas# p3 rtcds# r2 rtcrw# p1 rmrtccs# ae3 gpiocs# g26 pa[22] 2 a20 pa[23] b1 pirq pin # pin name for note definition see table 2-2 definition of signal pins c2 sirq c1 pdrq d2 sdrq d3 pdack# d1 sdack# e2 pdior# e4 pdiow# e3 sdior# e1 sdiow# e23 irq_mux[0] d26 irq_mux[1] e24 irq_mux[2] c25 irq_mux[3] a24 dreq_mux[0] b23 dreq_mux[1] c23 dack_enc[0] a23 dack_enc[1] b22 dack_enc[2] d22 tc n3 kbcs# ae5 gpio[0] ac5 gpio[1] ad5 gpio[2] af5 gpio[3] ae6 gpio[4] ac7 gpio[5] ad6 gpio[6] af6 gpio[7] ae7 gpio[8] af7 gpio[9] ad7 gpio[10] ad8 gpio[11] ae9 gpio[12] af9 gpio[13] ae10 gpio[14] ad9 gpio[15] c5 spkrd b5 scl c7 sda b3 scan_enable g3 tclk n1 tms w1 tdi ac2 tdo pin # pin name for note definition see table 2-2 definition of signal pins
pin description issue 0.1 - october 17, 2000 21/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. g24 vdd_cpuclk_pll 1 f25 vdd_devclk_pll 1 ac17 vdd_mclki_pll 1 ac15 vdd_mclko_pll 1 f26 vdd_hclk_pll 1 d11 vdd_core 1 l23 vdd_core 1 t4 vdd_core 1 ac6 vdd_core 1 d6 vdd d16 vdd d21 vdd f4 vdd f23 vdd l4 vdd t23 vdd aa4 vdd aa23 vdd ac11 vdd ac16 vdd ac21 vdd e25 vdd_pll_skew a1:2 vss a26 vss b2 vss b25:26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss n4 vss n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss pin # pin name for note definition see table 2-2 definition of signal pins ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad14 vss ad24 vss ae1:2 vss ae25 vss af1 vss af25 vss af26 vss ad11 unconnected ac9 unconnected ac10 unconnected ac12 unconnected ac14 unconnected ad10 unconnected ad12 unconnected ad13 unconnected ae11 unconnected ae12 unconnected ae13 unconnected ae14 unconnected ae15 unconnected af8 unconnected af10 unconnected af11 unconnected af12 unconnected af13 unconnected af14 unconnected a16 unconnected b11 unconneted b9 unconnected d18 unconnected e26 unconnected c15 unconnected pin # pin name for note definition see table 2-2 definition of signal pins
pin description 22/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.
strap option issue 0.1 - october 17, 2000 23/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 3 strap option this chapter defines the strap options and their location. some strap options have been left programmable for future versions of silicon. . memory data lines refer to designation location actual settings set to '0' set to '1' md0 reserved index 4a, bit 0 - - - md1 reserved index 4a, bit 1 - - - md2 hclk pll speed hckl_pll index 5f, bit 6 user defined see section 3.1.4 md3 hclk pll speed hckl_pll index 5f, bit 7 user defined md4 pci clock pci_clko divisor index 4a, bit 4 user defined see section 3.1.3 md5 mckl mclk_hclk_synch index4, bit 5 user defined unsynch synchronized md6 pci clock pci_clk setup index 4a, bit 6 user defined see section 3.1.1 md7 index 4a, bit 7 user defined md8 reserved index 4b, bit 0 - - - md9 reserved index 4b, bit 1 - - - md10 pci clock pci_clki skew index 4b, bit 2 user defined enabled bypassed md11 index 4b, bit 3 user defined default user control md12 index 4b, bit 4 user defined disable enabled md13 index 4b, bit 5 user defined disable enabled md14 reserved index 4b, bit 6 - - - md15 reserved index 4b, bit 7 - - - md16 gpio gpio_config index 4c, bit 0 user defined test mode normal md17 pci clock pci_cklo divisor index 4c, bit 1 user defined see section 3.1.3 md18 hclk hclk direction index 4c, bit 2 pull up external internal md19 mclko mclko direction index 4c, bit 3 pull up external internal md20 cpu clock multiplier hardware - see section 3.1.7 md21 reserved index 5f, bit 0 pull up - - md22 reserved index 5f, bit 1 pull up - - md23 reserved index 4c, bit 7 pull up - - md24 hclk hclk pll speed index 5f, bit 3 md[3:2] - md[26:24] mhz md25 index 5f, bit 4 00-000 25 md26 index 5f, bit 5 00-001 50 00-010 60 00-100 66 01-001 75 01-110 82.5 10-011 90 11-001 100 others reserved md27 reserved hardware pull down md28 reserved hardware pull down md29 reserved hardware pull down md30 reserved hardware pull down md31 reserved hardware pull down md32 reserved hardware pull down md33 reserved hardware pull down
strap option 24/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 3.1 power on strap registers description 3.1.1 strap register 0 configuration index 4ah (strap0) bits 7-6 pciclk programming; the pciclk pll is setup through md[7:6]. the pll setup will vary depending on the pciclk frequency. bit 5 this bit reflects the value sampled on md[5] pin and controls the mclk/hclk synchroniza- tion. when mclk and hclk frequency are the same, when set to 1 it unifies hclk and mclk and so improve system performances. bit 4 this bit reflects the value sampled on md[4] pin and controls the pciclko division. it works with md[17] refer to section 3.1.3 bit 1 for more detail. bits 3-2 these bits are the same as index 5fh bits [7:6]. bits 1-0 reserved . 3.1.2 strap register 1 configuration index 4bh (strap1) bits 7-6 reserved . bits 5-4 these bits reflect the value sampled on md[13:12] pin and controls t he deskew logic on pciclki. if bit 3 is set to 1, this programmes the 2 msb of the delay start point of the deskewer. bit 3 this bit reflects the value sampled on md[11] pin and controls the deskew logic on pci- clki. if 1, it allows the user to control the starting point of this logic (see bits 5-4 above). if 0, we use default start. bit 2 this bit reflects the value sampled on md[10] pin and controls the deskew logic on pci- clki. if 0, this logic is enabled, if 1 it is bypassed. bits 1-0 reserved . 3.1.3 strap register 2 configuration index 4ch (strap2) bits 7-4 reserved . md34 reserved hardware pull down md35 cpu clock cpu clk skew hardware user defined clk lead clk lag md40 cpu clock multiplier hardware user defined md[20,40] multiplier 00 x1 01 x2 10 reserved 11 reserved md41 reserved hardware pull down - - md42 reserved hardware pull up - - md43 reserved hardware pull down - - md44 reserved hardware pull down - - md45 hclk hclki pll md[46:45] hclk md46 00 < 32mhz 01 32 - 64 10 > 64mhz 11 disabled md47 sdram power on sequence hardware user defined disabled enabled md48 mclki skew corrector pll hardware user defined disabled enabled memory data lines refer to designation location actual settings set to '0' set to '1' bit 7 bit 6 description 00 pciclk frequency between 16 & 32 mhz 01 pciclk frequency between 32 & 64 mhz 10 pciclk frequency greater than 64 mhz 1 1 reserved
strap option issue 0.1 - october 17, 2000 25/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. bit 3 this bit reflects the value sampled on md[19] pin and controls the memory clock output (mclko) source as follows: 0: external. mclko pin is tristated. 1: internal. mclko pin is an output and is con- nected to the internal frequency synthesizer output. bit 2 this bit reflects the value sampled on md[18] pin and controls the host/cpu clock source as follows: 0: external. hclk pin is an input. 1: internal. hclk pin is an output and is con- nected to the internal frequency synthesizer output. bit 1 this bit reflects the value sampled on md[17] pin and controls the pci clock output as follows and is programmed in parallel with md[4]: bit 0 this bit reflects the value sampled on md[16] pin and controls the configuration of gpio[8:0]. 0: configured as test bus. 1: configured as normal ios. this register defaults to the values sampled on md[23] & md[20:16] pins after re set. 3.1.4 strap register 0 configuration index 5fh bits 7-3 these bits reflect the values sampled on md[3:2] and md[26:24] pins respectively and control the host clock frequency synthesizer as follows: bit 2-0 reserved this register defaults to the values sampled on above pins after reset. 3.1.5 delay programming for dll the bits md[30:27] are used to set the delay of the host clock entering the on c hip dll used to gen- erate pci_clko that is synchronous with hclk. these bits must be set to the values stated in the table above. 3.1.6 hclki programming the hclki clock signal is selected and pro- grammed through strap values on md[35:31] & md[46:45]. md[46:45] set the source of the hclki and the programming value if the pll option is chosen. md[46:45] hclki source the bits md[35:31] are used to set the correct skew between the chipset host clock (hclki) and the cpu clock. md[35] controls whether the cpu clock leads (strap to vss) or lags (strap to vdd) the chipset host clock. md[34:31] must be set to the values stated in the table above. these bits are only enabled when md[46:45] are set to 11. md[4] md[17] description 0 0 pci clock output = hclk / 4 0 1 pci clock output = hclk / 4 1 0 pci clock output = hclk / 3 1 1 pci clock output = hclk / 2 bit 7 bit 6 bit 5 bit 4 bit 3 hclk frequency 00000 25mhz 00001 50mhz 00010 60mhz 00011 66mhz 01001 75mhz 0 1 1 1 0 82.5 mhz 10011 90mhz 1 1 0 0 1 100 mhz bit 46 bit 45 hclk source 00 hclki pll enabled & hclki frequen- cy between 16 & 32 mhz 01 hclki pll enabled & hclki frequen- cy between 32 & 64 mhz 10 hclki pll enabled & hclki frequen- cy greater than 64 mhz 11 hclki pll disabled; delay chains se- lected bit 7 bit 6 bit 5 bit 4 bit 3 hclk frequency
strap option 26/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 3.1.7 x86 clock programming the bits md[40] and md[20] are used to set the clock multiplication factor of the 486 core. the default value of the resistors on these strap inputs should be 2 resistors to gnd (dx mode). 3.1.8 sdramc power on sequence this bit reflects the value sampled on md[47] pin . when this bit is strapped to logic one, then the sdram power on sequence is activated. when strapped to logic one the power on se- quence is disabled. 3.1.9 mclki selection this bit reflects the value sampled on md[48] pin . when this bit is strapped to logic one, then the mclki skew corrector pll is disabled; other- wise it is enabled, as it should be in user mode. md20 md40 x86 mode 0 0 x1(x1) 0 1 x2 (x2) 10 reserved 11 reserved
electrical specifications issue 0.1 - october 17, 2000 27/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4 electrical specifications 4.1 introduction the electrical specifications in this chapter are val- id for the stpc elite. 4.2 electrical connections 4.2.1 power/ground connections/decoupling due to the high frequency of operation of the stpc elite, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc elite and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 k w ( 10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k w ( 10%) pull-up resistor to prevent spurious operation. 4.2.3 reserved designated pins pins designated reserved should be left discon- nected. connecting a reserved pin to a pull-up re- sistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc elite device. stresses be- yond those listed under table 4-1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that oper- ation under any conditions other than those spec- ified in section 14.4 ooperating conditionso. ex- posure to conditions beyondtable 4-1 may (1) re- duce device reliability and (2) result in premature failure even when there is no immediately appar- ent sign of failure. prolonged exposure to condi- tions at or near the absolute maximum ratings ( ta- ble 4-1) may also result in reduced useful life and reliability. table 4-1. absolute maximum ratings symbol parameter minimum maximum units v ddx dc supply voltage -0.3 4.0 v v core dc supply voltage for core 2.75 v v i ,v o digital input and output voltage -0.3 vdd + 0.5 v v 5t 5volt tolerance 5.5 v v esd esd capacity (human body mode) 2000 v t stg storage temperature -40 +150 c t oper operating temperature (tcase) -40 +115 c p tot total power dissipation (package) 5 w
electrical specifications 28/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4.4 dc characteristics notes: 1. mhz ratings refer to cpu clock frequency. 2. not 100% tested. 3. consider vdd = 5v for 5v tolerant i/os. 4.5 ac characteristics table 4-4 through table 4-7 list the ac character- istics including output delays, input setup require- ments, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 and figure 4-2. the rising clock edge reference level vref , and other reference levels are shown in table 4-3 below for the stpc elite. input or output signals must cross these levels during testing. figure 4-1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, de- fining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. note: refer to figure 4-1. table 4-2. dc characteristics recommended operating conditions : vdd = 3.3v 0.3v, vcore = 2.5v 0.25v, tcase = -40 to 115 c unless otherwise specified symbol parameter test condition s min typ max unit v dd operating voltage 3.0 3.3 3.6 v v core operating voltage 2.25 2.50 2.75 v v dd5 5v operating voltage note 3 4.5 5 5.5 v p dd supply power v dd = 3.3v, v core = 2.5v, h clk = 100mhz 1.5 w h clk internal clock (note 1) 133 mhz v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.9 v v ih input high voltage except xtali 2 v dd +0.5 v (note 3) xtali 2.35 v dd +0.5 v i lk input leakage current input, i/o -1 2 m a c in input capacitance (note 2) pf c out output capacitance (note 2) pf c clk clock capacitance (note 2) pf table 4-3. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v
electrical specifications issue 0.1 - october 17, 2000 29/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 4-1. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd figure 4-2. clk timing measurement points clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1 legend: t1 - one clock cycle t2 - minimum time at v ih t3 - minimum time at v il t4 - clock fall time t5 - clock rise time note; all signals are sampled on the rising edge of the clk.
electrical specifications 30/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4.5.1 power on sequence sysrsti# has no constraint on its rising time but needs to be set to high at least 10 m s after power supply is stable. strap options are continuously sampled during sysrsti# low and should be stable. once sysrsti# is high, they must not change until sysrsto# is high. strap options 3.3v supply sysrsti# sysrsto# 14mhz 1.6v valid configuration >10us hclk pci_clk 2.3 ms frame#
electrical specifications issue 0.1 - october 17, 2000 31/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4.5.2 ac timing characteristics table 4-4. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 11 ns t2 pci_clki to frame valid 2 11 ns t3 pci_clki to cbe[3:0] valid 2 11 ns t4 pci_clki to par valid 2 11 ns t5 pci_clki to trdy valid 2 11 ns t6 pci_clki to irdy valid 2 11 ns t7 pci_clki to stop valid 2 11 ns t8 pci_clki to devsel valid 2 11 ns t9 pci_clki to pci_gnt valid 2 12 ns t10 ad[31:0] bus setup to pci_clki 7 ns t11 ad[31:0] bus hold from pci_clki 0 ns t12 pci_req[2:0] setup to pci_clki 10 ns t13 pci_req[2:0] hold from pci_clki 0 ns t14 cbe[3:0] setup to pci_clki 7 ns t15 cbe[3:0] hold to pci_clki 0 ns t16 irdy setup to pci_clki 7 ns t17 irdy hold to pci_clki 0 ns t18 frame setup to pci_clki 7 ns t19 frame hold from pci_clki 0 ns table 4-5. ide bus ac timing name parameter min max unit t20 dd[15:0] setup to pior/sior falling 15 ns t21 dd[15:0} hold to pior/sior falling 12 ns table 4-6. sdram bus ac timing name parameter min max unit t22 mclki to output signal valid on ma[11:0], ras#[1:0], cas#[1:0], mwe# 1.5 6.2 ns t23 mclki to output signal valid on cs# 1.5 7.6 ns t24 mclki to output signal valid on dqm[7:0] 1.5 8.1 ns t25 mclki to output signal valid on md[63:0] 1.5 8.2 ns t26 input setup time to mclki on md[63:0] 3.1 - ns t27 input hold time from mclki on md[[63:0] 3.0 - ns
electrical specifications 32/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 4.5.3 isa interface ac timing charcteristics figure 4-3 isa cycle (ref table table 4-7 ) note 1; stands for smemr#, smemw#, memr#, memw#, ior# & iow#. note; the clock has not been represented as it cannot be accuratly represented depending on the isa slave mode. valid aenx valid address valid address,sbhe* v.data validdata 54 28 26 64 59 58 55 28 23 61 48 47 26 23 57 27 24 42 41 10 11 34 33 3 22 56 29 25 9 18 2 12 38 37 15 14 13 12 ale aen la [23:17] sa [19:0] control (note 1) iocs16# mcs16# iochrdy read data write data table 4-7. isa bus ac timing name parameter min max units 2 4 la[23:17] valid before ale# negated 5t cycles 3 4 la[23:17] valid before memr#, memw# asserted 3a 4 memory access to 16 bit isa slave 5t cycles 3b 4 memory access to 8 bit isa slave 5t cycles 9 4 sa[19:0] & sbhe valid before ale# negated 1t cycles 10 4 sa[19:0] & sbhe valid before memr#, memw# asserted 10a 4 memory access to 16 bit isa slave 2t cycles 10b 4 memory access to 8 bit isa slave 2t cycles 10 4 sa[19:0] & shbe valid before smemr#, smemw# asserted 10c 4 memory access to 16 bit isa slave 2t cycle 10d 4 memory access to 8 bit isa slave 2t cycle note; the signal numbering refers to table 4-3 note 4; these timings are extracted from simulations and are not garanteed by testing
electrical specifications issue 0.1 - october 17, 2000 33/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 10e 4 sa[19:0] & sbhe valid before ior#, iow# asserted 2t cycles 11 4 xtalo to iow# valid 11a 4 memory access to 16 bit isa slave - 2bclk 2t cycles 11b 4 memory access to 16 bit isa slave - standard 3bclk 2t cycles 11c 4 memory access to 16 bit isa slave - 4bclk 2t cycles 11d 4 memory access to 8 bit isa slave - 2bclk 2t cycles 11e 4 memory access to 8 bit isa slave - standard 3bclk 2t cycles 12 4 ale# asserted before ale# negated 1t cycles 13 4 ale# asserted before memr#, memw# asserted 13a 4 memory access to 16 bit isa slave 2t cycles 13b 4 memory access to 8 bit isa slave 2t cycles 13 4 ale# asserted before smemr#, smemw# asserted 13c 4 memory access to 16 bit isa slave 2t cycles 13d 4 memory access to 8 bit isa slave 2t cycles 13e 4 ale# asserted before ior#, iow# asserted 2t cycles 14 4 ale# asserted before al[23:17] 14a 4 non compressed 15t cycles 14b 4 compressed 15t cycles 15 4 ale# asserted before memr#, memw#, smemr#, smemw# negated 15a 4 memory access to 16 bit isa slave- 4 bclk 11t cycles 15e 4 memory access to 8 bit isa slave- standard cycle 11t cycles 18a 4 ale# negated before la[23:17] invalid (non compressed) 14t cycles 18a 4 ale# negated before la[23:17] invalid (compressed) 14t cycles 22 4 memr#, memw# asserted before la[23:17] 22a 4 memory access to 16 bit isa slave. 13t cycles 22b 4 memory access to 8 bit isa slave. 13t cycles 23 4 memr#, memw# asserted before memr#, memw# negated 23b 4 memory access to 16 bit isa slave standard cycle 9t cycles 23e 4 memory access to 8 bit isa slave standard cycle 9t cycles 23 4 smemr#, smemw# asserted before smemr#, smemw# negated 23h 4 memory access to 16 bit isa slave standard cycle 9t cycles 23l 4 memory access to 16 bit isa slave standard cycle 9t cycles 23 4 ior#, iow# asserted before ior#, iow# negated 23o 4 memory access to 16 bit isa slave standard cycle 9t cycles 23r 4 memory access to 8 bit isa slave standard cycle 9t cycles 24 4 memr#, memw# asserted before sa[19:0] 24b 4 memory access to 16 bit isa slave standard cycle 10t cycles 24d 4 memory access to 8 bit isa slave - 3blck 10t cycles 24e 4 memory access to 8 bit isa slave standard cycle 10t cycles 24f 4 memory access to 8 bit isa slave - 7bclk 10t cycles 24 4 smemr#, smemw# asserted before sa[19:0] 24h memory access to 16 bit isa slave standard cycle 10t cycles 24i 4 memory access to 16 bit isa slave - 4bclk 10t cycles 24k 4 memory access to 8 bit isa slave - 3bclk 10t cycles 24l 4 memory access to 8 bit isa slave standard cycle 10t cycles table 4-7. isa bus ac timing name parameter min max units note; the signal numbering refers to table 4-3 note 4; these timings are extracted from simulations and are not garanteed by testing
electrical specifications 34/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 24 4 ior#, iow# asserted before sa[19:0] 24o 4 i/o access to 16 bit isa slave standard cycle 19t cycles 24r 4 i/o access to 16 bit isa slave standard cycle 19t cycles 25 4 memr#, memw# asserted before next ale# asserted 25b 4 memory access to 16 bit isa slave standard cycle 10t cycles 25d 4 memory access to 8 bit isa slave standard cycle 10t cycles 25 4 smemr#, smemw# asserted before next ale# aserted 25e 4 memory access to 16 bit isa slave - 2bclk 10t cycles 25f 4 memory access to 16 bit isa slave standard cycle 10t cycles 25h 4 memory access to 8 bit isa slave standard cycle 10t cycles 25 4 ior#, iow# asserted before next ale# asserted 25i 4 i/o access to 16 bit isa slave standard cycle 10t cycles 25k 4 i/o access to 16 bit isa slave standard cycle 10t cycles 26 4 memr#, memw# asserted before next memr#, memw# asserted 26b 4 memory access to 16 bit isa slave standard cycle 12t cycles 26d 4 memory access to 8 bit isa slave standard cycle 12t cycles 26 4 smemr#, smemw# asserted before next smemr#, smemw# asserted 26f 4 memory access to 16 bit isa slave standard cycle 12t cycles 26h 4 memory access to 8 bit isa slave standard cycle 12t cycles 26 4 ior#, iow# asserted before next ior#, iow# asserted 26i 4 i/o access to 16 bit isa slave standard cycle 12t cycles 26k 4 i/o access to 8 bit isa slave standard cycle 12t cycles 28 4 any command negated to memr#, smemr#, memr#, smemw# asserted 28a 4 memory access to 16 bit isa slave 3t cycles 28b 4 memory access to 8 bit isa slave 3t cycles 28 4 any command negated to ior#, iow# asserted 28c 4 i/o access to isa slave 3t cycles 29a 4 memr#, memw# negated before next ale# asserted 1t cycles 29b 4 smemr#, smemw# negated before next ale# asserted 1t cycles 29c 4 ior#, iow# negated before next ale# asserted 1t cycles 33 4 la[23:17] valid to iochrdy negated 33a 4 memory access to 16 bit isa slave - 4 bclk 8t cycles 33b 4 memory access to 8 bit isa slave - 7 bclk 14t cycles 34 4 la[23:17] valid to read data valid 34b 4 memory access to 16 bit isa slave standard cycle 8t cycles 34e 4 memory access to 8 bit isa slave standard cycle 14t cycles 37 4 ale# asserted to iochrdy# negated 37a 4 memory access to 16 bit isa slave - 4 bclk 6t cycles 37b 4 memory access to 8 bit isa slave - 7 bclk 12t cycles 37c 4 i/o access to 16 bit isa slave - 4 bclk 6t cycles 37d 4 i/o access to 8 bit isa slave - 7 bclk 12t cycles 38 4 ale# asserted to read data valid 38b 4 memory access to 16 bit isa slave standard cycle 4t cycles 38e 4 memory access to 8 bit isa slave standard cycle 10t cycles 38h 4 i/o access to 16 bit isa slave standard cycle 4t cycles table 4-7. isa bus ac timing name parameter min max units note; the signal numbering refers to table 4-3 note 4; these timings are extracted from simulations and are not garanteed by testing
electrical specifications issue 0.1 - october 17, 2000 35/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 38l 4 i/o access to 8 bit isa slave standard cycle 10t cycles 41 4 sa[19:0] sbhe valid to iochrdy negated 41a 4 memory access to 16 bit isa slave 6t cycles 41b 4 memory access to 8 bit isa slave 12t cycles 41c 4 i/o access to 16 bit isa slave 6t cycles 41d 4 i/o access to 8 bit isa slave 12t cycles 42 4 sa[19:0] sbhe valid to read data valid 42b 4 memory access to 16 bit isa slave standard cycle 4t cycles 42e 4 memory access to 8 bit isa slave standard cycle 10t cycles 42h 4 i/o access to 16 bit isa slave standard cycle 4t cycles 42l 4 i/o access to 8 bit isa slave standard cycle 10t cycles 47 4 memr#, memw#, smemr#, smemw#, ior#, iow# asserted to iochrdy negated 47a 4 memory access to 16 bit isa slave 2t cycles 47b 4 memory access to 8 bit isa slave 5t cycles 47c 4 i/o access to 16 bit isa slave 2t cycles 47d 4 i/o access to 8 bit isa slave 5t cycles 48 4 memr#, smemr#, ior# asserted to read data valid 48b 4 memory access to 16 bit isa slave standard cycle 2t cycles 48e 4 memory access to 8 bit isa slave standard cycle 5t cycles 48h 4 i/o access to 16 bit isa slave standard cycle 2t cycles 48l 4 i/o access to 8 bit isa slave standard cycle 5t cycles 54 4 iochrdy asserted to read data valid 54a 4 memory access to 16 bit isa slave 1t(r)/2t(w) cycles 54b 4 memory access to 8 bit isa slave 1t(r)/2t(w) cycles 54c 4 i/o access to 16 bit isa slave 1t(r)/2t(w) cycles 54d 4 i/o access to 8 bit isa slave 1t(r)/2t(w) cycles 55a 4 iochrdy asserted to memr#, memw#, smemr#, smemw#, ior#, iow# negated 1t cycles 55b 4 iochry asserted to memr#, smemr# negated (refresh) 1t cycles 56 4 iochrdy asserted to next ale# asserted 2t cycles 57 4 iochrdy asserted to sa[19:0], sbhe invalid 2t cycles 58 4 memr#, ior#, smemr# negated to read data invalid 0t cycles 59 4 memr#, ior#, smemr# negated to daabus float 0t cycles 61 4 write data before memw# asserted 61a 4 memory access to 16 bit isa slave 2t cycles 61b 4 memory access to 8 bit isa slave (byte copy at end of start) 2t cycles 61 4 write data before smemw# asserted 61c 4 memory access to 16 bit isa slave 2t cycles 61d 4 memory access to 8 bit isa slave 2t cycles 61 4 write data valid before iow# asserted 61e 4 i/o access to 16 bit isa slave 2t cycles 61f 4 i/o access to 8 bit isa slave 2t cycles 64a 4 memw# negated to write data invalid - 16 bit 1t cycles 64b 4 memw# negated to write data invalid - 8 bit 1t cycles table 4-7. isa bus ac timing name parameter min max units note; the signal numbering refers to table 4-3 note 4; these timings are extracted from simulations and are not garanteed by testing
electrical specifications 36/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 64c 4 smemw# negated to write data invalid - 16 bit 1t cycles 64d 4 smemw# negated to write data invalid - 8 bit 1t cycles 64e 4 iow# negated to write data invalid 1t cycles 64f 4 memw# negated to copy data float, 8 bit isa slave, odd byte by isa master 1t cycles 64g 4 iow# negated to copy data float, 8 bit isa slave, odd byte by isa master 1t cycles table 4-7. isa bus ac timing name parameter min max units note; the signal numbering refers to table 4-3 note 4; these timings are extracted from simulations and are not garanteed by testing
mechanical data issue 0.1 - october 17, 2000 37/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 5. mechanical data 5.1 388-pin package dimension the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1. dimensions are shown in figure 5-2, table 5-1 and figure 5-3, table 5-2. figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 1113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 11 13 15 17 19 21 23 25 2468101214161820222426
mechanical data 38/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c
mechanical data issue 0.1 - october 17, 2000 39/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g
mechanical data 40/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 5.2 388-pin package thermal data 388-pin pbga package has a power dissipation capability of 4.5w which increases to 6w when used with a heatsink. structure in shown in figure 5-4. thermal dissipation options are illustrated infig- ure 5-5 and figure 5-6. figure 5-4. 388-pin pbga structure thermal balls power & ground layers signal layers figure 5-5. thermal dissipation without heatsink ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centered on board copper thickness: -17 m m for internal layers -34 m m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the center balls
mechanical data issue 0.1 - october 17, 2000 41/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centered on board copper thickness: -17 m m for internal layers -34 m m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1 c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the center balls
mechanical data 42/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.
board layout issue 0.1 - october 17, 2000 43/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6. board layout 6.1 thermal dissipation thermal dissipation of the stpc depends mainly on supply voltage. as a result, when the system does not need to work at 3.45v, it is interesting to reduce the voltage to 3.15v, for example, if it is possible. this may save few 100's of mw. the second area to look at is unused interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dy- namic adjustment is also a solution that can be used along with the integrated power manage- ment unit. the standard way to route thermal balls to internal ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga 388 pack- age does 90% of the thermal dissipation through the ground balls, and especially the central ther- mal balls which are directly connected to the die, the remaining 10% is dissipated through the case. adding a heat sink reduces this value to 85%. as a result, some basic rules has to be applied when routing the stpc in order to avoid thermal problems. first of all, the whole ground layer acts as a heat sink and ground balls must be directly connected to it as illustrated in figure 6-1. if one ground layer is not enough, a second ground plane may be added on solder side. figure 6-1. ground routing pad for ground ball thru hole to ground layer t o p l a y e r : s i g n a l s g r o u n d l a y e r p o w e r l a y e r b o t t o m l a y e r : s i g n a l s + l o c a l g r o u n d l a y e r ( i f n e e d e d ) note: for better visibility, ground balls are not all routed.
board layout 44/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. when considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-2. the use of a 8-mil wire results in a thermal resistance of 105 c/w assuming copper is used (418 w/ m. k). this high value is due to the thickness (34 m m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9 c/w. this can be easily im- proved using four 10 mil wires to connect to the four vias around the ground pad link as infigure 6-3. this gives a total of 49 vias and a global re- sistance for the 36 thermal balls of 0.6 c/w. the use of a ground plane like in figure 6-4 is even better. to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad), this gives a di- ameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no lo- cal boar d distortion is tolerated. the thickness of the copper on pcb layers is typ- ically 34 m m for external layers and 17 m m for inter- nal layers. that means thermal dissipation is not good and temperature of the board is concentrat- ed around the devices and falls quickly with in- creased distance. when it is possible to place a metal layer inside the pcb, this improves dramatically the heat spreading and hence thermal dissipation of the board. figure 6-2. recommended 1-wire ground pad layout figure 6-3. recommended 4-wire ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 10 mil) via (diameter = 24 mil) 34 . 5mil 1 mil = 0.0254 mm 4 via pads for each ground ball
board layout issue 0.1 - october 17, 2000 45/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. the pbga package dissipates also through pe- ripheral ground balls. when a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipa- tion through the peripheral ground balls. the more via pads are connected to each ground ball, the more heat is dissipated . the only limita- tion is the risk of lossing routing channels. figure 6-5 shows a routing with a good trade off between thermal dissipation and number of rout- ing channels. a local ground plane on opposite side of the board as shown in figure 6-6 improves thermal dissipa- tion. it is used to connect decoupling capacitances but can also be used for connection to a heat sink or to the system's metal box for better dissipation. this possibility of using the whole system's box for thermal dissipation is very usefull in case of high temperature inside the system and low tempera- ture outside. in that case, both sides of the pbga should be thermally connected to the metal chas- sis in order to propagate the heat flow through the metal. figure 6-7 illustrates such implementation. 6.2 high speed signals some interfaces of the stpc run at high speed and have to be carefully routed or even shielded. here is the list of these interfaces, in decreasing speed order: 1) memory interface. 2) graphics and video interfaces 3) pci bus 4) 14mhz oscillator stage all the clocks haves to be routed first and shielded for speeds of 27mhz or more. the high speed sig- nals follow the same contrainsts, like the memory control signals and the pci control signals. the next interfaces to be routed are memory, vid- eo/graphics, and pci. all the analog noise sensitive signals have to be routed in a separate area and hence can be rout- ed indepedently. figure 6-4. optimum layout for central ground ball via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil
board layout 46/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 6-5. global ground layout for good thermal dissipation figure 6-6. bottom side layout and decoupling ground pad via to ground layer ground plane for thermal dissipation via to ground layer
board layout issue 0.1 - october 17, 2000 47/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 6-7. use of metal plate for thermal dissipation figure 6-8. shielding signals metal planes thermal conductor board die ground ring ground pad shielded signal line ground pad shielded signal lines
board layout 48/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3 memory interface 6.3.1 introduction in order to achieve sdram memory interfaces which work at clock frequencies of 100mhz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. the guidelines described below are related to sdram components on dimm modules. for ap- plications where the memories are directly sol- dered to the motherboard, the pcb should be laid out such that the trace lengths fit within the con- straints shown here. the traces could be slightly longer since the extra routing on the dimm pcb is no longer present but it is then up to the user to verify the timings. 6.3.2 sdram clocking scheme the sdram clocking scheme deserves a special mention here. basically the memory clock is gen- erated on-chip through a pll and goes directly to the mclko output pin of the stpc. the nominal frequency is 100mhz. because of the high load presented to the mclk on the board by the dimms it is recommeded to rebuffer the mclko signal on the board and balance the skew to the clock ports of the different dimms and the mclki input pin of stpc. 6.3.3 board layout issues the physical layout of the motherboard pcb as- sumed in this presentation is as shown infigure 6-10. because all the memory interface signal balls are located in the same region of the stpc device it is possible to orientate the device to re- duce the trace lengths. the worst case routing length to the dimm1 is estimated to be 100mm. solid power and ground planes are a must in order to provide good return paths for the signals and to reduce emi and noise. also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change layers. if possible the traces should be routed adjacent to the same power or ground plane for the length of the trace. for the sdram interface the most critical signal is the clock. any skew between the clocks at the sdram components and the memory controller will impact the timing budget. in order to get well matched clocks at all the components it is recom- mended that all the dimm clock pins, stpc mem- ory clock input (mclki) and any other component using the memory clock are individually driven figure 6-9. clock scheme dimm1 mclki mclko dimm2 pll register pll ma[] + control md[] sdram controller
board layout issue 0.1 - october 17, 2000 49/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. from a low skew clock driver with matched routing lengths. this is shown infigure 6-11. the maximum skew between pins for this part is 250ps. the important factors for the clock buffer are a consistent drive strength and low skew be- tween the outputs. the delay through the buffer is not important so it does not have to be a zero de- lay pll type buffer. the trace lengths from the clock driver to the dimm ckn pins should be matched exactly. since the propagation speed can vary between pcb layers the clocks should be routed in a consistent way. the routing to the stpc memory input should be longer by 75mm to compensate for the extra clock routing on the dimm. also a 20pf capacitor should be placed as near as possible to the clock input of the stpc to compensate for the dimm's higher clock load. the impedance of the trace used for the clock routing should be matched to the dimm clock trace im- pedance (60-75 ohms ). to minimise crosstalk the clocks should be routed with spacing to adja- cent tracks of at least twice the clock trace width. for designs which use sdrams directly mounted on the motherboard pcb all the clock trace lengths should be matched exactly. the dimm sockets should be populated starting with the furthest dimm from the stpc device first (dimm1). there are 2 types of dimm devices; sin- gle row and dual row. the dual row devices re- figure 6-10. dimm placement dimm2 dimm1 stpc 35mm 35mm 15mm 10mm 116mm sdram i/f figure 6-11. clock routing mclko dimm ckn input stpc mclki dimm ckn input dimm ckn input low skew clock driver: l l+75mm* 20pf * no additionnal 75mm when sdram directly soldered on board
board layout 50/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. quire 2 chip select signals to select between the two rows. a stpc device with 4 chip select control lines could control either 4 single row dimms or 2 dual row dimms. when using dimm modules, schematics have to be done carefully in order to avoid data busses completely crossed on the board. this has to be checked at the library level. in order to achive lay- out shown in figure 6-12, schematics have to im- plement the crossing described on figure 6-13. the dqm signals must be exchanged using the same order. figure 6-12. optimum data bus layout for dimm figure 6-13. schematics for optimum data bus layout for dimm dimm stpc sdram i/f d[15:00] d[31:16] d[47:32] d[63:48] md[31:00] md[63:32] md[15:00],dqm[1:0] md[31:16],dqm[3:2] md[47:32],dqm[5:4] md[63:48],dqm[7:6] d[15:00],dqm[1:0] d[31:16],dqm[3:2] d[47:32],dqm[5:4] d[63:48],dqm[7:6] dimm stpc
board layout issue 0.1 - october 17, 2000 51/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.4 address & control signals this group encompasses the memory address ma[10:0], bank address ba[0], ras, cas and write enable we signals. the load of the dimm module on these signals is the most important one and depends upon the type of sdram compo- nents used (x4, x8 or x16) and whether the dimm module is single or dual row. the capacitive load- ing of the sdram inputs alone for an x8 single row dimm will be about 30-40pf. an equivalent circuit for the timing simulation is shown infigure 6-14 most of the delays are due to the pcb traces and loading rather than the pad itself. figure 6-14. address/control equivalent circuit dimm2 dimm1 rterm 100mm (0.7ns) 10mm z pcb
board layout 52/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.5 chip select signals (cs#[3:0]) there are 4 chip select pins per dimm. chip se- lects 0 and 2 are always used to select the first row of sdrams and chip selects 1 and 3 select the second row on dual bank sdrams. the chip select outputs only have to drive one dimm each figure 6-15. cs# equivalent circuit 130mm (0.9ns) dimm cs[0] cs[2]
board layout issue 0.1 - october 17, 2000 53/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.6 data write (md[63:0]) the load on the data signals is much lower than the address/control signals for an unbuffered dimm. for a registered dimm the data signals are the only memory pins of the dimm which are not registered. for the design to get maximum benefit from using registered dimms the timings should be compared to the timings for registered dimms for the other pins. 6.3.7 data read (md[63:0]) the data read simulation circuit is shown below.. figure 6-16. data read equivalent circuit 125mm (0.9ns) dimm2 10mm 10 ohms sdram dq dimm1
board layout 54/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 6.3.8 data mask (dqm[7:0]) the data mask load is quite similar to that of the data signals. 6.3.9 summary for unbuffered dimms the address/control signals will be the most critical for timing. the simulations show that for these signals the best way to drive them is to use a parallel termination. for applica- tions where speed is not so critical series termina- tion can be used as this will save power. using a low impedance such as 50 w for these critical trac- es is recommended as it both reduces the delay and the overshoot. the other memory interface signals will typically be not as critical as the address/control signals for unbuffered dimms. when using registered dimms the other signals will probably be just as critical as the address/control signals so to gain maximum benefit from using registered dimms the timings should also be considered in that situation. using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control signals they could use the de- fault value. using a lower impedance implies us- ing wider traces which may have an impact on the routing of the board. 6.4 sdram layout examples the stpc provides ma, ras#, cas#, we#, cs#, dqm#, ba0 (ma[11])and md for sdram control. from 2 to 128 mbytes of main memory are sup- ported in 1 to 4 banks. all banks must be 64 bits wide. the following memory devices are supported: 4mbit x 4, 8mbit x 2 & 16mbit x 1 or if in the case of two internal bank chips, 2mbit x 4 x 2, 4mbit x 2 x 2 & 8mbit x 1 x 2 . the following figure 6-17 and figure 6-18, shows two possible sdram organizations based on one or two bank configurations. notes for figure 6-17 and figure 6-18; all buffers must be low skew clock buffers one clock driver can operate upto four memory chips. all the clock lines must follow the rules below; mclki = mclk0 + mclk0a = ...... = mclk0 + mclk0d = mclk1 + mclk1a = ...... = mclk1 + mclk1d this means that all line lengths must go from the buffer to the memory chips (mclk1 or mclk0 or ...) and from the buffer to the stpc (mclki) must be identical. 6.4.1 host address to ma bus mapping graphics memory resides at the beginning of bank 0. host memory begins at the top of graphics memory and extends to the top of populated sdram. the bank attributes can be retrieved from a lookup table to select the final sdram row and column address mappings. (table 6-2). also table 6-1 shows the standard dimm pinout for the users that wish to design with dimms. .
board layout issue 0.1 - october 17, 2000 55/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 6-17. one memory bank with eight chips (8-bit) one memory bank with eight devices (8-bit) cas# cs0# ba0 (ma[11]) ma[10:0] we# (each signal needs ras# dqm# md[63:0] mclki mclko mclk0b mclk0c 16 mbit 16-bit wide 16 mbit 16-bit wide it's own line) 16 mbit 16-bit wide 16 mbit 16-bit wide dqm [3:2] dqm [5:4] dqm [1:0] reference knot mclk0a mclk0d [63:48] md [47:32] md [31:16] md [15:0] md dqm [7:6]
board layout 56/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. figure 6-18. two memory banks with eight chips on each (8-bit) two memory bank with eight devices (8-bit) cas#, ras# cs1#,3#, we# ma[10:0] (each signal needs it's own line) cas#, ras# cs0#,2#, we# ma[10:0] (each signal needs it's own line) ba0 (ma[11]) mclki mcklo mclk0/1 mclk2/3 dqm [7] dqm# md[63:0] 16 mbit 8-bit wide mclk0b mclk1a 16 mbit 8-bit wide 16 mbit 8-bit wide 16 mbit 8-bit wide mclk2a 16 mbit 8-bit wide 16 mbit 8-bit wide 16 mbit 8-bit wide 16 mbit 8-bit wide dqm [1] dqm [2] dqm [3] dqm [4] dqm [5] dqm [0] [63:56] mclk0a mclk1b mclk2b mclk3b mclk3a md [55:48] md [47:40] md [39:32] md [31:24] md [15:8] md [7:0] md dqm [6] clock buffer compulsary [23:16] md mclki mcklo mclk4/5 mclk6/7 clock buffer compulsary ba0 (ma[11]) dqm [7] dqm# md[63:0] 16 mbit 8-bit wide mclk4b mclk5a 16 mbit 8-bit wide 16 mbit 8-bit wide 16 mbit 8-bit wide mclk6a 16 mbit 8-bit wide 16 mbit 8-bit wide 16 mbit 8-bit wide 16 mbit 8-bit wide dqm [1] dqm [2] dqm [3] dqm [4] dqm [5] dqm [0] [63:56] mclk4a mclk5b mclk6b mclk7b mclk7a md [55:48] md [47:40] md [39:32] md [31:24] md [15:8] md [7:0] md dqm [6] [23:16] md
board layout issue 0.1 - october 17, 2000 57/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. table 6-1. standard memory dimm pinout memory banks pin number 16mbit(2 banks) ... ma[10:0] 123 - 126 - 39 - 122 ba0(ma11) table 6-2. address mapping address mapping: 16 mbit - 2 banks stpc i/f ba0(ma11) ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a22 a21 a2 a19 a18 a17 a16 a15 a14 a13 a12 cas address a11 0 a24 a23 a10 a9 a8 a7 a6 a5 a4 a3
board layout 58/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.
ordering data issue 0.1 - october 17, 2000 59/61 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 7 ordering data 7.1 ordering codes st pc e1 e c b c stmicroelectronics prefix product family pc: pc compatible product id e1: elite core speed e: 100mhz h: 133mhz memory interface speed c: 80mhz d: 90mhz package b: 388 overmoulded bga temperature range c: commercial case temperature (tcase) = 0 c to +100 c i: industrial case temperature (tcase) = -40 c to +115 c
ordering data 60/61 issue 0.1 - october 17, 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. 7.2 available part numbers 7.3 customer service more informations are available on stmicroelec- tronics internet site http://www.st.com/stpc . part number core frequency (mhz) cpu mode ( x1 / x2 ) memory interface speed (mhz) tcase range ( c) STPCE1DDBC 90 x1 90 0 cto+100 stpce1edbc 100 x1 90 stpce1hdc 133 x2 90 stpce1ddbi 90 x1 90 -40 c to +115 stpce1edbi 100 x1 90 stpce1hdbi 133 x2 90
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - swit zerland - taiwan - thailand - united kingdom - u.s.a. 61 issue 0.1 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice.

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