CTLDM8120-M832D surface mount dual, p-channel enhancement-mode silicon mosfets description: the central semiconductor CTLDM8120-M832D is an enhancement-mode dual p-channel field effect transistor, manufactured by the p-channel dmos process, designed for high speed pulsed amplifier and driver applications. this mosfet offers low r ds(on) and low threshold voltage. marking code: cfv features: ? esd protection up to 2kv ? low r ds(on) (0.24 max @ v gs =1.8v) ? high current (i d =0.95a) ? logic level compatibility applications: ? switching circuits ? dc - dc converters ? battery powered portable devices maximum ratings: (t a =25c) symbol units drain-source voltage v ds 20 v gate-source voltage v gs 8.0 v continuous drain current (steady state) i d 0.86 a continuous drain current, t<5.0s i d 0.95 a continuous source current (body diode) i s 0.36 a maximum pulsed drain current, tp=10s i dm 4.0 a maximum pulsed source current, tp=10s i sm 4.0 a power dissipation (note 1) p d 1.65 w operating and storage junction temperature t j, t stg -65 to +150 c thermal resistance (note 1) ja 76 c/w electrical characteristics per transistor: (t a =25c unless otherwise noted) symbol test conditions min typ max units i gssf , i gssr v gs =8.0v, v ds =0 1.0 50 na i dss v ds =20v, v gs =0 5.0 500 na bv dss v gs =0, i d =250a 20 24 v v gs(th) v ds =v gs, i d =250a 0.45 0.76 1.0 v v sd v gs =0, i s =360ma 0.9 v r ds(on) v gs =4.5v, i d =0.95a 0.085 0.150 r ds(on) v gs =4.5v, i d =0.77a 0.085 0.142 r ds(on) v gs =2.5v, i d =0.67a 0.130 0.200 r ds(on) v gs =1.8v, i d =0.2a 0.190 0.240 q g(tot) v ds =10v, v gs =4.5v, i d =1.0a 3.56 nc q gs v ds =10v, v gs =4.5v, i d =1.0a 0.36 nc q gd v ds =10v, v gs =4.5v, i d =1.0a 1.52 nc g fs v ds =10v, i d =810ma 2.0 s c rss v ds =16v, v gs =0, f=1.0mhz 80 pf c iss v ds =16v, v gs =0, f=1.0mhz 200 pf c oss v ds =16v, v gs =0, f=1.0mhz 60 pf t on v dd =10v, v gs =4.5v, i d =0.95a, r g =6.0 20 ns t off v dd =10v, v gs =4.5v, i d =0.95a, r g =6.0 25 ns notes: (1) fr-4 epoxy pcb with copper mounting pad area of 54mm 2 tlm832d case r2 (2-august 2011) www.centralsemi.com ? device is halogen free by design
CTLDM8120-M832D surface mount dual, p-channel enhancement-mode silicon mosfets tlm832d case - mechanical outline lead code: 1) gate q1 2) source q1 3) gate q2 4) source q2 5) drain q2 6) drain q2 7) drain q1 8) drain q1 marking code: cfv pin configuration www.centralsemi.com r2 (2-august 2011)
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