View TC55W800FT_3344657.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC55W800FT-55,-70 2001-10-03 1/13 toshiba mos digital integrated circuit silicon gate cmos 524,288-word by 16-bit/1,048,576-word by 8-bit full cmos static ram description the TC55W800FT is a 8,388,608-bit static random access memory (sram) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. fabricated using toshiba's cmos silicon gate process technology, this device operates from a single 2.3 to 3.3 v power supply. advanced circuit technology provides both high speed and low power at an operating current of 3 ma/mhz and a minimum cycle time of 55 ns. it is automatically placed in low-power mode at 0.5 a standby current (at v dd 3 v, ta 25c, maximum) when chip enable ( ce1 ) is asserted high or (ce2) is asserted low. there are three control inputs. ce1 and ce2 are used to select the device and for data retention control, and output enable ( oe ) provides fast memory access. data byte control pin ( lb , ub ) provides lower and upper byte access. this device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. and, with a guaranteed operating extreme temperature range of 40 to 85c, the TC55W800FT can be used in environments exhibiting extreme temperature conditions. the TC55W800FT is available in a plastic 48-pin thin-small-outline package (tsop). features low-power dissipation operating: 9.9 mw/mhz (typical) single power supply voltage of 2.3 to 3.3 v power down features using ce1 and ce2 data retention supply voltage of 1.5 to 3.3 v direct ttl compatibility for all inputs and outputs wide operating temperature range of 40 to 85c standby current (maximum): 3.3 v 10 a 3.0 v 5 a pin assignment (top view) pin names 48 pin tsop a0~a18 address inputs (word mode) a-1~a18 address inputs (byte mode) 1 ce , ce2 chip enable r/w read/write control oe output enable lb , ub data byte control i/o1~i/o16 data inputs/outputs byte byte ( 8 mode) enable v dd power gnd ground nc no connection pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin name a15 a14 a13 a12 a11 a10 a9 a8 nc nc r/w ce2 nc ub lb a18 pin no. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pin name a17 a7 a6 a5 a4 a3 a2 a1 a0 1 ce gnd oe i/o1 i/o9 i/o2 i/o10 pin no. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pin name i/o3 i/o11 i/o4 i/o12 v dd i/o5 i/o13 i/o6 i/o14 i/o7 i/o15 i/o8 i/o16 / a -1 gnd byte a16 access times (maximum): TC55W800FT -55 -70 access time 55 ns 70 ns 1 ce access time 55 ns 70 ns ce2 access time 55 ns 70 ns oe access time 30 ns 35 ns package: tsop 48-p-1220-0.50 (weight: 0.52 g typ) (normal) 25 48 24 1
TC55W800FT-55,-70 2001-10-03 2/13 block diagram a4 a5 a6 a7 a12 a14 a13 a15 a17 ce v dd gnd a3 i/o1 ce ce oe ub lb 1 ce a-1 a0 a1 a2 a8 a9 ce2 memory cell array 2,048 256 16 (8,388,608) sense amp column address register column address decoder a10 a18 control circuit byte a11 a16 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 r/w clock generator data input buffer data input buffer data output buffer data output buffer row address decoder row address buffer row address register column address buffer
TC55W800FT-55,-70 2001-10-03 3/13 operating mode mode 1 ce ce2 oe r/w byte lb ub i/o1~i/o8 i/o9~i/o15 i/o16 power l h l h l * * output high-z a-1 i ddo l h l h h l l output output output i ddo l h l h h h l high-z output output i ddo read l h l h h l h output high-z high-z i ddo l h * l l * * input high-z a-1 i ddo l h * l h l l input input input i ddo l h * l h h l high-z input input i ddo write l h * l h l h input high-z high-z i ddo l h h h l * * high-z high-z a-1 i ddo l h h h h * * high-z high-z high-z i ddo output deselect l h l h h h h high-z high-z high-z i ddo h * * * h or l * * high-z high-z high-z i dds standby * l * * h or l * * high-z high-z high-z i dds * = don't care h = logic high l = logic low maximum ratings symbol rating value unit v dd power supply voltage 0.3~4.2 v v in input voltage 0.3 * ~4.2 v v i/o input/output voltage 0.5~v dd 0.5 v p d power dissipation 0.6 w t solder soldering temperature (10s) 260 c t stg storage temperature 55~150 c t opr operating temperature 40~85 c * : 2.0 v when measured at a pulse width of 20ns dc recommended operating conditions ( ta 40 to 85c ) symbol parameter min typ max unit v dd power supply voltage 2.3 3.3 v v dd 2.3 v~3.3 v 2.0 v ih input high voltage v dd 2.7 v~3.3 v 2.2 v dd 0.3 v v il input low voltage 0.3 * v dd 0.22 v v dh data retention supply voltage 1.5 3.3 v * : 2.0 v when measured at a pulse width of 20ns
TC55W800FT-55,-70 2001-10-03 4/13 dc characteristics (ta 40 to 85c, v dd 2.3 to 3.3 v) symbol parameter test condition min typ max unit i il input leakage current v in 0 v~v dd 1.0 a i oh output high current v oh v dd 0.5 v 0.5 ma i ol output low current v ol 0.4 v 2.1 ma i lo output leakage current 1 ce v ih or ce2 v il or r/w v il or oe v ih , v out 0 v~v dd 1.0 a 55 ns 60 70 ns 50 l ddo1 1 ce v il and ce2 v ih and r/w v ih , i out 0 ma, other input v ih /v il , byte v dd or 0 v t cycle 1 s 10 ma 55 ns 55 70 ns 45 l ddo2 operating current 1 ce 0.2 v and ce2 v dd 0.2 v and r/w v dd 0.2 v, i out 0 ma, other input v dd 0.2 v/0.2 v, byte v dd or 0 v t cycle 1 s 5 ma i dds1 1 ce v ih or ce2 v il , byte v dd or 0 v 2 ma ta 25c 1 v dd 3.0 v 10% ta 40~85c 10 ta 25c 0.05 0.5 ta 40~40c 1 i dds2 (note) standby current 1 ce v dd 0.2 v or ce2 0.2 v, v dd 1.5 v~3.3 v, byte v dd or 0 v v dd 3.0 v ta 40~85c 5 a note: in standby mode with 1 ce v dd 0.2 v, these limits are assured for the condition ce2 v dd 0.2 v or ce2
0.2 v. capacitance (ta 25c, f 1 mhz) symbol parameter test condition max unit c in input capacitance v in gnd 10 pf c out output capacitance v out gnd 10 pf note: this parameter is periodically sampled and is not 100% tested.
TC55W800FT-55,-70 2001-10-03 5/13 ac characteristics and operating conditions (ta 40 to 85c, v dd 2.7 to 3.3 v) read cycle TC55W800FT -55 -70 symbol parameter min max min max unit t rc read cycle time 55 70 t acc address access time 55 70 t co1 chip enable( 1 ce ) access time 55 70 t co2 chip enable(ce2) access time 55 70 t oe output enable access time 30 35 t ba data byte control access time 30 35 t coe chip enable low to output active 5 5 t oee output enable low to output active 0 0 t be data byte control low to output active 0 0 t od chip enable high to output high-z 25 30 t odo output enable high to output high-z 25 30 t bd data byte control high to output high-z 25 30 t oh output data hold time 10 10 ns write cycle TC55W800FT -55 -70 symbol parameter min max min max unit t wc write cycle time 55 70 t wp write pulse width 45 50 t cw chip enable to end of write 50 60 t bw data byte control to end of write 45 50 t as address setup time 0 0 t wr write recovery time 0 0 t odw r/w low to output high-z 25 30 t oew r/w high to output active 0 0 t ds data setup time 25 30 t dh data hold time 0 0 ns ac test conditions parameter test condition output load 30 pf 1 ttl gate input pulse level 0.4 v, 2.4 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns
TC55W800FT-55,-70 2001-10-03 6/13 ac characteristics and operating conditions (ta 40 to 85c, v dd 2.3 to 3.3 v) read cycle TC55W800FT -55 -70 symbol parameter min max min max unit t rc read cycle time 70 85 t acc address access time 70 85 t co1 chip enable( 1 ce ) access time 70 85 t co2 chip enable(ce2) access time 70 85 t oe output enable access time 35 45 t ba data byte control access time 35 45 t coe chip enable low to output active 5 5 t oee output enable low to output active 0 0 t be data byte control low to output active 0 0 t od chip enable high to output high-z 30 35 t odo output enable high to output high-z 30 35 t bd data byte control high to output high-z 30 35 t oh output data hold time 10 10 ns write cycle TC55W800FT -55 -70 symbol parameter min max min max unit t wc write cycle time 70 85 t wp write pulse width 50 55 t cw chip enable to end of write 60 70 t bw data byte control to end of write 50 55 t as address setup time 0 0 t wr write recovery time 0 0 t odw r/w low to output high-z 30 35 t oew r/w high to output active 0 0 t ds data setup time 30 35 t dh data hold time 0 0 ns ac test conditions parameter test condition output load 30 pf 1 ttl gate input pulse level v dd 0.2 v, 0.2 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns
TC55W800FT-55,-70 2001-10-03 7/13 function symbol parameter min max unit t bs byte setup time 5 ms t br byte recovery time 5 ms timing diagrams byte byte ce2 t bs 1 ce t br byte
TC55W800FT-55,-70 2001-10-03 8/13 read cycle (see note 1) write cycle 1 (r/w controlled) (see note 4) ce2 t rc t acc t od valid data out t oe t be t bd hi-z hi-z t co1 1 ce oe t ba t coe t oh t odo t oee t co2 ub , lb indeterminate address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) r/w ce2 t as t cw t wr valid data in t odw t wp t ds t dh t oew hi-z t cw 1 ce t wc t bw ub , lb (see note 3) (see note 2) (see note 5) (see note 5) address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) d in i/o1~16 (word mode) i/o1~8 (byte mode)
TC55W800FT-55,-70 2001-10-03 9/13 write cycle 2 ( controlled) (see note 4) write cycle 3 (ce2 controlled) (see note 4) ce1 r/w t wc t as t wr t wp 1 ce t cw valid data in t ds t dh t be hi-z hi-z ce2 t cw t odw t bw t coe ub , lb (see note 5) address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) d in i/o1~16 (word mode) i/o1~8 (byte mode) r/w t wc t as t wr t wp 1 ce t cw valid data in t ds t dh hi-z hi-z t cw ce2 t bw t be t coe t odw ub , lb (see note 5) address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) d in i/o1~16 (word mode) i/o1~8 (byte mode)
TC55W800FT-55,-70 2001-10-03 10/13 write cycle 4 ( , controlled) (see note 4) note: (1) r/w remains high for the read cycle. (2) if ce1 goes low(or ce2 goes high) coincident with or after r/w goes low, the outputs will remain at high impedance. (3) if ce1 goes high(or ce2 goes low) coincident with or before r/w goes high, the outputs will remain at high impedance. (4) if oe is high during the write cycle, the outputs will remain at high impedance. (5) because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. ub lb r/w t wc t as t wr t wp 1 ce valid data in t ds t dh hi-z hi-z t cw ce2 t bw t be t coe t odw ub , lb t cw (see note 5) address a0~a18 (word mode) d out i/o1~16 (word mode) d in i/o1~16 (word mode)
TC55W800FT-55,-70 2001-10-03 11/13 data retention characteristics ( ta 40 to 85c ) symbol parameter min typ max unit v dh data retention supply voltage 1.5 3.3 v v dh 3.3 v ta 40~85c 10 ta 40~40c 1 i dds2 standby current v dh 3.0 v ta 40~85c 5 a t cdr chip deselect to data retention mode time 0 ns t r recovery time t rc (see note) ns note: read cycle time controlled data retention mode (see note 1) ce2 controlled data retention mode (see note 3) note: (1) in ce1 controlled data retention mode, minimum standby current mode is entered when ce2 0.2 v or ce2 v dd 0.2 v. (2) when ce1 is operating at the v ih level, the operating current is given by i dds1 during the transition of v dd from 2.3 to 2.2v. (3) in ce2 controlled data retention mode, minimum standby current mode is entered when ce2 0.2 v. ce1 v dd 2.3 v gnd v ih data retention mode t r (see note 2) (see note 2) t cdr v dd 0.2 v 1 ce v dd v dd v dd 2.3 v gnd v il data retention mode t r t cdr 0.2 v v ih ce2 v dd
TC55W800FT-55,-70 2001-10-03 12/13 package dimensions weight: 0.52 g (typ)
TC55W800FT-55,-70 2001-10-03 13/13 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

▲Up To Search▲

Price & Availability of TC55W800FT

	To Download TC55W800FT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .