 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 7 p m u b h f % f u f d u p s t % f m b z $ j s d v j u # v j m u * o 4 f s j f t 157 2 the xc61f series are highly accurate, low power consumption voltage detectors, manufactured using cmos and laser trimming technologies. a delay circuit is built-in to each detector. detect voltage is extremely accurate with minimal temperature drift. both cmos and n-channel open drain output configurations are available. since the delay circuit is built-in, peripherals are unecessary and high density mounting is possible. ( f o f s b m % f t d s j q u j p o highly accurate : detect voltage 2% low power consumption : typ 1.0 a [ v in =2.0v ] detect voltage range : 1.6v ~ 6.0v in 0.1v increments operating voltage range : 0.7v ~ 10.0v detect voltage temperature characteristics : typ 100ppm/? built-in delay circuit : 1ms ~ 50ms, 50ms ~ 200ms, 80ms ~ 400ms output configuration : n-channel open drain or cmos ultra small packages : sot-23 (150mw) mini-mold : sot-89 (500mw) mini-power mold : to-92 (300mw) * no parts are available with an accuracy of 1% microprocessor reset circuitry memory battery back-up circuits power-on reset circuits power failure detection system battery life and charge voltage monitors delay circuitry ' f b u v s f t " q q m j d b u j p o t cmos mini mold package highly accurate : 2% built-in delay circuit (1ms ~ 50ms) (50ms ~ 200ms) (80ms ~ 400ms) low power consumption : 1.0 a (v in = 2.0v) 5 z q j d b m " q q m j d b u j p o $ j s d v j u t $ . 0 4 p v u q v u / d i b o o f m p q f o e s b j o p v u q v u 3 l ? 7 * / 7 0 6 5 7 4 4 7 * / 7 0 6 5 7 4 4 7 * / 7 * / - 5 % - : n t f d " n c j f o u 5 f n q 5 b ? 5 z q j d b m 1 f s g p s n b o d f $ i b s b d u f s j t u j d " . # * & / 5 5 & . 1 & 3 " 5 6 3 & w t 5 3 " / 4 * & / 5 % & - " : 5 * . & 4 @ 9 $ ' ?? 9 $ ' 4 f j s f t 158 2 1 j o $ p o g j h v s b u j p o 1 j o " t t j h o n f o u 4 0 5 5 0 1 7 * & 8 4 0 5 5 0 1 7 * & 8 7 0 6 5 7 * / 7 4 4 7 4 4 7 0 6 5 7 * / pin sot-23 sot-89 name 32 v in supply voltage input 23 v ss ground 11 2 3 1v out output function to-92 (t) 1 2 3 to-92 (l) pin number 5 0 5 5 z q f 5 0 1 7 * & 8 7 0 6 5 y 7 * / y 7 4 4 5 0 - 5 z q f 5 0 1 7 * & 8 7 * / 7 4 4 7 0 6 5 4 @ 9 $ ' ?? 9 $ ' 4 f s j f t 159 2 1 s p e v d u $ m b t t j g j d b u j p o ordering information xc61f x x x x x x x yyyyyaaaaaaa y b c c d e f g output configuration : package type : c = cmos m = sot-23 n = n-ch open drain p = sot-89 t = to-92 (regular) l = to-92 (custom pin configuration) detect voltage (v df ) : 25 = 2.5v 38 = 3.8v output delay : device orientation : 1 = 50ms to 200ms r = embossed tape ( right ) 4 = 80ms to 400ms l = embossed tape ( left ) h: paper tape (to-92) b: bag (to-92) 5 = 1ms to 50ms detect accuracy : 2 = within 2.0% e f description designator description designator a b c d 1 b d l b h j o h * o g p s n b u j p o sot-23 ? ? ? ? n j o ? 4 @ 9 $ ' ?? 9 $ ' 4 f j s f t 160 2 to-92 ? n j o ? ? ? sot-89 ? ? n j o n b y ? ? ? ? ? ? 4 @ 9 $ ' ?? 9 $ ' 4 f s j f t 161 2 . b s l j o h sot-23, sot-89 4 0 5 5 0 1 7 * & 8 4 0 5 5 0 1 7 * & 8 q w er q w e r q represents the integer of the detect voltage and the output configuration cmos output (xc61fc series) n-channel open drain (xc61fn series) voltage (v) cmos n-ch cmos n-ch cmos n-ch cmos n-ch cmos n-ch cmos n-ch cmos n-ch w represents the decimal number of the detect voltage e indicates the presence of delay time r represents the assembly lot no. based on internal standards 6 80 to 400ms 7 1 to 50ms h designator configuration a b voltage (v) k l s mc d e f 0. w 1. w 0. w 1. w configuration designator 2. w 2. w 3. w 4. w n p 3. w 4. w 5. w 6. w 5. w 6. w r designator 0 1 q .4 3 4 2 q .0 q .1 q .2 designator 5 6 7 8 9 voltage (v) q .7 q .3 q .8 q .9 voltage (v) q .5 q .6 designator 50 to 200ms5 delay time to-92 2 3 4 5 6 7 1 5 0 - 5 z q f 5 0 1 7 * & 8 $ - 2 3 4 5 6 7 1 5 0 5 5 z q f 5 0 1 7 * & 8 $ q 3 f q s f t f o u t u i f p v u q v u d p o g j h v s b u j p o % & 4 * ( / " 5 0 3 0 6 5 1 6 5 $ 0 / ' * ( 6 3 " 5 * 0 / $ $ . 0 4 / / d i w 3 f w % r * o e j d b u f t % f m b z 5 j n f % & 4 * ( / " 5 0 3 % & - " : 5 * . & n t? n t n t? n t n t? n t % & 4 * ( / " 5 0 3 % & 5 & $ 5 7 0 - 5 " ( & " $ $ 6 3 " $ : x j u i j o 2% t 3 f q s f t f o u t u i f % f u f d u 7 p m u b h f " d d v s b d z w 3 f q s f t f o u t u i f % f u f d u 7 p m u b h f w e % & 4 * ( / " 5 0 3 7 0 - 5 " ( & 7 y 3 f q s f t f o u t b m f b t u t j h o j g j d b o u e j h j u p g u i f q s p e v d f e z f b sy % & 4 * ( / " 5 0 3 1 3 0 % 6 $ & % : & " 3 u % f o p u f t u i f q s p e v d u j p o m p u o v n c f s u p " u p ; s f q f b u f e ( * + 0 2 8 f y d f q u f e 4 @ 9 $ ' ?? 9 $ ' 4 f j s f t 162 2 # m p d l % j b h s b n & m f d u s j d b m $ i b s b d u f s j t u j d t 7 s f g % f m b z $ j s d v j u 7 s f g % f m b z $ j s d v j u $ . 0 4 p v u q v u / d i b o o f m p q f o e s b j o p v u q v u 7 0 6 5 7 * / 7 4 4 7 0 6 5 7 * / 7 4 4 ? 07 g 5 b ? symbol ratings units v in 12 v i out 50 ma v out v ss -0.3 ? v in +0.3 v ss -0.3 ? 9 v continuous total sot-23 pd 150 mw power dissipation sot-89 500 topr -30 ? +80 o c tstg -40 ? +125 o c output voltage parameter output current input voltage storage temperature operating ambient temperature cmos n-ch open drain to-92 300 " c t p m v u f . b y j n v n 3 b u j o h t 5 b1 ? 7 % ' 5 f t u b c m j t i f e e f u f d u w p m u b h f w b m v f 3 f m f b t f 7 p m u b h f 7 % 3 7 % ' 7 ) : 4 / p u f 5 i f q p x f s d p o t v n q u j p o e v s j o h q p x f s t u b s u u p p v u q v u c f j o h t u b c m f s f m f b t f p q f s b u j p o j t " h s f b u f s u i b o j u j t b g u f s u i b u q f s j p e d p n q m f u j p o p g s f m f b t f p q f s b u j p o c f d b v t f p g e f m b z d j s d v j u u i s p v h i d v s s f o u 5 s b o t j f o u % f m b z 5 j n f n t u p n t n t u p n t w f s t j p o t b s f b m t p b w b j m b c m f parameter symbol conditions min typ max units circuit detect voltage v df v df (t) v df (t) v df (t) v x 0.98 x 1.02 hysteresis range v hys v df v df v df v x 0.02 x 0.05 x 0.08 v in =1.5v 0.9 2.6 =2.0v 1.0 3.0 supply current i ss =3.0v 1.3 3.4 a 2 1 1 =4.0v 1.6 3.8 =5.0v 2.0 4.2 operating voltage v in v df =1.6v to 6.0v 0.7 10.0 v 1 n-ch v ds =0.5v v in =1.0v 2.2 =2.0v 7.7 3 =3.0v 10.1 output current i out =4.0v 11.5 ma =5.0v 13.0 p-ch v ds =2.1v v in =8.0v -10.0 4 ( cmos output ) detect voltage ? v df 100 ppm/ c - temperature characteristics ? topr ? v df transient delay time tdly * v in changes from 50 200 ms 5 (v dr v out inversion) 0.6v to 10v 4 @ 9 $ ' ?? 9 $ ' 4 f s j f t 163 2 ' v o d u j p o b m % f t d s j q u j p o functional description ( cmos output ) ew q r t y y ????????? q when a voltage higher than the release voltage (v dr ) is applied to the voltage input pin (v in ), the voltage will gradually fall. when a voltage higher than the detect voltage (v df ) is applied to v in , output (v out ) will be equal to the input at v in . note that high impedeance exists at v out with the n-channel open drain configuration. if the pin is pulled up, v out will be equal to the pull up voltage. w when v in falls below v df , v out will be equal to the ground voltage (v ss ) level (detect state). note that this also applies to n-channel open drain configurations. e when v in falls to a level below that of the minimum operating voltage (v min ) output will become unstable. because the output pin is generally pulled up with n-channel open drain configurations, output will be equal to pull up voltage. r when v in rises above the v ss level (excepting levels lower than minimum operating voltage), v out will be equal to v ss until v in reaches the v dr level. t although v in will rise to a level higher than v dr , v out maintains ground voltage level via the delay circuit. y following transient delay time, v in will be output at v out . note that high impedeance exists with the n-channel open drain configuration and that voltage will be dependent on pull up. notes : 1. the difference between v dr and v df represents the hysteresis range. 2. propagation delay time (tdly) represents the time it takes for v in to appear at v out once the said voltage has exceeded the v dr level. input voltage (v in ) minimum operating voltage ( v min ) detect release voltage (v dr ) detect voltage (v df ) output voltage (v out ) ground voltage (v ss ) ground voltage (v ss ) propagation delay time (t dly) timing chart 4 @ 9 $ ' ?? 9 $ ' 4 f j s f t 164 2 % j s f d u j p o t g p s v t f notes on use 7 * / 7 0 6 5 7 4 4 3 * / 9 $ ' / 4 f s j f t $ * / 7 * / 7 0 6 5 7 4 4 3 * / 9 $ ' $ 4 f s j f t $ * / ?? 1. oscillation (1) oscillation as a result of output current with the cmos output configuration : (2) oscillation as a result of through current : % j b h s b n 8 i f o v t j o h b o j o q v u s f t j t u p s 1. please use this ic within the stated maximum ratings. the ic is liable to malfunction should the ratings be exceeded. 2. when a resistor is connected between the v in pin and the input with cmos output configurations, oscillation may occur as a result of voltage drops at r in if load current (i out ) exists. it is therefore recommend that no resistor be added. ( refer to n.b. 1 - (1) below ) 3. when a resistor is connected between the v in pin and the input with cmos output configurations, irrespective of n-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (i out ) does not exist. ( refer to n.b. 1 - (2) below ) 4. with a resistor connected between the v in pin and the input, detect and release voltage will rise as a result of the ic's supply current flowing through the v in pin. 5. if a resistor (r in ) must be used, then please use with as small a level of input impedance as possible in order to control the occurences of oscillation as described above. further, please ensure that r in is less than 10k ? b o e u i b u $ * / j t n p s f u i b o ' % j b h s b n * o t v d i d b t f t e f u f d u b o e s f m f b t f w p m u b h f t x j m m s j t f e v f u p w p m u b h f e s p q t b u 3 in c s p v h i u b c p v u c z u i f * $ t t v q q m z d v s s f o u % f q f o e j o h p o d j s d v j u t p q f s b u j p o u s b o t j f o u e f m b z u j n f p g u i j t * $ d b o c f x j e f m z d i b o h f e e v f u p v q q f s m j n j u t p s m p x f s m j n j u t p g p q f s b u j p o b m b n c j f o u u f n q b s b u v s f when the voltage applied at in rises, release operations commence and the detector's output voltage increases. load current (i out ) will flow through r l . because a voltage drop ( r in x i out ) is produced at the r in resistor, located between the input (in) and the v in pin, the load current will flow via the ic's v in pin. the voltage drop will also lead to a fall in the voltage level at the v in pin. when the v in pin voltage level falls below the detect voltage level, detect operations will commence. following detect operations, load current flow will cease and since voltage drop at r in will disappear, the voltage level at the v in pin will rise and release operations will begin over again. oscillation may occur with this " release - detect - release " repetition. further, this condition will also appear via means of a similar mechanism during detect operations. since the xc61f series are cmos ic s , through current will flow when the ic's internal circuit switching operates ( during release and detect operations ). consequently, oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this through current ( diagram 3 ). since hysteresis exists during detect operations, oscillation is unlikely to occur. n.b. 4 @ 9 $ ' ?? 9 $ ' 4 f s j f t 165 2 7 p m u b h f e s p q 3 - * 0 6 5 7 * / 7 0 6 5 7 4 4 3 * / 3 * / 9 * 0 6 5 9 $ ' $ 4 f s j f t 7 p m u b h f e s p q 7 * / 7 0 6 5 7 4 4 3 * / 3 * / 9 * 0 6 5 9 $ ' / 4 f s j f t * 4 4 9 $ ' $ 4 f s j f t j o d m v e f t u i s p v h i d v s s f o u % j b h s b n 0 t d j m m b u j p o j o s f m b u j p o u p p v u q v u d v s s f o u % j b h s b n 0 t d j m m b u j p o j o s f m b u j p o u p u i s p v h i d v s s f o u 4 @ 9 $ ' ?? 9 $ ' 4 f j s f t 166 2 5 z q j d b m 1 f s g p s n b o d f $ i b s b d u f s j t u j d t 7 % 3 7 % ' 7 % 3 7 % ' ? ? 5 b ? - # - # - # ? 5 b ? ? - # ? 5 b ? ? - # 7 % 3 7 % ' ) b ? ? ? ) b ? ? ? 5 b ? ? ? - # - # - # - # 7 * / 7 0 6 5 l 7 * / 7 0 6 5 l 7 * / 7 0 6 5 l 7 5 b ? 7 * / 7 7 * / 7 7 5 b ? 7 * / 7 5 b ? 7 - # - # - # " n c j f o u 5 f n q 5 b ? (1) supply current vs. input voltage (2) detect voltage, release voltage vs. ambient temperature 4 v q q m z $ v s s f o u * 4 4 " * o q v u 7 p m u b h f 7 * / 7 % f u f d u 3 f m f b t f 7 p m u b h f 7 % ' 7 % 3 7 % f u f d u 3 f m f b t f 7 p m u b h f 7 % ' 7 % 3 7 4 v q q m z $ v s s f o u * 4 4 " * o q v u 7 p m u b h f 7 * / 7 4 v q q m z $ v s s f o u * 4 4 " * o q v u 7 p m u b h f 7 * / 7 " n c j f o u 5 f n q 5 b ? (3) output voltage vs. input voltage % f u f d u 3 f m f b t f 7 p m u b h f 7 % ' 7 % 3 7 0 v u q v u 7 p m u b h f 7 0 6 5 7 0 v u q v u 7 p m u b h f 7 0 6 5 7 0 v u q v u 7 p m u b h f 7 0 6 5 7 * o q v u 7 p m u b h f 7 * / 7 * o q v u 7 p m u b h f 7 * / 7 * o q v u 7 p m u b h f 7 * / 7 7 % 4 7 7 % 4 7 7 % 4 7 0 v u q v u $ v s s f o u * 0 6 5 n " 0 v u q v u $ v s s f o u * 0 6 5 " 0 v u q v u $ v s s f o u * 0 6 5 n " " n c j f o u 5 f n q 5 b ? (4) n-channel driver output current vs. v ds 4 @ 9 $ ' ?? 9 $ ' 4 f s j f t 167 2 7 * / 7 7 5 b ? 7 5 b ? 7 7 7 * / 7 7 * / 7 7 5 b ? - # - # - # 5 b ? ? ? ? ? 5 b ? 5 b ? ? ? - 7 5 b ? 7 7 7 5 b ? 7 7 - - # - # - # 7 % 4 7 7 % 4 7 7 % 4 7 - - - 7 % 4 7 7 % 4 7 7 % 4 7 7 % 4 7 7 % 4 7 0 v u q v u $ v s s f o u * 0 6 5 " 0 v u q v u $ v s s f o u * 0 6 5 n " 0 v u q v u $ v s s f o u * 0 6 5 " 0 v u q v u $ v s s f o u * 0 6 5 n " 0 v u q v u $ v s s f o u * 0 6 5 n " * o q v u 7 p m u b h f 7 * / 7 0 v u q v u $ v s s f o u * 0 6 5 n " * o q v u 7 p m u b h f 7 * / 7 * o q v u 7 p m u b h f 7 * / 7 0 v u q v u $ v s s f o u * 0 6 5 n " 0 v u q v u $ v s s f o u * 0 6 5 n " 5 % - : n t f d 5 % - : n t f d " n c j f o u 5 f n q 5 b ? " n c j f o u 5 f n q 5 b ? 5 % - : n t f d " n c j f o u 5 f n q 5 b ? (5) n-channel driver output current vs. input voltage (6) p-channel driver output current vs. input voltage (7) ambient temperature vs. transient delay time * o q v u 7 p m u b h f 7 * / 7 * o q v u 7 p m u b h f 7 * / 7 (4) n-channel driver output current vs. v ds 4 @ 9 $ ' ?? 9 $ ' 4 f j s f t 168 2 * o q v u 7 p m u b h f 7 * / 7 5 % - : n t f d - $ 5 b ? (8) input vs. transient delay time 4 @ 9 $ ' ?? |
Price & Availability of XC61FN2512LR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |