1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32512c july 2001 rev. 8 eco #14564 features ? 512kx32 bit cmos static ? random access memory ? access times: 15, 20, and 25ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o ? high density package ? 72 pin zip, no. 173 ? 72 lead simm, no. 174 (gold option) ? common data inputs and outputs ? single +5v (10%) supply operation the edi8f32512c is a high speed 16 megabit static ram module organized as 512k words by 32 bits. this module is constructed from four 512kx8 static rams in soj packages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. the edi8f32512c is offered in 72 pin zip and 72 lead simm packages, which enable 16 megabits of memory to be placed in less than 1.3 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. pins pd1- pd4, are used to identify module memory density in applications where alternate modules can be interchanged. pin configurations and block diagram pin names 512kx32 static ram cmos, high speed module a?-a18 address inputs e?-e3 chip enables w write enable g output enable dq?-dq31 common data input/output vcc power (+5v10%) vss ground nc no connection fig. 1 description 8g32512c pin config. pd0, pd1, pd3= open pd2= vss pd0, pd1, pd3= open pd2= vss 8g32512c blk dia.
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32512c july 2001 rev. 8 eco #14564 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics capacitance truth table (f=1.0mhz, vin=vcc or vss) ac test conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. (note: for tehqz,tghqz and twlqz, cl = 5pf) *typical: ta = 25c, vcc = 5.0v these parameters are sampled, not 100% tested. voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature, plastic -55c to +125c power dissipation 5.0 watts output current 20 ma parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf e w g mode output power h x x standby high z icc2/icc3 l h l read dout icc1 l l x write din icc1 output l h h deselect high z icc1 parameter sym max unit address lines ci 45 pf data lines cd/q 20 pf chip enable line cc 20 pf write line cn 45 pf parameter sym conditions min typ* max units operating power supply current icc1 w, e = vil, ii/o = 0ma, min cycle 800 ma standby (ttl) power supply current icc2 e 3 vih, vin vil or vin 3 vih 300 ma full standby power supply current icc3 e 3 vcc-0.2v 80 ma cmos vin 3 vcc-0.2v or vin 0.2v input leakage current ili vin = 0v to vcc -- -- 20 a output leakage current ilo v i/o = 0v to vcc -- -- 20 a output high voltage voh ioh = -4.0ma 2.4 -- -- v output low voltage vol iol = 8.0ma -- -- 0.4 v
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32512c july 2001 rev. 8 eco #14564 ac characteristics read cycle read cycle 2 - w high read cycle 1 - w high, g, e low notes: 1. parameter guaranteed, but not tested. fig. 3 fig. 2 symbol 15ns 20ns 25ns parameter jedec alt. min max min max min max units read cycle time t avav trc 15 20 25 ns address access time tavqv taa 15 20 25 ns chip enable access telqv tacs 15 20 25 ns chip enable to output in low z (1) telqx tclz 3 3 3 ns chip disable to output in high z (1) tehqz tchz 6 10 12 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 6 8 10 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 6 8 10 ns address 1 address 2 tavav data 1 data 2 tavqv tavqx 8f32512c rd cyc1 a q tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv 8f32512c rd cyc2
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32512c july 2001 rev. 8 eco #14564 notes: 1. parameter guaranteed, but not tested. ac characteristics write cycle write cycle 1 - w controlled fig. 4 symbol 15ns 20ns 25ns parameter jedec alt. min max min max min max units write cycle time t avav twc 15 20 25 ns chip enable to end of write telwh tcw 8 15 20 ns twleh tcw 8 15 20 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 8 15 15 ns taveh taw 8 15 15 ns write pulse width twlwh twp 10 15 15 ns teleh twp 10 15 15 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 6 0 8 0 12 ns data to write time tdvwh tdw 7 9 10 ns tdveh tdw 7 9 10 ns output active from end of write (1) twhqx twlz 3 3 3 ns e a tavav telwh tavwh twlwh tavwl twhax w high z data valid twlqz twhqx tdvwh twhdx q d 8f32512c write cyc1
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32512c july 2001 rev. 8 eco #14564 write cycle 2 - e controlled fig. 5 a tavel high z tavav 8f32512c write cyc2 teleh e taveh tehax w twleh tehdx tdveh q data valid d
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32512c july 2001 rev. 8 eco #14564 package description .032 .032 .022 .060 .018 3.865 max. 0.600 .100 typ. .050 typ. .100 typ. .273 max. max. max. ordering information note: to order gold simm option, change from "edi8f" to "edi8g". package no. 173: 72 pin zip package no. 174: 72 lead simm 4.255 max. 3.984 1.992 .125 dia. typ. (2 plcs.) .213 max. .125 min. .625 max. .400 .250 r.062 3.730 2.045 .050 typ. r.062 .250 p1 part number speed package (ns) no. edi8f32512c15mmc 15 174 edi8f32512c20mmc 20 174 edi8f32512c25mmc 25 174 not recommended for new designs part number speed package (ns) no. edi8f32512c15mzc 15 173 EDI8F32512C20MZC 20 173 edi8f32512c25mzc 25 173 all dimensions are in inches
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