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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) and xdcp are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners quad, 128 tap, low voltage digitally controlled potentiometer (xdcp?) isl23448 the isl23448 is a volatile, low vo ltage, low noise, low power, 128 tap, quad digitally controlled potentiometer (dcp) with an spi bus? interface. it integrates four dcp cores, wiper switches and control logic on a monolithic cmos integrated circuit. each digitally controlled potentiometer is implemented with a combination of resistor elements and cmos switches. the position of the wipers are cont rolled by the user through the spi bus interface. each potentiometer has an associated volatile wiper register (wri, i = 0, 1, 2, 3) that can be directly written to and read by the us er. the contents of the wri controls the position of the wiper. when powered on, the wiper of each dcp will always commence at mid-scale (64 tap position). the low voltage, low power consumption, and small package of the isl23448 make it an ideal choice for use in battery operated equipment. in addition, the isl23448 has a v logic pin allowing down to 1.2v bus operation, independent from the v cc value. this allows for low logic levels to be connected directly to the isl23448 with out passing through a voltage level shifter. the dcp can be used as a three- terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adju stments, and signal processing. applications ? power supply margining ? trimming sensor circuits ? gain adjustment in battery powered instruments ? rf power amplifier bias compensation features ? four potentiometers per package ?128 resistor taps ?10k ? , 50k ? or 100k ? total resistance ? spi serial interface - no additional level translator for low bus supply - daisy chaining of multiple dcps ?power supply -v cc = 1.7v to 5.5v analog power supply -v logic = 1.2v to 5.5v spi bus/logic power supply ? maximum supply current wi thout serial bus activity (standby) - 5a @ v cc and v logic = 5v - 2a @ v cc and v logic = 1.7v ?shutdown mode - forces the dcp into an end-to-end open circuit and rwi is connected to rli internally - reduces power consumption by disconnecting the dcp resistor from the circuit ? wiper resistance: 70 ? typical @ v cc = 3.3v ? power-on preset to mid-scale (64 tap position) ? extended industrial temperature range: -40 c to +125 c ? 20 ld tssop or 20 ld qfn packages ? pb-free (rohs compliant) figure 1. forward and back ward resistance vs tap position, 10k ? dcp figure 2. v ref adjustment 0 2000 4000 6000 8000 10000 0326496128 tap position (decimal) resistance ( ? ) v ref_m isl28114 1 dcp of isl23448 + - v ref rl1 rw1 rh1 august 19, 2011 fn7905.0
isl23448 2 fn7905.0 august 19, 2011 block diagram power up interface control and status logic i/o block v cc gnd sdi sdo sck v logic level shifter wr0 volatile register wr1 volatile register wr2 volatile register wr3 volatile register rh0 rw0 rl0 rh1 rw1 rl1 rh2 rw2 rl2 rh3 rw3 rl3 cs pin configurations isl23448 (20 ld tssop) top view isl23448 (20 ld qfn) top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 rl0 rw0 v cc rh0 rl1 rw1 gnd rh1 v logic sdi rl3 rh3 rl2 rw2 rw3 rh2 sck sdo gnd cs v logic rw1 sck rh2 sdi cs rl0 rw0 rl3 gnd rl2 rh0 rw2 rw3 v cc rl1 rh1 sdo 1 2 3 4 5 78910 15 14 13 12 11 20 19 18 17 6 gnd 6 rh3 16 pin descriptions tssop qfn symbol description 1 19 rl0 dcp0 ?low? terminal 2 20 rw0 dcp0 wiper terminal 31 v cc analog power supply. range 1.7v to 5.5v 42rh0dcp0 ?high? terminal 5 3 rl1 dcp1 ?low? terminal 6 4 rw1 dcp1 wiper terminal 75rh1dcp1 ?high? terminal 8, 12 6, 10 gnd ground pin 97v logic spi bus/logic supply range 1.2v to 5.5v 10 8 sdi logic pin - serial bus data input 11 9 cs logic pin - active low chip select 13 11 sdo logic pin - serial bus data output (configurable) 14 12 sck logic pin - serial bus clock input 15 13 rh2 dcp2 ?high? terminal 16 14 rw2 dcp2 wiper terminal 17 15 rl2 dcp2 ?low? terminal 18 16 rh3 dcp3 ?high? terminal 19 17 rw3 dcp3 wiper terminal 20 18 rl3 dcp3 ?low? terminal
isl23448 3 fn7905.0 august 19, 2011 ordering information part number (notes 1, 2, 3) part marking resistance option (k ? ) temp range (c) package (pb-free) pkg. dwg. # isl23448tfvz 23448 tfvz 100 -40 to +125 20 ld tssop m20.173 isl23448ufvz 23448 ufvz 50 -40 to +125 20 ld tssop m20.173 isl23448wfvz 23448 wfvz 10 -40 to +125 20 ld tssop m20.173 isl23448tfrz 448t 100 -40 to +125 20 ld 3x4 qfn l20.3x4 ISL23448UFRZ 448u 50 -40 to +125 20 ld 3x4 qfn l20.3x4 isl23448wfrz 448w 10 -40 to +125 20 ld 3x4 qfn l20.3x4 notes: 1. add ?-tk? suffix for 1k unit or ?-t7a? suffix for 250 unit tape and reel options . please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl23448 . for more information on msl please see techbrief tb363 .
isl23448 4 fn7905.0 august 19, 2011 absolute maximum rating s thermal information supply voltage range v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v v logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any dcp terminal pin . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v voltage on any digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v wiper current i w (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 6kv cdm model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . . . . . . . . 1kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 300v latch up (tested per jesd-78b; class 2, level a) . . . . 100ma @ +125c thermal resistance (typical) ja (c/w) jc (c/w) 20 ld tssop package (notes 4, 7) . . . . . . 85 33 20 ld qfn package (notes 5, 6) . . . . . . . . 40 4 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7v to 5.5v v logic supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2v to 5.5v dcp terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to v cc max wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center. analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units r total rh to rl resistance w option 10 k ? u option 50 k ? t option 100 k ? rh to rl resistance tolerance -20 2 +20 % end-to-end temperature coefficient w option 125 ppm/c u option 65 ppm/c t option 45 ppm/c v rh , v rl dcp terminal voltage v rh or v rl to gnd 0v cc v r w wiper resistance rh - floating, v rl = 0v, force i w current to the wiper, i w = (v cc - v rl )/r total, v cc = 2.7v to 5.5v 70 200 ? v cc = 1.7v 580 ? c h /c l /c w terminal capacitance see ?dcp macro model? on page 8 32/32/32 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to v cc -0.4 < 0.1 0.4 a noise resistor noise density wiper at middle point, w option 16 nv/ hz wiper at middle point, u option 49 nv/ hz wiper at middle point, t option 61 nv/ hz feed thru digital feed-through from bus to wiper wiper at middle point -65 db psrr power supply reject ratio wiper output change if v cc change 10%; wiper at middle point -75 db
isl23448 5 fn7905.0 august 19, 2011 voltage divider mode (0v @ rl; v cc @ rh; measured at rw, unloaded) inl (note 13) integral non-linearity, guaranteed monotonic w option -0.5 0.15 +1.0 lsb (note 9) u, t option -0.5 0.15 +0.5 lsb (note 9) dnl (note 12) differential non-linearity, guaranteed monotonic w option -0.5 0.15 +0.5 lsb (note 9) u, t option -0.5 0.15 +0.5 lsb (note 9) fserror (note 11) full-scale error w option -3 -1.5 0 lsb (note 9) u, t option -1.5 -0.9 0 lsb (note 9) zserror (note 10) zero-scale error w option 0 1.5 3 lsb (note 9) u, t option 0 0.9 1.5 lsb (note 9) vmatch (note 22) dcp to dcp matching dcps at same tap position, same voltage at all rh terminals, and same voltage at all rl terminals -2 0.5 2 lsb (note 9) tc v (note 14) ratiometric temperature coefficient w option, wiper register set to 40 hex 8 ppm/c u option, wiper register set to 40 hex 4 ppm/c t option, wiper register set to 40 hex 2.3 ppm/c t ls_settling large signal wiper settling time from code 0 to 7f hex, measured from 0 to 1lsb settling of the wiper 300 ns f cutoff -3db cutoff frequency wiper at middle point w option 1200 khz wiper at middle point u option 250 khz wiper at middle point t option 120 khz rheostat mode (measurements between rw and rl pins with rh not connected, or between rw and rh with rl not connected) r inl (note 18) integral non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -1.0 0.5 +1.0 mi (note 15) w option; v cc = 1.7v 4 mi (note 15) u, t option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) u, t option; v cc = 1.7v 1 mi (note 15) r dnl (note 17) differential non-linearity, guaranteed monotonic w option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) w option; v cc = 1.7v 0.4 mi (note 15) u, t option; v cc = 2.7v to 5.5v -0.5 0.15 +0.5 mi (note 15) u, t option; v cc = 1.7v 0.4 mi (note 15) analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units
isl23448 6 fn7905.0 august 19, 2011 r offset (note 16) offset, wiper at 0 position w option; v cc = 2.7v to 5.5v 0 1.8 3 mi (note 15) w option; v cc = 1.7v 3 mi (note 15) u, t option; v cc = 2.7v to 5.5v 0 0.3 1 mi (note 15) u, t option; v cc = 1.7v 0.5 mi (note 15) rmatch (note 23) dcp to dcp matching any two dcps at the same tap position with the same terminal voltages -2 0.5 2 lsb (note 9) tcr (note 19) resistance temperature coefficient w option; wiper register set between 19 hex and 7f hex 170 ppm/c u option; wiper register set between 19 hex and 7f hex 80 ppm/c t option; wiper register set between 19 hex and 7f hex 50 ppm/c analog specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units i logic v logic supply current (write/read) v logic = 5.5v, v cc = 5.5v, f sck = 5mhz (for spi active read and write) 1.5 ma v logic = 1.2v, v cc = 1.7v, f sck = 1mhz (for spi active read and write) 30 a i cc v cc supply current (write/read) v logic = 5.5v, v cc = 5.5v 110 a v logic = 1.2v, v cc = 1.7v 10 a i logic sb v logic standby current v logic = v cc = 5.5v, spi interface in standby 2 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 0.5 a i cc sb v cc standby current v logic = v cc = 5.5v, spi interface in standby 3 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 1.5 a i logic shdn v logic shutdown current v logic = v cc = 5.5v, spi interface in standby 2 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 0.5 a i cc shdn v cc shutdown current v logic = v cc = 5.5v, spi interface in standby 3 a v logic = 1.2v, v cc = 1.7v, spi interface in standby 1.5 a i lkgdig leakage current, at pins cs , sdo, sdi, sck voltage at pin from gnd to v logic -0.4 <0.1 0.4 a
isl23448 7 fn7905.0 august 19, 2011 t dcp wiper response time w option; cs rising edge to wiper new position, from 10% to 90% of final value. 0.4 s u option; cs rising edge to wiper new position, from 10% to 90% of final value. 1.5 s t option; cs rising edge to wiper new position, from 10% to 90% of final value. 3.5 s tshdnrec dcp recall time from shutdown mode cs rising edge to wiper re called position and rh connection 1.5 s v cc, v logic ramp v cc , v logic ramp rate (note 21) ramp monotonic at any level 0.01 50 v/ms serial interface specification for sck, sdi, sdo, cs unless otherwise noted. symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units v il input low voltage -0.3 0.3 x v logic v v ih input high voltage 0.7 x v logic v logic + 0.3 v hysteresis sdi and sck input buffer hysteresis v logic > 2v 0.05 x v logic v v logic < 2v 0.1 x v logic v ol sdo output buffer low voltage i ol = 3ma, v logic > 2v 0 0.4 v i ol = 1.5ma, v logic < 2v 0.2 x v logic v r pu sdo pull-up resistor off-chip maximum is determined by t ro and t fo with maximum bus load cb = 30pf, f sck =5mhz 1.5 k ? c pin sck, sdo, sdi, cs pin capacitance 10 pf f sck sck frequency v logic = 1.7v to 5.5v 5 mhz v logic = 1.2v to 1.6v 1 mhz t cyc spi clock cycle time v logic 1.7v 200 ns t wh spi clock high time v logic 1.7v 100 ns t wl spi clock low time v logic 1.7v 100 ns t lead lead time v logic 1.7v 250 ns t lag lag time v logic 1.7v 250 ns t su sdi, sck and cs input setup time v logic 1.7v 50 ns t h sdi, sck and cs input hold time v logic 1.7v 50 ns t ri sdi, sck and cs input rise time v logic 1.7v 10 ns t fi sdi, sck and cs input fall time v logic 1.7v 10 20 ns t dis sdo output disable time v logic 1.7v 0 100 ns t so sdo output setup time v logic 1.7v 50 ns t v sdo output valid time v logic 1.7v 150 ns t ho sdo output hold time v logic 1.7v 0 ns t ro sdo output rise time r pu = 1.5k, cbus = 30pf 60 ns operating specifications v cc = 2.7v to 5.5v, v logic = 1.2v to 5.5v over recommended operating conditions unless otherwise stated. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units
isl23448 8 fn7905.0 august 19, 2011 dcp macro model t fo sdo output fall time r pu = 1.5k, cbus = 30pf 60 ns t cs cs deselect time 2s notes: 8. typical values are for t a = +25c and 3.3v supply voltages. 9. lsb = [v(rw) 127 ? v(rw) 0 ]/127. v(rw) 127 and v(rw) 0 are v(rw) for the dcp register set to 7f hex and 00 hex respectively. lsb is the incremental voltage when changing from one tap to an adjacent tap. 10. zs error = v(rw) 0 /lsb. 11. fs error = [v(rw) 127 ? v cc ]/lsb. 12. dnl = [v(rw) i ? v(rw) i-1 ]/lsb-1, for i = 1 to 127. i is the dcp register setting. 13. inl = [v(rw) i ? i ? lsb ? v(rw) 0 ]/lsb for i = 1 to 127 14. for i = 8 to 127 decimal, t = -40c to +125c. max( ) is the maximum value of the wiper voltage and min( ) is the minimum value of the wiper voltage over the temperature range. 15. mi = |rw 127 ? rw 0 |/127. mi is a minimum increment. rw 127 and rw 0 are the measured resistances for the dcp register set to 7f hex and 00 hex respectively. 16. roffset = rw 0 /mi, when measuring between rw and rl. roffset = rw 127 /mi, when measuring between rw and rh. 17. rdnl = (rw i ? rw i-1 )/mi -1, for i = 8 to 127. 18. rinl = [rw i ? (mi ? i) ? rw 0 ]/mi, for i = 8 to 127. 19. for i = 8 to 127, t = -40c to +125c. max( ) is the maximum value of the resistance and min( ) is the minimum value of the resistance over the temperature range. 20. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. it is preferable to ramp up both the v logic and the v cc supplies at the same time. if this is not possible, it is recommended to ramp-up the v logic first followed by the v cc . 22. vmatch = [v(rwx)i - v(rwy)i]/lsb, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. 23. rmatch = (rwi,x - rwi,y)/mi, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. serial interface specification for sck, sdi, sdo, cs unless otherwise noted. (continued) symbol parameter test conditions min (note 20) typ (note 8) max (note 20) units tc v max v rw () i () min v rw () i () ? vrw i +25c () () ----------------------------------------------------------------------------- - 10 6 +165c --------------------- = tc r max ri () min ri () ? [] ri +25c () ------------------------------------------------------ - 10 6 +165c --------------------- = 32pf rh r total c h 32pf c w c l 32pf rw rl
isl23448 9 fn7905.0 august 19, 2011 timing diagrams input timing output timing xdcp? timing (for all load instructions) ... cs sck sdi sdo msb lsb t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck sdo sdi addr msb lsb t dis t ho t v ... t so ... cs sck sdi msb lsb v w t dcp ... sdo *when cs is high sdo at z or hi-z state
isl23448 10 fn7905.0 august 19, 2011 typical performance curves figure 3. 10k ? dnl vs tap position, v cc = 3.3v, +25c figure 4. 50k ? dnl vs tap position, v cc = 3.3v, +25c figure 5. 10k ? inl vs tap position, v cc = 3.3v, +25c figure 6. 50k ? inl vs tap position, v cc = 3.3v, +25c figure 7. 10k ? rdnl vs tap position, v cc = 3.3v, +25c figure 8. 50k ? rdnl vs tap position, v cc = 3.3v, +25c -0.12 -0.06 0.00 0.06 0.12 0 32 64 96 128 d n l ( l s b ) tap position (decimal) -0.04 -0.02 0.00 0.02 0.04 0 326496128 d n l ( l s b ) tap position (decimal) -0.16 -0.08 0.00 0.08 0.16 0 326496128 i n l ( l s b ) tap position (decimal) 0.00 0.04 0.08 0.12 0.16 0 326496128 i n l ( l s b ) tap position (decimal) -0.12 -0.06 0.00 0.06 0.12 0 32 64 96 128 r d n l ( m i ) tap position (decimal) -0.04 -0.02 0.00 0.02 0.04 0326496128 r d n l ( m i ) tap position (decimal)
isl23448 11 fn7905.0 august 19, 2011 figure 9. 10k ? rinl vs tap position, v cc = 3.3v, +25c figure 10. 50k ? rinl vs tap position, v cc = 3.3v, +25c figure 11. 10k ? wiper resistance vs tap position, v cc = 3.3v figure 12. 50k ? wiper resistance vs tap position, v cc = 3.3v figure 13. 10k ? tcv vs tap position, v cc = 3.3v figure 14. 50k ? tcv vs tap position, v cc = 3.3v typical performance curves (continued) 0.0 0.1 0.2 0.3 0.4 0 32 64 96 128 r i n l ( m i ) tap position (decimal) -0.08 -0.04 0.00 0.04 0.08 0 32 64 96 128 r i n l ( m i ) tap position (decimal) 0 20 40 60 80 100 0 32 64 96 128 +125c -40c +25c w i p e r r e s i s t a n c e ( ? ) tap position (decimal) 0 20 40 60 80 100 120 0 32 64 96 128 w i p e r r e s i s t a n c e ( ? ) tap position (decimal) +125c -40c +25c 0 50 100 150 200 15 43 71 99 127 t c v ( p p m / c ) tap position (decimal) 0 10 20 30 40 15 43 71 99 127 t c v ( p p m / c ) tap position (decimal)
isl23448 12 fn7905.0 august 19, 2011 figure 15. 10k ? tcr vs tap position figure 16. 50k ? tcr vs tap position, v cc = 3.3v figure 17. 100k ? tcv vs tap position, v cc = 3.3v figure 18. 100k ? tcr vs tap position, v cc = 3.3v figure 19. wiper digital feed-through figure 20. wiper transition glitch typical performance curves (continued) 0 100 200 300 400 15 43 71 99 127 t c r ( p p m / c ) tap position (decimal) 0 20 40 60 80 100 15 43 71 99 127 t c r ( p p m / c ) tap position (decimal) 0 5 10 15 20 15 43 71 99 127 t c v ( p p m / c ) tap position (decimal) 0 20 40 60 80 100 15 43 71 99 127 t c r ( p p m / c ) tap position (decimal) ch1: 1v/div, 1s/div ch2: 10mv/div, 1s/div sck clock rw pin wiper ch1: 20mv/div, 2s/div ch2: 2v/div, 2s/div cs rising
isl23448 13 fn7905.0 august 19, 2011 functional pin descriptions potentiometers pins rh i and rl i the high (rhi, i = 0, 1, 2, 3) and low (rli, i = 0, 1, 2, 3) terminals of the isl23448 are equivalent to the fixed terminals of a mechanical potentiometer. rhi and rli are referenced to the relative position of the wiper an d not the voltage potential on the terminals. with wri set to 127 de cimal, the wiper will be closest to rhi, and with the wri set to 0, the wiper is closest to rli. rw i rwi (i = 0, 1, 2, 3) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the wri register. power pins v cc power terminal for the potentiometer section analog power source. can be any value needed to support the voltage range of the dcp pins, from 1.7v to 5.5v, independent of the v logic voltage. bus interface pins serial clock (sck) this input is the serial clock of the spi serial interface. serial data input (sdi) the sdi is a serial data input pin for spi interface. it receives operation code, wiper address and data from the spi remote host device. the data bits are shif ted in at the rising edge of the serial clock sck, while the cs input is low. figure 21. wiper large signal settling time figure 22. power-on start-up in voltage divider mode figure 23. 10k ? -3db cut off frequency figure 24. standby current vs temperature typical performance curves (continued) 1v/div 0.2s/div wiper cs 0.5v/div 20s/div v cc wiper 0.5v/div, 0.2s/div -3db frequency = 1.437mhz at middle tap ch1: rh terminal ch2: rw terminal 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -40 -15 10 35 60 85 110 v cc = 1.7v, v logic = 1.2v v cc = 5.5v, v logic = 5.5v s t a n d b y c u r r e n t i c c ( a ) temperature (c)
isl23448 14 fn7905.0 august 19, 2011 serial data output (sdo) the sdo is a serial data output pi n. during a read cycle, the data bits are shifted out on the falling edge of the serial clock sck and will be available to the master on the following rising edge of sck. the output type is configured th rough acr[1] bit for push-pull or open drain operation. th e default setting for th is pin is push-pull. an external pull-up resistor is required for open drain output operation. when cs is high, the sdo pin is in tri-state (z) or high-tri-state (hi-z) depending on the selected configuration. chip select (cs ) cs low enables the isl23448, placing it in the active power mode. a high to low transition on cs is required prior to the start of any operation after power-up. when cs is high, the isl23448 is deselected and the sd o pin is at high impedance, and the device will be in the standby state. v logic digital power source for the logic control section. it supplies an internal level translator for 1.2v to 5.5v serial bus operation. use the same supply as the spi logic source. principles of operation the isl23448 is an integrated circuit incorporating four dcps with its associated registers and an spi serial interface providing direct communication between a host and the potentiometer. the resistor array is comprised of individual resistors connected in series. at either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operate in a ?make-before-break? mode when the wiper changes tap positions. voltage at any of the dcp pins, rhi, rli or rwi, should not exceed v cc level at any conditions during power-up and normal operation. the v logic pin is the terminal for the logic control digital power source. it should use the same supply as the spi logic source, which allows reliable communication with a wide range of microcontrollers and is independent from the v cc level. this is extremely important in systems where the master supply has lower levels than the dcp analog supply. dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical en ds of each dcp are equivalent to the fixed terminals of a mechan ical potentiometer (rhi and rli pins). the rwi pin of the dcp is connected to intermediate nodes, and is equivalent to the wipe r terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 8-bit volatile wiper register (wri). when the wr of a dcp contains all zeroes (wri[7:0 ] = 00h), its wiper terminal (rwi) is closest to its ?low? terminal (rli ). when the wri register of a dcp contains all ones (wri[7:0] = 7fh), its wiper terminal (rwi) is closest to its ?high? terminal (rhi). as the value of the wri increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position clos est to rli to the position closest to rhi. at the same time, the resistance between rwi and rli increases monotonically, while the resistance between rhi and rwi decreases monotonically. while the isl23448 is being powered up, all the wri are reset to 40h (64 decimal), which positions rwi at the center between rli and rhi. the wri can be read or written to directly using the spi serial interface as described in the following sections. memory description the isl23448 contains five volatile 8-bit registers: wiper register wr0, wiper register wr1, wiper register wr2, wiper register wr3 and access control register (acr). the memory map of isl23448 is shown in table 1. the wiper register wri at address i, contains current wiper position of dcpi (i = 0, 1, 2, 3). the access control register (acr) at address 10h contains information and control bits described in table 2. the sdo bit (acr[1]) configures th e type of sdo output pin. the default value of sdo bit is 0 fo r push-pull output. the sdo pin can be configured as open drain output for some applications. in this case, an external pull-up resistor is required. reference the ?serial interface specification? on page 7. shutdown function the shdn bit (acr[6]) disables or enables shutdown mode for all dcp channels simultaneously. when this bit is 0, i.e., each dcp is forced to end-to-end open circuit and each rw shorted to rl through a 2k ? serial resistor, as shown in figure 25. the default value of the shdn bit is 1. table 1. memory map address (hex) volatile register name default setting (hex) 10 acr 40 3wr3 40 2wr2 40 1wr1 40 0wr0 40 table 2. access control register (acr) bit # 76543210 name/ value 0shdn 00 0 0sdo0 figure 25. dcp connection in shutdown mode 2k ? rw rl rh
isl23448 15 fn7905.0 august 19, 2011 when the device enters shutdown, all current dcp wr settings are maintained. when the device exits shutdown, the wipers will return to the previous wr settings after a short settling time (see figure 26). in shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3v for more than 0.2 to 0.4s the wipers will be reset to their mid position. this is done to avoid an undefined state at the wiper outputs. spi serial interface the isl23448 supports an spi serial protocol, mode 0. the device is accessed via the sdi input and sdo output with data clocked in on the rising edge of sck, and clocked out on the falling edge of sck. cs must be low during communication with the isl23448. the sck and cs lines are controlled by the host or master. the isl23448 operates only as a slave device. all communication over the sp i interface is conducted by sending the msb of each byte of data first. protocol conventions the spi protocol contains instructio n byte followed by one or more data bytes. a valid instruction byte contains instruction as the three msbs, with the following five regi ster address bits (see table 3). the next byte sent to the isl23448 is the data byte. table 4 contains a valid instruction set for isl23448. if the [r4:r0] bits are zero, one, tw o or three then the read or write is to the wri register. if the [r4: r0] are 10000, then the operation is to the acr. write operation a write operation to the isl23448 is a two or more bytes operation. first, it requires that the cs transition from high-to-low. then, the host sends a valid instruction byte, followed by one or more data bytes to the sdi pin. the host terminates the write operation by pulling the cs pin from low-to-high. instruction is exec uted on the rising edge of cs (see figure 27). read operation a read operation to the isl23448 is a four byte operation. first, it requires that the cs transition from high-to-low. then, the host sends a valid instruction byte, followed by a ?dummy? data byte, nop instruction byte and another ?dummy? data byte to the sdi pin. the spi host receives the instruction byte (instruction code + register address) and requested data byte from the sdo pin on the rising edge of sck during the third and fourth bytes, respectively. the host terminates the read by pulling the cs pin from low-to-high (see figure 28). figure 26. shutdown mode wiper response power-up user programmed mid scale = 40h shdn activated shdn released after shdn wiper voltage, v rw (v) shdn mode time (s) wiper restore to the original position 0 table 3. instruction byte format bit #76543210 i2 i1 i0 r4 r3 r2 r1 r0 table 4. instruction set instruction set operation i2 i1 i0 r4 r3 r2 r1 r0 000xxxxxnop 001xxxxxacr read 011xxxxxacr wrte 1 0 0 r4r3r2r1r0wri or acr read 1 1 0 r4r3r2r1r0wri or acr wrte where x means ?do not care?.
isl23448 16 fn7905.0 august 19, 2011 applications information communicating with isl23448 communication with isl23448 proceeds using spi interface through the acr (address 10000b), wr0 (addresses 00000b), wr1 (addresses 00001b), wr2 (addresses 00010b), wr3 (addresses 00011b) registers. the wiper of the potentiometer is controlled by the wri register. writes and reads can be made directly to these registers to control and monitor the wiper position. daisy chain configuration when an application needs more than one isl23448, it can communicate with all of them without additional cs lines by daisy chaining the dcps, as shown in figure 29. in daisy chain configuration, the sdo pin of the previous chip is connected to the sdi pin of the following chip, and each cs and sck pins are connected to the corresponding mi crocontroller pins in parallel, like regular spi interface implementation. the daisy chain configuration can also be used for simultaneous setting of multiple dcps. note, the number of daisy chained dcps is limited only by the drivin g capabilities of sck and cs pins of microcontroller; for larger number of spi devices, buffering of sck and cs lines is required. daisy chain write operation the write operation starts by a high-to-low transition on the cs line, followed by n number of two bytes write instructions on the sdi line with reversed chain access sequence: the instruction byte + data byte for the last dcp in chain is going first, as shown in figure 30, where n is a number of dcps in chain. the serial data is going through dcps from dcp0 to dcp(n-1) as follows: dcp0 --> dcp1 --> dcp2 --> ... --> dcp(n-1). the write instruction is executed on the rising edge of cs for all n dcps simultaneously. daisy chain read operation the read operation consists of tw o parts: first, send the read instructions (n two bytes operatio n) with valid address; second, read the requested data while se nding nop instructions (n two bytes operation), as shown in figures 31 and 32. the first part starts by a high-to-low transition on the cs line, followed by n two bytes read instruction on the sdi line with reversed chain access sequence: the instruction byte + dummy data byte for the last dcp in chain is going first, followed by a low-to-high transition on the cs line. the read instructions are executed during the second part of the read sequence. it also starts by a high-to-low transition on the cs line, followed by n number of two bytes nop instru ctions on the sdi line and low-to-high transition of cs . the data is read on every even byte during the second part of the read sequence while every odd byte contains code 111b followed by the address from which the data is being read. figure 27. two byte write sequence cs sck sdi sdo wr instruction data byte 1 3 4 5 7 8 9 10111213141516 26 addr figure 28. four by te read sequence cs sck sdi sdo rd addr nop rd addr read data 1 8 16 24 32
isl23448 17 fn7905.0 august 19, 2011 wiper transition when stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/unders hoot, resulting from the sudden transition from a very low impe dance ?make? to a much higher impedance ?break? within a short period of time (<1s). there are several code transitions such as 0fh to 10h, 1fh to 20h,..., 6fh to 7fh, which have higher transient glitch. note, that all switching transients will settle well within the settling time as stated in the datasheet. a sm all capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus, this may not be a good solution for some applications. it may be a good idea, in this case, to use fast amplifiers in a signal chain for fast recovery. v logic requirements it is recommended to keep v logic powered all the time during normal operation. in a case where turning v logic off is necessary, it is recomme nded to ground the v logic pin of the isl23448. grounding the v logic pin or both v logic and v cc does not affect other devices on the same bus. it is good practice to put a 1f capacitor in parallel with 0.1f decoupling capacitor close to the v logic pin. v cc requirements and placement it is recommended to put a 1f capacitor in parallel with 0.1f decoupling capacitor close to the v cc pin. cs sck mosi miso cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo cs sck sdi sdo c dcp0 dcp1 dcp2 dcp(n-1) figure 29. daisy chain configuration n dcp in a chain cs sck sdi sdo 0 wr d c p2 wr d c p1 wr d c p0 wr d c p1 sdo 1 wr d c p2 sdo 2 wr d c p2 figure 30. daisy chain write sequence of n = 3 dcp 16 clkls 16 clks 16 clks
isl23448 18 fn7905.0 august 19, 2011 figure 31. two byte read instruction cs sck sdi sdo instruction addr data in data out 1 2 10 11 12 13 14 15 16 345 67 8 9 cs sck sdi sdo rd dcp1 rd dcp0 nop nop nop dcp2 out dcp1 out dcp0 out rd dcp2 16 clks 16 clks 16 clks 16 clks 16 clks 16 clks figure 32. daisy chain read sequence of n = 3 dcp
isl23448 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7905.0 august 19, 2011 for additional products, see www.intersil.com/product_tree revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. products intersil corporation is a leader in the desi gn and manufacture of high-performance an alog semiconductors. the company's product s address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. in tersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl23448 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php date revision change august 19, 2011 fn7905.0 initial release.
isl23448 20 fn7905.0 august 19, 2011 package outline drawing m20.173 20 lead thin shrink small outline package (tssop) rev 2, 5/10 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate bur rs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and toleranc ing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space betwee n protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 0.09-0.20 see detail "x" (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 20 0.20 c b a 2 1 3 9 b 1 3 10 a pin #1 i.d. mark 6.50 0.10 6.40 4.40 0.10 0.65 0.10 c seating plane 0.25 +0.05/-0.06 5 c h - 0.05 1.20 max 0.10 c b a m
isl23448 21 fn7905.0 august 19, 2011 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6

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