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LTC2953 1 2953f typical application features applications description push button on/off controller with voltage monitoring the ltc ? 2953 is a push button on/off controller that manages system power via a push button interface. an enable output toggles system power while an interrupt output provides debounced push button status. the inter- rupt output can be used in menu driven applications to request a system power down. the LTC2953 also features input and output power sup- ply monitors. an uncommitted power fail comparator provides real time input monitor information, while a de-glitched under voltage lockout comparator gracefully initiates a system power down. the under voltage lockout comparator prevents the system from powering from a low power supply. the adjustable supply monitor input is compared against an accurate internal 0.5v reference. the reset output remains low until the supply monitor input has been in compliance for 200ms. the LTC2953 operates over a wide 2.7v to 27v input voltage range and draws only 14a of current. two ver- sions of the part accommodate either positive or negative enable polarities. push button on/off control with interrupt wide operating voltage range: 2.7v to 27v push button control of system power low supply current: 14a power fail comparator generates warning uvlo comparator gracefully latches power off adjustable supply monitor with 200ms reset adjustable power down timer low leakage en output (LTC2953-1) allows dc/dc converter control high voltage ? e ? n output (LTC2953-2) allows circuit breaker control simple interface allows orderly system power up and power down 1.5% threshold tolerances 10kv esd hbm on ? p ? b input 12-pin 3mm 3mm dfn push button power path control battery power supervisor portable instrumentation, pda blade servers desktop and notebook computers , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. turn on pulse turns on stays on interrupt interrupt turns off short interrupt pulse long turn off pulse pb int 2954 td01b en v in v out on/off en v in vm rst pfo int kill rst gpio int kill LTC2953-1 pdt dc/dc shdn system logic 8.4v 3.3v 499k 100k 100k 100k 100k 100k t pdt = 6.4 seconds 2953 ta01 1 f pb gnd pfi uvlo 2150k 23.2k 196k +
LTC2953 2 2953f electrical characteristics absolute maximum ratings supply voltage (v in ) .................................. ?0.3v to 33v input voltages p b, p f i, uvlo ........................................... ?6v to 33v vm ......................................................... ?0.3v to 20v k i l l ....................................................... ?0.3v to 10v pdt ....................................................... ?0.3v to 2.7v output voltages en/ e n, p f o ............................................ ?0.3v to 50v r s t, i n t ................................................ ?0.3v to 10v operating temperature range LTC2953c ................................................ 0c to 70c LTC2953i ............................................. ?40c to 85c storage temperature range ................... ?65c to 125c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 2.7v to 27v, unless otherwise noted (note 2). symbol parameter conditions min typ max units supply pin (v in ) v in supply voltage range steady state operation 2.7 27 v i in v in supply current v in = 2.7v to 27v 14 26 a v uvl v in undervoltage lockout v in falling 2.2 2.3 2.5 v push button, enable ( p b, en/ e n) v pb(min, max) p b operating voltage range single-ended ?1 27 v i pb p b input current 2.5v < v pb < 27v v pb = 1v v pb = 0.6v ?1 ?3 ?6 ?9 1 ?12 ?15 a a a v pb(vth) p b input threshold p b falling 0.6 0.8 1 v v pb(voc) p b open circuit voltage i pb = ?1a 1 1.6 2 v pin configuration top view 13 dd package 12-lead (3mm 3mm) plastic dfn 12 11 8 9 10 4 5 3 2 1 int en/en rst pfo pfi uvlo gnd v m kill pdt pb v in 6 7 t jmax = 125c, ja = 43c/w exposed pad (pin 13) pcb ground connection optional order information lead free finish tape and reel part marking* package description temperature range LTC2953cdd-1#pbf LTC2953cdd-2#pbf LTC2953idd-1#pbf LTC2953idd-2#pbf LTC2953cdd-1#trpbf LTC2953cdd-2#trpbf LTC2953idd-1#trpbf LTC2953idd-2#trpbf lcwt lcqt lcwt lcqt 12-lead (3mm 3mm) plastic dfn 12-lead (3mm 3mm) plastic dfn 12-lead (3mm 3mm) plastic dfn 12-lead (3mm 3mm) plastic dfn 0c to 70c 0c to 70c ?40c to 85c ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
LTC2953 3 2953f electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 2.7v to 27v, unless otherwise noted (note 2). symbol parameter conditions min typ max units i en(lkg) en/ ? e ? n leakage current v en/ ? e ? n = 1v, sink current off v en/ ? e ? n = 40v, sink current off 0.1 1 a a v en(vol) en/ ? e ? n voltage output low i en/ ? e ? n = 500a 0.11 0.4 v t en, lock out en/ ? e ? n lock out time (note 3) enable released enable asserted 52 64 82 ms on/off timing pins ( ? p ? b, uvlo, pdt, ? i ? n ? t) t db, on turn on debounce time ? p ? b falling enable asserted 26 32 41 ms i pdt(pu) pdt pull up current v pdt = 0v C2.4 C3 C3.6 a i pdt(pd) pdt pull down current v pdt = 1.3v 2.433.6 a t db, off turn off interrupt debounce time ? p ? b, uvlo falling ? i ? n ? t falling 26 32 41 ms t pd, min internal ? p ? b power down delay time (note 4) ? p ? b, uvlo falling enable released pdt open 52 64 82 ms t pdt additional adjustable ? p ? b power down delay time c pdt = 1500pf 9 11.5 13.5 ms t int , min minimum ? i ? n ? t pulse width ? i ? n ? t asserted ? i ? n ? t released 26 32 41 ms t int, max maximum ? i ? n ? t pulse width c pdt = 1500pf, ? i ? n ? t asserted ? i ? n ? t released 35 43.5 54.5 ms p handshake pins ( ? k ? i ? l ? l, ? i ? n ? t) v kill(th) ? k ? i ? l ? l input threshold voltage ? k ? i ? l ? l falling 0.57 0.6 0.63 v v kill(hyst) ? k ? i ? l ? l input threshold hysteresis 10 30 50 mv t kill(pw) ? k ? i ? l ? l minimum pulse width 30 s t kill(pd) ? k ? i ? l ? l propagation delay ? k ? i ? l ? l falling enable released 30 s t kill, on blank ? k ? i ? l ? l turn on blanking (note 5) ? k ? i ? l ? l = low, enable asserted enable released 400 512 650 ms i kill(lkg) ? k ? i ? l ? l leakage current v kill = 0.6v 0.1 a i int (lkg) ? i ? n ? t leakage current v int = 3v 0.1 a v int (vol) ? i ? n ? t output voltage low i int = 3ma 0.11 0.4 v power fail and voltage monitor pins ( ? p ? f ? i, ? p ? f ? o, uvlo, vm, ? r ? s ? t) v pfi(th) ? p ? f ? i input threshold voltage falling 492 500 508 mv v uvlo(th) uvlo input threshold voltage falling 492 500 508 mv vm (th) adjustable reset threshold falling/rising 492 500 508 mv v th ? p ? f ? i-uvlo threshold mismatch C5 0 5 mv v pfi(hyst) ? p ? f ? i input hysteresis 2 4 10 mv v uvlo(hyst) uvlo input hysteresis 30 50 70 mv v pfo(vol) ? p ? f ? o output voltage low i pfo = 500a 0.11 0.4 v v rst(vol) ? r ? s ? t output voltage low i = 3ma 0.11 0.4 v
LTC2953 4 2953f electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 2.7v to 27v, unless otherwise noted (note 2). note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3: the enable lock out time is designed to allow an application to properly power down such that the next power up sequence starts from a consistent powered down con? guration. ? p ? b is ignored during this lock out time. this time delay does not include t db, on . note 4: to manually force a release of the en/ ? e ? n pin, either ? p ? b or uvlo must be held low for at least t pd, min (internal default power down timer) + t pdt (adjustable by placing external capacitor at pdt pin). note 5: the ? k ? i ? l ? l turn on blanking timer period (t kill, on blank ) is the waiting period immediately after enable output is asserted. this blanking time allows suf? cient time for the dc/dc converter and the p to perform power up tasks. the ? k ? i ? l ? l, ? p ? b and uvlo inputs are ignored during this period. if ? k ? i ? l ? l remains low at the end of this blanking period, the enable output is released, thus turning off system power. symbol parameter conditions min typ max units i pfi(lkg) ? p ? f ? i leakage current v pfi = 0.5v v pfi = 27v 2 10 1 na a i pfo(lkg) ? p ? fo leakage current v pfo = 1v v pfo = 40v 2 10 1 na a i uvlo(lkg) uvlo leakage current v uvlo = 0.5v v uvlo = 27v 2 10 1 na a i vm(lkg) vm input leakage current vm = 0.5v 2 10 na i rst(lkg) ? r ? s ? t output leakage current v rst = 3v 0.1 a t pfi ? p ? f ? i delay to ? p ? f ? o 40 100 200 s t rst reset timeout period 140 200 260 ms t uv vm under voltage detect to ? r ? s ? t vm less than vm (th) by more than 1% 250 s
LTC2953 5 2953f temperature ( c) ?0 5 i vin ( a) 10 15 20 ?5 0 25 50 2953 g01 75 100 v in = 27v v in = 3.3v v in = 2.7v v in (v) 05 10 i vin ( a) 14 20 10 20 25 2953 g02 12 18 16 15 30 35 t a = 25 c v in (v) 0 0 t db, on (ms) 10 20 30 40 50 5 10 15 20 2953 g03 25 30 t a = 25 c v in (v) 0 0 t db, off (ms) 10 20 30 40 50 5 10 15 20 2953 g04 25 30 t a = 25 c pdt external capacitance (nf) 1 10 t pd,min + t pdt (ms) 100 1000 10000 10 100 1000 t a = 25 c v in = 3.3v temperature ( c) pdt pull-down current ( a) 2953 g06 ?0 ?.6 ?.8 ?.0 ?.2 ?.4 ?5 0 25 50 75 100 v in = 3.3v temperature ( c) pdt pull-up current ( a) 2953 g07 ?0 2.6 2.8 3.0 3.2 3.4 ?5 0 25 50 75 100 v in = 3.3v pb voltage (v) ?0 0 pb current ( a) ?0 ?00 ?50 ?00 ?50 ?00 0102030 t a = 25 c v in = 3.3v external pb resistance to ground (k ) 0 0 pb voltage (mv) 50 100 150 200 250 300 5101520 v in = 3.3v t a = 100 c t a = ?5 c t a = 25 c typical performance characteristics supply current vs temperature supply current vs supply voltage turn on debounce time (t db, on ) vs v in turn off interrupt debounce time (t db, off ) vs v in forced power down delay time (t pd, min + t pdt ) vs pdt external capacitance pdt pull-down current vs temperature pdt pull-up current vs temperature ? p ? b current vs ? p ? b voltage ? p ? b voltage vs external ? p ? b resistance to ground
LTC2953 6 2953f v in (v) 0 en (v) 0.4 0.6 4 0.2 0 1 2 3 1.0 0.8 t a = 25 c 100k pull-up from en to v in v in (v) 0 en (v) 2 3 4 2953 g11 1 0 1 2 3 4 t a = 25 c 100k pull-up from en to v in v in (v) 0 0 pfo (v) 1 2 3 4 0.5 1.0 1.5 2.0 2953 g12 2.5 3.0 3.5 4.0 t a = 25 c pfi = 1v 100k pull-up from pfo to v in v in (v) 0 0 rst (v) 1 2 3 4 0.5 1.0 1.5 2.0 2953 g13 2.5 3.0 3.5 4.0 t a = 25 c vm = 1v 100k pull-up from rst to v in rst, int current load (ma) 0 0 rst, int v ol (mv) 100 200 300 400 500 600 2468 2953 g14 10 t a = 25 c v in = 3.3v temperature ( c) ?0 496 threshold (mv) 498 500 502 504 ?5 0 25 50 2953 g15 75 100 v in = 3.3v typical performance characteristics en (LTC2953-1) voltage vs v in ? e ? n (LTC2953-2) voltage vs v in ? p ? f ? o voltage vs v in ? r ? s ? t voltage vs v in ? r ? s ? t, ? i ? n ? t v ol vs current load threshold voltage (vm, ? p ? f ? i, uvlo) vs temperature en/en, pfo current load (ma) 0 en/en, pfo v ol (mv) 400 600 800 2.5 2953 g16 200 0 0.5 1 1.5 2 3 t a = 25 c v in = 3.3v en/ ? e ? n, ? p ? f ? o v ol vs current load
LTC2953 7 2953f pin functions gnd (pin 1): ground. vm (pin 2): voltage monitor input. input to an accurate comparator with a 0.5v threshold. vm controls the state of the ? r ? s ? t output pin and is independent of ? p ? b, ? p ? f ? i and uvlo status. a voltage below 0.5v on this pin asserts ? r ? s ? t low. connect to gnd if unused. ? k ? i ? l ? l (pin 3): ? k ? i ? l ? l input. forcing ? k ? i ? l ? l low releases the enable output. during system turn on, this pin is blanked by a 512ms internal timer (t kill, on blank ) to allow the system to pull ? k ? i ? l ? l high. this pin has an accurate 0.6v threshold and can be used as a power kill voltage monitor. set the pin voltage above its threshold if unused. pdt (pin 4): power down time input. a capacitor to ground determines the additional time (6.4 seconds/f) that ? p ? b or uvlo must be held low before releasing the en/ ? e ? n and ? i ? n ? t outputs. if this pin is left open, the power down delay time defaults to 64ms. ? p ? b (pin 5): push button input. connecting ? p ? b to ground through a momentary switch provides on/off control via the en/ ? e ? n and ? i ? n ? t outputs. an internal 100k pull-up resistor connects to an internal 1.9v bias voltage. the rugged ? p ? b input withstands 10kv esd hbm and can be pulled up to 27v externally without consuming extra current. voltages below ground will not damage the pin. v in (pin 6): power supply input: 2.7v to 27v. uvlo (pin 7): uvlo comparator input. when uvlo drops below its falling threshold (0.5v) for more than 32ms, the LTC2953 asserts ? i ? n ? t low, thereby requesting a system power down. if uvlo remains below its falling threshold (0.5v) for longer than the adjustable power down delay, the enable output is released. additionally, uvlo provides a ? p ? b lock out feature that prevents the user from asserting the enable output when uvlo falls below its threshold. connect to v in if unused. pfi (pin 8): power fail comparator input. input to an ac- curate comparator with a 0.5v falling threshold and 4mv of hysteresis. pfi controls the state of the ? p ? f ? o output pin and is independent of ? p ? b, vm and uvlo status. connect to gnd if unused. ? p ? f ? o (pin 9): power fail output. this pin is a high voltage open drain pull-down. ? p ? f ? o pulls low when pfi is below 0.5v. open circuit when unused. ? r ? s ? t (pin 10): reset output. this pin is an open drain pull-down. pulls low when vm input is below 0.5v and is held low for 200ms after vm input is above 0.5v. open circuit when unused. en (LTC2953-1, pin 11): open drain enable output. this output is intended to enable system power. en is asserted high after a valid ? p ? b turn on event (t db, on ). en is released low if: a) ? k ? i ? l ? l is not driven high (by p) within 512ms of the initial valid ? p ? b power turn on event, b) ? k ? i ? l ? l is driven low during normal operation, c) ? p ? b or uvlo is asserted and held low (t > t pd, min + t pdt ) during normal operation. ? e ? n (LTC2953-2, pin 11): open drain enable output. this output is intended to enable system power. ? e ? n is asserted low after a valid ? p ? b turn on event (t db, on ). ? e ? n is released high if: a) ? k ? i ? l ? l is not driven high (by p) within 512ms of the initial valid ? p ? b power turn-on event, b) ? k ? i ? l ? l is driven low during normal operation, c) ? p ? b or uvlo is asserted and held low (t > t pd, min + t pdt ) during normal operation. ? i ? n ? t (pin 12): open drain interrupt output. after a turn off event is detected (t db, off ) from ? p ? b or uvlo, the LTC2953 interrupts the system (p) by asserting ? i ? n ? t low. the p would perform power down and housekeeping tasks and then assert the ? k ? i ? l ? l pin low, thus releasing the enable out- put. the ? i ? n ? t pulse width is a minimum of 32ms and stays low as long as ? p ? b is asserted. if ? p ? b is asserted for longer than t pd, min + t pdt , however, the ? i ? n ? t and en/ ? e ? n outputs are immediately released. open circuit when unused. exposed pad (pin 13): exposed pad may be left open or connected to ground.
LTC2953 8 2953f block diagram logic oscillator 2.4v 34v zener 2.4v 1.5k 100k pb gnd en (?) en (?) kill int pdt 0.8v 0.5v 0.6v 0.5v 2953 bd regulator rst pfi pfo hv hv hv hv hv debounce and 10 s filter vm 200 ms rst delay uvlo 0.5v debounce and 10 s filter v in 2.7v to 27v hv indicates a high voltage pin + + +
LTC2953 9 2953f timing diagrams t db, on t kill, on blank pb kill en (LTC2953-1) 2953 td01 pb, uvlo and kill ignored do not care system sets kill high figure 1. power on timing (uvlo > 0.55v) t db, off t int, min t < t pdt uvlo int pdt en (LTC2953-1) t pd, min 2953 td02 pb and uvlo ignored uvlo ignored pb enable does not switch low figure 2. ? p ? b interrupt pulse: ? p ? b low for t db,off < t < (t pd, min + t pdt ) (enable remains active)
LTC2953 10 2953f timing diagrams t db, off t int, min t < t pdt uvlo int pdt en (LTC2953-1) t pd, min 2953 td03 pb and uvlo ignored pb ignored pb enable does not switch low pb int pdt 2953 td04 16 cycles en (LTC2953-1) t db, off pb ignored t pdt t pd, min t int, max uvlo uvlo ignored figure 3. uvlo interrupt pulse: uvlo low for t db,off < t < (t pd, min + t pdt ) (enable remains active) figure 4. push button power down timing: ? p ? b pressed and held low for t > (t pd, min + t pdt )
LTC2953 11 2953f timing diagrams pb int pdt 2953 td05 16 cycles en (LTC2953-1) t db, off uvlo ignored t pdt t pd, min t int, max uvlo pb ignored vm rst t uv t rst 2953 td06 0.5v 0.5v pfi pfo t pfi t pfi 2953 td07 0.5v 0.504v kill en (LTC2953-1) 2953 td08 0.6v 0.63v t kill(pw) t kill(pd) figure 5. uvlo power down timing: uvlo low for t > (t pd, min + t pdt ) figure 6. voltage monitor reset timing figure 7. power fail comparator timing figure 8. ? k ? i ? l ? l minimum pulse width and propagation delay
LTC2953 12 2953f operation the LTC2953 is a push button on/off controller with dual function input and output supply monitors. the part con- tains all the circuitry needed to debounce a push button input and provides a simple p handshake protocol for reliable toggling of system power. the LTC2953 operates over a wide 2.7v to 27v input voltage range and draws only 14a of current. the LTC2953 features dual function supply monitoring: a power fail comparator generates an early warning and an under voltage lock-out comparator initiates a controlled system power down. push button controller the push button input controls the enable and interrupt outputs. the enable output toggles system power while the interrupt output provides debounced push button status. the interrupt output can be used in menu driven applications to request a system power down. a power kill input allows a microprocessor or other logic to release the enable output, thus immediately powering down the system. to assert the enable output (turn on system power), press the push button ( ? p ? b) input and hold for at least 32ms. see figure 1. once system power has been enabled, a user can request a system power down by again pressing the push button for at least 32ms and releasing it before the pdt timer counts 16 cycles. the LTC2953 then asserts the interrupt output and the p subsequently sets the ? k ? i ? l ? l input low to turn off system power. note that the uvlo input can also assert the interrupt output. see figure 2 and figure 3 and dual function supply monitors section. in the event that the p does not respond to the interrupt request, the user can force release of the enable output by pressing and holding down the push button (or uvlo) until the pdt timer times out. see figure 4 and figure 5. dual function supply monitors an uncommitted power fail comparator provides real time supply threshold information. the power fail input (pfi) is compared against an accurate internal 0.5v refer- ence and the comparison result is passed directly to the power fail output ( ? p ? f ? o) pin. the operation of the power fail comparator is de-coupled from all other functionality and is always active. see figure 7. the under voltage lockout comparator provides the user with another method to initiate a controlled system power down. if the uvlo pin voltage falls below its falling thresh- old (0.5v) for longer than 32ms, the interrupt output is asserted for a minimum of 32ms. if the uvlo pin voltage remains below its threshold (0.5v) for an additional time given by the pdt external capacitor, then the enable pin is automatically released (thus powering down the system). see figure 3 and figure 5. this comparator also serves as an under voltage lockout. if system power is off (enable released) and uvlo < 0.5v, the uvlo comparator prevents the push button from turning on system power (asserting enable output). voltage supervisor with 200ms p reset the LTC2953 provides a single adjustable supply monitor with a nominal 200ms reset delay. when the vm input voltage drops below 0.5v, the ? r ? s ? t output is pulled low. ? r ? s ? t remains low for 200ms after the vm input has risen above 0.5v. the input 0.5v threshold has a guaranteed accuracy of 1.5% over temperature and process. the operation of the supply monitor is de-coupled from all other functionality and is always active. see figure 6.
LTC2953 13 2953f push button control power on sequence to enable system power, the push button input ( ? p ? b) must be held low continuously for 32ms (t db, on ). once the enable output (en/ ? e ? n) is asserted, the LTC2953 starts a 512ms internal timer (t kill, on blank ). the ? k ? i ? l ? l input must be driven high within this 512ms window. this blank- ing time represents the maximum time allowed for the system to power up and initialize the circuits driving the ? k ? i ? l ? l input. if ? k ? i ? l ? l remains low at the end of the blanking period, the enable output is released (see aborted power on sequence section). figure 9 shows a normal power on sequence. applications information short pulse interrupt to interrupt the p, either ? p ? b or uvlo must be low for at least 32ms (t db, off ). this signals the p either that a user has pressed the push button or that the supply is running low. the p would then perform power down and housekeeping tasks and assert ? k ? i ? l ? l low when done. this in turn releases the enable output, thus shutting off system power. see figure 10. note that either ? p ? b or uvlo can control the power down sequence, but not both at the same time. for example, if both ? p ? b and uvlo are high and the user presses the push button, ? p ? b will be active and uvlo will be ignored until ? p ? b is released or the power down sequence is complete. forced power off sequence the LTC2953 provides a failsafe feature that allows a user to manually force a system power down. for cases when the p fails to respond to the interrupt signal, the user can force a power down by pressing and holding either the push button or the uvlo inputs low. the length of time required to release the enable output is given by a ? xed internal 64ms delay (t pd, min ) plus an adjustable power down timer delay (t pdt ). the adjustable delay is set by placing an external capacitor on the pdt pin. use the following equation to calculate the capacitance for the desired extra delay. c pdt is the pdt pin external capacitor: c pdt = 1.56e-4 [f/ms] ? (t pdt C 1ms) see figure 11. t db, on t kill, on blank pb kill en (LTC2953-1) 2953 f09 pb, uvlo and kill ignored do not care system sets kill high t db, off t int, min pb or uvlo kill en (LTC2953-1) int 2953 f10 short pulse do not care system sets kill low system power off note that only the push button input can enable system power. the LTC2953 provides two enable output polarities to allow dc/dc converter control (LTC2953-1) and external power pfet control (LTC2953-2). pb or uvlo en (LTC2953-1) pdt 2953 f11 16 cycles long pulse t pdt t pd, min figure 10. power off interrupt timing figure 11. forced power off timing with adjustable delay (see figure 5 for more details) figure 9. power on timing (uvlo > 0.55v)
LTC2953 14 2953f applications information aborted power on sequence the LTC2953 provides an internal 512ms timer to detect when a system fails to power on properly. a power on sequence begins by debouncing the ? p ? b input. after the enable pin is subsequently asserted, the LTC2953 starts the 512ms blanking timer (t kill, on blank ). if the ? k ? i ? l ? l input is not driven high within this 512ms time window, the enable pin is immediately released, thus turning off system power. this failsafe feature prevents a user from turning on the device when the circuits driving the ? k ? i ? l ? l input do not respond within 512ms after enable has been asserted. see figure 12. p turns off system power during normal operation once the system has powered on and is operating normally, the p can turn off power by asserting the ? k ? i ? l ? l input low. see figure 13. dual function battery supervisor the LTC2953 provides two comparators for battery monitoring: an uncommitted power fail comparator and a latched low battery comparator with p interrupt. the application shown in figure 14 monitors a 2 cell li-ion battery stack. power fail comparator this comparator provides real time threshold information and can serve as the ? rst warning of a decaying battery or supply. the ? p ? f ? o output is driven low when the pfi input voltage drops below its falling threshold (0.5v) and is high impedance when pfi rises above its rising threshold (0.504v). the low leakage, high voltage pfi input (10na, maximum) allows the use of large valued external resistors, which lowers system current consumption. uvlo comparator the under voltage lockout comparator performs three functions: a) interrupts the p when a supply glitch drives the uvlo voltage below its falling threshold (0.5v) for longer than 32ms, followed by b) forces system power off when the uvlo voltage falls below its falling threshold (0.5v) for t pd, min + t pdt , c) locks out the enable (prevents system power on) output if uvlo voltage is below its fall- ing threshold (0.5v) during system power on. see figures 15a and 15b. the low leakage (10na, maximum), high voltage uvlo input allows the use of large valued external resistors. see figure 14. t db, on t kill, on blank pb kill en (LTC2953-1) 2953 f12 pb, uvlo and kill ignored system fails to set kill high turn on aborted t kill(pd) kill en (LTC2953-1) 2953 f13 system sets kill low system power off figure 12. aborted power on sequence, ? k ? i ? l ? l remaining low aborts power on sequence figure 13. p turns off system power
LTC2953 15 2953f applications information 2953 f14 LTC2953-1 + + + 0.5v 0.5v r14 2150k r13 23.2k r12 196k v th = 5.4v v th = 6.04v uvlo comparator power fail comparator pfo pfi uvlo en int v in 8.4v debounce and delay debounce 50mv 4mv which input initiated power down: ? p ? b or uvlo? the circuit in figure 14 determines whether a power down was initiated by a user pressing the push button or by a battery drooping too low. if both ? i ? n ? t and ? p ? f ? o outputs are low, then a low battery condition initiated a power down. pfi and uvlo thresholds the circuit depicted in figure 14 uses one resistive divider network for both power fail and low battery comparators. the power fail comparator trips at a higher battery voltage than the low battery comparator, thus providing a battery warning before a power down sequence is initiated. due to the low offset architecture of the comparators, the uvlo and ? p ? f ? i thresholds can be set to as close as 5mv apart. the trip thresholds of the circuit of figure 14 are 6.04v and 5.40v for the power fail and low battery (uvlo) comparators, respectively. push button lockout the LTC2953 provides a push button lock out feature that prevents a user from turning on a system with a dead battery. the push button input is ignored when the uvlo input voltage is less than the falling threshold (0.5v). see figure 15b. t db, off t int, min uvlo int 2953 f15a 0.5v 0.55v supply glitch t db, off t pd, min + t pdt uvlo en int 2953 f15b 0.5v low supply locks out enable low supply condition figure 14. dual function battery comparators figure 15a. supply glitch generates p interrupt figure 15b. low supply initiates system power down and locks out enable
LTC2953 16 2953f typical applications push button buffer the circuit of figure 16 shows the power fail comparator sensing the push button input. the ? p ? f ? o output toggles each time the push button crosses 0.5v. this application provides an early warning of push button activity. disconnect input resistive divider to save power in order to prolong battery life when system power has been turned off, the LTC2953-2 power fail comparator can be used to disconnect the external battery monitor resistive divider. the circuit in figure 18 connects ? p ? f ? i to ? e ? n and ? p ? f ? o to the bottom end of the resistive divider. pfo 2953 f16 pfi pb 0.5v on/off + on/off en v in LTC2953-2 2953 f17 pb r5 100k r9 100k 12v to load power path switching the high voltage ? e ? n output of the LTC2953-2 is designed to switch on/off an external power pfet. this allows a user to connect/disconnect a power supply (or battery) to its load by toggling the ? p ? b pin. figure 17 shows the LTC2953-2 in a 12v wall adapter application. en v in pfi LTC2953-2 2953 f18 uvlo pfo r5 100k r14 1070k r12 110k r9 100k 8.4v 0.5v + when the user presses the push button to turn on system power ( ? e ? n low), the output of the power fail comparator asserts ? p ? f ? o low. the low battery external resistive divider is thus enabled to monitor the input supply. if the voltage on the uvlo input falls to less than 0.5v, a system power down sequence is initiated. note that the ir drop across the internal nfet is typically less than 0.2mv when the uvlo pin voltage is 0.5v. once system power has been turned off ( ? e ? n high), the external resistive divider is disconnected and thus con- sumes zero dc current. figure 16. push button buffer figure 17. power path switching figure 18. disconnect input resistive divider to save power
LTC2953 17 2953f typical applications push button controlled p reset the circuit of figure 19 can be used to keep a p in reset for 200ms after the push button has enabled system power. after system power has stabilized, the voltage monitor input continues to monitor the supply at the load end. on/off en v in vm rst LTC2953-2 r3 499k r2 100k 2953 f19 pb vm rst pb r5 100k r9 100k r11 510k 3.3v to load 200ms 0.5v on/off en v in vm rst LTC2953-2 dc/dc #1 r3 866k r2 200k 2953 f20 pfi pfo pb r5 100k r9 100k dc/dc #2 r15 604k r16 200k shdn shdn v out v out v in v in v3 1.8v v2 2.5v v1 3.3v v th = 2.66v v th = 2.01v 3.3v push button controlled supply sequencing the circuit in figure 20 uses the LTC2953-2 to sequence 3 supply rails. power on sequencing begins by pressing the push button for 32ms. this asserts the ? e ? n output low, which turns on the v1 supply. 200ms after v1 reaches 80% of its ? nal value (2.66v), the v2 supply is enabled. when the v2 dc voltage reaches 80% of its ? nal value (2v), the v3 supply is enabled. note that there is no internal delay from the ? p ? f ? i input to the ? p ? f ? o output and so v3 is enabled at the same time v2 rises above 2v. a power down supply sequence begins when any of these inputs is asserted: ? p ? b , uvlo or ? k ? i ? l ? l . when ? e ? n pulls up to v in , v1 disconnects ? rst. when v1 decays to 2.66v, v2 is immediately disabled (there is no 200ms delay from vm to ? r ? s ? t during power down). when v2 decays to 2v, v3 is immediately disabled. see figure 21 timing diagram. 32ms 200ms pb v1 en 2953 f21 v2 v3 power on power off 80% 80% 80% 80% figure 19. push button controlled p reset figure 21. push button controlled supply sequence timing figure 20. push button controlled supply sequencing
LTC2953 18 2953f typical applications dual supply monitor with p reset the circuit of figure 22 monitors two supplies and provides a p reset. when either the ? p ? f ? i or the vm input voltage falls below its threshold (0.5v), the ? r ? s ? t output is asserted low. ? r ? s ? t remains low for 200ms after both inputs rise above 0.5v. the low leakage ? p ? f ? o output allows for large valued external resistors. reverse battery protection to protect the LTC2953 from a reverse battery connec- tion, place a 1k resistor (r8) in series with the v in pin. see figure 23. 2953 f22 LTC2953 + + 0.5v 0.5v rst rst pfi vm pfo p v2 v1 v in v out on/off en v in LTC2953-1 lt1761 shdn 8.4v r5 910k 2953 f23 pb + r8 1k figure 22. dual supply monitor with p reset figure 23. reverse battery protection using r8 operation with supply transients over 40v the application circuit of figure 24 operates from a 24v nominal supply, but can withstand supply transients as high as 40v. the high voltage ? e ? n output of the LTC2953-2 has an ab- solute maximum rating of 50v, which makes it suitable for driving the gate of the external power pfet. the external 30v zener diode (z1) and the 10k current limiting resistor (rz) protect the v in supply pin of the LTC2953-2. note that under normal 24v operation, the external zener diode does not conduct any current. the voltage drop across rz should be kept below 1v. z2 should have a breakdown voltage smaller than the pfets gate-to-source breakdown voltage. on/off en v in LTC2953-2 2953 f24 pb r5 100k rz 10k r9 100k 24v nominal, 40v transients fds4685 si2319ds nds9407 10v z2 bzx84c10 30v z1 bzx84c30 50v abs max 1 f 50v figure 24. operation with 40v supply transients power path controller with low battery detect the application in figure 25 uses the push button to completely disconnect the load from the battery. if the battery voltage falls below the user speci? ed threshold, the push button is prevented from turning on system power (asserting the enable output).
LTC2953 19 2953f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description dd package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1725 rev a) 3.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.65 0.10 0.75 0.05 r = 0.115 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dd12) dfn 0106 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.23 0.05 0.25 0.05 2.25 ref 2.38 0.05 1.65 0.05 2.10 0.05 0.70 0.05 3.50 0.05 package outline pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc 0.45 bsc
LTC2953 20 2953f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0607 ? printed in usa related parts typical application part number description comments ltc2900 programmable quad supply monitor adjustable reset, 10-lead msop and 3mm 3mm dfn packages ltc2904/ltc2905 pin-programmable dual supply monitors adjustable reset and tolerance, 8-lead sot-23 and 3mm 2mm dfn packages ltc2909 precision tripple/dual input uv, ov and negative voltage monitor 6.5v shunt regulator for high voltage operation ltc2912 single uv/ov monitor 3mm 2mm dfn, 8-pin thinsot packages ltc2950/ltc2951 push button on/off controllers high voltage, low power push button controller ltc2952 push button power path controller with supervisor automatic low loss switchover between dc sources ltc2954 push button on/off controller with p interrupt allow controlled software system shutdown ltc4055 usb power controller and li-ion charger automatic switchover, charges 1-cell li-ion batteries ltc4411 2.6a low loss ideal diode in thinsot no external mosfet, automatic switching between dc sources ltc4412hv powerpath controller in thinsot ef? cient diode-oring, automatic switching between dc sources, 3v to 36v v in v out on/off en v in vm rst pfo int kill rst pfo int kill LTC2953-2 pdt dc/dc shdn system logic 8.4v 3.3v r3 499k r11 100k r10 100k r1 100k r2 100k t pdt = 6.4 seconds 2953 f25 1 f pb gnd pfi uvlo r13 23.2k r12 196k r5 100k r14 2150k r9 100k fdn360p + figure 25. powerpath controller with low battery detect

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