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mixed-signal front end for broadband applications AD9878 features low cost 3.3 v cmos mxfe? f o r broadband applications do csis, euro -do c sis, dvb , davic compliant 232 mh z q u adr a ture digital u p converter 12-bit dir e ct if dac ( t xda c +? ) up to 65 mh z carrier freq uenc y d d s programmable sampling clock rates analog tx output le vel adjust dual 12-bit, 29 msps direct if adcs with v i deo clamp input 10-bit, 29 msp s sampling ad c 8-bit sigma-d el ta auxili ary da c direct interfac e to ad8 321/a d 8323 or ad83 22/ad8 3 27 pg a cable d r iver applic ati o ns cable set-top boxes cable and wire less modems func tio n a l block di agram 0327 7- 0 - 00 1 ? i q 12 tx d a ta - ? _o ut ca i n t mc l k os c i n rx 10 rx 12 b vi d e o rx 12 a cl am p l evel tx spo r t i f 1 0 [4 :0 ] i f 1 2 [ 1 1: 0] f l a g [2 :1 ] tx 16 dd s si n c ?1 - ? 4 10 3 12 12 mu x ad c ad c ad c mu x mu x mu x dac co nt r o l r e g i s t e rs pl l f i gur e 1 . f u nctio n al bl oc k dia g r a m general description the AD9878 is a sin g le-s u p p l y ca b l e m o dem/s e t-t o p bo x m i x e d - s i g n a l f r on t e n d. t h e d e v i c e c o n t a i ns a t r ans m i t p a t h i n te r p ol a t i o n f i lte r , a c o m p l e te qu a d r a t u re di g i t a l up c o n v e r te r , a n d tra n smi t d a c . t h e r e ce i v e pa th co n t a i n s d u al 12-b i t a d cs a nd a 10 -b i t ad c. a l l in ter n a l ly r e q u ir e d clo c ks a nd an o u tp u t sys t em clo c k a r e g e n e r a t e d b y t h e pll f r o m a s i n g le cr ys t a l o s c i l l a t or or cl o c k i n put . the t r a n sm i t p a t h in t e r p ola t ion f i l t er p r o v ides an u p s a m p l i n g fac t o r o f 16 wi th a n o u t p u t sig n al ban d wid t h u p t o 5.8 mh z. c a r r i er f r eq uen c ies u p t o 65 mh z wi th 26 b i ts o f f r eq uen c y t u ni n g r e s o l u t i on can b e ge n e r a te d b y t h e d i r e c t dig i t a l syn t h e sizer (d ds). the tra n s m i t d a c r e s o l u tio n is 12 b i ts and ca n r u n a t s a m p lin g ra t e s as hig h as 232 ms ps. analog o u t p u t s c alin g f r o m 0 db t o 7.5 db in 0. 5 db s t eps is a v aila b l e t o pre s e r ve snr w h e n re d u c e d out p ut l e vel s are re qu i r e d . the 12- b i t a d cs p r o v ide excel l en t unders a m plin g p e r f o r ma n c e , al lo win g this de vice t o de li ver bet t e r tha n 10 en o b s wi th if in p u ts u p t o 70 mh z. the 12-b i t if ad cs can s a m p l e a t r a te s up to 2 9 m h z , a l l o w i ng t h e m to pro c e s s wideb a n d sig n a l s. the AD9878 inc l udes a p r og ra mma b l e sig m a-de l t a d a c, whic h ca n be us e d t o c o n t r o l a n ext e r n al co m p on en t suc h as a va r i a b l e ga in am plif ier ( v ga) o r a v o l t age co n t r o l l e d t u n e r . the AD9878 als o in t e g r a t es a ca p o r t tha t enab les a h o s t p r o c es s o r t o in ter f ace wi th t h e ad8321/ad83 23 o r ad8322/ad83 27/ad8328 p r o g ra mma b l e ga in a m p l if ier (pga) ca b l e dr i v ers vi a t h e mxfe s e r i a l p o r t (s po r t ). the AD9878 is a v a i la b l e in a 10 0-lead l q fp p a c k a g e . the AD9878 is s p ecif ied o v er th e exten d ed ind u s t r i a l (C40c t o +85 c) t e m p era t ur e ra n g e . rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed .
AD9878 table of conte n ts s p ecifi c a t i o ns ........................................................................... 3 abso l u te m a ximu m r a tin g s ............................................. 6 d e finiti ons o f s p ecifi c a t i o ns ......................................... 7 t y pi cal p e r f o r man c e c h ar a c teris t i c s ................... 8 regis t er b i t d e finiti ons ................................................... 11 s e ri al i n te r f a c e fo r regis t e r c o ntr o l ................. 15 gener a l oper a t i o n o f the s e ri al i n te rf a c e ... 15 ins t r u c t i o n by te .............................................................. 15 s e ri al i n te r f a c e po r t p i n d e scrip t i o n ............... 15 ms b/ls b tr a n s f ers ............................................................. 16 n o tes o n s e ri al po r t o p er a t i o n ............................. 16 theo r y o f op er a t i o n .......................................................... 17 tr a n s m i t p a th ..................................................................... 18 inte rpo l a t i o n fil t er ..................................................... 18 d i gi t a l upc o nver ter . .................................................... 19 cl o c k a n d oscill a t o r cir c ui tr y ........................... 21 p r o g r a mma b l e cl o c k o u tp ut refc l k ................ 22 res e t a n d tr ans m it p o wer - d o wn ......................... 23 receive p a th (rx) ................................................................ 24 pcb d e s i g n c o ns id er a t i o ns ........................................ 25 pin c o nf i g u r a t i o n a n d pin f u n c ti on d e scripti o ins . .......................................................................... 27 o u tli n e d i mens i o ns ............................................................ 34 o r d e rin g g u id e . ................................................................. 34 revision history rev i s i o n 0: i n i t ial v e r s i o n rev. 0 | page 2 of 3 6
AD9878 specifications table 1. elec tric al ch ar acter i s t ics (v as = 3.3 v 5%, v ds = 3.3 v 10%, f osci n = 27 mh z, f sy s c l k = 216 mh z, f mc l k = 54 mh z (m = 8), ad c clo c k der i v e d f r o m o s cin, r set = 4.02 k?, m a x. f i ne ga in, 75 ? d a c l o ad .) parameter temp test lev e l min typ max unit oscin and xta l charac teri s t ics frequency range duty c y cle input impedance mclk cycle to c y cle j i tter (f mclk derived from pl l) full 25oc 25oc 25oc ii ii iii iii 3 35 50 100||3 6 29 65 mhz % m?||pf ps rms tx dac char ac teris t ics maximum sample rate resolution full-scale output current gain error (usin g internal reference) offset error reference volta g e (refio level) differential non l inearity (dnl) integral nonlinearity (in l ) output capacitance phase noise @ 1 khz offset, 42 mhz carrier output voltage compliance range wideband sfdr 5 mhz analog out, i ou t = 10 ma 65 mhz analog out, i out = 10 m a narrow - band sfdr ( 1 mhz window ) 5 mhz analog out, i ou t = 10 ma 65 mhz analog out, i out = 10 m a full n/a full full 25c 25c 25c 25c 25c 25c full full full full full ii n/a ii ii iii iii iii iii iii iii ii i i i i 232 4 C2.5 C0.5 62.4 50.3 71 61 12 10 C1 1.0 1.23 2.5 8 5 C110 68 53.5 74 64 20 +2.5 +1.5 mhz bits ma % fs % fs v lsb lsb pf dbc/ hz v db db db db tx modulator charac teris t i c s i/q offset pass-band amplitude ripple (f < f iqclk /8) pass-band amplitude ripple (f < f iqclk /4) stop-band resp onse ( f > f iqclk 3/4) full full full full ii ii ii ii 50 55 0.1 0.5 C63 db db db db t x g a i n cont rol gain step size gain step error settling time, 1 % (full-scale step) 25c 25c 25c iii iii iii 0.5 <0.05 1.8 db db s 10-bit adc ch a r acteristics resolution maximum conv ersion rate pipeline delay analog input input voltage range differential input impedance full power ba nd wid t h dynamic performance (f = 5 mhz) signal-to-nois e and distortion (sinad) effective numb er of bits (enob) t o tal harmonic distortion (t hd) spurious-free d y namic range (sfdr) reference voltage error, reft10 Crefb10 (1.0 v) n/a full n/a full 25c 25c full full full full full n/a ii n/a ii iii iii i i i i i 29 57.6 9.2 65.7 10 4.5 2 4||2 90 59.7 9.6 C71.1 72.4 4 C63.6 200 bits mhz adc cycles vppd k?||pf mhz db bits db db mv rev. 0 | page 3 of 3 6
AD9878 parameter temp test lev e l min typ max unit dynamic performance (f 50 mhz) signal-to-nois e and distortion (sinad) effective numb er of bits (enob) t o tal harmonic distortion (t hd) spurious-free d y namic range (sfdr) full full full full i i i i 54.8 8.8 56.9 57.8 9.3 C63.3 63.7 C56.9 db bits db db 12-bit adc ch a r acteristics resolution maximum conv ersion rate pipeline delay analog input input voltage range differential input impedance aperture delay aperture uncertainty ( itter) full power ba nd wid t h input referred noise reference voltage error, reft12 Crefb12 (1 v) dynamic performance (a in C0. 5 dbfs, f 5 mhz) adc sample cl ock oscin signal-to-nois e and distortion (sinad) effective numb er of bits (enobs) signal-to-noise ratio (snr ) t o tal harmonic distortion (t hd) spurious-free d y namic range (sfdr) adc sample cl ock pll signal-to-nois e and distortion (sinad) effective numb er of bits (enobs) signal-to-noise ratio (snr ) t o tal harmonic distortion (t hd) spurious-free d y namic range (sfdr) dynamic performance (a in C0. 5 dbfs, f 50 mhz) adc sample cl ock oscin signal-to-nois e and distortion (sinad) effective numb er of bits (enob) signal-to-noise ratio (snr ) t o tal harmonic distortion (t hd) spurious-free d y namic range (sfdr) differential phase differential gain n/a full n/a full 25c 25c 25c 25c 25c full full full full full full full full full full full full full full full full 25c 25c n/a ii n/a iii iii iii iii iii iii i i i i i i ii ii ii ii ii ii ii ii ii ii iii iii 29 C200 61.0 9.8 64.2 62.8 60.4 9.74 62.4 62.7 59.4 9.5 61.6 62.5 12 5.5 2 42 2.0 1.2 85 75 16 67 10.8 66 C72.7 74.6 64.4 10.4 65.1 C72.7 74.6 62.9 10.1 63.7 C71.7 72 0.1 1 +200 C61.7 C61.8 C61.5 bits mhz adc cycles vppd kpf ns ps rms mhz v mv db bits db db db db bits db db db db bits db db db degrees lsb video adc p e r f ormance (f 5 mhz) adc sample cl ock oscin signal-to-nois e and distortion (sinad) signal-to-noise ratio (snr ) t o tal harmonic distortion (t hd) spurious-free d y namic range (sfdr) full full full full ii ii ii ii 46.7 54.3 45.9 53 63.2 C50.2 50 C45.9 db bits db db rev. 0 page 4 of 3 6
AD9878 rev. 0 | page 5 of 36 parameter temp test level min typ max unit channel-to-channel isolation tx dac-to-adc isolation (5 mhz analog output) isolation between tx and 10-bit adc isolation between tx and 12-bit adcs adc-to-adc isolation (a in = C0.5 dbfs, f = 5 mhz) isolation between if10 and if12a/b isolation between if12a and if12b 25c 25c 25c 25c iii iii iii iii >60 >80 >85 >85 db db db db timing characteristics (10 pf load) wake-up time minimum reset pulsewidth low (t rl ) digital output rise/fall time tx/rx interface mclk frequency (f mclk ) txsync/txiq setup time (t su ) txsync/txiq hold time (t hd ) mclk rising edge to rxsync valid delay (t md ) oscout rising or falling edge to rxsync valid delay (t od ) oscout edge to mclk falling edge (t ee ) n/a n/a full full full full full full full n/a n/a ii ii ii ii ii ii ii 5 2.8 3 3 0 t osc /4 C 2.0 C1.0 200 4 66 1.0 t osc /4 + 3.0 +1.0 t mclk cycles t mclk cycles ns mhz ns ns ns ns ns serial control bus maximum sclk frequency (f sclk ) minimum clock pulsewidth high (t pwh ) minimum clock pulsewidth low (t pwl ) maximum clock rise/fall time minimum data/chip-select setup time (t ds ) minimum data hold time (t dh ) maximum data valid time (t dv ) full full full full full full full ii ii ii ii ii ii ii 30 30 25 0 15 1 30 mhz ns ns s ns ns ns cmos logic inputs logic 1 voltage logic 0 voltage logic 1 current logic 0 current input capacitance 25c 25c 25c 25c 25c ii ii ii ii iii v drvdd C 0.7 3 0.4 12 12 v v a a pf cmos logic outputs (1 ma load) logic 1 voltage logic 0 voltage 25c 25c ii ii v drvdd C 0.6 0.4 v v power supply supply current, i s (full operation) analog supply current i as digital supply current i ds supply current, i s standby ( pwrdn pin active) full power-down (register 02 = 0xff) power-down tx path (register 02 = 0x60) power-down if12 rx paths (register 02 = 0x1b) power supply rejection (differential signal) tx dac 10-bit adc 12-bit adc 25c 25c 25c 25c 25c 25c 25c 25c 25c 25c ii iii iii ii iii iii iii iii iii iii 184 105 79 46 46 124 131 <0.25 <0.0001 <0.0004 204 115 89 53 52 159 ma ma ma ma ma ma ma % fs % fs % fs
AD9878 absolute maximum ratings table 2. p a r a m e t e r r a t i n g power supply (v avdd , v dvdd , v drvdd ) 3 . 9 v digital output c u rrent 5 ma digital inputs C0.3 v to v drvdd + 0.3 v analog inputs C0.3 v to v avdd + 0.3 v operating temperature C40c to +85c maximum junction temperature 150c storage temperature C65c to +150c lead temperature (soldering 10 sec) 300c a b s o l u te max i m u m r a t i n g s a r e limi t i n g va l u e s , to b e a p plie d indivi d u a l ly , and b e yo nd w h ich t h e s e r v ice a b i li ty o f t h e cir c ui t m a y b e i m pa i r e d . f u n c ti o n al o p era b ili t y un d e r a n y o f th es e co ndi t i on s is n o t n e cess a r i l y im plie d . e x p o sur e t o a b s o l u t e m a xi m u m ra tin g co n d i ti o n s f o r e x t e n d ed pe ri od s o f ti m e m a y af fe c t d e v i c e rel i a b i l it y . explanation of test levels i. devices a r e 1 00% p r o d uc tion t e s t e d a t 25c and gua r an t e e d b y desig n an d cha r ac ter i z a t i o n test in g fo r i n d u st r i a l o p er a t in g t e m p era t ur e ra ng e (C40c t o +8 5c). ii. p a ra m e t e r is gua r a n tee d b y desig n an d/o r c h a r ac t e r i za tio n te st i n g . iii. p a ra m e t e r is a typ i cal val u e o n l y . n/a. t e st le ve l def i ni tion is n o t a p p l icab le . thermal c h aracteristics ther ma l resist a n c e : 100-l e ad l q fp : ja = 40.5c/w rev. 0 | page 6 of 3 6
AD9878 definitions of specifications di f f er en t i a l n o n l i n e a r i ty er r o r (d nl, n o mi s s i n g c o des) an ide a l con v er t e r exhi b i ts c o de t r a n si t i o n s t h a t a r e exac t l y 1 ls b a p a r t. dn l is t h e d e v i a t ion f r o m t h is ide a l va l u e . g u a r an t e ed n o mis s in g co des to 10-b i t r e s o l u tio n in dica t e s tha t al l 1,024 co des, r e s p ec ti v e l y , m u s t b e p r es en t o v er al l o p era t in g ra n g es. i n teg r a l n o n l i n e a r i ty er r o r ( i n l ) li n e a r i t y e r r o r r e f e r s t o th e devia t i o n o f ea ch in d i v i d u al code f r o m a line dr a w n f r o m nega t i ve f u l l s c a l e t h ro ug h p o si t i ve f u l l s c ale . th e p o in t us ed as n e g a ti ve f u l l s c ale o c c u rs ? ls b bef o r e th e f i r s t co d e tra n si ti o n . p o si ti v e full scale i s d e f i n e d a s a lev e l 1? l s b b e y o n d th e la s t cod e tra n si ti o n . th e de vi a t i o n i s m e as ur ed f r o m th e middle o f eac h p a r t ic u l a r co de t o the tr ue st r a ig h t l i ne. p h as e n o i s e sin g le-sideb an d phas e n o is e p o w e r is sp e c if ie d r e la t i v e t o t h e ca r r i er (db c /h z ) a t a g i ve n f r e q uen c y o f fs et (1 khz) f r o m t h e ca r r i er . p h as e no is e can b e m e as ur e d dir e c t l y i n sin g le- t on e tra n sm i t m o d e w i t h a s p ectr um a n al yz e r th a t s u p p o r t s n o i s e ma rk er m e as ur em e n ts. i t de t e c t s t h e re l a t i v e p o w e r b e tw e e n t h e ca r r i er a n d t h e o f fs et (1 kh z) si deb a n d n o is e and t a k e s t h e re s o lut i on b a n d w i d t h ( r bw ) i n t o a c c o u n t by s u bt r a c t i n g 1 0 log(rb w). i t als o adds a co r r ec tio n fac t o r tha t c o m p en s a t e s f o r th e im p l em en t a ti o n o f th e r e so l u ti o n ba n d w id th , log d i s p la y , a nd dete c t o r ch a r ac ter i st ic. ou t p u t c o m p lia n c e r a n g e the ra n g e o f al lo wa b l e v o l t a g e a t t h e o u t p ut o f a c u r r en t-o u t p ut d a c. opera t i o n b e y o n d t h e ma xi m u m co m p lia n ce li mi ts ma y c a u s e e i t h e r output st age s a tu r a t i on or bre a kd o w n , re su lt i n g i n non l i n e a r p e r f or m a nc e. s p ur io us-f r ee d y namic r a ng e (s f d r) the dif f er ence , i n db , b e tw e e n t h e r m s am pli t u d e o f t h e d a c s o u t p u t sig n al (o r ad c s in p u t sig n al) a nd t h e p e ak s p ur io us sig n al o v er th e sp e c if ie d ban d wid t h ( n yq uis t ban d wid t h, unles s ot he r w i s e note d ) . p i p e line d e la y (l a t enc y ) the n u m b er o f clo c k c y cles b e t w e e n con v ersion ini t i a t i on and th e as soci a t e d o u t p u t da t a be i n g m a d e a v a i la b l e . of fs et er r o r the f i rs t co de tra n si tion sh o u ld o c c u r a t an a n al og val u e ? ls b a b o v e n e ga t i v e f u l l s c ale . of fs et er r o r is def i n e d as t h e de v i a t io n o f th e a c t u al tra n si ti o n f r o m tha t po i n t . gain er r o r the f i rs t co de tra n si tion sh o u ld o c c u r a t an a n al og val u e ? ls b a b o v e n e ga t i v e f u l l s c ale . th e l a st tra n si tion sh ou ld o c c u r fo r a n a n alog val u e 1? ls b b e lo w th e n o minal f u l l s c a l e . ga in er r o r is t h e de v i a t ion o f t h e ac t u al dif f er en ce b e tw e e n f i rs t an d las t co de t r a n si t i o n s a nd t h e id e a l dif f er e n ce b e tw e e n f i r s t an d last co de tra n si ti o n s. ap e r t u r e d e l a y the a p er t u r e dela y is a m e as ur e o f t h e sam p le- a nd-h o ld am plif ier (s h a ) p e r f o r ma n c e t h a t sp e c if ies t h e t i me dela y b e tw e e n t h e r i sin g e d g e o f t h e s a m p ling clo c k i n p u t t o w h en t h e in p u t sig n a l is he ld fo r co n v ersi o n . ap e r t u r e un c e r t a i n t y ( j i t t e r ) a p er t u r e ji t t er is t h e va r i a t ion i n a p er t u r e dela y fo r s u cces si v e s a m p les and is ma nifeste d as no is e o n t h e i n p u t to t h e ad c. inp u t r e f e r r e d no i s e the r m s o u t p u t n o is e is m e asure d usin g hist og ra m t e chniq u es. the a d c o u t p ut co des st anda rd d e v i a t ion is ca lc u l a t e d i n ls b , a nd con v er t e d to a n e q ui v a len t v o l t a g e . t h is r e su l t s in a n o is e f i g u re t h a t c a n b e d i re c t ly re f e r r e d to t h e i n put of t h e m x f e . si g n a l - t o - n o i s e a n d d i s t or t i on ( s / n + d , si n a d ) r a t i o s/n+d is t h e r a t i o o f t h e r m s val u e o f t h e m e asur e d in pu t sig n al t o th e rm s s u m o f all o t h e r s p ec tral co m p o n en ts be lo w t h e n y q u ist f r e q ue nc y , in cl udi n g har m o n ics b u t excl udin g dc. the val u e fo r s/n+ d is exp r es s e d i n de c i b e ls. ef fe c t ive n u mb er o f bits (eno b) f o r a sin e w a ve, s i n a d can b e ex p r ess e d i n ter m s o f t h e n u m b er o f b i ts. u s in g t h e fol l o w in g fo r m u l a , i t is p o s s i b le t o g e t a me as ur e o f p e r f o r ma n c e exp r es s e d as n , t h e e f fe c t i v e n u m b er of bit s : n = ( si n a d C 1.76) db /6.02 th us, t h e ef fe c t i v e n u m b e r o f b i ts f o r a de vice f o r sin e wa v e in p u ts a t a g i v e n in p u t f r eq uen c y ca n b e calc u l a t e d direc t l y f r o m i t s meas ur ed s i n a d . s i gna l -t o-n o ise r a tio ( s nr) s n r is t h e r a t i o o f t h e r m s val u e o f t h e m e as ur e d i n p u t sig n a l to th e rm s s u m o f all o t h e r s p ectral co m p o n en t s b e lo w th e n y q u i s t f r e q uen c y , excl udin g ha r m o n ics a nd dc. t h e va lue fo r s n r is exp r es s e d i n de ci b e ls. t o t a l h a r m on i c d i st or t i on ( t h d ) t h d i s t h e ra tio o f th e rm s s u m o f th e f i r s t six h a rm o n i c co m p on e n ts t o t h e r m s val u e o f t h e m e as ur e d in p u t sig n a l , a n d is exp r es s e d as a p e r c en t a g e o r i n de c i b e ls. p o wer su pply rej e c t i o n p o we r su p p ly re j e c t ion sp e c if ie s t h e c o n v e r te r s max i m u m f u l l - s c ale cha n ge w h en t h e s u p p lie s a r e va r i e d f r o m n o minal t o mini m u m an d max i m u m sp e c i f ie d vol t a g es. cha n n e l-t o -cha nn e l i s ola t io n (cr o ss ta lk) i n an ide a l m u l t ic ha nn e l syst em, th e sig n al in on e c h a n n e l wil l not i n f l u e nc e t h e s i g n a l l e vel of anot he r ch an n e l. t h e c h an ne l - t o -cha n n e l is ol a t io n sp e c if ic a t ion is a m e a s ur e of t h e cha n ge t h a t o c c u rs i n a g r o u n d e d cha n n e l as a f u l l - s ca l e sig n a l is a p plie d to an o t h e r cha n nel. rev. 0 | page 7 of 3 6
AD9878 re page 8 of typical perf orm ance cha r acte ristics freuency mh m a gnitude db 8 8 9 8 7 77- - f i g u re 2. d u a l s i de band spec t r al plot , f c = 5 mh z, f = 1 m h z, r set = 10 k ? (i ou t = 4 ma ), r b w = 1 kh z frequec mhz m a gitude db 0 2 4 6 8 10 12 14 16 18 100 90 80 70 60 50 40 30 20 10 0 20 032 77- 0- 0 2 3 f i g u re 3. d u a l s i de band spec t r al plot , f c = 5 mh z, f = 1 m h z, r set = 4 k ? (i ou t = 1 0 ma), rbw= 1 k h z frequec mhz magitude db 55 57 59 61 63 65 67 69 70 73 100 90 80 70 60 50 40 30 20 10 0 75 032 77- 0- 0 2 4 f i g u re 4. d u a l s i de band spec t r al plot , f c = 65 m h z, f = 1 m h z, r set = 10 k ? (i ou t = 4 ma ), r b w = 1 kh z frequec mhz m a gitude db 55 57 59 61 63 65 67 69 71 73 100 90 80 70 60 50 40 30 20 10 0 75 032 77- 0- 0 2 5 f i g u re 5. d u a l s i de band spec t r al plot , f c = 65 m h z, f = 1 mh z, r set = 4 k ? (i ou t = 1 0 ma), rbw = 1 kh z frequec mhz m a gitude db 0 2 04 06 08 0 1 0 0 100 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 120 0 327 7- 0- 02 6 f i gure 6. s i ngl e s i d e band @ 6 5 m h z, r b w = 2 kh z, f c = 6 6 mh z, f = 1 mhz, r set = 10 k ? (i ou t = 4 m a ) frequec mhz m a gitude db 0 2 04 06 08 0 1 0 0 100 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 120 0 327 7- 0- 02 7 f i gure 7. s i ngl e s i d e band @ 6 5 m h z, r b w = 2 kh z, f c = 6 6 mh z, f = 1 mhz, r set = 4 k ? (i ou t = 10 m a )
AD9878 frequency mhz magnitude db 0 2 04 06 08 0 1 0 0 100 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 120 0 327 7- 0- 02 8 f i gure 8. s i ngl e s i d e band @ 4 2 m h z, r b w = 2 kh z ,f c = 4 3 mh z, f = 1 mhz, r set = 10 k ? (i ou t = 4 m a ) frequency mhz magnitude db 0 2 04 06 08 0 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 120 0 327 7- 0- 02 9 f i gure 9. s i ngl e s i d e band @ 4 2 m h z, r b w = 2 kh z, f c = 4 3 mh z, f = 1 mhz, r set = 4 k ? (i ou t = 10 m a ) frequency mhz magnitude db 0 2 04 06 08 0 1 0 0 100 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 120 0 327 7- 0- 03 0 f i gure 10. sing le si deband @ 5 mh z , r b w = 2 kh z, f c = 6 mh z, f = 1 mhz, r set = 10 k ? (i ou t = 4 m a ) frequec mhz magitude db 0 2 04 06 08 0 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 120 0 327 7- 0- 03 1 f i gure 11. sing le si deband @ 5 mh z , r b w = 2 kh z, f c = 6 mh z, f = 1 mhz, r set = 4 k ? (i ou t = 10 m a ) frequency mhz magnitude db 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 90 80 70 60 50 40 30 20 10 0 2.5 0 327 7- 0- 03 2 f i g u re 12. sing le si deband @ 6 5 m h z, r b w = 5 00 h z , f c = 66 m h z, f = 1 mhz, r set = 10 k ? (i ou t = 4 m a ) frequency mhz magnitude db 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 90 80 70 60 50 40 30 20 10 0 2.5 0 327 7- 0- 03 3 f i g u re 13. sing le si deband @ 6 5 m h z, r b w = 5 00 h z , f c = 66 m h z, f = 1 mhz, r set = 4 k ? (i ou t = 10 m a ) rev. 0 | page 9 of 3 6
AD9878 frequency ? mhz magnitude ? db ? 5 0 ? 40 ?30 ? 20 ?10 0 10 20 30 40 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 50 032 77- 0- 0 3 4 f i gure 14. sing le si deband @ 6 5 m h z, rbw = 5 0 h z , f c = 6 6 mh z, f = 1 mhz, r set = 10 k ? (i ou t = 4 m a ) magnitude ? db ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency ? mhz ? 2.5 ?2.0 ?1.5 ? 1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 327 7- 0- 03 5 f i gure 15. sing le si deband @ 6 5 m h z, rbw = 1 0 h z , f c = 6 6 mh z, f = 1 mhz, r set = 10 k ? (i ou t = 4 m a ) magnitude ? db ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency ? mhz 0 5 10 15 20 25 30 35 40 45 50 032 77- 0- 0 3 6 f i g u re 16. 1 6 - q a m @ 42 m h z spe c t r a l p l ot , r b w = 1 k h z magnitude ? db ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency ? mhz 0 5 10 15 20 25 30 35 40 45 50 032 77- 0- 0 3 7 f i gure 17. 1 6 - q am @ 5 m h z spec tr al plot, rb w = 1 kh z rev. 0 | page 10 of 36
AD9878 rev. 0 | page 11 of 36 register bit definitions t a ble 3 . a d 98 78 reg i ster map sdio b i d i r e ct i o na l ls b f i r st reset os c i n m u lt i p li e r m [ 4:0] 0x 08 pl l lock de te ct m c lk d i vi de r r [ 5:0] 0x 00 po w e r d o w n pl l po w e r d o w n dac t x pow e r d o w n di g i ta l t x po w e r d o w n a d c 12a po w e r d o w n a d c 12b po w e r d o w n a dc1 0 pow e r d o w n re f e r e n c e a d c 12a po w e r d o w n re fe r e n c e a d c 12b 0x 00 v i deo i nput i n to a d c 12b fl a g 2 f l a g 1 fl a g 0 en a b l e 0x 00 f l a g 0 s i g m a -d el ta out put c o n t ro l w ord [ 7:0] 0x 00 0x 00 0x 00 v i deo i n put e nabl e 0x 00 a d c c l o cked di r e ct fr o m os cin rx po r t f a st e dge r a t e po w e r d o w n rx s y nc gen p o w e r-do w n r e ference adc1 0 se n d a d c 12a d a ta onl y s end adc1 2 b da ta onl y 0x 80 0x 00 0x 00 0x 00 ve r s i o n [ 3: 0 ] 0x 00 tx fre q u e n c y t u n i n g w o r d pr o f il e 1 l sbs [ 1 : 0 ] t x f r eq uency t un i n g w o r d pr o f il e 0 l sbs [ 1 : 0 ] 0x 00 da c f i n e g a i n c ont r o l [3:0] 0x 00 tx p a t h se l e c t pr o f il e 1 tx p a t h a d 8321/3 g a i n c ontro l m ode tx p a t h b y pass si nc ?1 filter tx p a t h sp e c t r a l invers i o n tx p a t h tra n s m i t s i ng l e t o ne 0x 00 t x p a th f r eque n cy t u n i ng w o rd p r of i l e 0 [ 9 : 2 ] 0x 00 t x p a th f r eque ncy t un i n g w o r d p rof i l e 0 [ 1 7 : 10] 0x 00 t x p a th f r eque ncy t un i n g w ord p rof i l e 0 [ 2 5 : 18] 0x 00 c abl e d r i ver a m p l i f i e r c oars e ga i n c o ntro l p r o f i l e 0 [ 7:4] f i ne ga i n c o ntro l p ro fi l e 0 [ 3:0 ] 0x 00 tx p a t h fre q u e n c y tu n i n g w o rd p r o f i l e 1 [ 9 : 2 ] 0x 00 t x p a th f r eque ncy t un i n g w ord p rof i l e 1 [ 1 7 : 10] 0x 00 t x p a th f r eque ncy t un i n g w ord p rof i l e 1 [ 2 5 : 18] 0x 00 c abl e d r i ver a m p l i f i e r c oars e ga i n c o ntro l p r o f i l e 1 [ 7:4] f i ne ga i n c o ntro l p ro fi l e 1 [ 3:0 ] 0x 00 address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default (hex) type read/write 00 01 02 03 04 05 06 clamp level for vidio input [6:0] 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 read/write read/write read/write read/write read/write read-only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write register 0ini t ializ a tio n bits 0 to 4: os cin multiplie r this r e g i s t er f i e l d is us e d t o p r o g ra m t h e o n -chi p m u l t i p lier ( p l l ) t h a t ge ne r a te s t h e ch i p s h i g h f r e q u e nc y s y ste m cl o c k , f sy s c l k . f o r ex am pl e, to m u l t i p ly t h e e x te r n a l c r y s t a l cl o c k f osci n b y 16 decimal , p r og ra m reg i s t er 0, b i ts 4:0 as 0x10. th e defa u l t val u e o f m is 0x08. v a lid en tr ies ra n g e f r o m 1 t o 31. w h en m is ch o s en e q ua l to 1, t h e pll is dis a b l e d and a l l i n ter n a l clo c ks a r e der i v e d dir e c t l y f r o m oscin. th e pll r e q u ir es 200 m c lk c y cl es to reg a in f r e q u e nc y l o ck af ter a chang e i n m , t h e cl o c k m u l t i p lier va l u e. af t e r t h e r e c a pt ur e t i m e o f t h e p ll, t h e fr e q u e n c y o f f sy s c l k is st a b le .
AD9878 rev. 0 | page 12 of 36 bit 5: reset writing a 1 to this bit resets the registers to their default values and restarts the chip. the reset bit always reads back 0. the bits in register 0 are not affected by this software reset. however, a low level at the reset pin would force all registers, including all bits in register 0, to their default state. bit 6: lsb first active high indicates spi serial port access of instruction byte and data registers is least significant bit (lsb) first. default low indicates most significant bit (msb) first format. bit 7: sdio bidirectional active high configures the serial port as a three signal port with the sdio pin used as a bidirectional input/output pin. default low indicates the serial port uses four signals with sdio configured as an input and sdo configured as an output. register 1clock configuration bits [5:0]: mclk divider. this register determines the output clock on the oscout pin. at default 0 (r = 0), oscout provides a buffered version of the oscin clock signal for other chips. the register can also be used to divide the chips master clock f mclk by r, where r is an integer number between 2 and 63. the generated reference clock on oscout pin can be used for external frequency controlled devices. bit 7: pll lock detect when this bit is set low, the oscout pin functions in its default mode and provides an output clock with frequency f mckl /r as described above. if this bit is set to 1, the oscout pin is configured to indicate whether the pll is locked to f oscin . in this mode the oscout pin should be low-pass filtered with an rc filter of 1.0 k? and 0.1 f. a high output on oscout indicates that the pll has achieved lock with f oscin . register 2power-down sections of the chip that are not used can be powered down when the corresponding bits are set high. this register has a default value of 0x00; all sections active. bit 0: power-down adc 12b voltage reference active high powers down the voltage reference circuit for adc12b. bit 1: power-down adc12a voltage reference active high powers down the voltage reference circuit for adc12a. bit 2: power-down adc10 active high powers down the 10-bit adc. bit 3: power-down adc12b active high powers down the adc12b. bit 4: power-down adc12a active high powers down the adc12a. bit 5: power-down tx active high powers down the digital transmit section of the chip, similar to the function of the pwrdn pin. bit 6: power-down dac tx active high powers down the dac. bit 7: power-down pll active high powers down the oscin multiplier. register 3flag control bit 0: flag 0 enable active high, the sdelta pin will maintain a fixed logic level determined directly by the msb of the sigma-delta control word of register 4. bit 1: flag 1 the logic level of this bit will be applied at the flag1 pin. bit 4: flag 2 the logic level of this bit will be applied at the flag2 pin. bit 5: video input into adc12b if the video input is enabled, setting this bit high sends the signal applied to the video in pin to the adc12b. otherwise, the signal applied to the video in pin is sent to the adc12a. register 4sigma-delta control word bits [7:0]: sigma-delta control word the sigma-delta control word is 8 bits wide and controls the duty cycle of the digital output on the sigdelt pin. changes to the sigma-delta control word take effect immediately for every register write. sigma-delta output control words have a default value of 0. the control words are in straight binary format with 0x00 corresponding to the bottom of scale or 0% duty cycle, and 0xff corresponding to the top of scale or near 100% duty cycle.
AD9878 rev. 0 | page 13 of 36 ffse e i bit 7: flag 0 (sigma-delta control word msb) when the flag 0 enable bit (register 3, bit 0) is set, the logic level of this bit will appear on the output of the sigdelt pin. register 07video input configuration bits [6:0]: clamp level control value the 7-bit clamp level control value is used to set an offset to the automatic clamp level control loop. the actual adc output will have a clamp level offset equal to 16 times the clamp level control value as shown: clamp level o t clamp l vel control value = (x)16 the default value for the clamp level control value is 0x20. this results in an adc output clamp level offset of 512 lsbs. the valid programming range for the clamp level control value is from 0x16 to 0x127. register 8adc clock configuration bit 0: send adc12b data only when this bit is set high, the device enters a nonmultiplexed mode and only the data from the adc12b will be sent to the if[11:0] digital output port. bit 1: send adc12a data only when this bit is set high, the device enters a nonmultiplexed mode and only the data from the adc12a will be sent to the if[11:0] digital output port. note: if both the send adc12b data only and send adc12a data only register bits are set high, the device will send both adc12a and adc12b data in multiplexed mode. bit 3: power-down adc10 voltage reference active high powers down the voltage reference circuit for adc10. bit 4: power down rxsync generator setting this bit to 1 powers down the 10-bit adcs sampling clock and makes the rxsync output pin stay low. it can be used for additional power saving on top of the power-down selections in register 2. bit 5: rx port fast edge rate setting this bit to 1 increases the output drive strength of all digital output pins except mclk, refclk, sigdelt, and flag[2:1]. these pins always have high output drive capability. bit 7: adc clocked directly from osc n when set high, the adc sampling clock is derived directly from the input clock at oscin. in this mode, the clock supplied to the oscin pin should originate from an external crystal or low jitter crystal oscillator. when this bit is low, the adc sampling clock is derived from the internal pll and the frequency of the clock is equal to f oscin m/8. register cdie revision bits [3:0]: version the die version of the chip can be read from this register. register dtx frequency tuning words lsbs this register accommodates the two least significant bits each for both of the frequency tuning words. see the description of the burst parameter below. register edac gain control this register allows the user to program the dac gain if the txgain control select bit 3 in register f is set to 0. bits [3:0] dac gain (db) 0000 0.0 (default) 0001 0.5 0010 1.0 0011 1.5 1110 7.0 1111 7.5 register ftx path configuration bit 0: single tone tx mode active high configures the AD9878 for single-tone applications (e.g., fsk). the AD9878 will supply a single frequency output as determined by the frequency tuning word selected by the active profile. in this mode, the txiq input data pins are ignored but should be tied to a valid logic voltage level. default value is 0 (inactive). bit 1: spectral inversion tx when set to 1, inverted modulation is performed: modulator_out = [ i cos ( t ) + q sin ( t )]. default is logic 0, non-inverted modulation: modulator_out = [ i cos ( t ) C q sin ( t )].
AD9878 rev. 0 | page 14 of 36 bit 2: bypass inv s nc tx filter i i active high, configures the AD9878 to bypass the sin(x)/x compensation filter. default value is 0 (inverse sinc filter enabled). bit 3: ca interface mode select this bit changes the manner in which transmit gain control is performed. typically either ad8321/ad8323 (default 0) or ad8322/ad8327 (1) variable gain cable amplifiers are programmed over the chips 3-wire ca interface. the tx gain control select changes the interpretation of the bits in registers 13, 17, 1b, and 1f. see the cable driver gain control section below. bit 5: profile select the AD9878 quadrature digital upconverter is capable of storing two preconfigured modulation modes called profiles. each profile defines a transmit frequency tuning word and cable driver amplifier gain (/dac gain) setting. the profile select bit or profile pin programs the current register profile to be used. the profile select bit should always be 0 if the profile pin is used to switch between profiles. using the profile select bit as a means of switching between different profiles requires the profile pin to be tied low. registers 10 through 17: burst parameter tx frequency tun ng words the frequency tuning word (ftw) determines the dds generated carrier frequency (f c ) and is formed via a concatenation of register addresses. the 26-bit ftw is spread over four register addresses. bit 25 is the msb and bit 0 is the lsb. the carrier frequency equation is given as: f c = ( ftw f sysclk )/2 26 where : f sysclk = m f oscin , and ftw < 0x2000 changes to ftw bytes take effect immediately. cable driver gain control the AD9878 has a 3-pin interface to the ad832x family of programmable gain cable driver amplifiers. this allows direct control of the cable drivers gain through the AD9878. in its default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (ca) interface. if bit 3 of register f is set high, bits [7:4] of registers 0x13 and 0x17 will determine the 8-bit word sent over the ca interface according to the table below: bits [7:4] ca interface transmit word 0000 0001 0010 0011 0100 0101 0110 0111 1000 0000 0000 (default) 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 in this mode the lower bits of registers 0x13 and 0x17 determine the fine gain setting of the dac output: bits [3:0] dac fine gain (db) 0000 0001 0010 0011 ... 1110 1111 0.0 (default) 0.5 1.0 1.5 ... 7.0 7.5 new data is automatically sent over the 3-wire ca interface (and dac gain adjust) whenever the value of the active gain control register changes or a new profile is selected. the default value is 0x00 (lowest gain). the formula for the combined output level calculation of AD9878 fine gain and ad8327 or ad8322 coarse gain is: v 8327 = v 9878(0) + ( fine )/2 + ( coa e ) C 19 rs rs se v 8322 = v 9878(0) + ( fine )/2 + ( coa e ) C 14 where: fine = decimal value of bits [3:0] coar = decimal value of bits [7:4] v 9878(0) : level at AD9878 output in dbmv for fine = 0. v 8327 : level at output of ad8327 in dbmv. v 8322 : level at output of ad8322 in dbmv.
AD9878 serial interface for register control the AD9878 s e r i al p o r t is a f l exi b le , sy n c hr ono u s s e r i al co mm unic a t io ns p o r t tha t al lo ws easy in t e r f ace t o ma n y ind u s t r y s t andar d micr o c o n tr ol lers a n d micr o p r o ces s o r s. the in t e r f ace a l lo ws r e ad/ w r i t e access t o a l l r e g i st ers t h a t co nf igur e th e AD9878. s i n g le o r m u l t i p le b y t e tra n sf ers a r e s u p p o r t e d . a l s o , t h e in t e r f ace can b e p r og ra mm e d t o r e ad w o r d s ei t h er ms b f i rs t o r ls b f i rs t. the AD9878 s s e r i al in ter f ace p o r t i/o ca n b e conf igur e d to h a ve on e b i d i r e c t io na l i/ o (s di o) p i n or tw o unidir e c t i onal i/o (s d i o / s d o) p i ns. general operation of the serial interface ther e a r e tw o phas es t o a comm unic a t ion c y cle w i t h t h e AD9878. p h as e 1 is th e in s t r u c t io n c y c l e , whic h is th e wr i t in g o f a n ins t r u c t io n b y t e in t o th e AD9878, co in ciden t wi th t h e f i rs t eig h t s c lk r i si n g e d ges. t h e inst r u c t io n b y t e pr o v ides t h e AD9878 s e r i al p o r t co n t r o l l er wi t h inf o r m a t ion r e ga r d in g t h e d a t a t r an sfer c y cle , w h ich is ph as e 2 o f t h e com m unic a t ion cy c l e . the p h as e 1 inst r u c t io n b y t e de f i n e s w h et h e r t h e up co mi n g da ta tran sf er is r e ad o r wr i t e , the n u m b er o f b y t e s in t h e da ta tra n sf e r , a n d t h e s t a r ti n g r e gi s t er a d d r e s s f o r th e f i r s t b y t e o f th e da ta tran sfer . th e f i rs t e i g h t s c lk r i sin g e d g e s o f e a c h co mm uni c a t io n c y cle a r e us e d t o wr i t e t h e i n s t r u c t io n b y t e i n t o th e AD9878. the eig h t r e ma i n in g scl k e d ges a r e fo r p h as e 2 o f t h e co mm uni c a t io n c y cle . p h as e 2 is t h e ac t u al da t a t r a n sfer betw een t h e AD9878 a nd the sys t em co n t r o l l er . p h as e 2 o f the co mm uni c a t io n c y cle is a t r a n sf er o f 1 t o 4 da t a b y t e s as det e r m i n e d b y t h e i n st r u c t io n b y t e . n o r m a l ly , usin g o n e m u l t i- b y t e t r a n sfer is t h e p r efer r e d m e t h o d . h o w e v e r , sin g le-b yt e da t a t r a n sfers a r e us ef u l t o r e d u ce c p u o v erh e ad w h e n r e g i s t er ac c e ss re qu ire s one b y te on ly . r e g i ste r s chang e im me d i a t ely up on w r it i n g to t h e l a st bit of e a ch t r ans f e r by te. instruction byte the inst r u c t io n b y t e co n t a i n s t h e fol l o w in g info r m a t io n: msb 17 1 6 1 5 1 4 1 3 1 2 1 1 lsb 10 r / w n 1 n 0 a 4 a 3 a 2 a 1 a 0 the r/ w b i t o f t h e i n s t r u c t io n b y t e det e r m i n es w h et her a r e ad o r a wr i t e da t a t r a n sfer wi l l o c c u r a f t e r t h e i n s t r u c t io n b y t e wr i t e. l o g i c hig h i n di ca tes a r e a d o p er a t io n. l o g i c lo w in di ca te s a wr i t e o p er a t ion. th e [n1: n0] b i ts det e r m i n e t h e n u m b er o f b y t e s t o be tra n sf e r r e d d u ri n g th e da ta tra n sf e r c y c l e . t h e b i t de co des a r e sh ow n in t a b l e 4. t h e t i ming d i a g r a m s a r e sh o w n in f i gur e 18 and f i gur e 19. table 4. n 1 n 0 desc rip t io n 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes the bi ts [a4: a0 ] det e r m ine w h i c h r e g i s t er is ac ces s e d d u r i n g th e da ta tra n sf e r po r t i o n o f th e co m m un ica t i o n s c y c l e . f o r m u l t i b y t e t r a n sfers, t h is addr es s is t h e st a r t i n g b y t e addr es s. the r e ma inin g reg i st er addr es s e s a r e g e n e r a t e d b y t h e AD9878. sclk instruction bit 7 instruction bit 6 t sclk t dh t pwl t pwh t ds sdio cs t ds 0 327 7- 0- 00 5 f i gure 18. t i m i ng d i agr a m fo r r e gis t er w r ite sclk sdio sdo cs data bit n data bit n t dv 0 327 7- 0- 00 6 f i gure 19. t i m i ng d i agr a m fo r r e gis t er r e ad serial interface port pin description sclks er ial c o c k . t h e s e r i a l clo c k p i n is us e d t o sy n c hr o n iz e da ta tran sf ers f r o m the AD9878 a nd t o r u n the s e r i al p o r t s t a t e machi n e. t h e m a x i m u m s c lk f r e q uen c y is 15 mh z. i n p u t d a t a t o th e AD9878 is s a m p le d o n t h e r i sin g edg e o f sclk. o u t p u t da ta c h a n g e s o n th e fallin g ed g e o f sc l k . l cs chi p s e lec t . a c t i v e lo w in put st a r ts an d g a t e s a co mm unic a t io n c y c l e . i t al l o ws m u l t i p le de vices t o s h a r e a co mm o n s e r i al p o r t b u s. the s d o an d s d i o p i n s g o t o a hig h im p e dan c e st a t e w h en cs is hig h . c h i p s e le c t sh ou ld s t a y lo w d u r i n g t h e en t i r e co mm u n ic a t ion c y cle . sdio s e r i l d a a i o . d a ta is al wa ys wr i t ten in t o the AD9878 o n t h is p i n. h o w e ver , t h is p i n c a n b e us e d as a b i d i r e c t io na l da t a lin e . t h e co nf ig ura t io n o f t h is pin is con t r o l l e d b y bi t 7 o f reg i st er 0. th e defa u l t is l o g i c 0, w h ich co nf ig ur es t h e s d i o p i n as u n idir e c t i o n a l . a t / t sd o s e r i a l d a a o u t . da ta i s r e a d f r o m th i s p i n f o r p r o t oco l s th a t use se pa ra t e li n e s f o r tra n sm i t ti n g a n d r e ce i v i n g d a ta . i n t h e cas e w h er e t h e AD9878 o p er a t es in a sin g le b i dir e c t io nal i/o m o de , th i s p i n do es n o t o u t p u t da ta a n d i s set to a h i gh im p e dan c e st a t e. rev. 0 | page 15 of 36
AD9878 rev. 0 | page 16 of 36 msb/ls b transfers the AD9878 s e r i al p o r t ca n s u p p o r t m o s t sig n if ica n t b i t (ms b ) f i rst o r le ast sig n if ican t b i t (lsb) f i rst da t a fo r m a t s (s e e f i gur e 20 a nd f i gur e 2 1 ). this f u n c tionali t y is con t r o l l ed b y th e l s b f i rst b i t i n reg i st er 0. th e def a u l t m o de is msb f i rst. w h en t h is b i t is s e t ac t i v e hig h , t h e a d 98 78 s e r i a l p o r t is in ls b f i rst fo r m a t . i n ls b f i rst m o de, t h e in st r u c t io n b y te a nd da t a b y tes m u st b e wr i t t e n f r o m t h e le ast sig n if ican t b i t t o t h e m o st sig n if ica n t b i t. i n ls b f i rst m o de , t h e s e r i a l p o r t in t e r n a l b y t e addr es s g e n e r a to r in cr e m en ts fo r e a ch b y t e o f t h e m u l t i b yt e co mm unic a t io n c y c l e . cs r/w n1 n0 a4 a3 a2 a1 a0 d7 n d6 n d2 0 d1 0 d0 0 d7 n d6 n d2 0 d1 0 d0 0 s cl k instruction cycle data transfer cycle sdio sdo 03 277 - 0 - 003 f i gure 20. s e ri al r e gis t er i n te r f ace tim i ng , msb f i rs t d0 0 d1 0 d2 0 d6 n d7 n s cl k instruction cycle data transfer cycle sdio sdo cs a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d6 n d7 n 032 77- 0- 0 0 4 f i gure 21. s e ri al r e gis t er i n te r f ace tim i ng , lsb f i rs t w h en this b i t is s e t def a u l t lo w , th e AD9878 s e r i al p o r t is in ms b f i rst fo r m a t . i n ms b f i rst m o d e , t h e in st r u c t io n b y te and d a t a b y te s m u st b e w r it te n f r om t h e mo st s i g n i f i c an t bi t to t h e le ast sig n if ic a n t b i t. i n m s b f i rst m o de , t h e s e r i a l p o r t in t e r n a l b y t e ad d r es s g e n e ra t o r d e cr emen ts f o r eac h b y t e o f th e m u l t i b y t e co m m unic a t ion c y cle . w h en in cr em en tin g f r o m 0x1f , th e addr es s g e n e ra t o r c h a n g e s t o 0x00. w h en decr em en tin g f r o m 0x00, th e addr es s g e n e ra t o r c h a n g e s t o 0x1f . notes on serial port operation the AD9878 s e r i al p o r t co nf igura t io n b i ts r e side in bi ts 6 and 7 o f reg i s t er a d dr es s 0x00. i t is im p o r t a n t t o n o te t h a t t h e co nf igura t io n cha n ges im me d i a t e l y up o n wr i t i n g t o t h e last b i t o f t h e r e g i s t er . f o r m u l t i b yte t r an sfers, wr i t in g to t h is r e g i s t er ma y o c c u r d u r i n g t h e middle of t h e co mm uni c a t io n c y cle . m e as ur es m u s t be ta k e n t o com p en s a t e f o r this new co nf igura t io n fo r t h e r e ma i n ing b y t e s o f t h e c u r r en t co mm unic a t io n c y c l e . the s a m e con s i d era t io n s a p pl y w h en s e t t in g t h e res e t b i t i n reg i st er a d dr ess 0x00. a l l o t h e r r e g i s t ers a r e s e t t o t h eir def a u l t val u es, b u t t h e s o f t wa r e r e s e t do es n o t a f fe c t t h e b i t s in r e g i s t er a ddr ess 0x 00. i t is r e co mm e nde d to us e o n ly si n g le-b y t e t r ans f e r s w h e n ch ang i ng s e r i a l p o r t c o n f i g u r a t i o ns or i n i t i a t i ng a s o f t wa r e r e s e t. a wr i t e t o b i ts 1, 2, a n d 3 o f a d dr es s 0x00 wi th th e s a me log i c lev e l s as bi ts 7, 6, a nd 5 (b i t p a t t er n: x y 1001yx b i na r y ) al lo ws th e us er t o r e p r og ra m a los t s e r i al p o r t co nf igur a t io n and to r e s e t t h e r e g i sters to t h eir defa u l t v a l u es. a s e con d wr i t e t o a ddr es s 0x00 w i t h t h e res e t b i t lo w a n d t h e s e r i a l p o r t co nf i g ura t io n as sp e c if ie d ab o v e (x y ) , r e p r ogra m s t h e os cin m u l t i p lier s e t t ing. a cha n g e d f sy s c lk fr e q u e n c y i s s t a b le a f t e r a maxim u m o f 200 f mc l k c y c l es (wak e-u p tim e ).
AD9878 rev. 0 | page 17 of 36 theory of operation f o r a g e n e ral u n derstan d in g o f th e AD9878, r e f e r t o f i gur e 22, a b l o c k dia g ra m of th e device a r chi t ec t u r e . th e device co n s ists o f a t r a n sm i t p a t h , r e cei v e p a t h , a nd a u xi l i a r y f u n c t i o n s, such as a pll, a sig m a - d e l t a d a c, a s e r i a l co n t r o l p o r t , a nd a c a b l e a m plif ier in t e r f ace . t h e t r ans m i t p a t h c o n t ai ns an i n te r p ol a t i o n f i lt e r , a c o m p l e te q u adr a t u r e dig i t a l u p -con v e r t er , a n i n v e rs e si n c f i l t er , a nd a 12-b i t c u r r en t ou t p ut d a c. the r e cei v e p a t h co n t a i n s a 10- b i t a d c and a d u a l 12 -b i t ad c. al l in t e r n al l y r e q u ir ed c l o c ks and a n o u t p u t sy s t em c l o c k a r e ge ne r a te d b y t h e pl l f r om a s i ng l e c r y s t a l or cl o c k i n put . the 12-b i t an d 10-b i t if ad cs ca n con v er t dir e c t if in p u ts u p to 70 mh z and r u n a t s a m p le r a tes u p to 33 msps. a vi de o i n put w i t h an a d j u st abl e s i g n a l cl am pi ng l e vel a l ong w i t h t h e 10-b i t ad c al lo w the AD9878 to p r o c es s a n nt sc an d a q a m chan nel s i m u l t ane o u sly . the p r o g r a mm a b le sig m a - delt a d a c ca n b e us e d to con t r o l ext e r n al co m p on en ts, s u c h as va r i a b le ga in am p l if iers (v g a s) o r vol t age co n t rol l e d t u n e rs. t h e capor t p r o v ides an in t e r f ace t o th e ad8321/ad83 23 o r ad8322/ad8327 p r og ra mma b l e ga in am plif ier (pga) ca b l e dr i v ers, ena b lin g h o s t p r oces so r co n t r o l vi a t h e mxfe se ri al po r t (s p o r t ). txiq txsync mclk refclk c a_por t profile sport if10[4:0] rxsync if12[11:0] fsadj xtal oscin - ? _out flag1 f10 input if12b input video input 6 3 12 12 10 12 AD9878 data assembler quadrature modulator fir lpf cic lpf cos sin dac gain control pll oscin m dds mux mux ca interface profile select serial interface 12 4 4 sinc ?1 mux dac if10 if12 adc adc 12 12 4 5 12 i q rx port tx - ? input reg 4 4 4 12 sinc ?1 bypass ( f oscin ) ( f oscin ) ( f mclk ) mux 12 adc mux if12a input dac + ? clamp level - ? r 4 8 2 2 2 ( f iqclk ) ( f sysclk ) ( f oscin ) 0 3277 - 0 - 007 f i gur e 2 2 . ad98 78 bl oc k dia g r a m
AD9878 rev. 0 | page 18 of 36 t su t hu mc l k t x syn c tx i q t x i [ 11 : 6 ] t xi [ 5 : 0 ] t xq [ 11: 6 ] t x q [ 5: 0] t x i [ 11: 6] ' t x i [ 5 : 0 ] ' t x q [ 11: 6] ' t xq [ 5 : 0 ] ' t x i [ 11: 6 ] ' ' t x i [ 5 : 0] ' ' 0 3277- 0- 0 0 8 f i g u re 23. t x ti min g d i ag r a m transmit path t h e t r ans m i t p a t h c o n t ai ns an i n te r p ol a t i o n f i lt e r , a c o m p l e te q u adr a t u r e dig i t a l u p -con v e r t er , a n i n v e rs e si n c f i l t er , a nd a 12-b i t c u r r en t ou t p ut d a c. the maxim u m o u t p u t c u r r en t o f t h e d a c is s e t b y a n ext e r n al r e sis t o r . th e tx ou t p ut pga p r o v i d e s a d di ti o n al tra n sm i t si gn al lev e l co n t r o l. t h e tra n sm i t pa th in t e r p o l a t io n f i l t e r p r o v i d es a n u p - s a m p l in g fa ct o r o f 16 wi t h an o u t p u t s i g n a l b a n d wi d t h as hig h as 5.8 mh z. c a r r i er f r eq uen c ies u p to 65 mh z wi t h 26 b i ts o f f r eq uen c y t u nin g r e s o l u t i o n can b e gen e r a te d b y t h e dir e c t d i g i t a l sy n t h e si zer (dds). th e t r an smi t d a c r e s o l u t i o n is 12 b i t s a nd i t can r u n a t s a m p ling ra t e s u p t o 232 ms ps . analog o u t p u t s c alin g f r o m 0 db t o 7.5 db in 0.5 db s t eps is a v a i la b l e t o p r es er v e s n r w h en re d u c e d outp ut l e vel s are re qu i r e d . data asse mbler the AD9878 da ta p a t h o p era t es o n tw o 12-b i t w o r d s, th e i and q co m p on e n ts, t h a t fo r m a com p lex sy m b ol. t h e d a t a ass e m b le r b u ilds t h e 24-b i t co m p lex sy m b ols f r o m f o ur co n s ec u t i v e 6-b i t w o r d s r e ad o v er t h e txi q [5:0] b u s. th e s e w o r d s a r e s t r o b e d in t o t h e da ta as s e m b ler sy n c hr on o u s t o the mast er c l o c k (mclk). a hig h le v e l o n txs y n c sig n als the sta r t o f a tra n smi t sym b ol. the f i rst tw o 6- b i t w o r d s o f t h e sy m b ol fo r m t h e i co m p on e n t; t h e s e co nd tw o 6- b i t w o r d s fo r m t h e q com p on e n t. s y m b ol co m p on en ts a r e as s u med t o be in tw os co m p lem e n t fo r m a t . the t i min g o f t h e in ter f ace is f u l l y des c r i b e d i n t h e t r a n smi t t i ming s e c t io n. the i/q s a m p le ra t e f iq clk put s a ba n d w id th lim i t o n th e m a xim u m tra n smi t spec tr um . t h i s i s th e famil i a r n y q u is t limi t ( h er e a f t er r e f e r r ed t o as f ny q ) a n d is eq ual t o o n e- h a l f f iq c l k . transmit timing the AD9878 p r o v ides a mas t er c l o c k m c lk and exp e c t s 6-b i t m u l t i p lexed txi q da ta on each r i sin g edg e (s ee f i gur e 23). t r a n smi t sy m b ols a r e f r a m e d wi t h t h e txs y nc in p u t. txs y nc hig h indic a t e s t h e sta r t o f a tran smi t s y m b ol . f o ur co n s e c u t i v e 6-b i t da ta p a ckag es f o r m a sy m b ol (i ms b , i ls b , q ms b , a nd q ls b). interp olation filter o n c e th r o u g h th e da ta a s se m b l e r , t h e i q d a ta s t r e a m s a r e f e d t h r o ug h a 4 fir lo w-p a ss f i l t e r a n d a 4 c a s c ade d i n teg r a t o r c o m b (c i c ) lo w-p a s s f i l t er . the co m b i n a t ion of t h es e t w o f i l t ers r e s u l t s in th e s a m p le ra t e in cr e a sin g b y a fac t o r o f 16. i n a d d i ti o n t o th e sa m p le ra t e in cr ea se , th e h a lf- b a n d f i l t e r s p r o v ide t h e lo w-p a s s f i l t er in g cha r ac t e r i s t ic ne ces s a r y t o s u p p r es s t h e sp e c t r al ima g es b e t w e e n t h e o r ig inal s a m p li n g f r e q u e nc y an d t h e n e w ( 1 6 h i g h e r ) s a m p l i ng f r e q u e nc y . half -band f i lters ( h b f s) hbf 1 an d h b f 2 a r e b o t h in ter p ola t in g f i l t ers, e a ch o f w h ich do u b les t h e s a m p lin g ra te . t o g e t h er , hb f 1 an d hb f 2 ha v e 26 t a p s a n d prov i d e a f a c t or of f o u r i n c r e a s e i n t h e s a m p l i ng r a te (4 f iq c l k or 8 f ny q ). i n r e l a t i on t o phas e r e s p on s e , b o t h hbfs a r e li n e a r phas e f i l t ers. a s such, vir t ua l l y n o phas e dist or t i o n is in t r o d uce d wi t h in t h e p a s s ban d o f t h e f i l t ers. this is a n im p o r t a n t f e a t ur e , as p h as e dist o r t i o n is ge n e ra l l y in t o lera b l e in a da t a t r an smissio n sy st e m . cascade d integrator comb (cic ) filter the ci c f i l t er is co nf igur e d as a p r og ra mma b l e in t e r p ol a t o r a nd p r o v ides a s a m p le ra t e in cr e a s e b y a fac t o r of 4. th e f r e q u e nc y re sp ons e of t h e c i c f i lte r i s g i ve n by : 3 3 2 )) 4 ( 2 ( ) sin( ) 4 sin( 4 1 1 1 4 1 ) ( ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? f f e e f h f j f j combine d filter response the com b i n e d f r e q uen c y r e s p on s e o f t h e hbf a nd cic f i l t ers p u ts a li mi t on t h e i n p u t sig n a l b a ndwi d t h t h a t ca n b e p r o p a g a t e d th r o ugh th e ad 9878. th e usa b le ba n d w i d t h o f th e f i l t er cha i n pu ts a limi t o n t h e max i m u m d a t a ra te t h a t c a n b e p r o p a g a t e d thr o ug h the ad987 8. a lo ok a t t h e p a s s -band det a i l o f th e com b in e d f i l t er r e s p o n s e (f igur e 24) in dica t e s tha t in o r der t o ma in t a in an a m p l i t ude er r o r o f n o m o r e tha n 1 db , sig n al ban d wid t h is r e s t r i c t ed t o n o m o r e tha n abo u t 60 % o f f ny q . th us, in o r der t o k e ep t h e b a ndwi d t h o f t h e da t a in t h e f l a t p o r t io n o f t h e f i l t er p a s s b a nd , t h e us er m u st o v ers a m p le t h e
AD9878 rev. 0 | page 19 of 36 bas e band da t a b y a t leas t a fac t or o f tw o p r io r t o p r es en ting i t t o th e AD9878. n o t e tha t wi t h o u t o v ers a m p lin g , t h e n y q u is t b a ndwi d t h o f t h e b a s e -b and da t a co r r esp o n d s to f ny q . a s s u c h , t h e u p p e r e n d of t h e da t a b a ndwi d t h wi l l suf f e r 6 db o r m o r e o f a t t e n u a t i o n d u e t o th e f r eq uen c y r e s p o n se o f th e d i gi tal f i l t e r s. f u r t h e r m o r e , if th e b a s e band da ta a p p l ied t o th e AD9878 has been p u l s e s h a p ed , th e r e i s a n ad d i ti o n al co n c ern . t y p i call y , p u ls e sha p in g is a p plie d t o t h e b a s e b a n d d a t a v i a a f i l t er h a vin g a ra is ed cosin e res p o n s e . i n s u ch cas e s, a n val u e is us ed t o m o dif y t h e b a nd w i d t h o f t h e da t a w h er e t h e va l u e o f is such th a t : 0 < < 1. a val u e o f 0 ca u s es t h e da t a b a nd w i d t h t o co r r es p o n d t o t h e n y q u is t b a ndwi d t h . a val u e o f 1 ca us es t h e da t a b a n d wi d t h t o b e ext e n d e d t o t w ice t h e n y q u ist b a n d wi d t h. th us, wi t h 2 o v ers a m p lin g o f t h e b a s e b a nd d a t a an d = 1, th e n y q u is t ba n d w id th o f th e da t a will co rr e s po n d wi th t h e i/ q n y q u i s t ba ndwid th. a s sta t e d ea rlier , this r e s u l t s in p r oblem s n e a r th e u p p e r e d ge o f t h e da t a b a n d wi d t h d u e t o t h e f r e q uen c y r e s p o n s e o f t h e f i l t ers. the max i m u m val u e o f th a t ca n be im ple m e n t e d is 0.45. this is b e c a us e t h e da t a b a n d wi d t h beco m e s: nyq nyq f f 725 . 0 ) 1 ( 2 / 1 = + ? w h ich p u ts t h e da t a b a n d wi d t h a t t h e ext r e m e e d g e o f t h e f l a t p o r t io n o f t h e f i l t er r e s p o n s e . i f a p a r t ic u l a r a p plica t io n r e q u i r es a n val u e b e tw een 0.45 and 1, t h en t h e us er m u s t o v ers a m p l e t h e b a s e b a nd da t a b y a t le ast a fac t o r o f fo ur . o v er t h e f r e q ue nc y ra n g e o f t h e da t a t o b e tra n sm i t t e d , th e co m b in e d h b 1, h b 2, a n d c i c f i l t e r i n tr o d uce s a w o rs t-cas e dro o p o f les s tha n 0.2 db . frequency relative to i/q nyq bw magnitude db 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 6 5 4 3 2 1 0 1 1.0 0 327 7- 0- 00 9 f i gur e 2 4 . c a sc a d ed f i l t er p a ss ba nd digital upconverter the dig i t a l quadra t u r e mo d u l a t o r s t a g e fol l o w in g t h e ci c f i l t e r s i s used t o f r eq ue n c y s h i f t (u pco n v e r t ) th e ba se b a n d s p ectr um o f th e in co m i n g da ta s t r e a m u p t o th e d e si r e d ca rri e r f r eq ue n c y . the ca r r i er f r eq uen c y is co n t r o l l ed n u m e r i cal l y b y a dir e c t dig i t a l syn t h e s i zer (d ds). th e d d s us es t h e in t e r n al sys t em cl o c k ( f sy s c l k ) to ge ne r a te t h e de s i re d c a r r i e r f r e q u e nc y w i t h a hig h d e g r e e o f p r e c isio n. t h e c a r r ier is a p plie d t o t h e i and q m u l t i p liers i n quadra t u r e fas h io n (90 phas e of fs et) a n d su m m e d to y i el d a d a t a st re am t h a t is t h e mo du l a te d c a r r ie r . t h e m o d u l a t e d c a rri e r bec o m e s th e 1 2 - b i t sa m p l e se n t t o t h e da c . tx signal level considerations t h e q u ad ra t u r e m o d u la t o r i t se lf in tr o d uces a maxim u m gain o f 3 d b i n si gnal le v e l . t o v i s u aliz e th i s , a s s u m e tha t bo t h th e i da t a a nd q da t a a r e f i xe d a t t h e max i m u m p o ssi b le d i g i t a l va l u e, x . then t h e o u t p ut o f t h e m o d u l a to r , z, is [ ] ) sin( ) cos( t x t x z ? = q x x i 0 327 7- 0- 01 0 f i g u re 25. 1 6 - q uad r at ure m o dul a t i on it c a n b e s h o w n t h a t | z | assu m e s a max i m u m v a l u e o f 2 2 2 x x x z = + = (a ga in o f +3 db). h o w e v e r , if th e s a me n u m b er o f b i ts w e r e us e d t o r e p r es en t t h e | z | val u es th a t w e r e used t o r e p r e s en t t h e x val u es, a n o v er f l o w w o u l d o c c u r . t o p r e v en t t h is p o ssi b i l i ty , an ef fe c t i v e C3 db a t t e n u a t io n is i n t e rn a l l y i m p l e m e n t e d o n th e i a n d q d a ta pa th : x / / z = + = 2 1 2 1 the fol l o w in g e x a m ple ass u m e s a p k /r m s le v e l o f 10 db: m a xim u m s y m b ol c o m p o n en i n p u t v a l u e = 2047 ls bs C 0. 2 db = 2000 ls bs t m a xim u m c o m p lex i n p u t rms v a l u e = 2000 ls bs 6 db C pk r m s ( db ) = 1265 ls bs r m s the maxi m u m co m p lex in p u t r m s val u e calc u l a t io n us es b o t h i a nd q sy m b ol c o m p on e n ts t h a t add a f a c t o r o f 2 (= 6 db) to t h e fo r m u l a . t a b l e 5 s h o w s ty p i cal i - q in p u t t e st sig n als wi t h a m pli t ude l e v e l s r e la te d t o 12-b i t f u l l s c a l e (fs).
AD9878 table 5. iCq input test s i gnals analo g output digital input input level modulator ou tpu t lev e l single tone (f c C f) i = cos( f) q = cos( f + 90) = Csin(f) fs C 0.2 db fs C 0.2 db fs C 3.0 db single tone (f c + f) i = cos( f) q = cos(f + 270) = +sin( f) fs C 0.2 db fs C 0.2 db fs C 3.0 db dual tone (f c f) i = cos(f) fs C 0. 2 db fs q = cos(f + 180) = Ccos(f) or q = +cos(f) fs C 0.2 db fs C 0.2 db fs tx thr o ug hput an d latenc y da t a in p u ts a f f e c t th e o u t p u t fa irl y q u ic kl y b u t r e ma in ef f e c t i v e d u e t o t h e ad9 878 s f i l t er c h a r ac t e r i s t ics. da t a tra n smi t la t e n c y thr o ug h th e AD9878 is easies t to des c r i be in t e r m s o f f sy s c l k cl o c k c y cl es ( 4 f mc l k ). th e n u m b ers q u o t e d ar e w h en an ef fe c t i s f i rst s e e n af te r an i n put v a lu e ch ange. l a t e n c y o f i/q da ta en t e r i ng the da t a as s e m b ler (AD9878 in p u t) t o th e d a c o u t p u t is 119 f sy s c l k cl o c k c y cl es ( 2 9. 7 5 f mc l k cy c l e s ) . d c val u es a p p l ied t o t h e da ta ass e m b ler in p u t wil l tak e u p t o 176 f sy s c l k cl o c k c y cl es ( 4 4 f mc l k c y cles) t o p r o p a g a t e and s e t t le at t h e d a c o u t p u t . f r e q uen c y h o pp in g is accom p l i sh e d vi a chan g i n g t h e profil e i n pu t pi n . t h e t i me re qu i r e d to s w itc h f r om on e f r e q u e nc y to a n o t h e r is les s t h a n 232 f sy s c l k c y c l es (58.5 f mc l k cy c l e s ) . d/a co nve r ter a 1 2 - bi t di g i t a l - to - a na l o g c o n v e r te r ( d a c ) i s u s e d to c o n v e r t t h e dig i t a l l y p r o c es s e d wa vefo rm in t o a n a n alog sig n al . the w o rs t-c a s e sp ur io us sig n als d u e t o t h e d a c a r e t h e ha r m o n ics o f th e fun d a m en tal si gn al a n d t h e i r ali a se s (s ee th e a n alog de v i ce s d d s t u t o ri al a t w w w . a n a l o g .co m /dds ). th e con v ersion p r o c es s w i l l p r o d uce al ias e d com p on e n ts o f t h e f u ndam e n t al sig n al a t n f sy s c l k f ca rrier ( n = 1, 2, 3). th es e a r e typ i cal l y f i l t er e d wi t h an ext e r n al rl c f i l t er a t t h e d a c o u t p ut. i t is i m p o rt a n t f o r t h i s a n a l o g fi l t e r t o h a v e a s u ffi c i e n t l y f l a t g a i n an d l i ne ar p h a s e re sp ons e a c ro ss t h e b a nd w i d t h of i n te re s t s o a s t o a v o i d mo d u l a t i o n im p a ir m e n t s. a r e la t i v e l y in exp e n s i v e s e ve n t h orde r el l i p t ic a l l o w-p a ss f i l t e r is su f f i c i e n t to sup p r e s s t h e a l ias e d com p o n e n ts fo r hf c n e tw o r k a p pli c a t ion s . the AD9878 p r o v ides tr ue a nd co m p lem e n t c u r r en t o u t p u t s. t h e full - s cal e o u t p u t cu rr e n t i s se t b y th e r set re s i s t o r at p i n 4 9 a nd t h e d a c g a in r e g i ster . a s sumin g max i m u m d a c gain, t h e val u e o f r set fo r a p a r t ic u l ar f u l l -s c a l e i ou t is deter m in e d usin g th e e q ua ti o n : r set = 32 v dac r s e t / i out = 39.4/ i ou t f o r exa m p l e , if a f u l l -s cale o u t p u t c u r r en t o f 20 ma is desir e d , th en r set = (39. 4/0.02), o r a p p r o x ima t e l y 2 k?. the fol l o w in g e q ua t i o n calc u l a t es t h e f u l l -s cale o u t p ut c u r r en t in cl u d in g t h e p r og ra mma b l e d a c ga in con t r o l. i ou t = 39.4/ r set 10 (C7.5 + 0.5 ng a i n )/2 0 w h er e n gai n is t h e va l u e o f d a c f i n e gain c o n t r o l[3:0]. the f u l l -s c a le ou t p u t c u r r en t ra n g e o f th e ad9 878 is 4 ma t o 2 0 m a . f u l l - s c a l e output c u r r e n t s out s i d e of t h i s r a nge w i l l de g r ade sf dr p e r f or manc e. sf dr is a l s o sl ig h t ly af fe c t e d b y output m a tch i n g ; t h a t i s , t h e t w o output s s h ou l d b e te r m i n a t e d e q u a l l y f o r b e st sf dr p e r f or m a nc e. t h e output l o a d shou l d b e lo ca ted as c l os e as p o s s ib le t o the AD9878 p a cka g e t o minimize s t ra y c a pa ci ta n c e a n d in d u cta n ce . t h e l o a d m a y be a s i m p l e re s i stor to g r oun d , an op a m p c u r r e n t - to - v o l t a g e c o n v e r te r , or a t r a n sfo r m e r - cou p le d cir c ui t. i t is b e st n o t t o a t tem p t t o dir e c t ly dr i v e hig h l y r e ac ti v e lo ads, s u c h as a n lc f i l t er . dr i v in g a n lc f i l t er w i t h ou t a t r a n sfo r m e r r e q u ir es t h a t t h e f i l t er b e do ub l y t e r m ina t e d fo r b e s t p e r f o r ma nce; t h a t is, t h e f i l t er in p u t an d o u t p u t sh o u ld b o th b e r e si s t i v e l y t e rm i n a t e d w i th th e a p p r o p r i a t e v a l u es. th e p a ral l el co m b ina t ion of t h e tw o t e r m ina t ion s wi l l det e r m in e t h e lo ad tha t t h e AD9878 s e es f o r sig n als wi t h in t h e f i l t er p a s s b a nd . f o r exa m ple , a 50 ? t e r m ina t e d in p u t/o u t p u t lo w-p a s s f i l t er wil l lo ok li k e a 25 ? lo ad t o th e ad9 878. th e o u t p u t co m p lian ce v o l t a g e o f the AD9878 is C0.5 v t o +1.5 v . an y sig n al dev e l o p ed a t the d a c output s h ou l d n o t e x c e e d + 1 . 5 v ; ot he r w i s e s i g n a l d i stor t i on wi l l r e s u l t . f u r t h e r m o r e , t h e sig n al ma y ext e n d b e lo w g r o u nd as m u ch a s 0 . 5 v w i t h out d a m a ge or s i g n a l d i stor t i on . t h e AD9878 tr ue a nd co m p lem e n t o u t p u t s can be dif f er en tial l y co m b in e d f o r co mm on-mo d e rejec t io n usin g a b r o a d b and 1:1 tra n sf o r m e r . u s in g a g r o u nded cen t er t a p r e s u l t s in sig n als a t th e AD9878 d a c output pi n s t h a t are s y m m e t r i c a l ab out g r ou n d . a s p r e v i ou sly me n t ione d, b y dif f e r e n t i a l ly c o mb in i n g t h e two sig n als, t h e us er ca n p r o v i d e s o m e deg r e e o f comm on- m o d e sig n al r e je c t io n. a d i f f e r e n t i a l c o mbi n e r m i g h t c o ns i s t of a t r an s f or me r or an op a m p . th e ob j e c t is t o co m b i n e or a m plif y o n l y t h e dif f er en ce b e tw e e n tw o sig n a l s a nd t o r e je c t a n y co mm onusua l ly u n des i r a bl e char ac ter i st ic , su ch as 6 0 h z h u m or cl o c k fe e d - th r o ugh th a t i s eq uall y p r e s e n t o n bo t h in di v i d u al si gn als. ad832x AD9878 variable gain cable driver amplifier 3 tx ca dac 75 ? low-pass filter ca_en ca_data ca_clk 032 77- 0- 0 1 1 f i g u re 26. cab l e a m pl if ie r conn ec t i o n rev. 0 | page 20 of 36
AD9878 c o nn ec t i n g t h e AD9878 tr ue a nd co m p lem e n t o u t p u t s t o the dif f er en t i al in puts o f t h e p r og ra mma b l e ga i n cab l e dr i v ers ad8321/ad83 23 o r ad8322/ad8327 (s ee f i gur e 26) p r o v ides a n o p t i mi ze d s o l u t i o n fo r t h e st a nda rd co m p l i an t cab l e m o de m u p s t r e a m channe l . th e cab l e dr iv er s ga in c a n b e p r og ra mm e d thr o ug h a dir e c t 3-wir e in t e r f ace usin g th e ad9 878 s p r o f ile re g i ste r s . programming the ad8321/ad832 3 or ad8322/ad8327 cable driver amplifier p r og ra mmin g th e ga in o f the ad832x fa mil y o f ca b l e dr i v er a m p l if iers can b e acco m p lis h ed via t h e AD9878 ca b l e am p l if ier co n t r o l in ter f ace . t w o 8-b i t r e g i s t ers wi thin t h e AD9878 (o ne p e r p r o f i l e) s t o r e t h e gain va l u e t o b e wr i t t e n t o t h e s e r i al 3- wir e p o r t . t y p i cal l y , ei ther th e ad83 21/ad8323 o r ad8322/ad83 27 v a r i abl e g a i n c a bl e am pl i f i e rs are c o n n e c te d to t h e ch i p s 3 - w i re ca b l e am plif ier i n t e r f ace . t h e t x ga in c o n t r o l s e le c t b i t in r e gi st e r 0x0f c h a n g e s th e in t e r p r e ta ti o n o f th e b i t s i n re gi s t e r s 0x13, 0x17, 0 x 1 b , a nd 0x1f . s e e f i gur e 27 a nd c a b l e dr i v er ga in c o n t r o l r e g i s t er des c r i p t io n. ca enable ca_clk ca_data msb 8 t mclk 8 t mclk 8 t mclk 4 t mclk 4 t mclk lsb 0 327 7- 0- 01 2 f i g u re 27. cab l e a m pl if ie r in ter f ac e ti ming d a t a t r a n sfers to t h e p r og ra mma b l e ga i n cab l e dr i v er a m plif i e r a r e i n it i a t e d by f o u r c o n d it i o n s : 1. p o w e r - u p a nd h a r d wa r e res e tu p on in i t ia l p o w e r - u p an d ev er y ha r d wa r e r e s e t, th e ad98 78 c l ea rs th e con t en ts o f the ga in c o n t r o l r e g i s t ers t o 0, whic h def i n e s t h e l o w e s t ga in s e t t in g o f th e ad832x. th us, the AD9878 wr i t es al l 0s o u t o f the 3-w i r e ca b l e a m plif ier co n t r o l in t e r f ace . 2. s o f t wa r e res e tw r i t in g a 1 to b i t 5 o f a ddr es s 0x00 ini t ia t e s a so ftw a r e r e se t . o n a so f t w a r e r e se t , th e ad 9 8 7 8 c l ea r s th e co n t e n ts o f t h e ga in c o n t r o l r e g i s t ers t o 0 f o r th e lo w e s t ga in a nd s e ts t h e p r o f ile s e lec t t o 0. the AD9878 wr i t es al l 0s o u t o f t h e 3- w i r e cab l e a m plif ier co n t rol in t e r f ace if t h e ga in w a s o n a dif f er en t s e t t in g (dif fer e n t f r o m 0) b e fo r e . 3. cha n g e in p r o f ile s e lec t io nthe AD9878 s a m p les t h e p r o f il e i n p u t p i n t o g e t h e r w i th th e t w o p r o f ile s e lect b i t s a n d wr i t es t o th e ad832x ga in c o n t r o l r e g i s t ers w h en a c h an g e in p r o f i l e a n d gain is deter m i n e d . the da t a wr i tte n to t h e cab l e dr i v er a m p l if ier co m e s f r o m t h e AD9878 g a in c o n t r o l r e g i s t er a s soci a t e d wi th th e curr e n t p r o f ile . 4. w r i t e t o t h e AD9878 c a b l e dr i v er am p l if ier c o n t r o l reg i st ersth e AD9878 wil l wr i t e ga in con t r o l da ta as s o c i a t e d wi t h t h e c u r r en t p r o f ile t o th e ad832x when ev er th e s e lec t e d AD9878 cab l e dr i v er a m p l if ier ga in s e t t in g is c h a n g e d . o n c e a new sta b le ga in val u e has been det e c t e d (48 t o 64 m c lk c y c l e s a f t e r i n i t ia ti o n ) da ta w r i t e s t a r t s w i t h ca_en going l o w . the AD9878 wil l alwa ys f i nis h a wr i t e s e q u en ce t o t h e ca b l e dr i v er a m plif ier on ce i t is st a r t e d . t h e log i c co n t r o l l in g d a t a t r an sfers t o th e ca b l e dr i v er a m p l if ier us es u p t o 200 m c lk c y c l es a n d has b e en des i g n e d t o p r e v en t er r o n e o u s wr i t e c y cles f r o m e v er oc cu rri n g . oscin cloc k multiplier the AD9878 can accep t ei t h er a n in p u t c l o c k in t o the osci n p i n o r a f u ndam e n t a l m o de cr y s t a l acr o ss t h e oscin and xt al p i n s as t h e de vice s main c l o c k s o ur ce . the in t e r n al p ll th en ge ne r a te s t h e f sy s c l k si gn al f r o m wh i c h all o t h e r i n t e rn al si gn als a r e der i v e d . the d a c us es f sy s c l k as i t s s a m p lin g clo c k. f o r dds a p plic a t ion s , t h e ca r r ier is ty p i ca l l y limi t e d t o ab o u t 30% o f f sy s c l k . f o r a 65 mh z ca r r i er , t h e sy st em clo c k r e q u ir e d is ab o v e 216 mh z. the oscin m u l t i p lier f u n c tio n ma in ta in s c l o c k in teg r i t y as e v iden ce d b y the AD9878 sys t em s exce l l en t p h as e n o is e ch a r ac t e r i st ics an d lo w cl o c k-r e la t e d sp u r in t h e o u t p u t sp e c t r u m . e x t e r n al lo o p f i l t er co m p on en ts co n s is tin g o f a s e r i es r e sis t o r (1.3 k?) a nd c a p a ci t o r (0.01 f) p r o v ide the co m p en sa tio n zer o fo r t h e osci n m u l t i p lier pll lo o p . the o v eral l lo o p p e r f o r ma n c e has b e e n o p t i mi ze d fo r t h es e com p o n e n t v a l u es. clock a n d oscilla tor circuitry the AD9878 s in t e r n al os cil l a t o r g e n e ra t e s al l s a m p ling c l o c ks f r o m a sim p le, l o w co st, p a r a l l el r e s o na n c e, f u ndam e n t a l f r eq ue n c y q u a r tz cr ys tal . f i gur e 28 s h o w s h o w th e q u a r tz cr y s t a l is co nn e c te d b e tw e e n o s cin (pi n 61) a nd xt al (pi n 60) wi t h p a ral l el r e s o na n t lo ad ca p a c i t o rs as sp ecif ied b y the cr ys tal ma n u fac t ur er . th e in t e r n al os cil l a t o r circ ui tr y ca n als o b e o v er dr i v en b y a t t l le ve l cl o c k a p plie d t o oscin w i t h xt a l lef t unconn e c t e d . f osci n = f mc l k m a n i n t e rn al p h ase- lock e d loo p (p ll) g e n e ra t e s th e d a c sa m p l i n g f r eq u e n c y , f sy s c l k , b y m u l t i p l y i n g t h e o s c i n f r eq uen c y b y m. th e m c l k sig n al (p in 23), f mc l k , is der i ve d b y dividi n g f sy s c l k by 4 . f sy s c l k = f os c i n m f mc l k = f os c i n m / 4 an ext e r n al p l l lo o p f i l t er (p in 57) co n s is ting o f a s e r i es r e sis t o r a nd cera mic c a p a ci t o r ( f igur e 28: r1 = 1.3 k?, c12 = 0.01 f) is r e q u ir e d fo r st a b i l i t y o f t h e pll. a l s o , a shie l d s u r r o u n d in g t h es e co m p on en ts is r e co mm e nde d t o minimize ext e r n al n o is e c o u p lin g in t o t h e p l l s v o l t a g e con t r o l l e d o s ci l l a t o r i n p u t (gua r d t r ace conn e c te d to a v ddpll). rev. 0 | page 21 of 36
AD9878 f i gur e 22 s h o w s th a t a d c s a r e e i th e r sa m p le d d i r e ctl y b y a lo w ji t t er clo c k a t o s cin o r b y a clo c k t h a t is der i ve d f r o m t h e pl l o u t p ut. o p er a t i n g mo des c a n b e s e le c t e d i n re g i ster 8. sa m p l i n g t h e ad c s dir e c t l y wi t h t h e os cin clo c k r e q u i r es mclk p r o g ra mm e d to b e t w ice t h e os cin f r e q ue n c y . programmable clock output refclk the AD9878 p r o v ides a n a u xil i a r y o u t p u t c l o c k o n p i n 69, refclk. th e v a l u e o f t h e mc lk divi der b i t f i e l d , r , d e t e rm in e s i t s o u t p u t f r eq ue n c y a s s h o w n i n t h e eq ua ti o n s f refclk = f mc l k / r , f o r r = 2 t o 63 f refclk = f osci n , f o r r = 0 i n i t s def a u l t s e t t in g (0x00 in reg i s t er 1), th e re fclk p i n prov i d e s a bu f f e r e d output of f osci n . 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 av dd agnd video in agnd if12a+ if12a ? agnd av dd reft12a re fb1 2 a av dd agnd if12b+ if12b ? agnd av dd reft12b re fb1 2 b av dd agnd av dd1 0 agnd1 0 if10+ if10 ? agnd 76 reft10 75 refb10 74 agnd10 73 avdd10 72 drvdd 71 drgnd 70 refclk 69 sigdelt 68 flad(0) 67 flag(1) 66 ca_en 65 ca_data 64 ca_clk 63 dvddosc c10 20pf c11 20pf c12 0.01 f guard trace r1 1.3k ? 62 oscin 61 xtal 60 dgndosc 59 agndpll 58 pllfilt 57 avddpll 56 dvddpll 55 dgndpll 54 avddtx 53 tx+ 52 tx? c13 0.1 f r set 4.02 ? 51 txsyn c 26 ( m s b) txiq( 5) 27 txiq( 4) 28 txiq( 3) 29 txiq( 2) 30 txiq( 1) 31 txiq( 0) 32 dv dd 33 dgnd 34 dv dd 35 dgnd 36 profile 37 r eset 38 dv dd 39 dgnd 40 sc lk 41 cs 42 sd io 43 sd o 44 dgndtx 45 dv ddtx 46 p w rdn 47 re fio 48 fs adj 49 agndtx 50 drgnd 1 drvdd 2 (msb) if12(11) 3 if12(10) 4 if12(9) 5 if12(8) 6 if12(7) 7 if12(6) 8 if12(5) 9 if12(4) 10 if12(3) 11 if12(2) 12 if12(1) 13 if12(0) 14 (msb) if10(4) 15 if10(3) 16 if10(2) 17 if10(1) 18 if10(0) 19 rxsync 20 drgnd 21 drvdd 22 mclk 23 dvdd 24 dgnd 25 AD9878 top view (not to scale) c5 0.1 f c6 0.1 f c4 0.1 f cp2 10 f c2 0.1 f c3 0.1 f c1 0.1 f cp1 10 f c2 0.1 f c3 0.1 f c1 0.1 f cp1 10 f 0327 7- 0- 01 3 f i gure 28. bas i c connec t ion d i ag r a m rev. 0 | page 22 of 36
AD9878 reset and tra n s m it powe r-d o wn power-up sequence on in i t ia l p o w e r - u p , t h e res e t p i n sho u ld be he ld lo w un til t h e p o we r su p p ly is st abl e ( s e e f i g u re 2 9 ) . o n c e res e t is deas s e r t e d , the AD9878 can be p r og ra mm e d o v er th e s e r i a l p o r t . the o n -chi p p ll r e q u ir es a maxim u m o f 1 m s a f t e r t h e ri s i n g ed g e o f reset or a ch ange of t h e m u lt ipl i e r f a c t or ( m ) to co m p lete l y s e t t l e . i t is r e co mmen d e d tha t t h e pwrdn pi n b e h e ld l o w d u ri n g th e r e se t a n d p l l se t t l i n g tim e . ch a n g e s t o ad c clo c k s e l e c t (reg is t e r 0x08) o r s y s clo c k divider n (reg ist e r 0x01) s h o u ld b e p r og ra mm ed bef o r e t h e r i sin g e d g e of pwrdn . o n c e th e p l l i s fr e q u e n c y l o c k ed a n d a f t e r th e pwrdn p i n i s b r o u gh t h i gh , tra n s m i t da ta c a n be sen t r e l i a b l y . if t h e pwrdn p i n c a nno t be he ld lo w thr o ug h o u t t h e res e t an d p l l s e t t l i n g t i m e pe ri od , th e n th e p o w e r - d o w n d i gi t a l t x b i t or t h e pwrdn p i n sh o u ld be p u ls e d a f ter th e p l l has s e t t le d . this wi l l ensur e co r r e c t t r a n smi t f i l t er ini t ia l i z a t i o n . 0 3277 - 0 - 0 1 4 v s 1ms min. 5mclk min. reset pwrdn f i gu r e 2 9 . p o w e r - up se que n c e fo r t x da ta p a th reset t o i n it i a te h a rd w a re re s e t , t h e res e t p i n sh o u ld b e he ld lo w f o r a t least 100 n s . al l in t e r n al l y g e n e ra t e d c l o c ks excep t osco ut s t o p d u r i n g r e s e t. th e r i sin g edge o f res e t r e s e ts t h e pll c l o c k m u l t i p lier and reini t ial i zes t h e p r og ra mma b l e r e g i s t ers t o t h e i r defa u l t v a l u es. th e s a me s e q u e n ce as des c r i b e d a b o v e in t h e p o we r - u p s e qu e n c e s e c t i o n s h ou l d b e f o l l owe d af te r a re s e t or change i n m . a s o f t wa r e r e s e t (wr i tin g a 1 in to b i t 5 o f reg i s t er 0x00) is f u nc t i on a l ly e q u i v a l e n t to t h e h a rdw a re re s e t but d o e s not f o rc e reg i st er 0x00 t o i t s def a u l t va l u e. transmi t p o wer-dow n a lo w le v e l o n t h e pwrdn p i n st o p s al l c l o c ks lin k e d t o th e d i gi t a l tra n smi t da ta p a th a n d r e se t s t h e c i c f i l t e r . dea s se r t i n g pwrdn r e ac t i va t e s a l l clo c ks. t h e cic f i l t er is held i n a r e s e t st a t e fo r 8 0 mclk c y cl es af ter t h e r i sing e d ge of pwrdn to a l lo w fo r f l ushin g o f t h e ha lf- b a nd f i l t ers wi t h ne w i n p u t d a t a . t r a n sm i t da t a b u rsts sh o u l d b e p a dde d w i t h a t l e ast 20 sy m b ols o f n u l l da t a dir e c t ly b e fo r e t h e pwrdn p i n is de ass e r t e d . im m e d i at e l y a f t e r t h e pwrdn p i n is de ass e r t e d , t h e t r an smi t b u rs t sh o u ld star t wi th a minim u m o f 20 n u l l da ta sy m b ols (s e e f i gur e 30). this a v o i ds uni n te nde d d a c o u t p ut s a m p les c a us e d b y th e tra n smi t pa th la t e n c y a n d f i l t e r set t li n g t i m e . s o f t wa r e p o w e r - do wn dig i tal tx (b i t 5 in reg i s t er 0x02) is fun c ti o n all y eq ui v a le n t t o th e h a r d w a r e pwrdn p i n and t a k e s ef fe c t imme dia t e l y a f t e r t h e last r e g i s t er b i t has b e e n wr i t t e n o v er t h e s e r i al p o r t . pwrdn txiq txsync 20 null symbols data symbols 20 null symbols 00 00 0 0 0 0 5mclk min. 03 27 7- 0- 0 1 5 f i gure 30. t i m i ng s e quence to f l ush t x d a t a p a th sigma-del t a ou tpu t s the AD9878 con t a i n s an o n -chi p sig m a-de l t a ou t p u t tha t p r o v ides a dig i t a l log i c b i t s t r e am wi t h a n a v erag e d u ty c y cle tha t va r i es between 0 % an d (40 95/4096)%, dep e ndin g on t h e p r o g r a mm e d co de, as sh o w n i n f i gur e 31. 000h 8 t mclk 001h 002h 800h fffh 4096 8 t mclk 8 t mclk 4096 8 t mclk 032 77- 0 - 0 1 6 f i gur e 3 1 . si g m a-d e l t a output si gna l s this b i t s t r e a m ca n be lo w-p a s s f i l t er ed t o g e n e ra t e a p r og ra mma b l e dc v o l t a g e o f : v dc = [( sig m a-d e l t a c o de /4096) v h ]+ v l wh er e: v h = v dr v d d C 0.6 v v l = 0.4 v i n cab l e m o dem s e t-t o p bo x a p plica t ion s , the o u t p u t can b e us ed t o co n t r o l ext e r n al va r i a b l e ga in am p l if iers o r rf t u n e rs. a sim p le sin g le -p ole r c lo w-p a s s f i l t er p r o v ide s s u f f i cien t f i l t er in g (s ee f i gur e 32). rev. 0 | page 23 of 36
AD9878 AD9878 mclk dac 12 control word typical: r = 50k ? ? inpu t sig n al range a n d digi tal outpu t codes the if ad cs ha v e dif f er en tial a n alog in p u ts labe le d if+ an d if C. th e sig n al in p u t, v ai n , is t h e v o l t a g e dif f er en ce b e tw e e n t h e tw o in p u t p i n s , v ai n = v if + C v if C . th e f u l l -s cale in p u t v o l t a g e ra n g e is det e r m i n e d b y t h e in t e r n al r e fer e n c e v o l t a g es, reft a nd ref b , w h ich def i n e t h e to p a nd b o tto m o f t h e s c a l e. t h e peak in p u t v o l t a g e t o th e a d c is th e d i f f e r e n ce bet w een r e ft a nd refb , w h ich is 1 v pd . this r e su l t s in t h e a d c f u l l s c a l e in p u t v o l t a g e ra n g e o f 2 v pp d . t h e dig i t a l o u t p ut co de is st r a ig h t b i na r y a nd is i l lust r a te d in t a b l e 6. f i gur e 3 2 . si g m a-d e l t a r c f i lt e r i n m o r e dem a ndin g a p plic a t ions w h er e add i t i ona l ga in, le vel shif t, o r dr i v e c a p a b i li ty is r e q u i r e d , a f i rst o r s e co nd o r der ac ti v e f i l t er mig h t be co n s ider e d (s ee f i gur e 33 ). table 6 if12[11:0] input signal v o ltage 111...111 111...111 111...110 ... 100...001 100...000 011...111 ... 000...001 000...000 000...000 v ain +1.0 v v ain = +1.0 v C (1 lsb) v ain = +1.0 v C (2 lsb) v ain = 0 v + 1 lsb v ain = 0.0 v v ain = 0 v C 1 ls b v ain = C1.0 v + ( 2 lsb) v ain = C1.0 v v ain < C1.0 v AD9878 sigma-delta ? ? f i gur e 3 3 . si g m a-d e l t a a c ti v e f i l t er with ga in and o ffse t drivi n g th e inpu t recei v e p a th ( r x) the if ad cs ha v e dif f er en t i al sw i t ch e d c a p a ci t o r s a m p le- a n d - h o ld am plif ier (s h a ) i n p u ts. th e n o minal dif f er en t i a l in p u t im p e d a n c e is 4. 0 k?||3 pf . this im p e d a n c e c a n b e us e d as t h e ef fe c t i v e t e r m ina t io n im p e dan c e w h en calc u l a t in g f i l t er t r a n sfer ch ar a c te r i st i c s a nd volt ag e s i g n a l a tte n u a t i o n f r om non z e r o s o ur ce im p e dances. i t sh o u ld b e n o te d , h o w e ver , t h a t fo r b e st perf o r m a n c e , ad d i ti o n al r e q u i r em en t s m u s t be m e t b y t h e si gnal s o ur ce . the s h a has in p u t ca p a ci t o rs tha t m u st be r e c h a r g e d e a ch t i m e t h e in p u t is s a m p le d . this r e su l t s i n a d y na mic in pu t c u r r en t a t t h e de v i ce i n p u t, an d deman d s t h a t t h e s o ur ce has l o w ( < 5 0 ? ) output i m p e d a nc e a t f r e q u e nc i e s up to t h e a d c sa m p l i n g f r eq u e n c y . al so , th e so u r c e m u s t h a v e se t t l i n g t o be t t e r t h a n 0.1 % in <1 /2 ad c cl k p e r i o d . the AD9878 inc l udes thr e e hig h s p e e d , hig h p e r f o r ma n c e ad cs. t h e 10- b i t an d d u a l 12 - b i t dir e c t if ad cs deli ver exce l l en t unders a m pling p e r f o r ma nce wi t h in pu t f r e q uen c ies a s hig h as 70 m h z. th e s a m p lin g r a t e can b e as hig h as 33 ms ps. the a d c s a m p lin g f r e q uen c y c a n b e der i ve d di r e c t ly f r o m t h e o s c i n s i g n a l o r f r om t h e on - c h i p o s c i n m u lt ipl i e r . f o r hig h e s t dy na mi c p e r f o r ma n c e, i t is r e co m m e n d e d to ch o o s e an oscin f r eq uenc y tha t can b e dir e c t l y us ed as th e ad c s a m p ling c l o c k. dig i tal 12 -b i t ad c o u t p u t s a r e m u l t i p lexe d t o on e 1 2 - b it bu s , c l o c ke d by a f r e q u e n c y ( f mc l k ) o f f o ur ti m e s th e s a m p ling ra te . th e if ad cs us e a m u l t i p lexer t o a 12-b i t i n te r f a c e w i t h a n output word r a te of f mc l k . a n ot he r c o ns i d e r a t i o n f o r ge tt i n g t h e b e st p e r f or m a nc e f r om th e a d c i n p u t s i s th e d c b i a s i n g o f th e in p u t sign al . i d eall y , th e sig n al s h o u l d b e b i as e d t o a dc l e v e l e q ual t o the mid p o i n t o f th e a d c re f e re nc e vo lt age s , r e f t 1 2 an d r e f b 1 2 . n o m i n a l l y , t h i s lev e l wil l be 1.2 v . w h en ac -co u p l ed , th e ad c in p u ts wil l s e lf- b i as t o t h is v o l t a g e and r e q u ir e n o ad di t i o n a l in p u t cir c ui t r y . f i gur e 34 il l u s t ra t e s a r e co mm en de d cir c ui t tha t eas e s t h e b u r d en on t h e s i g n al s o ur ce b y is ola t in g i t s o u t p u t f r o m the ad c i n p u t. t h e 33 ? s e r i es t e rmina t io n r e sisto r s is ola t e t h e a m plif ier o u t p uts f r o m a n y c a p a ci t i v e lo ad , w h i c h ty p i ca l l y im p r o v es s e t t ling t i me . th e s e r i es ca p a c i t o rs p r o v ide ac sig n al c o u p l i n g w h i c h e n s u r e s t h at t h e a d c i n p u t s o p e r at e at t h e if10 and if12 adc operation the if10 an d if 12 ad cs ha v e a co mm on a r c h i t ec t u r e an d sh are m a n y of t h e s a m e ch ar a c t e r i st i c s f r om an a p pl i c a t i o ns st a ndp oi n t . m o s t of t h e i n f o r m at i o n i n t h e s e c t i o n b e l o w w i l l b e a p plicab le t o b o t h if ad c s . dif f er en ces, w h er e t h e y exis t, wi l l be hi ghli g h t e d . rev. 0 | page 24 of 36
AD9878 opt i ma l dc bi as vol t age. t h e sh u n t c a p a c i tor s o u r c e s t h e d y na mic c u r r en ts r e q u ir e d t o cha r g e t h e sh a i n p u t ca p a c i t o rs, r e m o vi n g t h is r e q u ir e m en t f r o m t h e a d c b u f f er . th e val u es o f c c a nd c s sh o u ld b e calc u l a t e d t o g e t th e co r r e c t hp f an d l p f co r n er f r eq uen c ies. ainp ainn 33 ? c c c s c c v s 33 ? 03 277 - 0 - 019 f i g u re 34. si mpl e a d c d r ive co nf ig ur a t ion receive timing the AD9878 s e n d s m u l t i p lexed da ta t o th e if1 0 a nd if12 output s on e v e r y r i s i ng e d ge of m c l k . r x s y n c f r ame s t h e s t a r t o f eac h if10 da ta s y m b ol . 10-b i t and 12-b i t ad cs a r e co m p lete l y r e ad o n ev er y s e cond m c lk c y c l e . rxs y nc is hig h f o r ev er y s e co nd 10-b i t ad c da ta (if 10-b i t ad c is n o t in p o w e r - do w n mo de).t h e rx t i min g d i a g ra m i s sh own i n f i gu r e 35. t od t ee t md oscout mclk if10 dat a if10[9:5] if10[4:0] if10[9:5] if10[4:0] m/n = 2 if10[9:5] if10[4:0] if12a if12b if12b if12b if12a if12b rxsync if12 dat a rx port timing (default mode: muxed if12 adc data) m/n = 2 oscout if12a or if12b if12a or if12b if10[9:5] if10[4:0] if10[9:5] if10[4:0] if10[9:5] if10[4:0] if12a or if12b mclk if10 dat a rxsync if data t md t ee t od rx port timing (output data from only one if12 adc) 032 77- 0 - 0 2 0 f i g u re 35. r x p o r t tim i ng adc voltage references the AD9878 has thr e e in dep e nden t in ter n al r e f e r e n c es f o r i t s 10-b i t and 12-b i t ad cs. b o th 1 2 -b i t and 10-b i t ad cs a r e desig n e d f o r 2 v p-p in p u t v o l t a g es wi th eac h o f th em ha vin g i t s ow n i n te r n a l re f e re nc e. f i g u re 2 8 show s t h e pro p e r c o n n e c t i ons of t h e re f e re nc e pi ns r e f t a n d r e f b . e x te r n a l re f e re nc e s m a y b e ne c e ss ar y for s y ste m s t h a t re qu ire hig h ac c u r a c y g a in ma t c hin g b e tw e e n a d cs o r fo r im p r o v emen t s i n t e m p er a t ur e dr if t a nd n o is e cha r ac ter i st ics. e x ter n a l r e fer e n c es ref t and refb n e e d t o b e cen t er e d a t a v d d /2 wi t h o f fs et v o l t a g es as sp e c if ie d: reft -10, -12: a v d d /2 + 0.5 v refb-10, -12: a v d d /2 C 0.5 v a dif f er en t i al le v e l o f 1 v b e tw e e n t h e r e fer e n c e p i n s r e s u l t s i n a 2 v p-p ad c in p u t leve l ai n. i n t e r n al r e f e r e n c e s o ur ces ca n b e p o w e r e d do w n w h en ext e r n al refer e n c es a r e us e d (r eg is t e r a ddr es s 0x02). vide o i n pu t f o r s a m p lin g video-typ e wa v e f o r m s, s u c h as nt sc an d p a l sig n a l s, t h e v i de o i n p u t ch a n n e l p r o v ides b l ack l e vel clam p i ng. f i gur e 36 s h o w s th e cir c ui t co nf igura t io n f o r usin g th e v i deo cha n n e l in p u t (p in 98). an ext e r n al b l o c kin g c a p a ci t o r is us ed w i th th e o n - c h i p v i d e o c l a m p ci r c u i t t o l e v e l - s h i f t th e i n p u t s i g n a l to a d e s i r e d re f e re nc e p o i n t . t h e c l a m p c i rc u i t a u t o ma ticall y sen s e s th e m o s t n e ga ti v e po r t i o n o f th e i n p u t si gn al , a n d ad j u s t s th e v o l t a g e acr o s s th e in p u t ca pa ci t o r . t h i s fo r c es t h e b l ack le v e l o f t h e in p u t sig n al t o b e e q ual t o t h e val u e p r og ra mm e d in t o t h e c l a m p l e v e l r e g i s t er ( r eg is t e r a d dr es s 0x07).v ideo i n p u t can be m u l t i p lexed t o th e i f 12a ad c (defa u l t ) o r t o t h e if12b ad c b y p r og ra mmin g reg i st er a ddr es s 0x03. 2ma v ideo inpu t 0.1 f clamp level +fs/2 clamp level AD9878 offset bufer 12 + ? dac adc lpf clamp level 032 77- 0- 0 2 1 f i g u re 36. vide o c l amp ci r c u i t input pcb desi g n consid erati o ns al th o u g h the AD9878 is a mixed-si g n al de vic e , th e p a r t sh o u ld be tr e a t e d a s a n a n alog co m p o n e n t . th e d i g i tal ci r c ui tr y o n - c h i p has be e n sp e c ial l y desig n e d t o minimize th e im p a c t tha t t h e dig i t a l s w i t chin g n o is e wi l l ha v e on t h e o p e r a t io n o f t h e a n a l o g c i r c u i t s . fo l l o w i n g t h e p o w e r , g r ou n d i n g , a n d l a y o ut r e co mme n d a t ion s in t h is s e c t ion w i l l he l p t h e u s er get t h e b e st p e r f or m a nc e f r om t h e m x f e . component placeme n t i f t h e t h r e e fol l o w i n g guide l in e s o f co m p on en t place m e n t a r e f o l l owe d , ch anc e s f o r ge tt i n g t h e b e s t p e r f or m a nc e f r om t h e mxfe a r e gr ea tl y i n cr ea se d . rev. 0 | page 25 of 36
AD9878 rev. 0 | page 26 of 36 x first, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the mxfe or analog circuits. x second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. x third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. in order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this will keep the highest frequency return current paths short, and prevent them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generou sly bypassed at each device to further reduce the high frequency ground currents. the mxfe should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections will not flow in the ground plane under the mxfe. the analog circuits should be placed furthest from the power supply. the AD9878 has several pins that are used to decouple sensitive internal nodes. these pins are refio, refb12a, reft12a, refb12b, reft12b, refb10, and reft10. the decoupling capacitors connected to these points should have low esr and esl. the capacitors should be placed as close to the mxfe as possible and be connected directly to the analog ground plane. the resistor connected to the fsadj pin and the rc network connected to the pllfilt pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling the AD9878 evaluation board (figure 38 and figure 39) demonstrates a good power supply distribution and decoupling strategy. the board has four layers: two signal layers, one ground plane, and one power plane. the power plane is split into a 3 vdd section that is used for the 3 v digital logic circuits, a dvdd section that is used to supply the digital supply pins of the AD9878, an avdd section that is used to supply the analog supply pins of the AD9878, and a vanlg section that supplies the higher voltage analog components on the board. the 3 vdd section will typically have the highest frequency currents on the power plane and should be kept the furthest from the mxfe and analog sections of the board. the dvdd portion of the plane carries the current used to power the digital portion of the mxfe to the device. this should be treated similarly to the 3 vdd power plane and be kept from going underneath the mxfe or analog components. the mxfe should largely sit above the avdd portion of the power plane. the avdd and dvdd power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the dvdd portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads between the voltage source and dvdd, and between the source and avdd. both dvdd and avdd should have a low esr, bulk decoupling capacitor on the mxfe side of the ferrite as well as low esr, esl decoupling capacitors on each supply pin (i.e., the AD9878 requires 17 power supply decoupling capacitors). the decoupling capacitors should be placed as close to the mxfe supply pins as possible. an example of proper decoupling is shown in the AD9878 evaluation board schematic (figure 38 and figure 39). ground planes in general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. all ground connections should be made as short as possible. this will result in the lowest impedance return paths and the quietest ground connections. if the components cannot be placed in a manner that would keep the high frequency ground currents from traversing under the mxfe and analog components, it may be necessary to put current steering channels into the ground plane to route the high frequency currents around these sensitive areas. these current steering channels should be made only when and where necessary. signal routing the digital rx and tx signal paths should be kept as short as possible. also, these traces should have a controlled impedance of about 50 ?. this will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, then series termination resistors (33 ? to 47 ?) should be placed close to all signal sources. it is a good idea to series terminate all clock signals at their source regardless of trace length. the receive signals are the most sensitive signals on the entire board. careful routing of these signals is essential for good receive path performance. the if+/ifC signals form a differential pair and should be routed together as a pair. by keeping the traces adjacent to each other, noise coupled onto the signals will appear as common mode and will be largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe will further reduce the possibility of noise corrupting these signals.
AD9878 rev. 0 | page 27 of 36 pin conf iguration and pi n function descriptioins 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 av dd agnd video in agnd if12a + if12a ? agnd av dd r e ft12a r e fb 12a av dd agnd if12b + if12b ? agnd av dd r e ft12b r e fb 12b av dd agnd av dd1 0 agnd1 0 if10+ if10 ? agnd 76 reft10 75 refb10 74 agnd10 73 avdd10 72 drvdd 71 drgnd 70 refclk 69 sigdelt 68 flad(0) 67 flag(1) 66 ca_en 65 ca_data 64 ca_clk 63 dvddosc 62 oscin 61 xtal 60 dgndosc 59 agndpll 58 pllfilt 57 avddpll 56 dvddpll 55 dgndpll 54 avddtx 53 tx+ 52 tx? 51 txsyn c 26 txiq( 5) 27 txiq( 4) 28 txiq( 3) 29 txiq( 2) 30 txiq( 1) 31 txiq( 0) 32 dv dd 33 dgnd 34 dv dd 35 dgnd 36 profile 37 r eset 38 dv dd 39 dgnd 40 sc lk 41 cs 42 sd io 43 sd o 44 dgndtx 45 dv ddtx 46 p w rdn 47 re fio 48 fs adj 49 agndtx 50 drgnd 1 drvdd 2 if12(11) 3 if12(10) 4 if12(9) 5 if12(8) 6 if12(7) 7 if12(6) 8 if12(5) 9 if12(4) 10 if12(3) 11 if12(2) 12 if12(1) 13 if12(0) 14 if10(4) 15 if10(3) 16 if10(2) 17 if10(1) 18 if10(0) 19 rxsync 20 drgnd 21 drvdd 22 mclk 23 dvdd 24 dgnd 25 AD9878 100-lead lqfp top view (not to scale) 03 277 - 0 - 002 f i gur e 3 7 . p i n c o nfigur a t io n table 7. p i n f u nction descriptions pin no. mnemonic pin function 1, 21, 70 2, 22, 71 3C14 15C19 20 23 24, 35, 39 25, 34, 36, 40 26 27:32 37 38 41 42 43 44 45 46 47 48 49 drgnd drvdd if12[11:0] if10[4:0] rxsync mclk dvdd dgnd tx sync tx iq[5:0] profile reset sclk cs sdio sdo dgndtx dvddtx pwrdn refio fsadj pin driver digital ground pin driver digital 3.3 v supply 12-bit adcs digital ouput 10-bit adc digit a l ouput sync output, 10 - and 12-bit ad cs master clock ou tput digital 3.3 v sup p ly digital ground sync input for transmit port digital input for transmit port profile selection input chip reset input sport clock sport chip select sport data i/o sport data out p ut tx path digital ground tx path digital 3.3 v supply power-down transmit path txdac decoupli ng (to agnd ) dac output adj u st (ex t ernal res.)
AD9878 rev. 0 | page 28 of 36 pin no. mnemonic pin function 50 51, 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66, 67 68 69 72, 80 73, 79 74 75 76, 81, 86, 89, 94, 97, 99 77, 78 82, 85, 90, 93, 100 83 84 87, 88 91 92 95, 96 98 agndtx txC, tx+ avddtx dgndpll dvddpll avddpll pllfilt agndpll dgndosc xtal oscin dvddosc ca_clk ca_data ca_en flag[2:1] sigdelt refclk avdd10 agnd10 refb10 reft10 agnd if10-, if10+ avdd refb12b reft12b if12bC, if12b+ refb12a reft12a if12aC, if12a+ video in tx path analog ground tx path complementary outputs tx path analog 3.3 v supply pll digital ground pll digital 3.3 v supply pll analog 3.3 v supply pll loop filter connection pll analog ground oscillator digital ground crystal oscillator inverted output oscillator clock input oscillator digital 3.3 v supply serial clock to cable driver serial data to cable driver serial enable to cable driver programmable flag outputs sigma-delta dac output reference clock output 10-bit adc analog 3.3 v supply 10-bit adc analog ground 10-bit adc ref decoupling node 10-bit adc ref decoupling node 12-bit adc analog ground differential input to 10-bit adc 12-bit adc analog 3.3 v supply adc12b ref decoupling node adc12b ref decoupling node differential input to adc12b adc12a ref decoupling node adc12a ref decoupling node differential input to adc12a video clamp input
AD9878 re page 9 of 1k 10k r c 0805 s m a 200u p c c 0805 rc0 8 0 5 sm a e d g e ag nd;3, 4, 5 rc0 7 c up r c 0805 c c 060 3 r c 0805 l c 1210 l c 1210 rc0 8 0 5 c c 060 3 l c 1210 rc0 8 0 5 l c 1210 c c 0603 c c 0805 cc0 8 0 5 b a b a tokob5f sp c c 0603 c c 0805 vcc gnd1 gnd2 vi n+ vi n- gnd3 dataen sdata clk gnd4 sleep nc byp vout- vout+ ramp txen vcc1 gnd5 gnd ad8328 c c 0603 c c 060 3 r c 0805 r c 0805 sm a e d g e ag nd;3, 4, 5 c c 0603 r c 0805 r c 0805 val bcas e c c 0805 c c 0 805 c c 0805 c c 0805 rc0 8 0 5 sm a e d g e ag nd;3, 4, 5 di p 0 6 rcup s m ae dg e ag nd;3, 4, 5 s m ae dg e ag nd;3, 4, 5 c c 0805 r c 0805 r c 0805 c c 0603 b a di p 0 6 rcup di p 0 6 rcup c c 0603 r c 0805 r c 0805 r c 0805 c c 060 3 r c 0805 r c 0805 cc0 6 0 3 r c 0805 r c 0805 r c 0805 c c 0805 bcas e r c 0805 r c 0805 ba di p 0 6 rcup b a c c 1206 c c 0805 r c 0805 c c 0805 bcas e c c 1206 c c 0603 c c 0603 agnd; 5 b a ba ba s m ae dg e ag nd;3, 4, 5 r c 0805 r c 0805 ri bbon h e ade r r a r i bbo n 22 r2 r1 rc o m r3 r4 r5 r6 r7 r8 r9 r c 0805 s m ae dg e ag nd;3, 4, 5 r c 0805 cc0 6 0 3 vcc gnd reset adm1818- 1 0art cc0 6 0 3 cc0 6 0 3 bcas e c c 0603 c c 0603 c c 0603 c c 0603 bcas e c c 0603 c c 0603 c c 0603 c c 0603 bcas e r c 0805 c c 060 3 r c 0805 c c 0603 c c 0603 c c 0603 cc0 8 0 5 cc0 6 0 3 c c 0603 c c 0805 AD9878lqfp dgnd1 dgnd2 dgnd3 dgnd4 dgndtx dvdd1 dvdd2 dvdd3 dvdd4 dvddtx fsadj if 0 if 1 if 1 0 if 2 if 3 if 4 if 5 if 6 if 7 if 8 if 9 if b 0 if b 1 if b 2 if b 3 mclk profi l e refi o rxsync sclk sdi o sdo txi q 0 txi q 1 txi q 2 txi q 3 txi q 5 txsync cs pwrdn reset drvdd1 if 1 1 drgnd1 agnd1 txi q 4 if b 4 agnd10 agnd10- a agnd2 agnd3 agnd4 agnd5 agnd6 agnd7 agndpll agndtx avdd1 avdd10 avdd10- a avdd2 avdd3 avdd4 avdd5 avddpll avddtx caclk cadata dgndosc dgndpll drgnd drvdd drgnd2 drvdd2 dvddosc dvddpll flag1 flag2 i f 10b+ i f 10b- i f 12a+ i f 12a- i f 12b+ i f 12b- osci n pllfi lt refb10 refclk refb12b refb12a reft12a reft12b reft10 si gdelt tx- tx+ vi deoi n caen xtal ad8138 -i n +i n vee vc c vo c vo + vo - r c 0805 cw osc_i n _clk vi deo i n transf ad8328 ad8328 transf ext_clk transf ad8138 transf i f - 12a reset ad8138 transf ad8138 transf ad8138 transf ad8138 transf i f - 12b if -1 0 ad8138 ad8138 di g i tal t rans m i t tx_out ad8328 transf tx_out duty cycle pot1 10k r6 500 tx+ dvddpllosc avddtx tx- sdo, sdi o , c s, sclk sclk sdo sdi o cs if [0 :1 1 ] if 1 1 if 1 if 0 if 6 if 5 if 2 if 3 if 4 if 7 if 8 if 9 if 1 0 if b [ 0 : 4 ] if b 4 if b 2 if b 3 if b 1 if b 0 if 1 2 b - if 1 2 b - if 1 2 b + if 1 2 b + if 1 0 - if 1 0 - if 1 0 + if 1 0 + sdelta0 if 1 2 a - if 1 2 a + 1 8 6 3 2 4 5 u9 76 73 79 81 86 89 94 97 99 58 50 82 72 80 85 90 93 100 56 53 63 64 25 34 36 40 59 54 45 70 1 21 71 2 22 24 33 35 39 62 55 46 67 66 49 14 13 4 78 77 3 96 95 88 87 12 11 10 9 8 7 6 5 19 18 17 16 15 23 61 57 37 74 91 83 69 48 75 92 84 20 41 43 44 68 52 51 32 31 30 29 28 27 26 98 60 65 42 47 38 u2 c98 20pf c24 0. 1uf 0. 1uf c23 c20 18pf 0. 1uf c6 0. 1uf c69 wht tp4 0. 01uf c16 r4 1. 3k c15 0. 01uf wht tp3 100k r3 wht tp15 tp6 wht w ht tp5 c4 10v 10uf c5 0. 1uf 0. 1uf c3 c2 0. 1uf 0. 1uf c12 c14 16v 10uf c13 0. 1uf c11 0. 1uf tp1 wht w ht tp2 c7 0. 1uf 0. 1uf c9 10uf 10v c8 10k r10 0. 1uf c22 0. 1uf c21 2 3 1 u1 c1 0. 1uf r22 499 1 2 j11 r20 49. 9 3 2 1 4 5 6 7 8 9 10 rp 1 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 34 56 78 9 j2 r21 33 33 r19 1 2 j12 31 2 jp31 31 2 jp25 2 13 jp26 jp4 13 4 2 sw1 0. 1uf c101 c94 0. 1uf c88 47pf c91 10uf 16v c90 0. 1uf 49. 9 r33 c108 20pf c95 2 13 jp23 1 2 3 5 4 6 t2 31 2 jp21 r18 499 523 r23 10uf 16v c96 0. 1uf c97 r15 10k r13 33 49. 9 r24 0. 1uf c86 499 r17 33 r14 c87 c112 0. 1uf jp22 49. 9 r27 r26 33 33 r25 c102 0. 1uf jp24 1 2 3 5 4 6 t3 1 2 3 5 4 6 t5 jp30 2 13 jp32 0. 1uf c111 33 r32 r31 33 c92 20pf 1 2 j15 1 2 j13 1 2 34 5 6 t1 1 2 j4 jp1 500 r7 0. 1uf c84 c17 18pf 18pf c18 24 u13 ag nd;3 v _ cl k;5 33 r5 c110 0. 1uf c83 16v 10uf 3 1 2 y1 37. 5 r12 r11 37. 5 8138- a_buff- vcml vcml vcml 8138+ 8138+ 8138- 8138- drvdd c66 0. 1uf 1 2 j8 r39 43. 3 r40 86. 6 0. 1uf c115 c116 0. 1uf 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 u4 0. 1uf c72 c117 0. 1uf 1 2 3 4 5 t6 13 2 jp8 13 2 jp7 18pf c58 33pf c57 0. 01uf c114 l15 220 r38 75 220 l16 c113 0. 01uf 75 r36 220 l14 l13 220 r37 59 caenable cadata caclk pwrdown rxsync mclk dvddtx dvdd drvdd drvdd avdd refclk flag1 flag2 caenable cadata caclk txi q 1 txi q 2 txi q 3 txi q 5 txsync 0. 1u f c1 0 r2 33ohm r1 75ohm 1 2 j1 v_clk xtal xtal osci n osci n reset 49. 9 r9 c19 0. 1uf j3 ag nd;3, 4, 5 47pf vcml a_buff+ rc0 8 0 5 r29 jp9 txi q 0 profi l e1 txi q 4 ca_sleep r28 5v_ad8328 5v_ad8328 c c 0805 r c 08 05 8138+ 5. 11k r16 0. 1uf r c 0805 drvdd pwrdown nc7s z 04 r c 0805 03277- 0 - 0 38 f i g u re 38. a d 9 8 7 8 ev aluat i on pcb s c h e m a t i c (pag e 1 )
AD9878 re page of 100 1k rj45 s m ae dg e ag nd;3, 4, 5 22 22 22 22 22 22 22 22 22 22 22 22 22 22 74 l v x c 32 45 t sso p2 4 a1 a2 a3 a4 a5 a6 a7 g nd1 g nd2 g n d3 b7 b6 b5 b4 b3 b2 b1 b0 nc vcc b a0 vc c a oe t/ r 22 22 22 a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 g nd1 g nd2 g n d3 nc t/ r vc c a v c c b oe 74 l v x c 32 45 t sso p2 4 b a b a nc7s z 04 74 l v x c 32 45 t sso p2 4 a1 a2 a3 a4 a5 a6 a7 g nd1 g nd2 g n d3 b7 b6 b5 b4 b3 b2 b1 b0 nc vcc b a0 vc c a oe t/ r 22 22 22 h d r 040r a a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 g nd1 g nd2 g n d3 nc t/ r vc c a v c c b oe 74 l v x c 32 45 t sso p2 4 dcn2 5 r pt b a i n ver t c l k d i gi t a l r ec ei ve mcl k de l _ cl k pc pa r a l l e l p or t mc l k rx s y nc de l _ cl k ifb [ 0:4] ifb4 if b 2 if b 1 if b 0 if b 3 3 1 2 jp 13 dbuf f 3 - 5 v dbuf f 5 v sdo p c ssdi o 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 3 4 5 6 7 8 9 j6 sdo 3 4 5 6 7 8 9 10 21 20 19 18 17 16 15 14 11 12 13 23 12 4 22 2 u5 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 5 7 3 1 j5 ribbon 1 16 rp 5 11 6 rp 5 98 rp 5 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 3 1 22 2 u7 89 rp 4 2 2 71 0 22 rp 4 61 1 rp 4 2 2 51 2 22 rp 4 41 3 rp 4 2 2 31 4 22 rp 4 21 5 rp 4 2 2 11 6 22 rp 4 24 u3 ag nd;3 dbuf f 5 v ; 5 1 3 2 jp 5 r3 5 33 2 3 1 jp 6 8 9 rp 3 22 7 10 22 r p 3 6 11 rp 3 22 5 12 22 r p 3 4 13 rp 3 22 3 14 22 r p 3 2 15 rp 3 22 1 16 22 r p 3 8 9 rp 2 22 7 10 22 r p 2 6 11 rp 2 22 5 12 22 r p 2 4 13 rp 2 22 3 14 22 r p 2 2 15 rp 2 22 1 16 22 r p 2 2 22 24 1 23 13 12 11 14 15 16 17 18 19 20 21 10 9 8 7 6 5 4 3 u6 18 rp 7 7 10 rp 6 98 rp 6 2 22 1 3 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 u8 5 4 rp 7 36 rp 7 7 2 rp 7 7 10 rp 5 5 12 rp 5 13 4 rp 5 3 14 rp 5 15 2 rp 5 11 6 rp 6 5 12 rp 6 13 4 rp 6 3 14 rp 6 15 2 rp 6 1 16 rp 6 1 2 j7 del _ cl k sd o p c sdi o cs scl k r8 r3 4 dvdd ca_ sl eep 1 2 3 4 5 6 7 8 91 0 1 11 2 p1 sscl k scs if0 if 2 if 3 if 1 if 4 if 5 if 6 if 7 if 8 if 9 if10 if11 if[0:11] r c 0603 r c 0603 jp 3 r c 0603 0.1u f val 10u f 16v c c 0805 l c 1210 bcas e cl r c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 cl r cl r cl r cl r cl r cl r cl r cl r l c 1210 c c 0805 l c 1210 c c 0805 c c 0805 l c 1210 c c 0805 c c 0805 l c 1210 c c 0805 bcas e l c 1210 c c 0805 l c 1210 c c 0805 bcas e l c 1210 c c 0805 l c 1210 c c 0805 c c 0805 l c 1210 bcas e l c 1210 bcas e bcas e bcas e l c 1210 bcas e bcas e bcas e bcas e bcas e c c 0805 bcas e cl r cl r cl r cl r c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 c c 0603 a d 83 28 c5 3 0.1u f c4 8 0.1u f c5 1 0.1u f c5 4 0.1u f c5 6 0.1u f c3 3 0.1u f tp 19 tp 18 tp 17 tp 16 5 3 2 1 jp 2 c7 8 16v 10u f 4 c8 1 0.1u f c7 9 16v 10u f 10u f 16v c7 7 10u f 16v c6 0 c6 1 16v 10u f 10u f 16v c5 9 l12 v a l c2 5 16v 10u f c4 0 16v 10u f 10u f 16v c2 6 val l6 10u f 16v c2 7 val l3 0.1u f c3 0 c4 3 0.1u f l4 v a l c2 8 0.1u f l1 v a l c4 1 16v 10u f c4 4 0.1u f l5 v a l 0.1u f c2 9 val l2 10u f 16v c4 2 0.1u f c4 5 l9 v a l c6 4 0.1u f val l7 0.1u f c6 2 val l8 0.1u f c6 3 c8 2 0.1u f l11 v a l 0.1u f c8 0 val l10 8 7 6 tp 7 tp 8 tp 9 tp 10 tp 11 tp 12 tp 13 tp 14 0.1u f c6 7 c 7 0 0.1u f 0 .1u f c7 3 c 7 5 0.1u f c4 6 0.1u f c5 2 0.1u f c4 9 0.1u f 0.1u f c8 5 0.1u f 0 .1u f c7 4 c 7 1 0.1u f 0 .1u f c6 8 c 6 5 0.1u f 0.1u f c3 6 0.1u f c3 7 c3 4 0.1u f 0.1u f c3 1 0.1u f c3 9 c3 8 0.1u f 0.1u f c3 5 c3 2 0.1u f dvddtx avdd a_buff+ abuff+ abuff- 3_3va dbuff5v 5v_ad8328 a_buff- dvddpllosc avddtx c5 5 0.1u f c5 0 0.1u f c4 7 0.1u f c 100 0.1u f dbuff3-5v l c 1210 avddpll v_clk tp 20 c9 3 c8 9 l17 c7 6 dvdd drvdd 3_3vd 5v 03277-0-039 f i g u re 39. a d 9 8 7 8 ev aluat i on pcb s c h e m a t i c (pag e 2 )
AD9878 re page of 03277-0-040 f i g u re 40. a d 9 8 7 8 ev aluat i on pcb t o p a s s e mbly 03277-0-041 f i g u re 41. a d 9 8 7 8 ev aluat i on pcb b o t t o m a s s e mb ly
AD9878 re page of 03277-0-042 f i g u re 42. a d 9 8 7 8 ev aluat i on pcb lay o ut t op laye r 03277-0-043 f i g u re 43. a d 9 8 7 8 ev aluat i on pcb lay o ut b ot to m l a ye r
AD9878 rev. 0 | page 33 of 36 03277-0-044 f i g u re 44. a d 9 8 7 8 ev aluat i on pcb p o we r p l an e f i g u re 45. a d 9 8 7 8 ev aluat i on pcb gr ou nd p l ane
AD9878 rev. 0 | page 34 of 36 outline dimensions to p v i e w (p i n s d o w n ) 1 25 26 51 50 75 76 100 14 . 0 0 b s c s q 0. 50 b s c 0 . 2 7 0 . 2 2 0 . 1 7 1. 60 m a x se a t i n g pl a n e 12 ty p 0. 75 0. 60 0. 45 vi e w a 16 . 0 0 b s c s q 12 . 0 0 re f 0. 2 0 0. 0 9 1. 4 5 1. 4 0 1. 3 5 0. 08 m a x c o p l an ar i t y vi e w a ro t a t e d 9 0 c c w se a t i n g pl a n e 10 6 2 7 3. 5 0 0. 15 0. 05 pi n 1 c o m p l i a n t t o j e de c s t an da r d s m s - 0 2 6 b e d f i g u re 46. 1 00-l e ad l o w p r of i l e q u a d f l ap p a ckag e [l q f p ] (st - 10 0) di me nsio ns sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. o r de r i ng gui de model temperature r a nge package descri ption package option AD9878bst C40 c to +85 c 1 0 0 - l q f p s t - 1 0 0 AD9878bstrl C40 c to +85 c 1 0 0 - l q f p s t - 1 0 0
AD9878 rev. 0 | page 35 of 36 notes
AD9878 rev. 0 | page 36 of 36 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . c03277-0-5/03(0)

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